Input power supply circuit with input supply frequency control mechanism

Abstract

The present application provides an input power supply circuit with input supply frequency control mechanism. The input power supply circuit includes an input switch, a current detection circuit, a clock signal generation circuit and a charging circuit. A first terminal of the input switch is coupled to an input voltage. The current detection circuit detects a total input current flowing from a second terminal of the input switch to output an input current detection signal. The clock signal generation circuit sets a frequency of a plurality of pulses of a charging clock signal according to the input current detection signal. The charging circuit outputs a charging signal to a control terminal of the input switch based on the frequency of the plurality of pulses of the charging clock signal.

Description

Technical Field

[0001] This invention relates to input power supply circuits, and more particularly to an input power supply circuit having an input power supply frequency control mechanism. Background Technology

[0002] For electronic devices, power converters are indispensable. Power converters are used to convert the input voltage received from the input power supply circuit and supply the converted input voltage as the output voltage to the electronic device.

[0003] However, conventional power supply circuits, specifically charging circuits, supply a fixed amount of power to electronic devices based on a fixed frequency and a predetermined clock signal. These circuits do not adjust the frequency and amount of power supplied to the device according to its power requirements. In particular, when the device requires only a low amount of power, the conventional power supply circuit maintains the same level of power without reducing it. This results in unnecessary power waste. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an input power supply circuit with an input supply frequency control mechanism. The input power supply circuit of this invention includes an input switch, a current detection circuit, a clock signal generation circuit, and a charging circuit. A first terminal of the input switch is coupled to an input voltage. A second terminal of the input switch is connected to the power receiving terminal of each of a plurality of power receiving circuits. The current detection circuit is connected to the second terminal of the input switch. The current detection circuit is configured to detect a total input current flowing from the second terminal of the input switch and output an input current detection signal. The clock signal generation circuit is connected to the current detection circuit. The clock signal generation circuit is configured to set the frequency of each of a plurality of pulses of a charging clock signal based on the input current detection signal. The charging circuit is connected to the clock signal generation circuit and the control terminal of the input switch. The charging circuit is configured to output a charging signal to the control terminal of the input switch based on the frequency of each pulse of the charging clock signal.

[0005] As described above, the present invention provides an input power supply circuit with an input supply frequency control mechanism. The charging circuit of the input power supply circuit of the present invention can reduce the charging frequency of the voltage at the control terminal of the input switch as the total input current drawn from the second terminal of the input switch by multiple power receiving circuits (e.g., multiple power converters) decreases. Therefore, the input power supply circuit of the present invention only supplies an appropriate amount of power to the multiple power receiving circuits, and does not supply excessive power, thereby preventing the input power supply circuit of the present invention from generating unnecessary power consumption, thereby effectively saving power. Furthermore, if the input power supply circuit of the present invention includes a main control circuit, the clock signal generation circuit can stop supplying the main control clock signal to the main control circuit in power-saving mode to save even more power.

[0006] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to the first embodiment of the present invention.

[0008] Figure 2 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to a second embodiment of the present invention.

[0009] Figure 3 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to a third embodiment of the present invention.

[0010] Figure 4 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism according to the fourth embodiment of the present invention.

[0011] Figure 5 The waveform diagrams are of the input power supply circuits with input supply frequency control mechanisms according to the first to fourth embodiments of the present invention.

[0012] Figure 6 The waveform diagrams are of the input power supply circuits with input supply frequency control mechanisms according to the first to fourth embodiments of the present invention.

[0013] Figure 7 This is a circuit diagram of a clock synchronization circuit for an input power supply circuit with an input supply frequency control mechanism, according to the fifth embodiment of the present invention.

[0014] Figure 8The waveform diagram shows the signal of the clock synchronization circuit of the input power supply circuit with input supply frequency control mechanism according to the fifth embodiment of the present invention.

[0015] Figure 9 The waveform diagrams are of the input power supply circuits with input supply frequency control mechanisms according to the first to fifth embodiments of the present invention. Detailed Implementation

[0016] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of one or more of the associated listed items.

[0017] Please see Figure 1 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to the first embodiment of the present invention.

[0018] The input power supply circuit of the present invention is suitable for supplying power to, for example, power to, such as Figure 1 The multiple input currents IL shown are respectively connected to multiple power receiving circuits PR1 to PRn. The multiple power receiving circuits PR1 to PRn serve as multiple loads of the input power supply circuit of this invention. Each of the multiple power receiving circuits PR1 to PRn can be any electronic circuit, such as, but not limited to, multiple power converters.

[0019] Multiple power receiving circuits PR1 to PRn each have multiple output terminals that can supply multiple output voltages VOUT to multiple electronic devices. These electronic devices act as multiple loads for each of the power receiving circuits PR1 to PRn. It should be understood that the amount of input current IL required by each of the power receiving circuits PR1 to PRn depends on the electrical power required for the operation of the connected electronic device.

[0020] It is worth noting that the input power supply circuit of the present invention can appropriately modulate the current value and power supply frequency of the total input current ISUM supplied, based on the current amount of the total input current ISUM of the multiple input currents IL drawn by the multiple power receiving circuits PR1 to PRn from the input power supply circuit of the present invention.

[0021] In order to properly control and modulate the total input current ISUM supplied to the multiple power receiving circuits PR1 to PRn, such as Figure 1 As shown, the input power supply circuit of the present invention includes an input switch SWIN, a current detection circuit 100, a clock signal generation circuit 200, and a charging circuit 300.

[0022] The first terminal (e.g., the drain) of the input switch SWIN is coupled to an input voltage VBUS. The second terminal (e.g., the source) of the input switch SWIN serves as an output terminal of the input power supply circuit of this invention. The voltage at the second terminal (e.g., the source) of the input switch SWIN serves as an output voltage VBUSO.

[0023] The second terminal of the input switch SWIN, which is an output terminal of the input power supply circuit of the present invention, is connected to a power receiving terminal of each of the plurality of power receiving circuits PR1 to PRn. The input power supply circuit of the present invention is configured to supply a total input current ISUM, which is split into a plurality of input currents IL and supplied to the plurality of power receiving circuits PR1 to PRn respectively.

[0024] Furthermore, after each power receiving circuit PR1 to PRn receives the input current IL from the input power supply circuit of the present invention, each power receiving circuit PR1 to PRn operates using or converting the input current IL to supply the output voltage VOUT to the connected electronic device.

[0025] The current detection circuit 100 is connected to or contacts the second terminal (and the first terminal) of the input switch SWIN. The current detection circuit 100 detects a total input current ISUM flowing out from the second terminal of the input switch SWIN to output an input current detection signal IAS.

[0026] The first input terminal of the clock signal generation circuit 200 is connected to the output terminal of the current detection circuit 100. The clock signal generation circuit 200 sets the frequency of each of the multiple pulses of a charging clock signal CLK based on an input current detection signal IAS received from the current detection circuit 100.

[0027] The input terminal of the charging circuit 300 is connected to a charging clock output terminal of the clock signal generation circuit 200 and the control terminal of the input switch SWIN. Based on the frequency of each of the multiple pulses of a charging clock signal CLK received from the clock signal generation circuit 200, the charging circuit 300 outputs a charging signal CHG to the control terminal of the input switch SWIN. This charging signal CHG can be a voltage signal or a current signal.

[0028] In other words, the charging circuit 300 of the input power supply circuit of the present invention can determine the change in the current value of a total input current ISUM drawn from the output voltage VBUSO of the second terminal of the input switch SWIN by the multiple power receiving circuits PR1 to PRn based on an input current detection signal IAS received from the current detection circuit 100, thereby modulating the frequency of voltage charging at the control terminal of the input switch SWIN, and thus modulating the operating state of the input switch SWIN, thereby modulating the amount and frequency of the total input current ISUM supplied to the multiple power receiving circuits PR1 to PRn.

[0029] The greater the total power required by the electronic devices connected to the output terminals of the power receiving circuits PR1 to PRn, the greater the total input current ISUM drawn by the power receiving terminals of the multiple power receiving circuits PR1 to PRn from the output terminal of the input power supply circuit of the present invention. Conversely, the smaller the total power required by the electronic devices connected to the output terminals of the power receiving circuits PR1 to PRn, the smaller the total input current ISUM drawn by the power receiving terminals of the multiple power receiving circuits PR1 to PRn from the output terminal of the input power supply circuit of the present invention.

[0030] When the current drawn from the total input current ISUM increases for the multiple electronic devices connected to the multiple output terminals of the multiple power receiving circuits PR1 to PRn respectively, the charging circuit 300 of the input power supply circuit of the present invention increases the frequency of voltage charging to the control terminal of the input switch SWIN according to the increase in the total input current ISUM, so as to change the conduction state of the input switch SWIN, for example, by increasing the conduction time of the input switch SWIN, allowing a larger amount of total input current ISUM to flow through the second terminal of the input switch SWIN to the multiple power receiving circuits PR1 to PRn.

[0031] It is worth noting that when the total input current ISUM at the second terminal of the input switch SWIN of the input power supply circuit of the present invention decreases, the charging circuit 300 of the input power supply circuit of the present invention reduces the frequency of supplying power to the control terminal of the input switch SWIN according to the amount of decrease in the total input current ISUM, thereby modulating the conduction state of the input switch SWIN and causing a smaller amount of the total input current ISUM to flow out from the second terminal of the input switch SWIN. In this way, under the condition that the multiple power receiving circuits PR1 to PRn obtain sufficient power as required, the power consumption of the input power supply circuit of the present invention is reduced to the maximum extent, thereby achieving power saving.

[0032] Please see Figure 2 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to the second embodiment of the present invention.

[0033] The second embodiment of the present invention is the same as the first embodiment, and will not be repeated herein.

[0034] The difference between the second embodiment and the first embodiment of the present invention is that, as Figure 2 As shown, in the second embodiment, the input power supply circuit of the present invention, in addition to including the input switch SWIN, the current detection circuit 100, the clock signal generation circuit 200, and the charging circuit 300, also includes a main control circuit 400, wherein the current detection circuit 100 includes a current detection amplifier CSA. In practice, as... Figure 1 The current sensing circuit 100 shown may also include a current sensing amplifier CSA.

[0035] like Figure 2 As shown, the first input terminal of the current sense amplifier CSA, for example, the non-inverting input terminal, is connected to the second terminal of the input switch SWIN, and the second input terminal of the current sense amplifier CSA, for example, the inverting input terminal, can be connected to the first terminal of the input switch SWIN. The current sense amplifier CSA detects the total input current ISUM flowing from the first terminal of the input switch SWIN to the second terminal of the input switch SWIN.

[0036] The output of the current sense amplifier CSA is connected to the first input of the clock signal generation circuit 200. The current sense amplifier CSA multiplies the detected total input current ISUM by a set gain to output an input current sense signal IAS to the first input of the clock signal generation circuit 200.

[0037] The output terminal of the main control circuit 400 is connected to the second input terminal of the clock signal generation circuit 200. A main control clock output terminal of the clock signal generation circuit 200 is connected to a clock receiver terminal of the main control circuit 400. A charging clock output terminal of the clock signal generation circuit 200 is connected to an input terminal of the charging circuit 300.

[0038] In non-power-saving mode / normal mode, the main control circuit 400 can control the clock signal generation circuit 200 to set the frequency of each of the multiple pulses of a charging clock signal CLK to a set frequency, and output a charging clock signal CLK with this set frequency to the charging circuit 300.

[0039] It is worth noting that in power-saving mode, the main control circuit 400 controls the clock signal generation circuit 200 to set the frequency of multiple pulses of a charging clock signal CLK based on the current value of an input current detection signal IAS received from the current detection amplifier CSA, and outputs this charging clock signal CLK to the charging circuit 300. The charging circuit 300, based on the frequency of the multiple pulses of the charging clock signal CLK received from the clock signal generation circuit 200, outputs a charging signal CHG to the control terminal of the input switch SWIN. Thus, when the current value of the input current detection signal IAS required by the multiple power receiving circuits PR1 to PRn decreases, the power supplied by the charging circuit 300 to the multiple power receiving circuits PR1 to PRn can be effectively reduced, achieving power saving.

[0040] Furthermore, in non-power-saving / normal mode, the main control circuit 400 can control or enable the clock signal generation circuit 200 to output a main control clock signal CLKCR with a set frequency according to a set frequency of a charging clock signal CLK. That is, the frequency of each of the multiple pulses of the main control clock signal CLKCR is equal to a set frequency. The main control circuit 400 performs its operation based on the frequency of the multiple pulses of the main control clock signal CLKCR received from the clock signal generation circuit 200; in other words, the main control circuit 400 uses the frequency of the pulses of this main control clock signal CLKCR as its own operating frequency.

[0041] The main control circuit 400 controls the operation of multiple power receiving circuits PR1 to PRn and processes data from these circuits based on the frequency of multiple pulses in the main control clock signal CLKCR. For example, ... Figure 1 As shown, the main control circuit 400 can set and output multiple main control command signals SCT to multiple power receiving circuits PR1 to PRn respectively based on the frequency of multiple pulses of the main control clock signal CLKCR, so as to control the operation of multiple power receiving circuits PR1 to PRn.

[0042] It is worth noting that in power-saving mode, the main control circuit 400 can instruct the clock signal generation circuit 200 to stop outputting the main control clock signal CLKCR to the main control circuit 400, so as to reduce the workload of the clock signal generation circuit 200 and thereby further reduce the overall power consumption of the input power supply circuit of the present invention.

[0043] Please see Figure 3 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism and multiple power receiving circuits according to the third embodiment of the present invention.

[0044] The third embodiment of the present invention is the same as the first and second embodiments, and will not be repeated herein.

[0045] The input power supply circuit of the present invention is suitable for supplying power to, for example, power to, such as Figure 3 The multiple input currents IL shown are respectively connected to two power receiving circuits PR1 and PR2, for example, a power converter. For ease of explanation, in... Figure 3 Only two power receiving circuits, PR1 and PR2, are shown in the diagram. In practice, more power receiving circuits can be set up. The internal configuration of other power receiving circuits can be the same as that of power receiving circuits PR1 or PR2.

[0046] like Figure 3 As shown, in the third embodiment, the input power supply circuit of the present invention, in addition to including the input switch SWIN, the current detection circuit 100, the clock signal generation circuit 200, the charging circuit 300, and the main control circuit 400, also includes an output capacitor Cbuso. In practice, as... Figure 1 and Figure 2 The input power supply circuit of the present invention shown may also include, for example, Figure 3 The output capacitor Cbuso is shown.

[0047] like Figure 3 As shown, the first terminal of the output capacitor Cbuso is connected to the second terminal of the input switch SWIN, and the second terminal of the output capacitor Cbuso is grounded.

[0048] Multiple power receiving circuits PR1 and PR2 can obtain multiple input currents IL, which are shunted from a total input current ISUM, from the first terminal of the connected output capacitor Cbuso or the second terminal of the input switch SWIN.

[0049] For example, each of the multiple power receiving circuits PR1 and PR2 is a power converter, including a control circuit CTR, a drive circuit DRV, an upper bridge switch HS, and a lower bridge switch LS.

[0050] The main control terminal of the main control circuit 400 of the input power supply circuit of the present invention is connected to a signal input terminal of the control circuit CTR of each of the plurality of power receiving circuits PR1 and PR2. A signal output terminal of the control circuit CTR is connected to a signal input terminal of the drive circuit DRV. The first signal output terminal of the drive circuit DRV is connected to the control terminal of the upper bridge switch HS, and the second signal output terminal of the drive circuit DRV is connected to the control terminal of the lower bridge switch LS.

[0051] In each of the multiple power receiving circuits PR1 and PR2, the first terminal of the upper bridge switch HS serves as a power receiving terminal, obtaining an input current IL from the output voltage VBUSO of the connected input switch SWIN or the first terminal of the output capacitor Cbuso. If necessary, this input current IL can be divided into multiple currents, flowing to the first terminal of the upper bridge switch HS, a power receiving terminal of the control circuit CTR, and another power receiving terminal of the control circuit CTR.

[0052] If each of the multiple power receiving circuits PR1, PR2 is as follows Figure 3 The diagram also includes an input capacitor Cin. Multiple input currents IL supplied by the first terminal of the output capacitor Cbuso of the input power supply circuit of this invention, or the second terminal of the input switch SWIN, can flow to multiple input capacitors Cin of multiple power receiving circuits PR1 and PR2 respectively, to charge the multiple input capacitors Cin. The first terminal of the upper bridge switch HS, a power receiving terminal of the control circuit CTR, and a power receiving terminal of the control circuit CTR can obtain the voltage (i.e., the input voltage VIN) of the first terminal of the connected output capacitor Cbuso, or obtain multiple shunt currents shunted from the input current IL discharging from the output capacitor Cbuso.

[0053] In each of the multiple power receiving circuits PR1 and PR2, the second terminal of the upper bridge switch HS is connected to the first terminal of the lower bridge switch LS. The second terminal of the lower bridge switch LS is grounded. The node between the second terminal of the upper bridge switch HS and the first terminal of the lower bridge switch LS is connected to the first terminal of the inductor L. The second terminal of the inductor L is connected to the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is grounded.

[0054] The main control circuit 400 can be connected to multiple control circuits CTR of multiple power receiving circuits PR1 and PR2 respectively. Based on the frequency of multiple pulses of a main control clock signal CLKCR received from the clock signal generation circuit 200, the main control circuit 400 outputs multiple main control command signals SCT to the multiple control circuits CTR of the multiple power receiving circuits PR1 and PR2 respectively. Each control circuit CTR, according to a main control command signal SCT received from the main control circuit 400, controls or modulates the driving circuit DRV to drive the upper bridge switch HS and the lower bridge switch LS, thereby controlling or modulating an output voltage VOUT at an output node between the second terminal of inductor L and the first terminal of output capacitor Cout.

[0055] Please see Figures 4 to 6 ,in Figure 4 This is a circuit diagram of an input power supply circuit with an input supply frequency control mechanism according to the fourth embodiment of the present invention. Figure 5 and Figure 6The waveform diagrams are of the input power supply circuits with input supply frequency control mechanisms according to the first to fourth embodiments of the present invention.

[0056] like Figures 1 to 3 The current detection circuit 100, clock signal generation circuit 200, charging circuit 300, and main control circuit 400 shown can be the same as those described above. Figure 4 The circuit shown includes a current detection circuit 100, a clock signal generation circuit 200, a charging circuit 300, and a main control circuit 400. The clock signal generation circuit 200 and the charging circuit 300 may be, for example, but are not limited to, such as... Figure 4 The settings shown are in the same package 23.

[0057] like Figure 4 As shown, the clock signal generation circuit 200 may include an oscillation circuit 210 and a clock synchronization circuit 220, and the main control circuit 400 may include a clock synchronization enable circuit 401 and a processing circuit 402.

[0058] like Figure 4 As shown, a signal receiving terminal of the clock synchronization enable circuit 401 can be connected to a signal output terminal of the processing circuit 402. The clock synchronization enable output terminal of the clock synchronization enable circuit 401 is connected to a clock enable terminal of the oscillation circuit 210 and a clock enable terminal of the clock synchronization circuit 220.

[0059] like Figure 4 One detection receiver of the oscillation circuit 210 shown is connected as follows: Figures 1 to 4 The output terminal of the current detection circuit 100 shown.

[0060] like Figure 4 As shown, a clock output terminal of the oscillation circuit 210 is connected to an input terminal of the charging circuit 300 and a clock receiver terminal of the clock synchronization circuit 220. A clock output terminal of the clock synchronization circuit 220 is connected to a clock receiver terminal of the clock synchronization enable circuit 401. A clock output terminal of the clock synchronization enable circuit 401 is connected to a clock receiver terminal of the processing circuit 402.

[0061] like Figure 4 The multiple main control terminals of the processing circuit 402 of the main control circuit 400 shown can be connected to, for example... Figure 2 A signal input terminal of each of the plurality of power receiving circuits PR1 to PRn shown, or a connection thereof, is available. Figure 3 The signal input terminal of a control circuit CTR for each of the multiple power receiving circuits PR1 to PRn shown.

[0062] If needed, the clock synchronization enable circuit 401 can receive analog signals from the oscillation circuit 210, clock synchronization circuit 220 and charging circuit 300 in package 23 and transmit them to the processing circuit 402.

[0063] If needed, such as Figure 4 The processing circuit 402 shown has multiple external data receivers that can be connected to one or more external circuits to output a processing signal based on multiple external data signals VSEL1, VSEL2, PSSEL, SLP, SCL, SDA from these one or more external circuits and analog signals from package 23.

[0064] The clock synchronization enable circuit 401 determines whether to wake up the processing circuit 402 and the charging circuit 300 for synchronization based on a processing signal received from the processing circuit 402. Specifically, the clock synchronization enable circuit 401 determines whether to synchronize the frequency of the operation performed by the processing circuit 402 with the frequency of the charging circuit 300 charging the voltage at the control terminal of the input switch SWIN, thereby setting the level of a clock enable signal ENCK. If necessary, the clock synchronization enable circuit 401 can also output digital signals to the oscillation circuit 210, the clock synchronization circuit 220, and the charging circuit 300 in package 23.

[0065] For example, the operations performed by the processing circuit 402 include setting multiple master control command signals SCT, outputting multiple master control command signals SCT to multiple power receiving circuits PR1 to PRn respectively to control multiple power receiving circuits PR1 to PRn, processing the data of multiple power receiving circuits PR1 to PRn and setting or modulating multiple master control command signals SCT accordingly.

[0066] In non-power-saving / normal mode, the clock synchronization enable circuit 401 determines the synchronization between the wake-up processing circuit 402 and the charging circuit 300, thereby setting the level of a clock enable signal ENCK to be equal to a first level (e.g., a high level). The first level described herein can be a voltage level or a logic level.

[0067] In non-power-saving / normal mode, the oscillation circuit 210 receives a clock enable signal ENCK with a first level (e.g., high level) from the clock synchronization enable circuit 401, thereby setting the frequency of each of the plurality of pulses of the charging clock signal CLK to be maintained at a set frequency.

[0068] For example, when the oscillator circuit 210 receives a clock enable signal ENCK at a first level (e.g., a high level), the oscillator circuit 210 generates an oscillation signal OSC having multiple set waveforms (e.g., multiple triangular wave waveforms). Then, the oscillator circuit 210 will... Figure 5 and Figure 6 The voltages on multiple set waveforms of the oscillation signal OSC shown are respectively related to, for example: Figure 5 and Figure 6 The first set threshold voltage VL shown is compared with the second set threshold voltage VH, and a setting is made accordingly. Figure 5 and Figure 6 The level of a charging clock signal CLK is shown, thus generating multiple pulses of the charging clock signal CLK. At this time, the frequency of each of the multiple pulses of the charging clock signal CLK is used as a set frequency, such as, but not limited to, 1MHz.

[0069] In non-power-saving mode / normal mode, the charging circuit 300 outputs a charging signal CHG to the control terminal of the input switch SWIN based on a set frequency of each of the multiple pulses of a charging clock signal CLK received from the oscillation circuit 210.

[0070] In non-power-saving mode / normal mode, the clock synchronization circuit 220 outputs a master control clock signal CLKCR with a set frequency to the clock synchronization enable circuit 401 based on a set frequency of each of the multiple pulses of a charging clock signal CLK received from the oscillation circuit 210.

[0071] like Figure 5 and Figure 6 As shown, when the clock enable signal ENCK is at a high level, the clock synchronization enable circuit 401 receives a master control clock signal CLKCR from the clock synchronization circuit 220, which has multiple pulses, each of which has a frequency equal to a set frequency, such as 1MHz.

[0072] It is worth noting that in power-saving mode, the clock synchronization enable circuit 401 decides not to wake up or to disable the synchronization between the processing circuit 402 and the charging circuit 300, thereby setting the level of a clock enable signal ENCK to be equal to an initial level (e.g., a low level). The initial level described herein can be a voltage level or a logic level.

[0073] In power-saving mode, the oscillator circuit 210 receives a clock enable signal ENCK at an initial level (e.g., a low level) from the clock synchronization enable circuit 401. In this case, the oscillator circuit 210, based on the signal received from the clock synchronization enable circuit 401... Figures 1 to 4 The current detection circuit 100 shown receives an input current detection signal IAS to set the frequency of multiple pulses of a charging clock signal CLK, and outputs this charging clock signal CLK to the charging circuit 300.

[0074] For example, when the oscillation circuit 210 receives a clock enable signal ENCK at an initial level (e.g., a low level) from the clock synchronization enable circuit 401, the oscillation circuit 210, according to the signal received from the clock synchronization enable circuit 401, performs the following actions: Figures 1 to 4The current detection circuit 100 shown receives an input current detection signal IAS and sets multiple voltage values ​​for multiple modulation waveforms (e.g., multiple triangular wave waveforms) of an oscillation signal OSC. Then, the oscillation circuit 210... Figure 5 and Figure 6 The voltages on multiple modulation waveforms of the oscillating signal OSC shown are respectively related to, as... Figure 5 and Figure 6 The first set threshold voltage VL shown is compared with the second set threshold voltage VH, and a setting is made accordingly. Figure 5 and Figure 6 The level of a charging clock signal CLK is shown, thus generating multiple pulses of the charging clock signal CLK. The frequency of each of the multiple pulses of the charging clock signal CLK is used as a modulation frequency, for example, but not limited to, 200kHz.

[0075] In power-saving mode, the charging circuit 300 outputs a charging signal CHG to the control terminal of the input switch SWIN based on the frequency of multiple pulses of a charging clock signal CLK set according to the input current detection signal IAS. As the current value of the input current detection signal IAS decreases, the oscillation circuit 210 reduces the frequency of multiple pulses of the charging clock signal CLK, for example, but not limited to, from 1MHz to 200kHz. Accordingly, the charging circuit 300 reduces the charging frequency of the voltage at the control terminal of the input switch SWIN, thereby achieving the effect of power saving.

[0076] In other words, the input power supply circuit of the present invention can proportionally or linearly modulate the change in the charging frequency of the voltage at the control terminal of the input switch SWIN based on the change in the total input current ISUM drawn from the second terminal of the input switch SWIN by the multiple power receiving circuits PR1 and PR2.

[0077] It is worth noting that as the total input current ISUM drawn from the second terminal of the input switch SWIN by the multiple power receiving circuits PR1 and PR2 decreases, the charging frequency of the voltage at the control terminal of the input switch SWIN is reduced proportionally or linearly. Thus, while supplying sufficient power to the multiple power receiving circuits PR1 and PR2 for operation, the power supply circuit of this invention effectively saves power.

[0078] In power-saving mode, clock synchronization circuit 220 receives a clock enable signal ENCK with an initial level (e.g., a low level) from clock synchronization enable circuit 401.

[0079] like Figure 5 and Figure 6As shown, when the clock synchronization circuit 220 receives a low-level clock enable signal ENCK, the clock synchronization circuit 220 does not generate any pulse in the master control clock signal CLKCR based on the multiple pulses of the charging clock signal CLK, and does not output a master control clock signal CLKCR to the clock synchronization enable circuit 401, so that the input power supply circuit of the present invention saves more power.

[0080] Please see Figure 7 and Figure 8 ,in Figure 7 This is a circuit diagram of a clock synchronization circuit for an input power supply circuit with an input supply frequency control mechanism according to the fifth embodiment of the present invention. Figure 8 The waveform diagram shows the signal of the clock synchronization circuit of the input power supply circuit with input supply frequency control mechanism according to the fifth embodiment of the present invention.

[0081] like Figure 4 The clock synchronization circuit 220 shown can be the same as that shown. Figure 7 The clock synchronization circuit 220 shown is shown.

[0082] like Figure 7 As shown, the clock synchronization circuit 220 includes a first NOT gate GN1, a first flip-flop FF1, a second flip-flop FF2, an AND gate GA1, and a delay circuit DEY. The AND gate GA1 can practically be replaced with several other types of logic gates. If needed, the clock synchronization circuit 220 may also include a second NOT gate GN2 and a third NOT gate GN3, which can practically be replaced with buffers or other circuit components.

[0083] like Figure 7 The first flip-flop FF1 and the second flip-flop FF2 shown are both D-type flip-flops, but in practice they can be replaced with other types of flip-flops.

[0084] like Figure 7 The input terminals of the first NOT gate GN1 shown are connected as follows: Figure 4 The clock synchronization enable circuit 401 of the main control circuit 400 shown has an enable output terminal to receive a clock enable signal ENCK from the enable output terminal of the clock synchronization enable circuit 401.

[0085] like Figure 7 As shown, the first input terminal D of the first flip-flop FF1 is coupled to a common voltage VDD, or in practice, receives a high logic level "1". The first input terminal D of the second flip-flop FF2 is connected to the output terminal Q of the first flip-flop FF1.

[0086] The second input terminal R of the first flip-flop FF1 and the second input terminal R of the second flip-flop FF2 are connected to the output terminal of the first NOT gate GN1.

[0087] like Figure 7 The input terminal of the delay circuit DEY shown serves as a clock receiver terminal of the clock synchronization circuit 220, and is connected as follows: Figure 4 The clock output terminal of the oscillation circuit 210 shown is used to receive a charging clock signal CLK from the clock output terminal of the oscillation circuit 210.

[0088] like Figure 7 As shown, a clock output terminal of the delay circuit DEY is connected to a clock receiver terminal CK of the first flip-flop FF1.

[0089] like Figure 7 The clock receiver CK of the second flip-flop FF2 shown is connected as follows: Figure 4 The clock output terminal of the oscillation circuit 210 shown is used to receive a charging clock signal CLK from the clock output terminal of the oscillation circuit 210.

[0090] like Figure 7 The first input terminal of the AND gate GA1 shown is connected as follows: Figure 4 The clock output terminal of the oscillation circuit 210 shown is used to receive a charging clock signal CLK from the clock output terminal of the oscillation circuit 210. For example... Figure 7 As shown, the second input of AND gate GA1 is connected to the output Q of the second flip-flop FF2. The output of AND gate GA1 is connected to the input of the second NOT gate GN2. The input of the third NOT gate GN3 is connected to the output of the second NOT gate GN2.

[0091] like Figure 7 The output of the third NOT gate GN3 shown is connected as follows: Figure 4 The clock receiving terminal of the clock synchronization enable circuit 401 of the main control circuit 400 shown.

[0092] like Figure 7 As shown, after receiving a charging clock signal CLK from a clock output terminal of the oscillation circuit 210, the delay circuit DEY outputs multiple pulses of the charging clock signal CLK to a clock receiving terminal CK of the first flip-flop FF1 after a delay time.

[0093] When Figure 4 The clock synchronization enable circuit 401 shown determines the wake-up function. Figure 4 The processing circuit 402 shown is synchronized with the charging circuit 300, as follows: Figure 7 The input of the first NOT gate GN1 shown receives a high-level clock enable signal ENCK from the clock synchronization enable circuit 401.

[0094] It is worth noting that when, Figure 4The clock synchronization enable circuit 401 shown here, in order to save power to the input power supply circuit of the present invention, decides not to synchronize the wake-up processing circuit 402 with the charging circuit 300, such as... Figure 7 The input terminal of the first NOT gate GN1 shown receives a low-level clock enable signal ENCK from the clock synchronization enable circuit 401.

[0095] Next, NOT gate GN1 inverts the received low-level clock enable signal ENCK into a high-level clock enable signal ENCK.

[0096] When the second input terminal R of the first flip-flop FF1 receives a high-level clock enable signal ENCK from the output terminal of the first NOT gate GN1, the first input terminal D of the first flip-flop FF1 receives a high-level common voltage VDD, and the clock receiving terminal CK of the first flip-flop FF1 receives a high-level charging clock signal CLK from the delay circuit DEY, the output terminal Q of the first flip-flop FF1 outputs a high-level first wake-up signal to the first input terminal D of the second flip-flop FF2.

[0097] Next, when the first input terminal D of the second flip-flop FF2 receives a high-level first wake-up signal, the second input terminal R of the second flip-flop FF2 receives a high-level clock enable signal ENCK from the output terminal of the first NOT gate GN1, and the clock receiving terminal CK of the second flip-flop FF2 receives a high-level charging clock signal CLK from the delay circuit DEY, the output terminal Q of the second flip-flop FF2 outputs a high-level second wake-up signal to the second input terminal of the AND gate GA1.

[0098] Next, when the second input terminal of AND gate GA1 receives a high-level second wake-up signal from the output terminal Q of the second flip-flop FF2 and the first input terminal of AND gate GA1 receives a high-level charging clock signal CLK from a clock output terminal of the oscillation circuit 210, AND gate GA1 outputs a high-level master control clock signal CLKCR, which is transmitted to a clock receiving terminal of the clock synchronization enable circuit 401 via the second NOT gate GN2 and the third NOT gate GN3.

[0099] It is worth noting that the delay circuit DEY delays the time by which the charging clock signal CLK is output from the clock receiver CK of the first flip-flop FF1 of the oscillation circuit 210. The result is as follows: Figure 5As shown, after the clock enable signal ENCK transitions from an initial level (e.g., low level) to a first level (e.g., high level) at a certain time point, the clock synchronization circuit 220 generates multiple identical complete pulses in a pulse master clock signal CLKCR based only on the first pulse after the other pulses in a charging clock signal CLK, and outputs this pulse master clock signal CLKCR to a clock receiving terminal of the clock synchronization enable circuit 401. This prevents the generation of pulses with the same characteristics in the pulse master clock signal CLKCR. Figure 8 The first incomplete pulse, indicated by the dashed line, is also called a glitch. The clock synchronization enable circuit 401 can operate normally based on a master clock signal CLKCR, which has multiple complete pulses.

[0100] Please see Figure 9 The waveform diagrams are of the input power supply circuits with input supply frequency control mechanisms according to the first to fifth embodiments of the present invention.

[0101] like Figure 1 , Figure 2 or Figure 3 The input power supply circuit of the present invention shown can receive, for example, power supplies such as power supplies for power supply. Figure 9 The input voltage VBUS shown generates the following: Figure 9 The diagram shows a supply current IVBUSO, a voltage VG, a charging signal CHG, a charging clock signal CLK, and an output voltage VBUSO.

[0102] When the power supply circuit of the present invention continuously receives an input voltage VBUS of a fixed voltage value and a supply current IVBUSO drawn from the voltage VBUSO of the output capacitor Cbuso of the power supply circuit of the present invention by the multiple power receiving circuits PR1 to PRn gradually decreases from 1A to 100mA, the voltage VBUSO of the output capacitor Cbuso gradually increases.

[0103] It is worth noting that when the supply current IVBUSO drawn from the output capacitor Cbuso of the power supply circuit input of the present invention by multiple power receiving circuits PR1 to PRn gradually decreases from 1A to 100mA, the clock signal generation circuit 200 of the power supply circuit input of the present invention reduces the frequency of the pulse of the charging clock signal CLK, i.e. Figure 9 The charging clock signal frequency Fclk (CLK Frequency) is shown. Based on the decrease in the charging clock signal CLK, the charging circuit 300 gradually reduces the frequency of the charging signal CHG supplied to the control terminal of the input switch SWIN. As a result, the voltage VG at the control terminal of the input switch SWIN gradually decreases.

[0104] In other words, when the discharge current IVBUSO drawn from the output capacitor Cbuso of the power supply circuit of the present invention by the multiple power receiving circuits PR1 to PRn (e.g., multiple power converters) of the power supply circuit of the present invention decreases, the power supply circuit of the present invention can reduce the frequency of internal circuit operation to supply power, thereby effectively achieving the effect of saving power.

[0105] In summary, this invention provides an input power supply circuit with an input supply frequency control mechanism. The charging circuit of this invention's input power supply circuit can reduce the charging frequency of the voltage at the control terminal of the input switch as the total input current drawn from the second terminal of the input switch by multiple power receiving circuits (e.g., multiple power converters) decreases. Therefore, the input power supply circuit of this invention only supplies an appropriate amount of power to the multiple power receiving circuits, without supplying excessive power, thus preventing unnecessary power consumption and effectively saving power. Furthermore, if the input power supply circuit of this invention includes a main control circuit, the clock signal generation circuit can stop supplying the main control clock signal to the main control circuit in power-saving mode to save even more power.

[0106] The above-disclosed content is only a preferred and feasible embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. An input power supply circuit with an input supply frequency control mechanism, characterized in that, The input power supply circuit with input supply frequency control mechanism includes: An input switch, the first end of which is coupled to an input voltage, and the second end of which is connected to the power receiving terminal of each of a plurality of power receiving circuits; A current detection circuit, connected to the second terminal of the input switch, is configured to detect a total input current flowing out from the second terminal of the input switch to output an input current detection signal; A clock signal generation circuit, connected to the current detection circuit, is configured to set the frequency of each of a plurality of pulses of a charging clock signal based on the input current detection signal. as well as The charging circuit is connected to the clock signal generation circuit and the control terminal of the input switch, and is configured to output a charging signal to the control terminal of the input switch based on the frequency of each pulse of the charging clock signal.

2. The input power supply circuit with input supply frequency control mechanism according to claim 1, characterized in that, The current detection circuit includes: A current-sensing amplifier, connected to the second terminal of the input switch, is configured to detect the total input current and multiply the total input current by a set gain to output the input current detection signal.

3. The input power supply circuit with input supply frequency control mechanism according to claim 1, characterized in that, The input power supply circuit with input supply frequency control mechanism further includes: An output capacitor, the first end of which is connected to the second end of the input switch, and the second end of which is grounded.

4. The input power supply circuit with input supply frequency control mechanism according to claim 1, characterized in that, The plurality of power receiving circuits include a plurality of power converters.

5. The input power supply circuit with input supply frequency control mechanism according to claim 1, characterized in that, The input power supply circuit with input supply frequency control mechanism further includes: The main control circuit, connected to the clock signal generation circuit, is configured to, in power-saving mode, control the clock signal generation circuit to set the frequency of each pulse of the charging clock signal according to the input current detection signal.

6. The input power supply circuit with input supply frequency control mechanism according to claim 5, characterized in that, The main control circuit is configured to, in normal mode, control the clock signal generation circuit to set the frequency of each pulse of the charging clock signal to be equal to a set frequency.

7. The input power supply circuit with input supply frequency control mechanism according to claim 6, characterized in that, The clock signal generation circuit is configured to output a master control clock signal having the set frequency based on the charging clock signal in the normal mode. The main control circuit is configured to control or process data from multiple power receiving circuits based on a set frequency of the main control clock signal in the normal mode.

8. The input power supply circuit with input supply frequency control mechanism according to claim 7, characterized in that, The main control circuit is configured to instruct the clock signal generation circuit to stop outputting the main control clock signal in the power-saving mode.

9. The input power supply circuit with input supply frequency control mechanism according to claim 5, characterized in that, The clock signal generation circuit includes: An oscillation circuit, connected to the main control circuit, the current detection circuit, and the charging circuit, is configured to, upon receiving a clock enable signal with an initial level from the main control circuit, set the frequency of each pulse of the charging clock signal according to the input current detection signal, and output the charging clock signal to the charging circuit.

10. The input power supply circuit with input supply frequency control mechanism according to claim 9, characterized in that, The clock signal generation circuit further includes: A clock synchronization circuit, connected to the oscillation circuit and the main control circuit, is configured to output a main control clock signal without relying on the charging clock signal when the clock enable signal with the initial level is received.

11. The input power supply circuit with input supply frequency control mechanism according to claim 10, characterized in that, The oscillation circuit is configured to, upon receiving the clock enable signal having a first level from the main control circuit, set the frequency of each pulse of the charging clock signal to remain equal to a set frequency.

12. The input power supply circuit with input supply frequency control mechanism according to claim 11, characterized in that, The clock synchronization circuit is configured to, upon receiving the clock enable signal having the first level from the main control circuit, output the main control clock signal having the set frequency to the main control circuit based on the charging clock signal having the set frequency.

13. The input power supply circuit with input supply frequency control mechanism according to claim 12, characterized in that, The clock synchronization circuit is configured to output the master clock signal based solely on the first of the plurality of pulses following the first of the plurality of pulses in the charging clock signal after a point in time when the clock enable signal transitions from the initial level to the first level.

14. The input power supply circuit with input supply frequency control mechanism according to claim 12, characterized in that, The main control circuit includes: A clock synchronization enable circuit, connected to the clock synchronization circuit and the oscillation circuit, is configured to output the clock enable signal having the first level in normal mode and receive the master control clock signal from the clock synchronization circuit, and output the clock enable signal having the initial level in power-saving mode. as well as A processing circuit, connected to the clock synchronization enable circuit, is configured to control or process data from the plurality of power receiving circuits based on the frequency of each pulse of the master control clock signal obtained from the clock synchronization enable circuit.

15. The input power supply circuit with input supply frequency control mechanism according to claim 14, characterized in that, The processing circuit outputs a processing signal based on multiple external data signals, and the clock synchronization enable circuit sets the level of the clock enable signal based on the processing signal.

16. The input power supply circuit with input supply frequency control mechanism according to claim 10, characterized in that, The clock synchronization circuit includes: The first NOT gate, the input of which is connected to the main control circuit to receive the clock enable signal; A first flip-flop, the first input terminal of the first flip-flop is coupled to a common voltage, and the second input terminal of the first flip-flop is connected to the output terminal of the first NOT gate; A second flip-flop, wherein the first input terminal of the second flip-flop is connected to the output terminal of the first flip-flop, the second input terminal of the second flip-flop is connected to the output terminal of the first NOT gate, and a clock receiving terminal of the second flip-flop is connected to the oscillation circuit to receive the charging clock signal from the oscillation circuit; A delay circuit, connected to the oscillation circuit, is configured to delay the time when the charging clock signal is output from the oscillation circuit to the clock receiver of the first flip-flop; as well as An AND gate is used, the first input of which is connected to the oscillation circuit to receive the charging clock signal, the second input of which is connected to the output of the second flip-flop, and the output of which outputs the master control clock signal to the connected master control circuit.

17. The input power supply circuit with input supply frequency control mechanism according to claim 16, characterized in that, The clock synchronization circuit also includes: A second NOT gate, the input of which is connected to the output of the AND gate; and The third NOT gate has its input connected to the output of the second NOT gate, and its output outputs the master control clock signal to the connected master control circuit.

Images