Two-bridge-arm power quality conditioner and control strategy thereof

Abstract

The application provides a two-bridge-arm power quality regulator and a control strategy thereof, and belongs to the field of power systems; the problem of easy saturation of a power frequency transformer is solved; and the specific control strategy is as follows: the given value of the fundamental wave and harmonic corresponding current on the parallel side is calculated; the fundamental wave actual current and the harmonic actual current on the parallel side are separated, the fundamental wave and harmonic current deviation is calculated, the point position balance correction amount and the grid voltage feedforward compensation amount are superposed, and the parallel side modulation wave is obtained through inverse Park transformation; the modulation wave is processed, and the parallel side power switch driving signal is output; the series side compensation current deviation is calculated, the series side grid voltage feedforward compensation amount is superposed, and the series side modulation wave is obtained through inverse Park transformation; through coordinate transformation and double closed loop PI processing on the grid and load electrical signals, the modulation waves on the parallel side and the series side are adjusted, and the power quality treatment function of voltage disturbance suppression, harmonic reactive power compensation and DC bus stability is realized.

Description

Technical Field

[0001] This invention relates to a two-arm power quality regulator and its control strategy, belonging to the field of power system and automation technology. Background Technology

[0002] The Unified Power Quality Conditioner (UPQC) is a customized power device that can comprehensively solve the voltage and current quality problems of the distribution network. It has the dual functions of series compensation and parallel compensation and can suppress both voltage-type and current-type power quality disturbances at the same time. Therefore, it is recognized as the most complete power quality management solution.

[0003] However, traditional UPQC typically employs a back-to-back full-bridge converter structure, requiring independent bridge arm units for both the series and parallel sides. Each bridge arm contains multiple switching transistors, resulting in high construction and maintenance costs. Furthermore, the increased number of power switching devices increases the complexity of the drive circuitry and the system failure rate, reducing reliability. Additionally, in traditional UPQC, the series side is coupled to the grid via a power frequency isolation transformer. This transformer is bulky and heavy, occupying significant installation space and severely restricting flexible deployment. Moreover, the magnetic saturation characteristics of the power frequency transformer limit the response speed and depth of series compensation. Under severe conditions such as significant grid voltage drops, the transformer may enter the saturation region, leading to reduced compensation effectiveness or even device failure.

[0004] To address the aforementioned issues, a limited number of studies on transformerless UPQCs with two bridge arms have emerged in recent years. However, this research is still in its early stages, and the relevant topologies and control strategies require further optimization and refinement. Therefore, there is an urgent need to propose a novel two-bridge power quality regulator and its control strategy that, while reducing the number of power electronic devices and lowering system costs, completely eliminates the need for series-coupled transformers, achieving comprehensive management of both voltage and current quality with a lightweight and highly flexible structure. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a two-arm power quality regulator and its control strategy, which addresses the problems of traditional UPQC devices being numerous and costly, power frequency transformers being prone to saturation, and the difficulty in comprehensively managing both voltage and current.

[0006] To achieve the above objectives, the present invention provides a control strategy for a two-arm power quality regulator, comprising: Calculate the given values ​​of the fundamental d-axis and q-axis currents on the parallel side; extract the given values ​​of the harmonic d-axis and q-axis currents on the parallel side; perform Park transform on the orthogonal components of the currents in the parallel branch to separate the actual fundamental current and actual harmonic currents on the parallel side; calculate the fundamental current deviation and harmonic current deviation, synthesize the total voltage regulation on the d-axis and q-axis through a PI controller, superimpose the point balance correction and grid voltage feedforward compensation, and obtain the parallel side modulation wave after inverse Park transform; process the parallel side modulation wave and output the drive signal to control the power switch on the parallel side; Calculate the setpoint values ​​of the d-axis and q-axis compensation voltages on the series side; calculate the actual feedback voltages on the d-axis and q-axis on the series side; calculate the difference between the setpoint values ​​and actual feedback values ​​of the corresponding compensation voltages on the d-axis and q-axis on the series side, and obtain the setpoint values ​​of the compensation currents on the d-axis and q-axis on the series side through a PI controller; calculate the actual compensation currents on the d-axis and q-axis on the series side; calculate the difference between the setpoint values ​​and actual feedback values ​​of the corresponding compensation currents on the d-axis and q-axis on the series side, input the difference into the PI controller, and superimpose the feedforward compensation amount of the grid voltage on the series side. After inverse Park transformation, obtain the series-side modulation wave; process the parallel-side modulation wave, and output the drive signal to control the power switch on the series side. Calculate the steady-state deviation of DC bus voltage, reactive power compensation deviation on the parallel side, steady-state deviation of load voltage amplitude, and steady-state deviation of midpoint potential on the parallel and series sides after actual adjustment, and adjust the given values ​​of the corresponding parameters on the parallel and series sides to perform adaptive correction.

[0007] Furthermore, the steps for generating the parallel-side modulated wave are as follows: Obtain the voltage of the upper and lower capacitors on the DC bus. and Calculate the actual total voltage of the DC bus. ; Obtained grid voltage ,generate orthogonal voltage components and ; Obtaining grid phase and the voltage setpoint of the DC bus Calculate DC voltage deviation ;Will Input the PI controller to obtain the setpoint value of the fundamental d-axis current on the parallel side. ; Calculate the fundamental effective value of the grid voltage Based on the given value of reactive power Calculate the given value of the fundamental q-axis current on the parallel side. ; Acquire and process load current This yields the α-axis and β-axis current components of the load current. and ; In phase As a reference, for current and Perform the Park transform to obtain the d-axis and q-axis components of the load current. and ; right and Perform filtering to extract current. and Harmonic components on the d-axis and q-axis and ; right and Inverting the values ​​yields the harmonic d-axis and q-axis current reference values. and ; Obtain and process branch current The orthogonal components of the branch current are obtained. and ; In phase As a reference, for current and Perform the Park transform to obtain the d-axis and q-axis components of the branch current. and .

[0008] Furthermore, the subsequent steps for generating the parallel-side modulated wave are as follows: For current and Perform filtering to extract the fundamental current. and ; In current and In the process, the actual harmonic current is extracted. and ; Calculate the fundamental current deviation between the d-axis and q-axis. and and harmonic current deviation and ; Will and By inputting the fundamental current into the inner-loop PI controller, the voltage regulation of the fundamental voltage on the d-axis and q-axis is obtained. and ; Will and Input the harmonic current to the inner-loop PI controller to obtain the harmonic voltage regulation on the d-axis and q-axis. and ; Will and Add them together, and By adding them together, we obtain the voltage regulation amounts along the d-axis and q-axis. and ; exist and Based on this, the grid voltage feedforward is superimposed to obtain the total regulating voltage along the d-axis and q-axis. and ; In phase Based on, for and Perform an inverse Park transform and superimpose a potential balance correction to obtain the modulated wave on the parallel side. ; Processing the modulated wave on the parallel side The output drives the power switches on the parallel side.

[0009] Furthermore, the calculation steps for the grid voltage feedforward and potential balance correction are as follows: Calculate the grid voltage feedforward on the parallel side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Set the feedforward scaling factor on the parallel side, and adjust the feedforward scaling factor based on the parallel side. and Scaling is performed to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; Calculate the potential balance correction at the midpoint of the DC bus: Calculate the voltage deviation between the upper and lower capacitors on the DC bus. ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. .

[0010] Furthermore, the processing steps for the parallel-side modulated wave are as follows: Based on the parallel side modulation wave Two carrier signals are generated to obtain the upper carrier. With download wave ; Point-by-point comparison of parallel side modulation waves The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave ≥Upcarrier When port A1 outputs a positive level, Q1 and Q2 are turned on, and Q3 and Q4 are turned off; Current carrier <Modulated wave <Upcarrier> When port A1 outputs a zero level, Q1 is disconnected, Q2 and Q3 are turned on, and Q4 is disconnected; When the modulated wave ≤Download Wave When port A1 outputs a negative level, Q1 and Q2 are disconnected, and Q3 and Q4 are turned on. When the state of the parallel-side switch changes, a dead time is inserted to generate a power switch drive signal on the parallel side; Narrow pulse suppression is applied to the power switch drive signal after dead-time processing. Hardware interlocking and state transition mechanisms are set to limit the power switch drive signal generated on the parallel side, thus obtaining the final drive signal of the power switch on the parallel side.

[0011] Furthermore, the steps for generating the series-modulated wave are as follows: Obtained grid voltage ,generate orthogonal voltage components and ; Obtaining grid phase ; in phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Obtain the given value of the load's rated voltage. Calculate the given value of the d-axis compensation voltage on the series side. ; The setpoint of the q-axis compensation voltage on the series side Set to zero; Obtain and process the compensation voltage of the series filter capacitor. The orthogonal components of the series-side compensation voltage are obtained. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback voltages on the d-axis and q-axis of the series side. and ; Calculate the d-axis voltage deviation on the series side Deviation from q-axis voltage ,Will and The input voltage outer loop PI controller obtains the current setpoints for the d-axis and q-axis on the series side. and ; Obtain the compensation current of the series filter inductor ,Will The input to the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis current components of the series-side compensation current, thus obtaining the current. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback currents on the d-axis and q-axis of the series side. and .

[0012] Furthermore, the step of generating the series-modulated wave also includes: Calculate the voltage feedforward on the series side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Set the feedforward scaling factor on the series side, and adjust it according to the feedforward scaling factor on the series side. and Scaling is performed to obtain the grid voltage feedforward components corresponding to the d-axis and q-axis on the series side. and ; Calculate the active current deviation and reactive current deviation on the series side. and ,Will and The input current inner-loop PI controller obtains the series-side regulated voltage corresponding to the d-axis and q-axis. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage corresponding to the d-axis and q-axis of the series side is obtained. and ; right and Perform an inverse Park transform to obtain the modulated wave on the series side. ; Process the modulated wave on the parallel side and output the drive signal to control the power switch on the series side.

[0013] Furthermore, the processing steps for the parallel-side modulated wave are as follows: Based on the series-side modulation wave Generate triangular carrier signal ; Point-by-point comparison of series-modulated waves With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave ≥carrier When port A2 outputs a positive level, Q5 is turned on and Q6 is turned off; When the modulated wave <carrier> When port A2 outputs a negative level, Q5 is off and Q6 is on; When the state of the series-side switch changes, a dead zone is inserted to prevent Q5 and Q6 from conducting simultaneously. Hardware and software constraints are set to prevent Q5 and Q6 from conducting simultaneously. Narrow pulse suppression is applied to the power switch drive signal generated on the series side to obtain the final drive signal of the power switch on the series side.

[0014] Furthermore, the adaptive correction steps are as follows: Calculate the steady-state deviation of DC bus voltage Parallel-side reactive power compensation deviation Load voltage amplitude steady-state deviation Steady-state deviation from midpoint potential ; Adjust the given values ​​of the corresponding parameters on the parallel side: Set correction coefficient Correcting the DC voltage setpoint in the next fundamental cycle : Calculate the temporary value of the DC voltage setpoint ; Obtain the maximum voltage of the DC bus With minimum voltage ,calculate ; Correcting the reactive power setpoint in the next fundamental cycle : Calculate the temporary value of the reactive power setpoint ; The rated reactive power of the acquisition device ,calculate ; Without modifying the setpoint value of the DC bus midpoint potential, Input the value into the PI controller that calculates the potential balance correction at the midpoint of the DC bus. Adjust the given values ​​of the corresponding parameters on the series side: Correcting the load rated voltage setpoint in the next fundamental cycle : Calculate the temporary value of the load rated voltage setpoint ; Obtain the maximum value of the load's rated voltage. and minimum value ,calculate .

[0015] A two-arm power quality conditioner includes: Parallel side arm and series side arm; The parallel bridge arm includes: power switches Q1, Q2, Q3, Q4, and clamping diode D. a1 With D a2 Parallel filter inductor L f1 The parallel-connected bridge arm output port A1 shares the same DC bus capacitor C. Bus1 With C Bus2 ; Capacitor C Bus1 The upper end is connected to the DC positive bus, and the capacitor C Bus2 The lower end is connected to the DC negative bus; capacitor C Bus1 The lower end is connected to capacitor C Bus2 Connect the upper ends and bring out the DC midpoint O; Power switches Q1, Q2, Q3, and Q4 are connected in series from top to bottom, with the collector of Q1 connected to capacitor C. Bus1 At the top, the emitter of Q2 is connected to the output port A1 of the parallel side bridge arm, and the emitter of Q4 is connected to capacitor C. Bus2 lower end; clamp tube D a1 Anode terminals A1, D a1 The cathode is connected to the DC midpoint O; clamp tube D a2 Cathode terminals A1, D a2 The anode is connected to the DC midpoint O; Inductor L f1 Connect one end to port A1 and the other end to the power grid neutral wire; The series-connected bridge arm includes: power switches Q5 and Q6, and a series filter inductor L. f2 Series compensation capacitor C f1 The output port A2 of the series-connected bridge arm shares the DC bus capacitor C. Bus1 With C Bus2 Load R L ; Power switches Q5 and Q6 are connected in series, and the collector of Q5 is connected to capacitor C.Bus1 At the top, the collector of Q6 is led out to the output port A2 of the series-side bridge arm, and the emitter of Q6 is connected to capacitor C. Bus2 lower end; Series filter inductor L f2 Series compensation capacitor C f1 They are connected in series to form an LC low-pass filter circuit and connected to the output port A2 of the series side bridge arm. Series compensation capacitor C f1 Keep away from series filter inductor L f2 One end is connected to the power grid and the load R L The phase line of the power grid between them, and the load R L It is connected in parallel between the phase line and the neutral line of the power grid.

[0016] Compared with the prior art, the beneficial effects of the present invention are: Fewer topological components reduce hardware costs and device size. The control strategy provided by this invention is adaptable to UPQC topologies with two bridge arms without power frequency transformers. It only uses one side of the NPC three-level parallel bridge arm and one side of the two-level series half-bridge arm, eliminating the power frequency coupling transformer that must be configured on the series side of traditional UPQC. The control algorithm is deeply matched with the hardware topology, eliminating the need for additional compensation logic for transformer magnetic saturation and inrush current, and eliminating the need to add a voltage conversion module for the transformer. The overall size and weight of the device are significantly reduced, making it suitable for mass production in factories to reduce manufacturing costs, and also suitable for on-site installation conditions in small cabinets in distribution stations, thus having better engineering promotion value.

[0017] Independent switching control on both the parallel and series sides, taking into account both harmonic mitigation and voltage compensation performance: This invention supports the use of different switching frequencies on the parallel and series sides. Through two independent modulation processes provided in steps S1 and S2, modulation waves are generated on both sides according to the differences in functional requirements: the parallel side is mainly responsible for DC bus voltage regulation, load harmonic mitigation, and reactive power compensation, while the series side is mainly responsible for load voltage sag, swell, and distortion suppression, focusing on fundamental voltage amplitude and phase control. The two modulation processes share the same SOGI-PLL phase-locked phase reference, ensuring phase coordination of the compensation vectors on both sides and preventing phase mismatch due to different switching frequencies.

[0018] The device incorporates a self-testing design to enhance its adaptability to complex power grid and load conditions. In addition to the traditional inner loop regulation, this invention adds online detection of modulation effect and adaptive correction of given value in step S3. Using the fundamental frequency of the power grid as the execution cycle, step S3 reuses the SOGI orthogonal decomposition and Park transformation results already completed in steps S1 and S2. It does not require repeated large-scale coordinate calculations and will not interfere with the dynamic response of the current and voltage inner loop. While retaining the original dual closed-loop regulation function, it corrects the input given of steps S1 and S2 in the next cycle by real-time detection of the steady-state deviation of DC bus, reactive power, and load voltage, thereby realizing closed-loop verification of modulation effect. Attached Figure Description

[0019] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the two-arm power quality regulator of the present invention; Figure 2 This is a schematic diagram of the equivalent circuit on the parallel side of the present invention; Figure 3 This is a schematic diagram of the equivalent circuit on the series side of the present invention; Figure 4 This is a schematic diagram of the control strategy for the two-arm power quality regulator of the present invention. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Example 1

[0022] Please see Figure 1 A two-arm power quality regulator includes: a parallel side arm and a series side arm; Parallel side bridge arm: Power switches Q1, Q2, Q3, Q4, clamping transistor D a1 With D a2 Parallel filter inductor L f1 The parallel-connected bridge arm output port A1 shares the same DC bus capacitor C. Bus1 (Upper capacitor) and C Bus2 (Lower capacitor), DC midpoint O; U g L represents the power grid, and N represents the neutral wire. Capacitor C Bus1 The upper end is connected to the DC positive bus, and the capacitor C Bus2 The lower end is connected to the DC negative bus; capacitor C Bus1 The lower end is connected to capacitor C Bus2 Connect the upper ends and bring out the DC midpoint O; Power switches Q1, Q2, Q3, and Q4 are connected in series from top to bottom: Q1 collector capacitor C Bus1 At the top (corresponding to the DC positive bus), the emitter of Q1 is connected to the collector of Q2; The emitter of Q2 leads to the output port A1 of the parallel side bridge arm; The collector of Q3 is connected to the output port A1, and the emitter of Q3 is connected to the collector of Q4. Q4 emitter capacitor C Bus2 Lower end (corresponding to DC negative bus); clamp tube D a1 Anode terminals A1, D a1 The cathode is connected to the DC midpoint O; clamp tube D a2 Cathode terminals A1, D a2 The anode is connected to the DC midpoint O; Inductor L f1 Connect one end to port A1 and the other end to the power grid neutral wire; The parallel bridge arm can output three levels: positive, zero, and negative. Q1 and Q2, and Q3 and Q4 in the parallel bridge arm cannot be turned on at the same time. Output positive level: Q1 and Q2 are on, Q3 and Q4 are off; The current path is: DC midpoint O → Q1 → Q2 → port A1 → inductor L f1 →Power grid; When the current reverses, the current path is: mains → inductor L f1 →Port A1→Q2→Q1→DC Midpoint O; Output zero level: Q2 and Q3 are on, Q1 and Q4 are off; Current flows out of port A1: Port A1 → clamping transistor D a1 →DC midpoint O; Current flows into port A1: DC midpoint O → clamping transistor D a2 →Port A1; Output negative level: Q3 and Q4 are turned on, Q1 and Q2 are turned off; The current path is: DC midpoint O → capacitor C Bus2 Negative terminal → Q4 → Q3 → Port A1 → Inductor L f1 →Power grid; When the current reverses, the current path is: mains → inductor L f1 →Port A1→Q3→Q4→Capacitor C Bus2 negative electrode; Please see Figure 2 The equivalent circuit diagram on the parallel side also includes: grid voltage V s Load voltage V LGrid current i s Load current i L Compensation current i apf ; Figure 2 The electrical parameters in the middle satisfy: i s =i L +i apf ; Serial side arms: Power switches Q5 and Q6, series filter inductor L f2 Series compensation capacitor C f1 The output port A2 of the series-connected bridge arm shares the DC bus capacitor C. Bus1 (Upper capacitor) and C Bus2 (Lower capacitor), load R L ; Power switches Q5 and Q6 are connected in series: Q5 collector capacitor C Bus1 At the top (corresponding to the DC positive bus), the emitter of Q5 is connected to the collector of Q6; The collector of Q6 leads out to the output port A2 of the series-side bridge arm; Q6 emitter capacitor C Bus2 Lower end (corresponding to DC negative bus); Series filter inductor L f2 Series compensation capacitor C f1 They are connected in series to form an LC low-pass filter circuit and connected to the output port A2 of the series side bridge arm. Series compensation capacitor C f1 Keep away from series filter inductor L f2 One end is connected to the power grid and the load R L The phase line of the power grid between them, and the load R L Connected in parallel between the phase line and the neutral line of the power grid; The parallel bridge arm can output both positive and negative voltage levels; Output positive level: Q5 is on, Q6 is off; The current path is: capacitor C Bus1 Positive electrode → Capacitor C Bus1 Negative terminal → Q5 → Port A2 → Inductor L f2 →Capacitor C f1 →Load R L →Power grid; When the current reverses, the current path is: power grid → load R L →Capacitor C f1 →Inductance L f2 →Port A2→Q5→Capacitor C Bus1 Negative electrode → Capacitor C Bus1 positive electrode; Output negative level: Q5 is off, Q6 is on; The current path is: power grid → load R L →Capacitor C f1 →Inductance L f2 →Port A2→Q6→Capacitor C Bus1 Negative electrode → Capacitor C Bus1 positive electrode; When the current reverses, the current path is: capacitor C Bus1 Positive electrode → Capacitor C Bus1 Negative terminal → Q6 → Port A2 → Inductor L f2 →Capacitor C f1 →Load R L →Power grid; Please see Figure 3 The equivalent circuit diagram on the series side also includes: Grid voltage V s Series compensation voltage V c Load voltage V L , Figure 3 The electrical parameters in V satisfy: L =V s +V c。

[0023] Example 2

[0024] Please see Figure 4 A control strategy for a two-arm power quality regulator includes: Step S1: Generate parallel-side modulated wave u A1（ref） This enables DC bus voltage regulation and current quality control on the parallel side. Obtain the DC bus voltage setpoint and reactive power compensation setpoint; obtain the voltages of the upper and lower capacitors on the DC bus, and calculate the actual total voltage of the DC bus; calculate the DC bus voltage deviation ΔU. dc , will ΔU dc Input the DC outer loop PI controller and output the fundamental d-axis current setpoint on the parallel side; calculate the fundamental q-axis current setpoint based on the reactive power compensation setpoint; extract and invert the harmonics from the load current to obtain the harmonic d-axis and q-axis current setpoints; Obtain the branch current of the parallel-side filter inductor, process the branch current using a second-order SOGI generalized integrator, and obtain the quadrature current component i. α（a） with i β（a） ; Obtain the grid voltage U Grad The phase θ of grid 1 is obtained through a second-order generalized integrator (SOGI) and a phase-locked loop (PLL). Grad ; With grid voltage phase θ Grad Based on i α（a）with i β（a） Perform a Park transform to obtain the actual d-axis and q-axis currents of the inner current loop on the parallel side. Use a low-pass filter to separate the fundamental current i from the actual d-axis and q-axis currents of the inner current loop on the parallel side. d（sh） with i q（sh） Harmonic actual current i d（hsh） with i q（hsh） ; Calculate the fundamental current deviation Δi d（sh） With Δi q（sh） and harmonic current deviation Δi d（hsh） With Δi q（hsh） ; Δi d（sh） , Δi q（sh） , Δi d（hsh） , Δi q（hsh） The signal is fed into the inner-loop PI controller, where the total voltage regulation of the d-axis and q-axis is synthesized and then superimposed with the "point balance correction" and "grid voltage feedforward compensation". After inverse Park transform, the parallel-side modulated wave u is obtained. A1（ref） ; The parallel-side modulation wave is processed using SPWM modulation. A1（ref） It outputs drive signals to control the parallel-side power switches Q1, Q2, Q3, and Q4, and adjusts the amplitude and phase of the parallel-side output compensation current, thereby achieving multiple control objectives such as DC bus voltage regulation, load reactive power compensation, and load harmonic control. The specific steps of step S1 are as follows: Obtain the voltage of the upper and lower capacitors on the DC bus. and Calculate the actual total voltage of the DC bus. : ; Obtained grid voltage ,Will Inputting the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis voltage components, yielding... and ; Will and Inputting a PLL (phase-locked loop) yields the grid phase. ; Generate modulated wave at parallel port ; Obtain the DC bus voltage setpoint Calculate DC voltage deviation (Right now and The difference );Will The input voltage outer loop PI controller obtains the setpoint value of the fundamental d-axis current (active current) on the parallel side. ; Based on the orthogonal α-axis and β-axis voltage components of the power grid and Calculate the fundamental effective value of the grid voltage. : ; Obtain the given value of reactive power. Calculate the given value of the fundamental q-axis current (reactive current) on the parallel side. : ; Get load current Using the SOGI second-order generalized integrator for processing This yields the α-axis and β-axis current components of the load current, denoted as current. and ; In phase As a reference, for current and Performing the Park transform yields the d-axis and q-axis components of the load current, denoted as current. and ; ; ; Use a low-pass filter to filter the current. and Perform filtering to extract current. and fundamental component of and ; In current and In, subtract the fundamental component and The d-axis and q-axis harmonic components of the load current are obtained. and ; right and Inverting the values ​​yields the harmonic d-axis and q-axis current reference values. and ; Obtain the parallel side filter inductor L f1 Branch current Using the SOGI second-order generalized integrator for processing The orthogonal components of the branch current are obtained. and ; In phase As a reference, for current and Performing the Park transform yields the d-axis and q-axis components of the branch current, denoted as current. and ; ; ; Use a low-pass filter to filter the current. and Perform filtering to extract current. and fundamental component of and ,Will and As the fundamental frequency actual current and ; In current and In, subtract the fundamental component and The d-axis and q-axis harmonic components of the branch current are obtained. and ,Will and As harmonic actual current and ; Calculate the grid voltage feedforward on the parallel side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; ; ; Set the feedforward scaling factor on the parallel side, and adjust the feedforward scaling factor based on the parallel side. and Scaling is performed to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; Calculate the potential balance correction at the midpoint of the DC bus: Calculate the voltage deviation between the upper and lower capacitors on the DC bus. : ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. (Voltage); Calculate the fundamental current deviation between the d-axis and q-axis. and and harmonic current deviation and ; ; ; ; ; Will and By inputting the fundamental current into the inner-loop PI controller, the voltage regulation of the fundamental voltage on the d-axis and q-axis is obtained. and ; Will and Input the harmonic current to the inner-loop PI controller to obtain the harmonic voltage regulation on the d-axis and q-axis. and ; Will and Add them together, and By adding them together, we obtain the voltage regulation amounts along the d-axis and q-axis. and ; exist and Based on this, superimposed grid voltage feedforward and The total regulating voltage of the d-axis and q-axis is obtained. and ; ; ; In phase Based on, for and Perform an inverse Park transformation to obtain the control voltages on the parallel side along the α and β axes. and ; ; ; exist Above, superimposed potential balance correction amount The modulated wave on the parallel side is obtained. ; ; Based on the parallel side modulation wave Two high-frequency triangular carrier signals with the same frequency and amplitude are generated to obtain the upper carrier. With download wave ; upcarrier The amplitude range is This corresponds to the modulation between zero level and positive level; Download Wave The amplitude range is This corresponds to the modulation between negative and zero levels; Point-by-point comparison of parallel side modulation waves The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave Instantaneous value ≥ upcarrier The instantaneous value of Q1 and Q2 is turned on, while Q3 and Q4 are turned off. Current carrier Instantaneous value < modulated wave Instantaneous value < upcarrier The instantaneous value of Q1 indicates that the output of port A1 on the parallel side is zero, Q1 is disconnected, Q2 and Q3 are connected, and Q4 is disconnected. When the modulated wave Instantaneous value ≤ Download wave The instantaneous value of Q1 indicates that port A1 on the parallel side outputs a negative level, Q1 and Q2 are disconnected, and Q3 and Q4 are turned on. When the state of the parallel-side switch changes, a dead time (usually 2-5μs) is inserted to ensure that the next switch is turned on only after the previous switch is completely turned off; and a power switch drive signal is generated on the parallel side. Narrow pulse suppression: Real-time detection of the power switch drive signal after dead-time processing. If the conduction time of a certain pulse in the drive signal is less than the minimum turn-on time of the power switch, the pulse is blocked, and the power switch corresponding to the pulse is forced to remain off, so as to avoid overheating damage to the device due to incomplete turn-on. Set up hardware interlocking and state transition mechanisms to limit the power switch drive signals generated on the parallel side, and obtain the final drive signals of the power switch on the parallel side. Hardware interlocking mechanism: Q1 and Q4 cannot be high at the same time; to avoid Q1 and Q4 being turned on at the same time, which would cause a direct short circuit between the positive and negative terminals of the DC bus; State transition mechanism: The bridge arm level on the forced parallel side can only transition in the order of "positive level → zero level → negative level" or "negative level → zero level → positive level", and direct transition between positive and negative levels is prohibited, ensuring that the switching process always passes through the zero level transition, reducing switching stress and impact.

[0025] Step S2: Generate the series-modulated wave u A2（ref）This enables voltage quality management and control on the series side; Obtain the given value U of the load's rated voltage. L（ref） Obtain the series-side filter inductance L f2 Branch current i （ser） Series filter capacitor C f1 Voltage U at both ends c（ser） ; Obtain grid-side voltage U Grad The SOGI second-order generalized integrator and PLL phase-locked loop are used to extract the grid phase θ. Grad And extract the d-axis grid voltage component; (Source: step S1) Calculate the voltage outer loop deviation: Set the rated load voltage value U L（ref） The difference between the voltage and the d-axis component of the grid voltage is used to obtain the setpoint U of the d-axis compensation voltage on the series side. d（ser）（ref） Set the series-side q-axis compensation voltage setpoint U q（ser）（ref） ; For the series filter capacitor voltage Uc （ser） Perform the Park transformation to obtain the actual feedback voltage U on the d-axis and q-axis of the series side. d（ser） with U q（ser） ; For U d（ser）（ref） with U d（ser） , and U q（ser）（ref） with U q（ser） The difference is calculated by the input voltage outer loop PI controller, which outputs the series-connected d-axis and q-axis current setpoints i. d（ser）（ref） with i q（ser）（ref） ; Obtain the series-side filter inductance L f2 Actual branch current i （ser） Using the SOGI second-order generalized integrator to process i （ser） The orthogonal components of the current i are obtained. α（ser） with i β（ser） ; With grid voltage phase θ Grad Based on i α（ser） with i β（ser） Performing the Park transformation yields the actual feedback current i along the d-axis and q-axis of the inner current loop on the series side. d（ser） with i q（ser） ; Calculate i d（ser）（ref） with i d（ser） , and i q（ser）（ref） with i q（ser） The current deviation is input to the inner-loop PI controller and superimposed with the "series-side grid voltage feedforward compensation amount". After inverse Park transform, the series-side modulated wave u is obtained. A2（ref） ; The process of obtaining the voltage feedforward of the series-connected grid: Set the feedforward proportional coefficient on the series side (distinct from the feedforward proportional coefficient for "parallel side grid voltage feedforward"); obtain the grid-side voltage U. Grad The SOGI second-order generalized integrator is used to process the grid voltage U. Grad The voltage components U along the α and β axes are obtained. Grad（α） with U Grad（β） ; with grid voltage phase θ Grad Based on U Grad（α） with U Grad（β） Perform Park transform to obtain the d-axis and q-axis voltage feedforward components on the series side.

[0026] It should be noted that although the signal extraction and signal processing procedures for "series-side grid voltage feedforward" and "parallel-side grid voltage feedforward" are the same, the superposition position of the two feedforwards, the closed-loop object they serve, and the control objectives are different. Therefore, they are not the same feedforward.

[0027] The series-side modulation wave is processed using SPWM modulation. A2（ref） The output controls the drive signals for the series-connected power switches Q5 and Q6, and adjusts the series filter capacitor C. f1 By adjusting the amplitude and phase of the corresponding compensation voltage, multiple control objectives can be achieved, including grid voltage sag compensation, voltage rise suppression, voltage distortion control, and load-side voltage stabilization.

[0028] The specific steps of step S2 are as follows: Obtained grid voltage ,Will Inputting the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis voltage components, yielding... and ; Will and Inputting a PLL (phase-locked loop) yields the grid phase. ; In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Obtain the given value of the load's rated voltage. Calculate the given value of the d-axis compensation voltage on the series side. ; ; The setpoint of the q-axis compensation voltage on the series side Set to zero; It should be noted that the design goal of the series side of this invention is to only correct the load voltage amplitude without changing the phase relationship between the load voltage and the power grid. Therefore, this invention directly sets the given value of the q-axis compensation voltage on the series side to zero. Obtain the compensation voltage of the series filter capacitor Using the SOGI second-order generalized integrator for processing The orthogonal components of the series-side compensation voltage are obtained. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback voltages on the d-axis and q-axis of the series side. and ; ; ; Calculate the d-axis voltage deviation on the series side Deviation from q-axis voltage ,Will and The input voltage outer loop PI controller obtains the current setpoints for the d-axis and q-axis on the series side. and ; Obtain the compensation current of the series filter inductor ,Will The input to the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis current components of the series-side compensation current, thus obtaining the current. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback currents on the d-axis and q-axis of the series side. and ; ; ; Calculate the voltage feedforward on the series side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Set the feedforward scaling factor on the series side, and adjust it according to the feedforward scaling factor on the series side. and Scaling is performed to obtain the grid voltage feedforward components corresponding to the d-axis and q-axis on the series side. and ; calculate and as well as and The difference between the active current deviation and the reactive current deviation on the series side is obtained. and ,Will and The input current inner-loop PI controller obtains the series-side regulated voltage corresponding to the d-axis and q-axis. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage corresponding to the d-axis and q-axis of the series side is obtained. and ; ; ; right and Performing an inverse Park transform yields the control voltages on the series side along the α and β axes. and ; ; ; Will Modulated wave as the series side ; Based on the series-side modulation wave A high-frequency triangular carrier signal with the same frequency and amplitude (the frequency of this carrier signal is higher than the fundamental frequency of the power grid) is generated to obtain the carrier wave. carrier The amplitude range is ; Point-by-point comparison of cascaded side modulated waves With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave Instantaneous value ≥ carrier The instantaneous value of Q5 indicates that the output port A2 on the series side outputs a positive level, Q5 is turned on, and Q6 is turned off. When the modulated wave Instantaneous value < carrier The instantaneous value of Q5 indicates that the output port A2 on the series side outputs a negative level, Q5 is off, and Q6 is on. When the state of the series-side switch changes, a dead time is inserted (this dead time is consistent with the dead time set in step S1) to prevent Q5 and Q6 from being turned on at the same time. Hardware and software constraints are set to prevent Q5 and Q6 from conducting simultaneously. Narrow pulse suppression is applied to the power switch drive signal generated on the series side to obtain the final drive signal of the power switch on the series side.

[0029] Step S3: Calculate the steady-state deviation of DC bus voltage, reactive power compensation deviation of parallel side, steady-state deviation of load voltage amplitude and steady-state deviation of midpoint potential after actual adjustment on the parallel side and series side, and adjust the given values ​​of the corresponding parameters on the parallel side and series side to achieve adaptive correction of modulation effect. Calculate the steady-state deviation of DC bus voltage : ; in, This represents the given value of the DC bus voltage. This represents the average value of the DC bus voltage during the fundamental period; Calculate the reactive power compensation deviation on the parallel side : ; in, This represents a given value for reactive power. This represents the average measured reactive power of the power grid during the fundamental period; Calculate the steady-state deviation of the load voltage amplitude : ; in, This represents the given value of the load voltage. This represents the fundamental effective value of the load voltage; Calculate the steady-state deviation of the midpoint potential : ; in, This represents the average voltage across the upper capacitor during the fundamental frequency period. This represents the average voltage across the lower capacitor during the fundamental frequency period; Adjust the given values ​​of the corresponding parameters on the parallel side: Set correction coefficient Correcting the DC voltage setpoint in the next fundamental cycle : Calculate the temporary value of the DC voltage setpoint : ; Obtain the maximum voltage of the DC bus With minimum voltage ,calculate : ; Where Lim represents the restriction function; function The meaning is: like ,but The value is ; like ,but The value is ; like ,but The value is ; Correcting the reactive power setpoint in the next fundamental cycle : Calculate the temporary value of the reactive power setpoint : ; The rated reactive power of the acquisition device (i.e., the "two-arm power quality regulator" of the present invention) ,calculate : ; Without modifying the setpoint value of the DC bus midpoint potential, Input (in step S1) into the PI controller that calculates the potential balance correction at the midpoint of the DC bus; Adjust the given values ​​of the corresponding parameters on the series side: Correcting the load rated voltage setpoint in the next fundamental cycle : Calculate the temporary value of the load rated voltage setpoint : ; Obtain the maximum value of the load's rated voltage. and minimum value ,calculate : .

[0030] Compared to the problems described in the background art, this invention uses a two-arm transformerless topology to replace the traditional back-to-back full-bridge UPQC hardware architecture. One side uses an NPC three-level bridge arm as a parallel compensation unit, and the other side uses a two-level half-bridge as a series compensation unit. It eliminates the bulky and heavy power frequency series coupling transformer, and relies on series filter capacitors to achieve voltage coupling and DC isolation. It eliminates the hardware and compensation logic related to the transformer excitation circuit, reduces the number of power switches, drive circuits and magnetic devices, and effectively alleviates the problems of traditional UPQC such as a large number of devices, high overall cost, large size and weight, easy magnetic saturation of power frequency transformers and compensation failure under severe voltage drop conditions. It also reduces the manufacturing, transportation and cabinet installation costs of the device.

[0031] Furthermore, this invention utilizes a second-order generalized integrator (SOGI) to construct virtual orthogonal components, achieving orthogonal decomposition and phase-locked loop (PLL) of voltage and current signals. The parallel and series sides employ dq dual-closed-loop PI control architectures, combined with grid voltage feedforward and midpoint potential balance control, to comprehensively manage DC bus voltage stabilization, load harmonic suppression, reactive power compensation, and disturbances such as grid voltage dips, swells, and distortions. This invention adds a slow-loop step S3, using the grid fundamental cycle as the execution period to achieve online modulation effect detection and upper-level adaptive correction without interfering with the high-speed dynamic response of the inner loop. It also introduces inter-bridge collaborative control logic to handle active and reactive power coupling disturbances caused by the shared DC bus between parallel and series bridge arms. Simultaneously, it supports differentiated switching frequency configurations for both bridge arms, with high-frequency operation on the parallel side ensuring harmonic mitigation effects, and a lower switching frequency on the series side to reduce switching losses. The entire control architecture is hierarchical and highly modular, ensuring both steady-state compensation accuracy and dynamic disturbance rejection capabilities under complex conditions such as load abrupt changes and severe grid disturbances.

[0032] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to specific implementation methods. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The present invention is limited only to the technical solutions and their full scope and equivalents.

Claims

1. A control strategy for a two-arm power quality regulator, characterized in that, Control strategies include: Calculate the given values ​​of the fundamental d-axis and q-axis currents on the parallel side; extract the given values ​​of the harmonic d-axis and q-axis currents on the parallel side; perform Park transform on the orthogonal components of the currents in the parallel branch to separate the actual fundamental current and actual harmonic currents on the parallel side; calculate the fundamental current deviation and harmonic current deviation, synthesize the total voltage regulation on the d-axis and q-axis through a PI controller, superimpose the point balance correction and grid voltage feedforward compensation, and obtain the parallel side modulation wave after inverse Park transform; process the parallel side modulation wave and output the drive signal to control the power switch on the parallel side; Calculate the setpoint values ​​of the d-axis and q-axis compensation voltages on the series side; calculate the actual feedback voltages on the d-axis and q-axis on the series side; calculate the difference between the setpoint values ​​and actual feedback values ​​of the corresponding compensation voltages on the d-axis and q-axis on the series side, and obtain the setpoint values ​​of the compensation currents on the d-axis and q-axis on the series side through a PI controller; calculate the actual compensation currents on the d-axis and q-axis on the series side; calculate the difference between the setpoint values ​​and actual feedback values ​​of the corresponding compensation currents on the d-axis and q-axis on the series side, input the difference into the PI controller, and superimpose the feedforward compensation amount of the grid voltage on the series side. After inverse Park transformation, obtain the series-side modulation wave; process the parallel-side modulation wave, and output the drive signal to control the power switch on the series side. Calculate the steady-state deviation of DC bus voltage, reactive power compensation deviation on the parallel side, steady-state deviation of load voltage amplitude, and steady-state deviation of midpoint potential on the parallel and series sides after actual adjustment, and adjust the given values ​​of the corresponding parameters on the parallel and series sides to perform adaptive correction.

2. The control strategy for a two-arm power quality regulator according to claim 1, characterized in that, The steps for generating the parallel-side modulated wave are as follows: Obtain the voltage of the upper and lower capacitors on the DC bus. and Calculate the actual total voltage of the DC bus. ; Obtained grid voltage ,generate orthogonal voltage components and ; Obtaining grid phase and the voltage setpoint of the DC bus Calculate DC voltage deviation ;Will Input the PI controller to obtain the setpoint value of the fundamental d-axis current on the parallel side. ; Calculate the fundamental effective value of the grid voltage Based on the given value of reactive power Calculate the given value of the fundamental q-axis current on the parallel side. ; Acquire and process load current This yields the α-axis and β-axis current components of the load current. and ; In phase As a reference, for current and Perform the Park transform to obtain the d-axis and q-axis components of the load current. and ; right and Perform filtering to extract current. and Harmonic components on the d-axis and q-axis and ; right and Inverting the values ​​yields the harmonic d-axis and q-axis current reference values. and ; Obtain and process branch current The orthogonal components of the branch current are obtained. and ; In phase As a reference, for current and Perform the Park transform to obtain the d-axis and q-axis components of the branch current. and .

3. The control strategy for a two-arm power quality regulator according to claim 2, characterized in that, The subsequent steps for generating the parallel-side modulated wave are as follows: For current and Perform filtering to extract the fundamental current. and ; In current and In the process, the actual harmonic current is extracted. and ; Calculate the fundamental current deviation between the d-axis and q-axis. and and harmonic current deviation and ; Will and By inputting the fundamental current into the inner-loop PI controller, the voltage regulation of the fundamental voltage on the d-axis and q-axis is obtained. and ; Will and Input the harmonic current to the inner-loop PI controller to obtain the harmonic voltage regulation on the d-axis and q-axis. and ; Will and Add them together, and By adding them together, we obtain the voltage regulation amounts along the d-axis and q-axis. and ; exist and Based on this, the grid voltage feedforward is superimposed to obtain the total regulating voltage along the d-axis and q-axis. and ; In phase Based on, for and Perform an inverse Park transform and superimpose a potential balance correction to obtain the modulated wave on the parallel side. ; Processing the modulated wave on the parallel side The output drives the power switches on the parallel side.

4. The control strategy for a two-arm power quality regulator according to claim 2, characterized in that, The calculation steps for grid voltage feedforward and potential balance correction are as follows: Calculate the grid voltage feedforward on the parallel side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Set the feedforward scaling factor on the parallel side, and adjust the feedforward scaling factor based on the parallel side. and Scaling is performed to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; Calculate the potential balance correction at the midpoint of the DC bus: Calculate the voltage deviation between the upper and lower capacitors on the DC bus. ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. .

5. The control strategy for a two-arm power quality regulator according to claim 4, characterized in that, The processing steps for the parallel-side modulated wave are as follows: Based on the parallel side modulation wave Two carrier signals are generated to obtain the upper carrier. With download wave ; Point-by-point comparison of parallel side modulation waves The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave ≥Upcarrier When port A1 outputs a positive level, Q1 and Q2 are turned on, and Q3 and Q4 are turned off; Current carrier <Modulated wave <Upcarrier> When port A1 outputs a zero level, Q1 is disconnected, Q2 and Q3 are turned on, and Q4 is disconnected; When the modulated wave ≤Download Wave When port A1 outputs a negative level, Q1 and Q2 are disconnected, and Q3 and Q4 are turned on. When the state of the parallel-side switch changes, a dead time is inserted to generate a power switch drive signal on the parallel side; Narrow pulse suppression is applied to the power switch drive signal after dead-time processing. Hardware interlocking and state transition mechanisms are set to limit the power switch drive signal generated on the parallel side, thus obtaining the final drive signal of the power switch on the parallel side.

6. The control strategy for a two-arm power quality regulator according to claim 1, characterized in that, The steps for generating the series-modulated wave are as follows: Obtained grid voltage ,generate orthogonal voltage components and ; Obtaining grid phase ; in phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Obtain the given value of the load's rated voltage. Calculate the given value of the d-axis compensation voltage on the series side. ; The setpoint of the q-axis compensation voltage on the series side Set to zero; Obtain and process the compensation voltage of the series filter capacitor. The orthogonal components of the series-side compensation voltage are obtained. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback voltages on the d-axis and q-axis of the series side. and ; Calculate the d-axis voltage deviation on the series side Deviation from q-axis voltage ,Will and The input voltage outer loop PI controller obtains the current setpoints for the d-axis and q-axis on the series side. and ; Obtain the compensation current of the series filter inductor ,Will The input to the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis current components of the series-side compensation current, thus obtaining the current. and ; In phase Based on, for and Perform the Park transformation to obtain the actual feedback currents on the d-axis and q-axis of the series side. and .

7. The control strategy for a two-arm power quality regulator according to claim 6, characterized in that, The steps for generating the series-modulated wave also include: Calculate the voltage feedforward on the series side: In phase Based on, for and Perform the Park transform to obtain the grid voltage components along the d-axis and q-axis. and ; Set the feedforward scaling factor on the series side, and adjust it according to the feedforward scaling factor on the series side. and Scaling is performed to obtain the grid voltage feedforward components corresponding to the d-axis and q-axis on the series side. and ; Calculate the active current deviation and reactive current deviation on the series side. and ,Will and The input current inner-loop PI controller obtains the series-side regulated voltage corresponding to the d-axis and q-axis. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage corresponding to the d-axis and q-axis of the series side is obtained. and ; right and Perform an inverse Park transform to obtain the modulated wave on the series side. ; Process the modulated wave on the parallel side and output the drive signal to control the power switch on the series side.

8. The control strategy for a two-arm power quality regulator according to claim 7, characterized in that, The processing steps for the parallel-side modulated wave are as follows: Based on the series-side modulation wave Generate triangular carrier signal ; Point-by-point comparison of series-modulated waves With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave ≥carrier When port A2 outputs a positive level, Q5 is turned on and Q6 is turned off; When the modulated wave <carrier> When port A2 outputs a negative level, Q5 is off and Q6 is on; When the state of the series-side switch changes, a dead zone is inserted to prevent Q5 and Q6 from conducting simultaneously. Hardware and software constraints are set to prevent Q5 and Q6 from conducting simultaneously. Narrow pulse suppression is applied to the power switch drive signal generated on the series side to obtain the final drive signal of the power switch on the series side.

9. The control strategy for a two-arm power quality regulator according to claim 1, characterized in that, The steps of adaptive correction are as follows: Calculate the steady-state deviation of DC bus voltage Parallel-side reactive power compensation deviation Load voltage amplitude steady-state deviation Steady-state deviation from midpoint potential ; Adjust the given values ​​of the corresponding parameters on the parallel side: Set correction coefficient Correcting the DC voltage setpoint in the next fundamental cycle : Calculate the temporary value of the DC voltage setpoint ; Obtain the maximum voltage of the DC bus With minimum voltage ,calculate ; Correcting the reactive power setpoint in the next fundamental cycle : Calculate the temporary value of the reactive power setpoint ; The rated reactive power of the acquisition device ,calculate ; Without modifying the setpoint value of the DC bus midpoint potential, Input the value into the PI controller that calculates the potential balance correction at the midpoint of the DC bus. Adjust the given values ​​of the corresponding parameters on the series side: Correcting the load rated voltage setpoint in the next fundamental cycle : Calculate the temporary value of the load rated voltage setpoint ; Obtain the maximum value of the load's rated voltage. and minimum value ,calculate .

10. A two-arm power quality regulator, applicable to the control strategy of the two-arm power quality regulator according to any one of claims 1-9, characterized in that, The regulator includes: Parallel side arm and series side arm; The parallel bridge arm includes: power switches Q1, Q2, Q3, Q4, and clamping diode D. a1 With D a2 Parallel filter inductor L f1 The parallel-connected bridge arm output port A1 shares the same DC bus capacitor C. Bus1 With C Bus2 ; Capacitor C Bus1 The upper end is connected to the DC positive bus, and the capacitor C Bus2 The lower end is connected to the DC negative bus; capacitor C Bus1 The lower end is connected to capacitor C Bus2 Connect the upper ends and bring out the DC midpoint O; Power switches Q1, Q2, Q3, and Q4 are connected in series from top to bottom, with the collector of Q1 connected to capacitor C. Bus1 At the top, the emitter of Q2 is connected to the output port A1 of the parallel side bridge arm, and the emitter of Q4 is connected to capacitor C. Bus2 lower end; clamp tube D a1 Anode terminals A1, D a1 The cathode is connected to the DC midpoint O; clamp tube D a2 Cathode terminals A1, D a2 The anode is connected to the DC midpoint O; Inductor L f1 Connect one end to port A1 and the other end to the power grid neutral wire; The series-connected bridge arm includes: power switches Q5 and Q6, and a series filter inductor L. f2 Series compensation capacitor C f1 The output port A2 of the series-connected bridge arm shares the DC bus capacitor C. Bus1 With C Bus2 Load R L ; Power switches Q5 and Q6 are connected in series, and the collector of Q5 is connected to capacitor C. Bus1 At the top, the collector of Q6 is led out to the output port A2 of the series-side bridge arm, and the emitter of Q6 is connected to capacitor C. Bus2 lower end; Series filter inductor L f2 Series compensation capacitor C f1 They are connected in series to form an LC low-pass filter circuit and connected to the output port A2 of the series side bridge arm. Series compensation capacitor C f1 Keep away from series filter inductor L f2 One end is connected to the power grid and the load R L The phase line of the power grid between them, and the load R L It is connected in parallel between the phase line and the neutral line of the power grid.

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