A two-bridge-arm power flow regulator and a control strategy thereof

Abstract

The application provides a two-bridge-arm tide flow regulator and a control strategy thereof, and belongs to the field of power quality treatment; solves the problems of low tide flow regulation precision and poor adaptation to imbalance between transformer areas; and the specific control strategy is as follows: the voltage and phase of a power grid 1 are obtained, the d-axis and q-axis given currents are subtracted from the actual currents, the power grid voltage feedforward and the midpoint potential balance correction amount of a DC bus are superimposed, the modulation wave of a parallel side of a transformer area 1 is obtained, and the parallel side power device driving signal is output; the d-axis and q-axis current given values of a series side are calculated, the current deviation of the series side is calculated based on the phase of the power grid 1, the series side voltage feedforward compensation amount is superimposed after the input PI controller, the series side modulation wave is obtained, and the series side power device driving signal is output; the parallel side bus voltage and the series side transformer area tide flow are double-closed-loop regulated and flexibly handled, the voltage amplitude and phase deviation between transformer areas are adjusted, and the two-way mutual aid and safe and stable operation of the double transformer area tide flow are realized.

Description

Technical Field

[0001] This invention relates to a two-arm power flow regulator and its control strategy, belonging to the field of power quality management. Background Technology

[0002] With the increasing load differentiation in low-voltage distribution network areas and the continuous increase in the penetration rate of distributed power sources, problems such as uneven power flow distribution between distribution areas, voltage deviation, and weak power mutual assistance capabilities are becoming more and more prominent. Traditional methods of interconnection and control of distribution areas are difficult to adapt to the flexible operation requirements of modern distribution networks, and the balance of power supply and the economic efficiency of operation of distribution areas are limited.

[0003] To achieve power balance and power flow optimization between distribution stations, traditional solutions often employ separate power management equipment and power flow regulation devices in conjunction, or use a single two-level converter topology for regulation. These traditional devices have limited functionality and fragmented hardware architectures, requiring multiple devices to work together to meet the needs of bus voltage stabilization, reactive power compensation, and power flow regulation. This results in numerous problems, including high equipment redundancy, large footprint, high construction costs, and significant device operating losses. Furthermore, independent regulation by multiple devices can easily lead to mismatched control timing and conflicting control objectives, making it difficult to achieve layered, precise, and stable grid regulation.

[0004] Traditional transformer substation interconnection converters often employ single closed-loop or open-loop control strategies, lacking robust outer-loop voltage regulation and midpoint potential balancing correction mechanisms. Under complex operating conditions such as load fluctuations and grid disturbances, the DC bus voltage is prone to continuous drift and significant fluctuations, failing to provide a stable operating basis for power flow regulation. The application of traditional three-level topologies commonly suffers from midpoint potential imbalance, easily leading to uneven device stress, output waveform distortion, and increased harmonic content, severely degrading the power quality and operational stability of the transformer substation.

[0005] Furthermore, traditional power flow control strategies lack a decoupled power-current dual-closed-loop control architecture, often employing simple proportional regulation methods. This fails to achieve independent and precise control of active and reactive power flows, resulting in mutual coupling and interference between the two types of power regulation, leading to lag in dynamic response and large steady-state control errors. Simultaneously, the traditional control method lacks a capacitor voltage feedforward compensation stage, making it impossible to effectively cancel disturbances in series branches. This further reduces power flow tracking accuracy and dynamic response speed, hindering the achievement of bidirectional, smooth, and continuous power flow mutual assistance control between distribution stations. Consequently, it cannot effectively address practical problems such as uneven peak-valley load distribution, excessive line losses, and unreasonable power flow distribution within distribution stations.

[0006] In summary, simplifying the topology of power flow regulators, reducing equipment losses and costs, improving the DC bus voltage regulation accuracy and system operation stability, and achieving precise decoupling control of bidirectional power flow in distribution areas are the technical challenges that urgently need to be solved in the field of flexible interconnection of low-voltage distribution network areas. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a two-arm power flow regulator and its control strategy, which seeks to solve the problems of topological redundancy, voltage difference, low power flow control accuracy, and unbalanced adaptation in traditional transformer interconnection devices.

[0008] To achieve the above objectives, the present invention provides a control strategy for a two-arm power flow regulator, comprising: Obtain the grid voltage and phase of grid 1; calculate the difference between the actual voltage and the voltage setpoint of the DC bus on the parallel side, and obtain the d-axis setpoint current of the parallel side through a PI controller; calculate the q-axis setpoint current of the parallel side; process the actual compensation current corresponding to the parallel side to obtain the actual currents of the d-axis and q-axis of the parallel side; on the parallel side, calculate the difference between the setpoint current and the actual current on the d-axis and q-axis of the parallel side, and superimpose the grid voltage feedforward and DC bus midpoint potential balance correction on the parallel side, and obtain the parallel side modulation wave corresponding to substation 1 through inverse Park transformation; process the parallel side modulation wave and output the drive signal to control the power devices on the parallel side; Obtain the given values ​​of active and reactive power, obtain the actual feedback current on the series side and the grid voltage of grid 2, and calculate the actual active and reactive power on the series side; calculate the active power and active power deviation, and obtain the current given values ​​of the d-axis and q-axis on the series side through a PI controller; process the actual feedback current on the series side to obtain the orthogonal component of the feedback current on the series side; use the phase of grid 1 as a reference to perform coordinate transformation on the orthogonal component of the feedback current on the series side to obtain the actual current on the d-axis and q-axis of the series side; calculate the current deviation on the parallel side, input it into the PI controller and superimpose the voltage feedforward compensation amount on the series side to obtain the modulation wave on the series side; process the modulation wave on the series side and output the drive signal to control the power devices on the series side; Obtain the grid parameters on both the parallel and series sides, and determine whether transformer substation 1 and transformer substation 2 meet the synchronization conditions. If they do, issue a closing command to close the transformer substation interconnection circuit breaker between transformer substation 1 and transformer substation 2. If they do not meet the conditions, readjust the voltage and phase output of the series compensation capacitor.

[0009] Furthermore, the steps for generating the parallel-side modulated wave are as follows: Obtain the grid voltage corresponding to grid 1 Generate the modulated wave at the parallel port. ; Obtained via SOGI Voltage components corresponding to the α and β axes and ; The phase of power grid 1 is obtained through a PLL phase-locked loop. ; Obtain the actual voltage of the DC bus Obtain the DC bus voltage setpoint. Calculate the voltage difference on the parallel side, and obtain the given value of the d-axis current through a PI controller. ; Obtain the given value of reactive power corresponding to grid 1 Calculate the given value of the q-axis current. ; Obtain the actual compensation current corresponding to power grid 1 Through SOGI, we obtain Current components along the α and β axes and ; In phase Based on, for and Perform the Park transformation to obtain the actual currents along the d-axis and q-axis. and ; calculate and as well as and The difference is used to obtain the active current deviation on the parallel side. With reactive current deviation ,Will and Input to the PI controller to obtain the regulated voltages corresponding to the d-axis and q-axis on the parallel side. and ; exist and Based on this, the total regulating voltage of the d-axis and q-axis is obtained by superimposing the grid voltage feedforward component and the potential balance correction at the DC bus midpoint. and .

[0010] Furthermore, the subsequent steps for generating the parallel-side modulated wave are as follows: right and Perform an inverse Park transform to obtain the modulated wave on the parallel side. ; According to the modulation wave on the parallel side of power grid 1 Two carrier signals are generated to obtain the upper carrier. With download wave ; Modulated wave on the parallel side Standardize and compare the modulated waves point by point. The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave >Upcarrier When port A1 outputs a positive level, Q1 and Q2 are turned on, and Q3 and Q4 are turned off; Current carrier <Modulated wave <Upcarrier> When port A1 outputs a zero level, Q2 and Q3 are turned on, and Q1 and Q4 are turned off; When the modulated wave <Download Wave When port A1 outputs a negative level, Q3 and Q4 are turned on, and Q1 and Q2 are turned off. When the modulated wave The instantaneous values ​​of the uplink and downlink waves are equal, resulting in a zero-level output. In modulated wave The instantaneous value and the upcarrier When the instantaneous value crosses the boundary, a dead zone is inserted; Based on the comparison results between the modulation wave on the parallel side and the uplink and downlink waves, a PWM pulse sequence is generated to control the power switch transistor on the parallel side of phase A.

[0011] Furthermore, the calculation steps for the potential balance correction between the grid voltage feedforward component and the DC bus midpoint are as follows: Calculate grid voltage feedforward: In phase Based on, for and Perform a Park transform to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; Calculate the potential balance correction at the midpoint of the DC bus: Obtain the DC voltage DC voltage Calculate DC voltage deviation ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. .

[0012] Furthermore, the specific steps for inserting the dead zone are as follows: Operating condition 11: Positive level → Zero level. Before the level state switch: Q1 is on, Q2 is on, Q3 is off, Q4 is off. Q3 Insert dead zone After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Operating condition 12: Zero level → Positive level. Before the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off. Q1 Insert dead zone After the level state switch: Q1 is turned on, Q2 is turned on, Q3 is turned off, and Q4 is turned off; In modulated wave Instantaneous value and download wave When the instantaneous value crosses the boundary, a dead zone is inserted; Operating condition 21: Zero level → Negative level. Before the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off. Q4 Insert dead zone After the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on; Operating condition 22: Negative level → Zero level. Before the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on. Q2 Insert dead zone After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off.

[0013] Furthermore, the steps for generating the series-modulated wave are as follows: Obtain the grid voltage of grid 2 Generate the modulated wave at the series port. ; Obtained via SOGI α-axis and β-axis voltage components and ; Obtain the actual current of the series filter inductor corresponding to power grid 2. Obtained via SOGI α-axis and β-axis current components and ; Calculate the actual active power of power grid 2 With actual reactive power ; Obtain the given value of the active power corresponding to grid 2. With the given value of reactive power ; Calculate the active power deviation on the series side Deviation from reactive power ; Will and Input to the PI controller to obtain the d-axis current setpoint on the series side. With q-axis current setpoint ; Obtain the phase of power grid 1 , in phase As a reference, for current and Perform the Park transformation to obtain the actual d-axis current on the series side. With actual q-axis current ; Calculate the series-side voltage feedforward: Obtain the voltage across the series-side filter capacitor. Using a SOGI second-order generalized integrator to process voltage The voltage components along the α-axis and β-axis were obtained. and ; In phase Based on, for and Perform a Park transform to obtain the voltage feedforward components on the d-axis and q-axis of the series side. and ; Calculate the active current deviation on the series side Deviation from reactive current ,Will and Input to the PI controller to obtain the regulated voltages corresponding to the d-axis and q-axis on the series side. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage of the series-side d-axis and q-axis is obtained. and ; right and Perform an inverse Park transform to obtain the modulated wave on the series side. .

[0014] Furthermore, the subsequent steps for generating the series-modulated wave are as follows: According to the series side modulation wave Generate carrier ; Modulated wave on the series side Standardize and compare the series-modulated waves point by point. With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave > Carrier When port A2 outputs a positive level, Q5 is turned on and Q6 is turned off; When the modulated wave <carrier> When port A2 outputs a negative level, Q5 is off and Q6 is on; When the modulated wave With carrier If they are equal, then output a negative level; Set dead zone In modulated wave instantaneous value and carrier When the instantaneous value crosses the boundary, a dead zone is inserted on the series side; Based on the modulated wave and carrier wave on the series side The comparison results are used to generate PWM pulse sequences for controlling the two power switches on the series side.

[0015] Furthermore, the steps for inserting a dead zone on the series side are as follows: Operating condition A: Positive level → Negative level. Before the level state switch: Q5 is on, Q6 is off; Q6 Insertion Dead Zone After the level state switch: Q5 is off, Q6 is on; Operating condition B: Negative level → Positive level. Before the level state switch: Q5 is off, Q6 is on. Q5 Insert Dead Zone After the level state switch: Q5 is turned on, and Q6 is turned off.

[0016] Furthermore, the steps for readjusting the voltage and phase of the output of the series compensation capacitor are as follows: Obtain the corresponding grid voltages for transformer substation 1 and transformer substation 2 respectively, and calculate the voltage amplitude difference and phase difference for each phase of the two transformer substations. Compare the amplitude difference and phase difference with the preset synchronization threshold: Scenario 1: If all amplitude differences and phase differences do not exceed the synchronization threshold, it means that transformer area 1 and transformer area 2 meet the synchronization conditions. A closing command is issued to close the transformer area interconnection circuit breaker between transformer area 1 and transformer area 2, thus completing the flexible loop closure of the two transformer areas. Scenario 2: If Scenario 1 is not met, then the new power setting is calculated based on the voltage deviation between the two transformer areas; The grid voltage of grid 1 Converted into d-axis and q-axis voltage components and ; With the phase of power grid 1 Using the grid voltage of grid 2 as a reference... Transform to the two-phase rotating coordinate system corresponding to power grid 1 to obtain and ; Calculate the voltage deviation between the d-axis and q-axis of the two transformer areas. and ; Each and Input to the PI controller to obtain the new active power command. With the new reactive power given ; use and Replace the original active and reactive power inputs on the series side, and readjust the voltage and phase output of the corresponding series compensation capacitor in grid 2.

[0017] A two-arm power flow regulator includes: Parallel side arm and series side arm; The parallel bridge arm includes: power switches Q1, Q2, Q3, Q4, and clamping transistor D. a1 D a2 Shared DC bus capacitor C Bus1 C Bus2 AC output port A1, parallel side filter inductor L f1 ; Power switching transistors Q1, Q2, Q3, and Q4 are connected in series from top to bottom. The collector of Q1 is connected to the DC positive bus, and the emitter of Q2 is led out to the AC output port A1 of the parallel side bridge arm. D a1 The cathode is connected above the AC output port A1, and the anode is connected to the DC midpoint O; D a2 The anode is connected below the AC output port A1, and the cathode is connected to the DC midpoint O; Parallel side filter inductor L f1 One end is connected to port A1, and the other end is connected to the power grid phase line L; The tandem side arms include: Power switching transistors Q5 and Q6 share the same DC bus capacitor C. Bus1 C Bus2 The AC output node is A2, and the series-side filter inductor is L. f2 Series-side filter capacitor C f1 .

[0018] C Bus1 The upper end is connected to the DC positive bus, and the lower end is connected to C. Bus2 The upper part, C Bus2 The lower end is connected to the DC negative busbar; Q5 is used as the upper transistor, and Q6 is used as the lower transistor. The collector of Q5 is connected to the positive DC bus, and the emitter of Q6 is connected to the negative DC bus. The emitter of Q5 and the collector of Q6 are connected to form the AC output port A2 of the series side bridge arm. The parallel-side bridge arm is connected in parallel to the power grid 1, and the series-side bridge arm and the series-side filter inductor L f2 With series-side filter capacitor C f1 The entire system is connected in series between power grid 1 and power grid 2.

[0019] Compared with the prior art, the beneficial effects of the present invention are: It adopts a composite topology of parallel three-level and series two-level, which has high integration and low loss. This invention adopts a composite two-arm topology structure of parallel-side I-NPC three-level bridge arm and series-side two-level half-bridge arm, breaking through the functional limitations of a single converter that can only achieve grid-connected compensation or single power flow regulation. This device simultaneously has multiple functions such as DC bus voltage stabilization, grid reactive power compensation, and bidirectional power flow regulation of distribution areas, greatly improving the device integration and equipment utilization, effectively simplifying the equipment hardware architecture, reducing equipment size, manufacturing cost and operating power consumption, and adapting to the lightweight, low-cost and multifunctional transformation needs of distribution network distribution areas.

[0020] The parallel-side dual closed-loop control achieves DC bus voltage regulation and midpoint potential self-balancing, resulting in strong stability. Step S1 in this invention constructs a dual-closed-loop decoupled control system consisting of an outer voltage loop and an inner current loop. Simultaneously, a midpoint potential balance correction strategy is superimposed, completely resolving the technical defects of traditional interconnected converters, such as DC bus voltage fluctuations, midpoint potential shifts, and output current distortion, from a control perspective. The outer voltage loop collects real-time DC bus voltage, performs difference calculations with a given voltage, and generates an active current reference command via PI regulation. By dynamically adjusting the active power throughput between the grid and the device, high-precision constant control of the DC bus voltage is achieved. The inner current loop uses the grid phase-locked loop phase as a reference to complete coordinate decoupling, quickly tracks the current reference command, suppresses current disturbances caused by sampling noise and switching harmonics, and ensures the sinusoidal waveform of the grid-connected output current. The entire closed-loop control strategy has strong anti-interference capabilities and can adapt to conditions such as frequent load fluctuations in the distribution area and grid voltage disturbances, ensuring the long-term reliable operation of the entire device.

[0021] Series-side power-current dual closed-loop precise control enables bidirectional power flow mutual assistance within the transformer substation: Step S2 of this invention addresses the power flow regulation needs between distribution transformers by designing a dual-layer closed-loop control strategy consisting of an outer power loop and an inner current loop. This strategy enables precise bidirectional independent regulation of active and reactive power between distribution transformer 1 and distribution transformer 2. The outer power loop uses the deviation between the upper-level dispatched power setpoint and the real-time measured power as the basis for adjustment, accurately converting the power deviation into d-axis and q-axis current reference commands. This achieves decoupled control of active and reactive power flow, avoiding mutual coupling interference between active and reactive power regulation. The inner current loop, combined with a series capacitor voltage feedforward compensation strategy, effectively counteracts the disturbance caused by the back electromotive force of the series branch capacitor, improving current tracking accuracy and dynamic response speed, and reducing steady-state regulation error. This control strategy is adaptable to conditions such as unbalanced distribution transformer loads, power backflow, and reactive power deficit, optimizing the power flow distribution of the distribution network and improving the economic efficiency of power supply in the distribution transformer area. Attached Figure Description

[0022] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1This is a schematic diagram of the two-arm power flow regulator of the present invention; Figure 2 This is a schematic diagram of the parallel-side control flow of the present invention; Figure 3 This is a schematic diagram of the series-side control flow of the present invention; Figure 4 This is a schematic diagram of the control strategy for the two-arm power flow regulator of the present invention. Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Example 1

[0025] Please see Figure 1 A two-arm power flow regulator includes: a parallel side arm and a series side arm; The parallel side arms include: Power switching transistors Q1, Q2, Q3, Q4, and clamping transistor D a1 D a2 Shared DC bus capacitor C Bus1 C Bus2 AC output port A1, parallel side filter inductor L f1 ; U Grad1 L represents the phase line of the power grid, and N represents the neutral line of the power grid. The specific connection method is as follows: Power switching transistors Q1, Q2, Q3, and Q4 are connected in series from top to bottom, with the collector of Q1 connected to the positive DC bus (i.e., C). Bus1 (At the top), the emitter of Q1 is connected to the collector of Q2; The emitter of Q2 leads to the AC output port A1 of the parallel side bridge arm; The collector of Q3 is connected to the AC output port A1, and the emitter of Q3 is connected to the collector of Q4. The emitter of Q4 is connected to the DC negative bus (i.e., C). Bus2 (top) D a1 The cathode is connected above the AC output port A1 (i.e., the connection point between Q1 and Q2, also known as the collector of Q2), and the anode is connected to the DC midpoint O. D a2 The anode is connected to the AC output port A1 below (i.e., the connection point between Q3 and Q4, i.e., the emitter of Q3), and the cathode is connected to the DC midpoint O; The AC output port A1 of the parallel side bridge arm is externally connected to the parallel side filter inductor L. f1 Filter inductor L f1 The other end is connected to the phase line L of the power grid; Port A1 can output three levels: positive, zero, and negative. Positive level, zero level, and negative level are the potentials of port A1 relative to the DC midpoint O; (a) Output positive level: Q1 and Q2 are turned on, and the current path is: DC positive bus → Q1 → Q2 → port A1 → inductor L f1 →Power grid; When the current reverses, the current path is: mains → inductor L f1 →Port A1→Q2→Q1→DC Positive Bus→Capacitor C Bus1 ; (b) Output zero level: Q2 and Q3 are turned on.

[0026] Current flows out of port A1: Port A1 → clamping transistor D a1 →DC midpoint O; Current flows into port A1: DC midpoint O → clamping transistor D a2 →Port A1; (c) Output negative level: Q3 and Q4 are turned on, and the current path is: port A1 → Q3 → Q4 → DC negative bus; When the current reverses, the current path is: DC negative bus → Q4 → Q3 → port A1 → inductor L f1 →Power grid; The tandem side arms include: Power switching transistors Q5 and Q6 share the same DC bus capacitor C. Bus1 C Bus2 The AC output node is A2, and the series-side filter inductor is L. f2 Series-side filter capacitor C f1 ; The specific connection method is as follows: C Bus1 The upper end is connected to the DC positive bus, and the lower end is connected to C. Bus2 The upper part, C Bus2 The lower end is connected to the DC negative busbar; Q5 is used as the upper transistor, and Q6 is used as the lower transistor. The collector of Q5 is connected to the positive DC bus, i.e., C. Bus1 The upper end; the emitter of Q6 is connected to the DC negative bus, i.e., C. Bus2 The lower end of the bridge; the emitter of Q5 is connected to the collector of Q6, leading out the AC output port A2 of the series side bridge arm; U Grad2 This indicates that grid 2 is connected in parallel to grid 1, and the series-side bridge arm and series-side filter inductor L are connected in parallel. f2 With series-side filter capacitor C f1 The entire system is connected in series between power grid 1 and power grid 2.

[0027] Port A2 can only output positive and negative levels, but cannot output zero level; the positive and negative levels are the potentials of port A2 relative to the DC midpoint O; (a) Output positive level: Q5 is on, Q6 is off; The current path is as follows: Forward current path: DC positive bus → Q5 → Port A2 → Inductor L f2 →Capacitor C f1 →Power grid; When the current reverses, the current path is: power grid → capacitor C. f1 →Inductance L f2 →Port A2→Q5→DC positive bus; (b) Output negative level: The current path is as follows: Q5 is open, Q6 is on; Midpoint O → Capacitor C Bus2 →Q6→Port A2→Inductor L f2 →Capacitor C f1 →Power grid; When the current reverses, the current path is: Power grid → Capacitor C f1 →Inductance L f2 →Port A2→Q6→Capacitor C Bus2 → Midpoint O.

[0028] Example 2

[0029] Please see Figure 4 A control strategy for a two-arm power flow regulator includes: Step S1: Generate a parallel-side modulation wave to prioritize maintaining the stability of the DC bus voltage, and then perform reactive power compensation for area 1 (the area powered by grid 1). Obtain the grid voltage of grid 1, and obtain the phase of the grid voltage on the parallel side through a second-order generalized integrator (SOGI) and a phase-locked loop (PLL). Subtract the actual voltage of the DC bus on the parallel side from the voltage setpoint, and obtain the d-axis setpoint current on the parallel side through a PI controller. Calculate the q-axis setpoint current on the parallel side, and use a second-order generalized integrator (SOGI) and Park transform to process the corresponding actual compensation current on the parallel side, thereby obtaining the actual currents on the d-axis and q-axis of the parallel side. On the parallel side, the difference between the given current and the actual current on the d-axis and q-axis of the parallel side is calculated and superimposed with the grid voltage feedforward and DC bus midpoint potential balance correction on the parallel side. After inverse Park transformation, the parallel side modulation wave corresponding to substation 1 is obtained. The parallel-side modulation wave is processed using SPWM modulation to output the drive signal that controls the power devices on the parallel side. Please see Figure 2 The specific steps of step S1 are as follows: Obtain the grid voltage of grid 1 and generate a modulated wave at the parallel side port. ; Will Inputting the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis voltage components, yielding... and ; Will and Inputting a PLL (phase-locked loop) yields the phase of grid 1. ; Obtain the actual voltage of the DC bus Obtain the DC bus voltage setpoint. ,calculate and The difference ;Will The input voltage is controlled by an outer-loop PI controller to obtain the setpoint value of the d-axis current (active current). Used to maintain the stability of DC bus voltage; It should be noted that when When it is low (i.e.) (Positive), the outer loop PI increases the active current setpoint. It absorbs active power from grid 1 to charge the DC bus; when When it is too high (i.e.) (negative), the outer loop PI reduces the active current setpoint. It feeds back active power to grid 1, pulls the bus voltage back to the given value, and maintains the stability of the DC bus voltage; Obtain the given value of reactive power corresponding to grid 1 Calculate the given value of the q-axis current (reactive current). : ; Obtain the actual compensation current on the parallel filter inductor Using the SOGI second-order generalized integrator for processing We obtain the current components along the α-axis and β-axis, denoted as current. and ; In phase As a reference, for current and Perform the Park transformation to obtain the actual currents along the d-axis and q-axis. and ; ; ; Use a low-pass filter (LPF) to filter the current. and Perform filtering processing; Calculate grid voltage feedforward: In phase Based on, for and Perform a Park transform to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; ; ; Calculate the potential balance correction at the midpoint of the DC bus: Obtain the DC voltage (i.e., capacitor C) Bus1 (Voltage at both ends), DC voltage (i.e., capacitor C) Bus2 (Voltage at both ends) Calculate DC voltage deviation : ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. (Voltage); calculate and as well as and The difference is used to obtain the active current deviation. With reactive current deviation ,Will and Input to the PI controller to obtain the adjustable voltages for the d-axis and q-axis. and ; exist and Based on this, the "grid voltage feedforward component" and the "potential balance correction at the DC bus midpoint" are superimposed to obtain the total regulating voltage on the d-axis and q-axis. and ; ; ; right and Performing an inverse Park transform, we obtain the control voltages of grid 1 on the α and β axes. and ; ; ; Will Modulated wave as the parallel side ; According to the modulation wave on the parallel side of power grid 1 Two high-frequency triangular carrier signals with the same frequency and amplitude (the frequency of these carrier signals is higher than the fundamental frequency of the power grid) are generated to obtain the upper carrier. With download wave ; upcarrier The amplitude range is This corresponds to the modulation between zero level and positive level; Download Wave The amplitude range is This corresponds to the modulation between negative and zero levels; upcarrier With download wave Except for the instantaneous intersection at zero point (i.e.) ), which is always satisfied at any time; ; Modulated wave on the parallel side Standardize, The amplitude was compressed to The interval is used for comparison with the upstream and downstream waves; Point-by-point comparison of parallel side modulated waves The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave Instantaneous value > upcarrier The instantaneous value of Q1 and Q2 is turned on, while Q3 and Q4 are turned off. Current carrier Instantaneous value < modulated wave Instantaneous value < upcarrier The instantaneous value of Q1 indicates that the output of port A1 on the parallel side is zero, Q2 and Q3 are turned on, and Q1 and Q4 are turned off. When the modulated wave Instantaneous value < Download wave The instantaneous value of Q3 and Q4 is turned on, and Q1 and Q2 are turned off. When the modulated wave The instantaneous values ​​of the uplink and downlink waves are equal, that is... Instantaneous value ≈ upcarrier The instantaneous value, or Instantaneous value ≈ Download wave The instantaneous value, or Instantaneous value ≈ upcarrier Instantaneous value ≈ Download wave If the instantaneous value is zero, then a uniform zero level will be output. It should be noted that the equality of the amplitude of the modulating wave and the carrier wave is only a theoretical instantaneous intersection moment and does not exist in a sustained interval. Therefore, when judging the case of "equal amplitude of the modulating wave and the carrier wave", this invention uses an approximate equal sign instead of an equal sign.

[0030] In modulated wave The instantaneous value and the upcarrier When the instantaneous value crosses the boundary (i.e., the state switch between positive and zero level), a dead zone is inserted; Operating Condition 11: Positive Level → Zero Level, Modulated Wave The instantaneous value is greater than the upcarrier. The instantaneous value becomes less than the upcarrier. The instantaneous value; Before the level state switch: Q1 is on, Q2 is on, Q3 is off, and Q4 is off; Q3 Insert dead zone Dead Zone The value range is 1 to 5 microseconds, preferably 2 microseconds or 2.5 microseconds; Q1 disconnects immediately, Q2 remains conductive throughout, Q4 remains disconnected throughout, Q3 is delayed. Reconnect after a certain time; After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Operating Condition 12: Zero Level → Positive Level, Modulated Wave The instantaneous value is less than the upper carrier. The instantaneous value becomes greater than the upcarrier. The instantaneous value; Before the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Q1 Insert dead zone Q3 disconnects immediately, Q2 remains conductive throughout, Q4 remains disconnected throughout, and Q1 is delayed. Reconnect after a certain time; After the level state switch: Q1 is turned on, Q2 is turned on, Q3 is turned off, and Q4 is turned off; In modulated wave Instantaneous value and download wave When the instantaneous value crosses the boundary (i.e., the state switch between negative and zero level), a dead zone is inserted; Operating condition 21: Zero level → Negative level, modulated wave The instantaneous value is greater than the downloaded wave The instantaneous value becomes less than the downloaded wave. The instantaneous value; Before the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Q4 Insert dead zone Q2 disconnects immediately, Q1 remains disconnected throughout, Q3 remains conductive throughout, and Q4 is delayed. Reconnect after a certain time; After the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on; Operating condition 22: Negative level → Zero level, Modulated wave The instantaneous value is less than the downloaded wave The instantaneous value becomes greater than the downloaded wave. The instantaneous value; Before the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on; Q2 Insert dead zone Q4 disconnects immediately, Q1 remains disconnected throughout, Q3 remains conductive throughout, and Q2 is delayed. Reconnect after a certain time; After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Based on the comparison results between the modulation wave on the parallel side and the uplink and downlink waves, a PWM pulse sequence is generated to control the four power switching transistors (Q1, Q2, Q3, Q4) on the parallel side.

[0031] Step S2: Generate a series-side modulated wave to regulate the power flow between transformer substation 1 and transformer substation 2 (areas powered by power grid 2); Obtain the given values ​​of active power and reactive power, obtain the actual feedback current on the series side and the grid voltage of grid 2, and calculate the actual active power P and actual reactive power Q on the series side. Calculate the active power and the active power deviation ΔP and ΔQ, input ΔP and ΔQ into the PI controller, and obtain the current setpoint values ​​of the d-axis and q-axis on the series side; The actual feedback current on the series side is processed using a second-order generalized integrator of SOGI to obtain the orthogonal components of the feedback current on the series side; with the phase of grid 1 as a reference, the orthogonal components of the feedback current on the series side are subjected to Park transformation to obtain the actual current on the d-axis and q-axis of the series side. Calculate the current deviation on the parallel side, input it into the PI controller and add the "series side voltage feedforward compensation amount", and obtain the series side modulation wave after inverse Park transformation; The series-side modulated wave is processed using SPWM modulation to output the drive signal that controls the series-side power devices. Please see Figure 3 The specific steps of step S2 are as follows: Obtain the grid voltage of grid 2 ; Generate the modulated wave at the series port ; Will Inputting the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis voltage components, yielding... and ; Obtain the actual current of the series filter inductor corresponding to power grid 2. ,Will Inputting the SOGI second-order generalized integrator generates orthogonal α-axis and β-axis current components, yielding the current. and ; Calculate the actual active power of power grid 2 With actual reactive power ; ; ; Obtain the active power setpoint of power grid 2 With reactive power setpoint ; Calculate the active power deviation of power grid 2 Deviation from reactive power ; ; ; Will and Input to the PI controller to obtain the d-axis current setpoint on the series side. With q-axis current setpoint ; Obtain the phase corresponding to power grid 1 , in phase As a reference, for current and Perform the Park transformation to obtain the actual d-axis current on the series side. With actual q-axis current ; ; ; Calculate the series-side voltage feedforward: Obtain the voltage across the series-side filter capacitor. Using a SOGI second-order generalized integrator to process voltage The voltage components along the α-axis and β-axis were obtained. and ; In phase Based on, for and Perform a Park transform to obtain the voltage feedforward components on the d-axis and q-axis of the series side. and ; ; ; calculate and as well as and The difference is used to obtain the deviation of active current and reactive current on the series side. and ,Will and Input to the PI controller to obtain the regulated voltages on the d-axis and q-axis of the series side. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage of the series-side d-axis and q-axis is obtained. and ; ; ; right and Performing an inverse Park transform, we obtain the control voltages of grid 2 on the α and β axes. and ; ; ; Will Modulated wave as the series side ; According to the series-side modulation wave of power grid 2 A high-frequency triangular carrier signal with the same frequency and amplitude (the frequency of this carrier signal is higher than the fundamental frequency of power grid 2) is generated to obtain the carrier. carrier The amplitude range is ; Modulated wave on the series side Standardize, The amplitude was compressed to Interval, point-by-point comparison of the series-modulated wave With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave Instantaneous value > carrier At the instantaneous value of Q5, port A2 on the series side outputs a positive level, Q5 is turned on, and Q6 is turned off. When the modulated wave Instantaneous value < carrier The instantaneous value of Q5 indicates that port A2 on the series side outputs a negative level, Q5 is disconnected, and Q6 is turned on. When the modulated wave With carrier If the instantaneous values ​​are equal, then the output level is negative; Set dead zone The dead zone is consistent with the dead zone set in step S1; In modulated wave instantaneous value and carrier When the instantaneous value crosses the boundary (i.e., the state switch between positive and negative levels), a dead zone is inserted; Operating condition A: Positive level → Negative level, modulated wave The instantaneous value is greater than the carrier wave. The instantaneous value becomes less than the carrier wave. The instantaneous value; Before the level state switch: Q5 is on, Q6 is off; Q6 Insertion Dead Zone Q5 disconnects immediately, Q6 is delayed. Reconnect after a certain time; After the level state switch: Q5 is off, Q6 is on; Operating Condition B: Negative Level → Positive Level, Modulated Wave The instantaneous value is less than the carrier wave. The instantaneous value becomes greater than the carrier wave. The instantaneous value; Before the level state switch: Q5 is off, Q6 is on; Q5 Insert Dead Zone Q6 disconnects immediately, Q5 is delayed. Reconnect after a certain time; After the level state switch: Q5 is turned on, Q6 is turned off; Based on the series-side modulated wave and carrier The comparison results are used to generate PWM pulse sequences for controlling the two power switches (Q5 and Q6) on the series side.

[0032] Step S3: Obtain the grid parameters on both the parallel side and the series side, and determine whether the synchronization conditions of transformer substation 1 and transformer substation 2 are met; if they are met, issue a closing command to close the transformer substation interconnection circuit breaker between transformer substation 1 and transformer substation 2; if they are not met, readjust the voltage and phase output of the series compensation capacitor.

[0033] Obtain the grid voltage corresponding to transformer area 1 and transformer area 2 respectively, use a PLL phase-locked loop to obtain the voltage phase of the two transformer areas respectively, and calculate the voltage amplitude difference ΔU between the two transformer areas. Grid With phase difference Δθ Grad ; The amplitude difference and phase difference are compared with the "preset synchronization threshold" (i.e., the synchronization condition, also known as the "amplitude difference ΔU"). Grid "and "phase difference Δθ Grad Compare the range of values ​​for "" to: Scenario 1: If the amplitude difference and phase difference do not exceed the "preset synchronization threshold", it means that the synchronization conditions of transformer area 1 and transformer area 2 are met. The controller (i.e., the main controller of a two-arm power flow regulator) issues a closing command to close the transformer area interconnection circuit breaker between transformer area 1 and transformer area 2, and complete the flexible loop closing of the two transformer areas. Scenario 2: If the amplitude difference or phase difference exceeds the "preset synchronization threshold", or if both the amplitude difference and phase difference exceed the "preset synchronization threshold", then the new power input in step S2 is calculated based on the voltage deviation between the two substations. According to voltage deviation ΔU Grid Calculate the new power setpoint in step S2, adjust the voltage and phase output of the series compensation capacitor, and gradually reduce the amplitude difference and phase difference between the two transformer areas until the two transformer areas meet the synchronization condition: The grid voltage of grid 1 Converted into d-axis and q-axis voltage components, resulting in and ; With the phase of power grid 1 Using the grid voltage of grid 2 as a reference... Transform to the two-phase rotating coordinate system (i.e., the d-q coordinate system) corresponding to power grid 1 to obtain and ; Calculate the voltage deviations along the d-axis and q-axis of the two stations to obtain... and ; ; ; Each and The new active power command is obtained by inputting it into two PI controllers. With the new reactive power given ; use and Replace the original in step S2 and Then, the remaining process of step S2 is executed to readjust the voltage and phase of the corresponding series compensation capacitor output in power grid 2.

[0034] Compared to the problems described in the background technology, this invention adopts a two-arm composite topology of parallel three-level + series two-level to replace the traditional multi-device discrete control architecture. Through functional hierarchical integration design, the functions of bus voltage stabilization, potential balancing and power flow control in the transformer area are integrated into a single device. This eliminates the redundant configuration of the traditional solution that requires multiple independent devices to operate in coordination, significantly reduces the number of inverter arms, drive circuits and filter devices, effectively reduces the overall size of the device, reduces hardware manufacturing costs and overall operating losses, and solves the technical drawbacks of traditional transformer area control solutions such as scattered equipment, poor coordination, low device utilization and high maintenance costs. It also significantly improves the working efficiency of power devices and the integration of the device.

[0035] Furthermore, this invention utilizes a second-order generalized integrator (SOGI) to construct orthogonal components of electrical quantities, coupled with a globally unified phase-locked loop reference to ensure synchronization of control timing across multiple modules. It employs a hierarchical closed-loop control architecture combining parallel-side voltage stabilization and balancing dual closed loops, series-side power-current decoupling dual closed loops, capacitor voltage feedforward compensation, and three-phase synchronous flexible combination and decomposition loops. This effectively overcomes the shortcomings of traditional control strategies, such as poor voltage stabilization accuracy, severe power flow coupling, and lag in dynamic response. This control architecture can stably maintain a constant common DC bus voltage and balanced three-level midpoint potential, precisely adjust the amplitude and phase of the series compensation voltage, and achieve bidirectional independent, smooth, and precise control of active and reactive power flow between the two transformer substations.

[0036] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to specific implementation methods. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The present invention is limited only to the technical solutions and their full scope and equivalents.

Claims

1. A control strategy for a two-arm power flow regulator, characterized in that, The control strategy includes: Obtain the grid voltage and phase of grid 1; calculate the difference between the actual voltage and the voltage setpoint of the DC bus on the parallel side, and obtain the d-axis setpoint current of the parallel side through a PI controller; calculate the q-axis setpoint current of the parallel side; process the actual compensation current corresponding to the parallel side to obtain the actual currents of the d-axis and q-axis of the parallel side; on the parallel side, calculate the difference between the setpoint current and the actual current on the d-axis and q-axis of the parallel side, and superimpose the grid voltage feedforward and DC bus midpoint potential balance correction on the parallel side, and obtain the parallel side modulation wave corresponding to substation 1 through inverse Park transformation; process the parallel side modulation wave and output the drive signal to control the power devices on the parallel side; Obtain the given values ​​of active and reactive power, obtain the actual feedback current on the series side and the grid voltage of grid 2, and calculate the actual active and reactive power on the series side; calculate the active power and active power deviation, and obtain the current given values ​​of the d-axis and q-axis on the series side through a PI controller; process the actual feedback current on the series side to obtain the orthogonal component of the feedback current on the series side; use the phase of grid 1 as a reference to perform coordinate transformation on the orthogonal component of the feedback current on the series side to obtain the actual current on the d-axis and q-axis of the series side; calculate the current deviation on the parallel side, input it into the PI controller and superimpose the voltage feedforward compensation amount on the series side to obtain the modulation wave on the series side; process the modulation wave on the series side and output the drive signal to control the power devices on the series side; Obtain the grid parameters on both the parallel and series sides, and determine whether transformer substation 1 and transformer substation 2 meet the synchronization conditions. If they do, issue a closing command to close the transformer substation interconnection circuit breaker between transformer substation 1 and transformer substation 2. If they do not meet the conditions, readjust the voltage and phase output of the series compensation capacitor.

2. The control strategy for a two-arm power flow regulator according to claim 1, characterized in that, The steps for generating the parallel-side modulated wave are as follows: Obtain the grid voltage corresponding to grid 1 Generate the modulated wave at the parallel port. ; Obtained via SOGI Voltage components corresponding to the α-axis and β-axis and ; The phase of power grid 1 is obtained through a PLL phase-locked loop. ; Obtain the actual voltage of the DC bus Obtain the DC bus voltage setpoint. Calculate the voltage difference on the parallel side, and obtain the given value of the d-axis current through a PI controller. ; Obtain the given value of reactive power corresponding to grid 1 Calculate the given value of the q-axis current. ; Obtain the actual compensation current corresponding to power grid 1 Through SOGI, we obtain Current components along the α and β axes and ; In phase Based on, for and Perform the Park transformation to obtain the actual currents along the d-axis and q-axis. and ; calculate and as well as and The difference is used to obtain the active current deviation on the parallel side. With reactive current deviation ,Will and Input to the PI controller to obtain the regulated voltages corresponding to the d-axis and q-axis on the parallel side. and ; exist and Based on this, the total regulating voltage of the d-axis and q-axis is obtained by superimposing the grid voltage feedforward component and the potential balance correction at the DC bus midpoint. and .

3. The control strategy for a two-arm power flow regulator according to claim 2, characterized in that, The subsequent steps for generating the parallel-side modulated wave are as follows: right and Perform an inverse Park transform to obtain the modulated wave on the parallel side. ; According to the modulation wave on the parallel side of power grid 1 Two carrier signals are generated to obtain the upper carrier. With download wave ; Modulated wave on the parallel side Standardize and compare the modulated waves point by point. The switching states of power switches Q1, Q2, Q3, and Q4 are determined by the instantaneous values ​​of the uplink and downlink waves. When the modulated wave >Upcarrier When port A1 outputs a positive level, Q1 and Q2 are turned on, and Q3 and Q4 are turned off; Current carrier <Modulated wave <Upcarrier> When port A1 outputs a zero level, Q2 and Q3 are turned on, and Q1 and Q4 are turned off; When the modulated wave <Download Wave When port A1 outputs a negative level, Q3 and Q4 are turned on, and Q1 and Q2 are turned off. When the modulated wave The instantaneous values ​​of the uplink and downlink waves are equal, resulting in a zero-level output. In modulated wave The instantaneous value and the upcarrier When the instantaneous value crosses the boundary, a dead zone is inserted; Based on the comparison results between the modulation wave on the parallel side and the uplink and downlink waves, a PWM pulse sequence is generated to control the power switch transistor on the parallel side of phase A.

4. The control strategy for a two-arm power flow regulator according to claim 2, characterized in that, The calculation steps for the potential balance correction between the grid voltage feedforward component and the DC bus midpoint are as follows: Calculate grid voltage feedforward: In phase Based on, for and Perform a Park transform to obtain the grid voltage feedforward components along the d-axis and q-axis. and ; Calculate the potential balance correction at the midpoint of the DC bus: Obtain the DC voltage DC voltage Calculate DC voltage deviation ; Will Input to the PI controller to obtain the DC bus midpoint potential balance correction. .

5. The control strategy for a two-arm power flow regulator according to claim 3, characterized in that, The specific steps for inserting a dead zone are as follows: Operating condition 11: Positive level → Zero level. Before the level state switch: Q1 is on, Q2 is on, Q3 is off, Q4 is off. Q3 Insert dead zone After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off; Operating condition 12: Zero level → Positive level. Before the level state switch: Q1 is off, Q2 is on, Q3 is on, Q4 is off. Q1 Insert dead zone After the level state switch: Q1 is turned on, Q2 is turned on, Q3 is turned off, and Q4 is turned off; In modulated wave Instantaneous value and download wave When the instantaneous value crosses the boundary, a dead zone is inserted; Operating condition 21: Zero level → Negative level. Before the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off. Q4 Insert dead zone After the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on; Operating condition 22: Negative level → Zero level. Before the level state switch: Q1 is off, Q2 is off, Q3 is on, and Q4 is on. Q2 Insert dead zone After the level state switch: Q1 is off, Q2 is on, Q3 is on, and Q4 is off.

6. The control strategy for a two-arm power flow regulator according to claim 1, characterized in that, The steps for generating the series-modulated wave are as follows: Obtain the grid voltage of grid 2 Generate the modulated wave at the series port. ; Obtained via SOGI α-axis and β-axis voltage components and ; Obtain the actual current of the series filter inductor corresponding to power grid 2. Obtained through SOGI α-axis and β-axis current components and ; Calculate the actual active power of power grid 2 With actual reactive power ; Obtain the given value of the active power corresponding to grid 2. With the given value of reactive power ; Calculate the active power deviation on the series side Deviation from reactive power ; Will and Input to the PI controller to obtain the d-axis current setpoint on the series side. With q-axis current setpoint ; Obtain the phase of power grid 1 , in phase As a reference, for current and Perform the Park transformation to obtain the actual d-axis current on the series side. With actual q-axis current ; Calculate the series-side voltage feedforward: Obtain the voltage across the series-side filter capacitor. Using a SOGI second-order generalized integrator to process voltage The voltage components along the α-axis and β-axis were obtained. and ; In phase Based on, for and Perform a Park transform to obtain the voltage feedforward components on the d-axis and q-axis of the series side. and ; Calculate the active current deviation on the series side Deviation from reactive current ,Will and Input to the PI controller to obtain the regulated voltages corresponding to the d-axis and q-axis on the series side. and ; exist and Based on the series-side voltage feedforward, the total regulating voltage of the series-side d-axis and q-axis is obtained. and ; right and Perform an inverse Park transform to obtain the modulated wave on the series side. .

7. The control strategy for a two-arm power flow regulator according to claim 6, characterized in that, The subsequent steps for generating the series-modulated wave are as follows: According to the series side modulation wave Generate carrier ; Modulated wave on the series side Standardize and compare the series-modulated waves point by point. With carrier The instantaneous value is used to determine the switching states of power switches Q5 and Q6: When the modulated wave > Carrier When port A2 outputs a positive level, Q5 is turned on and Q6 is turned off; When the modulated wave <carrier> When port A2 outputs a negative level, Q5 is off and Q6 is on; When the modulated wave With carrier If they are equal, then output a negative level; Set dead zone In modulated wave instantaneous value and carrier When the instantaneous value crosses the boundary, a dead zone is inserted on the series side; Based on the modulated wave and carrier wave on the series side The comparison results are used to generate PWM pulse sequences for controlling the two power switches on the series side.

8. The control strategy for a two-arm power flow regulator according to claim 7, characterized in that, The steps for inserting a dead zone on the series side are as follows: Operating condition A: Positive level → Negative level. Before the level state switch: Q5 is on, Q6 is off; Q6 Insertion Dead Zone After the level state switch: Q5 is off, Q6 is on; Operating condition B: Negative level → Positive level. Before the level state switch: Q5 is off, Q6 is on. Q5 Insert Dead Zone After the level state switch: Q5 is turned on, and Q6 is turned off.

9. The control strategy for a two-arm power flow regulator according to claim 1, characterized in that, The steps to readjust the output voltage and phase of the series compensation capacitor are as follows: Obtain the corresponding grid voltages for transformer substation 1 and transformer substation 2 respectively, and calculate the voltage amplitude difference and phase difference for each phase of the two transformer substations. Compare the amplitude difference and phase difference with the preset synchronization threshold: Scenario 1: If all amplitude differences and phase differences do not exceed the synchronization threshold, it means that transformer area 1 and transformer area 2 meet the synchronization conditions. A closing command is issued to close the transformer area interconnection circuit breaker between transformer area 1 and transformer area 2, thus completing the flexible loop closure of the two transformer areas. Scenario 2: If Scenario 1 is not met, then the new power setting is calculated based on the voltage deviation between the two transformer areas; The grid voltage of grid 1 Converted into d-axis and q-axis voltage components and ; With the phase of power grid 1 Using the grid voltage of grid 2 as a reference... Transform to the two-phase rotating coordinate system corresponding to power grid 1 to obtain and ; Calculate the d-axis and q-axis voltage deviations of the two transformer areas. and ; Each and Input to the PI controller to obtain the new active power command. With the new reactive power given ; use and Replace the original active and reactive power inputs on the series side, and readjust the voltage and phase output of the corresponding series compensation capacitor in grid 2.

10. A two-arm power flow regulator, applicable to the control strategy of the two-arm power flow regulator according to any one of claims 1-9, characterized in that, The regulator includes: Parallel side arm and series side arm; The parallel bridge arm includes: power switches Q1, Q2, Q3, Q4, and clamping transistor D. a1 D a2 Shared DC bus capacitor C Bus1 C Bus2 AC output port A1, parallel side filter inductor L f1 ; Power switching transistors Q1, Q2, Q3, and Q4 are connected in series from top to bottom. The collector of Q1 is connected to the DC positive bus, and the emitter of Q2 is led out to the AC output port A1 of the parallel side bridge arm. D a1 The cathode is connected above the AC output port A1, and the anode is connected to the DC midpoint O; D a2 The anode is connected below the AC output port A1, and the cathode is connected to the DC midpoint O; Parallel side filter inductor L f1 One end is connected to port A1, and the other end is connected to the power grid phase line L; The tandem side arms include: Power switching transistors Q5 and Q6 share the same DC bus capacitor C. Bus1 C Bus2 The AC output node is A2, and the series-side filter inductor is L. f2 Series-side filter capacitor C f1 ; C Bus1 The upper end is connected to the DC positive bus, and the lower end is connected to C. Bus2 The upper part, C Bus2 The lower end is connected to the DC negative busbar; Q5 is used as the upper transistor, and Q6 is used as the lower transistor. The collector of Q5 is connected to the positive DC bus, and the emitter of Q6 is connected to the negative DC bus. The emitter of Q5 and the collector of Q6 are connected to form the AC output port A2 of the series side bridge arm. The parallel-side bridge arm is connected in parallel to the power grid 1, and the series-side bridge arm and the series-side filter inductor L f2 With series-side filter capacitor C f1 The entire system is connected in series between power grid 1 and power grid 2.

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