Flexible multi-state switch compensation method under unbalanced load

Abstract

The application discloses a flexible multi-state switch compensation method under unbalanced load. Electrical operation parameters at a flexible multi-state switch port are collected, and positive sequence components, negative sequence components and zero sequence components are obtained by processing the electrical operation parameters. After obtaining a voltage phase angle according to the positive sequence components, the positive sequence components are transformed into a positive sequence rotating coordinate system, and the negative sequence components are transformed into a negative sequence rotating coordinate system. Positive and negative sequence double-current inner loop feedforward decoupling control is performed, a direct-current current reference value is obtained based on an outer loop PI, double-current inner loop feedforward decoupling control is performed, a modulation reference voltage is generated, and the actual voltage of a capacitor of a Buck type active power decoupling circuit, a reference voltage and a double-frequency ripple component are processed and calculated to obtain an inductor current reference value. The inductor current reference value outputs a PWM driving signal to control absorption or release of double-frequency pulsating power. The application can improve three-phase imbalance of a distribution network feeder and improve the stability of the direct-current side voltage of the flexible multi-state switch.

Description

Technical Field

[0001] This invention specifically relates to a flexible multi-state switch compensation method under unbalanced load. Background Technology

[0002] With the widespread integration of distributed energy resources and single-phase loads into low-voltage distribution networks, the problem of three-phase imbalance in feeders has become increasingly prominent, bringing many adverse effects to the operation of the distribution network. Flexible multi-state switches (FMSS), relying on the rapid regulation capabilities of power electronic converters, can not only achieve flexible power flow regulation between feeders but also compensate for unbalanced currents in the system, providing an effective technical means to solve the aforementioned three-phase imbalance problem.

[0003] However, existing unbalanced compensation methods mostly focus on suppressing negative sequence current on the AC side, and usually do not adequately address the second-harmonic pulsating power caused by the instantaneous power imbalance transmitted to the DC side during the compensation process. This direct application of second-harmonic pulsating power to the DC bus will directly lead to second-harmonic ripple in the DC bus voltage, affecting the lifespan of the DC capacitor and the stable operation of the flexible multi-state switch. Therefore, this application proposes a flexible multi-state switch compensation method under unbalanced loads to solve the above problems. Summary of the Invention

[0004] Purpose of the invention: To provide a flexible multi-state switch compensation method under unbalanced load, which solves the above-mentioned problems existing in the prior art.

[0005] Technical solution: A flexible multi-state switch compensation method under unbalanced load, comprising the following steps:

[0006] Step 1: Collect the three-phase load voltage, three-phase load current, three-phase line current, DC bus voltage, and active and reactive power output from the converter at the flexible multi-state switch port. Convert the three-phase load voltage and three-phase load current to... The coordinate system was used, and the positive-order components, negative-order components, and zero-order components were obtained by processing it with a double second-order generalized integrator.

[0007] Step 2: Obtain the positive sequence component and build a DSOGI-PLL phase-locked loop to obtain the voltage phase angle. ;

[0008] Step 3: Based on the voltage phase angle Transform the positive-sequence components to a positive-sequence rotating coordinate system and the negative-sequence components to a negative-sequence rotating coordinate system;

[0009] Step 4: Using the negative sequence component as the unbalanced compensation current reference, perform positive and negative sequence dual current inner loop feedforward decoupling control respectively, and obtain the DC current reference value based on the outer loop PI controller.

[0010] Step 5: Obtain the current reference value in the negative sequence rotating coordinate system as the compensation quantity, perform dual current inner loop feedforward decoupling control, and generate a flexible multi-state switch AC side modulation reference voltage.

[0011] Step 6: Extract the second harmonic ripple component from the DC bus voltage deviation, convert the second harmonic ripple component into second harmonic pulsating power based on the power formula, and buffer the second harmonic pulsating power.

[0012] Step 7: Collect the difference between the actual capacitor voltage and the capacitor reference voltage of the Buck-type active power decoupling circuit APD to obtain the capacitor voltage deviation. Generate a DC current reference value based on the capacitor voltage deviation, and generate an AC compensation current reference value based on the second harmonic ripple component. Superimpose the DC current reference value and the AC compensation current reference value to obtain the inductor current reference value of the Buck-type active power decoupling circuit APD. Generate a PWM drive signal based on the inductor current reference value to drive the Buck-type active power decoupling circuit APD to absorb or release the second harmonic pulsating power.

[0013] Preferably, in step 1, the process of obtaining the positive-order components and the negative-order components is as follows:

[0014] Step 1.1: Use Clark transformation to convert the three-phase load voltage and three-phase load current to... In a stationary coordinate system;

[0015] Step 1.2: Use a double second-order generalized integrator to... In a stationary coordinate system, the three-phase load voltage is decomposed into positive sequence voltage components, negative sequence voltage components, and zero sequence voltage components;

[0016] Step 1.3: Use a dual second-order generalized integrator to decompose the three-phase load current into positive-sequence current components, negative-sequence current components, and zero-sequence current components.

[0017] Preferably, the transformation formula for transforming the positive-sequence components to the positive-sequence rotating coordinate system is as follows:

[0018] ;

[0019] In the formula, Indicates the voltage phase angle. Represents the Park transformation matrix. Represents the inverse transformation matrix of Park;

[0020] The transformation formula for transforming negative-order components to a negative-order rotating coordinate system is as follows:

[0021] .

[0022] Preferably, in step 2, the voltage phase angle The calculation process is as follows:

[0023] Obtain the positive-sequence voltage component and negative-sequence voltage component from step 1, transform them to a synchronous rotating coordinate system using Park transform, and obtain the positive-sequence voltage component. shaft and Axis voltage components , The transformation formula is as follows:

[0024]

[0025] In the formula: , These represent the positive sequence load voltages in the two-phase stationary coordinate system. shaft and Axial components, Indicates the voltage phase angle;

[0026] In ascending order Axis voltage components As a phase detection error signal, it is input to the PI controller for closed-loop adjustment calculation to obtain the angular frequency deviation. :

[0027]

[0028] In the formula: This represents the proportional adjustment parameter of the phase-locked loop PI controller. This represents the integral adjustment parameter of the phase-locked loop PI controller. Represents the Laplace transform operator;

[0029] angular frequency deviation With the rated resonant angular frequency of the power grid The voltage phase angle is obtained by superposition and then integration. :

[0030]

[0031] In the formula: Indicates the resonant angular frequency. Represents the time infinitesimal element;

[0032] The calculated voltage phase angle Then, the feedback is sent to the Park transformation stage to form a closed-loop phase-locked loop, and the output is used as the reference phase for subsequent positive and negative sequence coordinate transformations.

[0033] Preferably, in step 4, the negative sequence component is used as a reference quantity for the unbalanced compensation current. The process of feedforward decoupling control for the cross-coupling term of the current inner loop is as follows:

[0034] Step 4.1: Obtain the phase angle The positive sequence voltage component obtained by the separation of the two second-order generalized integrators is used as the input of the phase-locked loop of the synchronous rotating coordinate system to suppress the phase double frequency fluctuation caused by the three-phase imbalance.

[0035] Step 4.2: Extract the actual and reference values ​​of DC bus voltage, active power and reactive power, and generate positive sequence d-axis current reference value and positive sequence q-axis current reference value through the outer loop PI controller;

[0036] Step 4.3: Based on the positive sequence voltage component of the DSOGI-PLL phase-locked loop input, obtain the accurate positive and negative sequence coordinate transformation and the phase of the current inner loop control;

[0037] Step 4.4: Using the negative sequence component of the load current obtained by DSOGI separation as the reference quantity of the unbalanced compensation current, establish positive and negative sequence dual current inner loop control models in the positive sequence rotating coordinate system and the negative sequence rotating coordinate system respectively, and perform feedforward decoupling compensation on the cross-coupling terms of the current inner loop.

[0038] Step 4.5: Extract the negative sequence component from the load current as a reference quantity for unbalanced compensation current, and use the inner loop feedforward decoupling to cancel the inherent coupling.

[0039] Preferably, the process of obtaining the modulation reference voltage in step 5 is as follows:

[0040] Step 5.1: Obtain the current reference value in the negative sequence rotating coordinate system as the compensation quantity and transform it to the positive sequence rotating coordinate system to obtain the transformed current reference value. The formula for the coordinate system transformation matrix is ​​as follows:

[0041] ;

[0042] In the formula: This represents the coordinate transformation matrix from a negative-order rotating coordinate system to a positive-order rotating coordinate system. Indicates the voltage phase angle;

[0043] Step 5.2: Obtain the superposition of the transformation current reference value and the positive sequence control quantity to obtain the AC side modulation reference voltage of the flexible multi-state switch;

[0044] Step 5.3: Input the AC side modulation reference voltage of the flexible multi-state switch into the modulation circuit and apply negative sequence compensation current.

[0045] Preferably, in step 7, the process by which the Buck-type active power decoupling circuit (APD) absorbs or releases the second harmonic pulsating power is as follows:

[0046] Step 7.1: The Buck-type active power decoupling circuit (APD) includes a decoupling inductor. Decoupling capacitors and switching transistors, among which, decoupling inductors With decoupling capacitor Series, decoupling capacitors The voltage is lower than the DC bus voltage, reducing the voltage stress on the switching transistor;

[0047] Step 7.2, based on decoupling capacitor voltage The second harmonic power and the fourth harmonic component are calculated from the second harmonic pulsation power of the buffer.

[0048] Step 7.3: When the second harmonic power generated by the Buck-type active power decoupling circuit APD has the same amplitude and opposite phase to the second harmonic pulsating power transmitted from the AC side to the DC side, the second harmonic ripple of the DC bus can be suppressed.

[0049] Preferably, the calculation process for the second harmonic power and the fourth harmonic component is as follows:

[0050] First, preset the decoupling capacitor current. With decoupling inductor current They are equal, as shown in the following formula:

[0051] ;

[0052] In the formula: This represents the decoupling capacitor current. This indicates the decoupling inductor current. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates the phase of the decoupling capacitor current;

[0053] Since the decoupling capacitor voltage consists of an AC component and a DC bias component, the calculation formula for the decoupling capacitor voltage is as follows:

[0054] ;

[0055] In the formula: This represents the actual instantaneous voltage across the decoupling capacitor. This indicates the capacitance value of the decoupling capacitor. Describes the differential operator. Indicates time, This represents the DC bias voltage component of the decoupling capacitor. Indicates the angular frequency of the power grid. This indicates the current amplitude of the APD circuit. This represents the decoupling capacitor current;

[0056] The buffer power in a Buck-type active power decoupling circuit (APD) consists of capacitor power and inductor power, and the formula for calculating the buffer power is as follows:

[0057] ;

[0058] In the formula, This indicates the instantaneous total buffer power of the Buck-type active power decoupling circuit (APD). This represents the instantaneous power absorbed or released by the decoupling capacitor. This represents the instantaneous power absorbed or released by the decoupling inductor. This represents the actual instantaneous voltage across the decoupling capacitor. This represents the decoupling capacitor current. This represents the instantaneous voltage of the decoupling inductor. To represent the decoupled inductor current, we can obtain:

[0059] ;

[0060] The formulas for calculating the second harmonic power and the accompanying fourth harmonic component are as follows:

[0061] Second harmonic power component The calculation formula is as follows:

[0062] ;

[0063] In the formula: Represents the second harmonic power component. This represents the voltage across the decoupling energy storage capacitor in the Buck-type active power decoupling circuit (APD). This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates the fundamental angular frequency of the power grid. Indicates time, Indicates the voltage phase angle;

[0064] Fourth harmonic component The calculation formula is as follows:

[0065] ;

[0066] In the formula: This represents the fourth harmonic power component. Indicates decoupling inductance. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates time, Indicates the voltage phase angle;

[0067] The total buffer power of the Buck-type active power decoupling circuit (APD) is the sum of the second harmonic power and the fourth harmonic component. .

[0068] Beneficial effects: This invention relates to a flexible multi-state switch compensation method under unbalanced load. It uses DSOGI to separate the positive and negative sequence components of unbalanced voltage and current, which can accurately obtain the negative sequence component of the load current under three-phase unbalanced conditions, avoiding the problem of insufficient extraction accuracy of traditional direct detection methods under voltage distortion or unbalanced conditions.

[0069] The DSOGI-PLL phase-locked loop method based on positive-sequence voltage components can weaken the impact of negative-sequence voltage on the phase-locked loop, improve the accuracy of grid synchronization phase angle extraction, provide a stable phase reference for unbalanced compensation control under positive and negative sequence dual coordinate systems, and cooperate with the positive and negative sequence dual current inner loop control method to use the negative-sequence component of the load current as the compensation reference quantity, so that the flexible multi-state switch port actively injects negative-sequence compensation current, thereby making the three-phase current on the feeder side tend to be balanced and improving the problem of unbalanced distribution of three-phase active and reactive power.

[0070] A Buck-type active power decoupling circuit (APD) is introduced at the DC port of the flexible multi-state switch to buffer the DC-side second-harmonic pulsating power generated during the unbalance compensation process, thereby preventing the second-harmonic pulsating power from directly acting on the DC bus capacitor and reducing the DC bus second-harmonic voltage ripple.

[0071] Combining AC-side unbalance compensation control with DC-side second harmonic ripple suppression control can improve the DC-side voltage stability of flexible multi-state switches while improving the three-phase imbalance of distribution network feeders, thereby enhancing the operational reliability and power quality management capabilities of flexible multi-state switches under unbalanced load conditions. Attached Figure Description

[0072] Figure 1 This is a block diagram of the three-phase load imbalance compensation control of the present invention;

[0073] Figure 2 This is a circuit diagram of the Buck-type active power decoupling circuit (APD) of the present invention.

[0074] Figure 3 This is a control block diagram of the second harmonic ripple suppression strategy of the present invention;

[0075] Figure 4 This is a comparison diagram of the phase-locked loop waveforms of the DSOGI-PLL of the present invention and a conventional PLL;

[0076] Figure 5 The current transmitted through the power grid before the imbalance compensation of this invention;

[0077] Figure 6 The active power transmitted by the power grid before the imbalance compensation of this invention;

[0078] Figure 7 The reactive power transmitted by the power grid before the imbalance compensation of this invention;

[0079] Figure 8 The unbalanced current transmitted through the power grid after compensation according to the present invention;

[0080] Figure 9 The active power transmitted by the power grid after imbalance compensation according to the present invention;

[0081] Figure 10 The present invention provides the power grid transmission reactive power after imbalance compensation.

[0082] Figure 11 The DC bus voltage before frequency doubling suppression in this invention;

[0083] Figure 12 This refers to the DC bus voltage after frequency doubling suppression according to the present invention. Detailed Implementation

[0084] like Figures 1 to 12 As shown, this invention provides a technical solution: a flexible multi-state switch compensation method under unbalanced load. This embodiment uses a VSC port in a three-port or multi-port FMSS as an example for illustration. Other ports can adopt the same or equivalent compensation process, specifically including the following steps:

[0085] Step 1: Collect the three-phase load voltage, three-phase load current, three-phase line current, DC bus voltage, and active and reactive power output from the converter at the flexible multi-state switch port. The preset three-phase unbalanced load current is:

[0086] ;

[0087] In the formula, This represents the load current of phase a. This represents the amplitude of the load current in phase a. This represents the instantaneous phase angle of the load current in phase a. This represents the phase b load current. This indicates the amplitude of the phase b load current. This represents the instantaneous phase angle of the b-phase load current. This represents the c-phase load current. This represents the magnitude of the c-phase load current. This represents the instantaneous phase angle of the c-phase load current, transforming the three-phase load current to... A coordinate system in which the three-phase load voltage is transformed in the same way to coordinate system

[0088] The positive-order component, negative-order component, and zero-order component are obtained by processing the sample using a double second-order generalized integrator. The process for obtaining the positive-order component and the negative-order component is as follows:

[0089] Step 1.1: Use Clark transformation to convert the three-phase load voltage and three-phase load current to... In a stationary coordinate system, the transformation formula is as follows:

[0090] ;

[0091] In the formula, Represents load current Axial components, Represents the Clark transformation matrix. This represents the phase b load current. This represents the c-phase load current;

[0092] Step 1.2: Use a double second-order generalized integrator to... The three-phase load voltage in the stationary coordinate system is decomposed into positive-sequence voltage components, negative-sequence voltage components, and zero-sequence voltage components. The calculation process is as follows: After completing... After the stationary coordinate system transformation, DSOGI generates in-phase components. and orthogonal components The transfer function can be expressed as follows:

[0093] ;

[0094] ;

[0095] In the formula: The transfer function representing the in-phase component of DSOGI. Indicates the resonant angular frequency. Represents the system gain coefficient. Represents the Laplace transform operator. The transfer function representing the orthogonal components of DSOGI;

[0096] When the resonant angular frequency With grid angular frequency When equal, DSOGI can perform error-free tracking of a given fundamental signal, and Compared to Lag Using this orthogonal relation, The positive-sequence and negative-sequence current components in the coordinate system satisfy the following calculation formula:

[0097] ;

[0098] ;

[0099] In the formula: Represents positive sequence load current Axial components, Represents positive sequence load current Axial components, This indicates a phase shifter with a 90° lead. This indicates a phase shifter with a 90° lag. Represents load current Axial components, Represents load current Axial components;

[0100] Step 1.3: Using a dual second-order generalized integrator, the three-phase load current is decomposed into positive-sequence current components, negative-sequence current components, and zero-sequence current components. Based on the content of Step 1.2, the positive-sequence voltage component can be obtained similarly. , and negative sequence voltage components , ;

[0101] Step 1.4: The formulas for calculating the active and reactive power output of the converter are as follows:

[0102] ;

[0103] In the formula: This represents the instantaneous active power output of the converter. This represents the load voltage of phase a. This represents the load current of phase a. This represents the voltage of phase b of the load. This represents the phase b load current. This represents the voltage of phase c of the load. This represents the c-phase load current. The instantaneous reactive power output of the converter is represented by the formula above. Substituting the positive-sequence, negative-sequence, and zero-sequence components into the formula, it can be seen that unbalanced loads will cause both active and reactive power to produce second-harmonic pulsating components. The active power can be written as the sum of the average component and the pulsating component, as shown in the following formula:

[0104] ;

[0105] In the formula, This represents the average component of active power. Indicates the magnitude of the positive sequence load voltage. Indicates the magnitude of the positive sequence load current. This represents the initial phase angle difference between the positive-sequence load voltage and the positive-sequence load current. Indicates the magnitude of negative sequence load voltage. This indicates the magnitude of the negative sequence load current. This represents the initial phase angle difference between the negative-sequence load voltage and the negative-sequence load current. Indicates the zero-sequence load voltage amplitude. Indicates the magnitude of the zero-sequence load current. This represents the initial phase angle difference between the zero-sequence load voltage and the zero-sequence load current. This represents the second harmonic pulsation phase angle under the action of positive-sequence voltage and negative-sequence current. This represents the second harmonic pulsation phase angle under the action of negative sequence voltage and positive sequence current. This represents the phase angle of the second harmonic pulsation under the action of zero-sequence voltage and zero-sequence current.

[0106] Reactive power can also be written as the sum of the average component and the pulsating component:

[0107] ;

[0108] In the formula, Represents the average component of reactive power. This represents the second harmonic pulsation component of instantaneous reactive power.

[0109] Step 2: Obtain the positive sequence component and build a DSOGI-PLL phase-locked loop to obtain the voltage phase angle. Among them, voltage phase angle The calculation process is as follows:

[0110] Obtain the positive-sequence voltage component and negative-sequence voltage component from step 1, transform them to a synchronous rotating coordinate system using Park transform, and obtain the positive-sequence voltage component. shaft and Axis voltage components , The transformation formula is as follows:

[0111]

[0112] In the formula: , These represent the positive sequence load voltages in the two-phase stationary coordinate system. shaft and Axial components, Indicates the voltage phase angle;

[0113] In ascending order Axis voltage components As a phase detection error signal, it is input to the PI controller for closed-loop adjustment calculation to obtain the angular frequency deviation. :

[0114]

[0115] In the formula: This represents the proportional adjustment parameter of the phase-locked loop PI controller. This represents the integral adjustment parameter of the phase-locked loop PI controller. Represents the Laplace transform operator;

[0116] angular frequency deviation With the rated resonant angular frequency of the power grid The voltage phase angle is obtained by superposition and then integration. :

[0117]

[0118] In the formula: Indicates the resonant angular frequency. Represents the time infinitesimal element;

[0119] The calculated voltage phase angle Then, the feedback is sent to the Park transformation stage to form a closed-loop phase-locked loop, and the output is used as the reference phase for subsequent positive and negative sequence coordinate transformations;

[0120] Step 3: Based on the voltage phase angle The positive-sequence components are transformed to a positive-sequence rotating coordinate system, and the negative-sequence components are transformed to a negative-sequence rotating coordinate system. The transformation formula for the positive-sequence components to the positive-sequence rotating coordinate system is as follows:

[0121] ;

[0122] In the formula, Indicates the voltage phase angle. Represents the Park transformation matrix. Represents the inverse transformation matrix of Park;

[0123] The transformation formula for transforming negative-order components to a negative-order rotating coordinate system is as follows:

[0124] .

[0125] Step 4: Using the negative sequence component as the unbalanced compensation current reference, perform positive and negative sequence dual-current inner loop feedforward decoupling control respectively. Based on the outer loop PI controller, obtain the DC current reference value. The process of feedforward decoupling control for the cross-coupling term of the current inner loop is as follows:

[0126] Step 4.1: Obtain the phase angle The positive sequence voltage component obtained by the separation of the two second-order generalized integrators is used as the input of the phase-locked loop of the synchronous rotating coordinate system to suppress the phase double frequency fluctuation caused by the three-phase imbalance.

[0127] Step 4.2: Extract the actual and reference values ​​of DC bus voltage, active power, and reactive power. Generate positive-sequence d-axis current reference values ​​and positive-sequence q-axis current reference values ​​via the outer-loop PI controller. Based on Kirchhoff's voltage law, filter inductors... Equivalent resistance Load side voltage and converter output voltage The following calculation formula applies between them:

[0128] ;

[0129] In the formula: This represents the voltage drop across the filter inductor of phase a. This represents the voltage drop across the equivalent resistance of phase a. This represents the voltage on the load side of phase a. This represents the output voltage of phase a of the converter. This represents the voltage drop across the b-phase filter inductor. This represents the voltage drop across the equivalent resistance of phase b. This represents the voltage on the load side of phase b. This represents the output voltage of phase b of the converter. This represents the voltage drop across the c-phase filter inductor. This represents the voltage drop across the equivalent resistance of phase c. This represents the voltage on the load side of phase c. This represents the output voltage of phase c of the converter;

[0130] In the positive-sequence rotating coordinate system, the calculation formula is as follows:

[0131] ;

[0132] In the formula: This represents the voltage drop across the d-axis filter inductor in the positive-sequence rotating coordinate system. This represents the d-axis component of the load-side voltage in the positive-sequence rotating coordinate system. This represents the d-axis component of the converter output voltage in a positive-sequence rotating coordinate system. This represents the voltage drop across the equivalent resistance along the d-axis in a positive-sequence rotating coordinate system. Indicates the fundamental angular frequency of the power grid. This represents the q-axis filter inductance flux linkage in a positive-sequence rotating coordinate system. This represents the voltage drop across the q-axis filter inductor in the positive-sequence rotating coordinate system. This represents the q-axis component of the load-side voltage in the positive-sequence rotating coordinate system. This represents the q-axis component of the converter output voltage in the positive-sequence rotating coordinate system. This represents the voltage drop across the equivalent resistance along the q-axis in a positive-sequence rotating coordinate system. This represents the d-axis filter inductance flux linkage in the positive-sequence rotating coordinate system.

[0133] In a negative-order rotating coordinate system, since the rotation directions are opposite and the signs of the cross terms are opposite, the calculation formula is as follows:

[0134] ;

[0135] In the formula: This represents the voltage drop across the d-axis filter inductor in the negative-sequence rotating coordinate system. This represents the d-axis component of the load-side voltage in a negative-sequence rotating coordinate system. This represents the d-axis component of the converter output voltage in a negative-sequence rotating coordinate system. This represents the voltage drop across the equivalent resistance along the d-axis in a negative-sequence rotating coordinate system. Indicates the fundamental angular frequency of the power grid. This represents the q-axis filter inductance flux linkage in the negative-order rotating coordinate system. This represents the voltage drop across the q-axis filter inductor in the negative-sequence rotating coordinate system. This represents the q-axis component of the load-side voltage in a negative-sequence rotating coordinate system. This represents the q-axis component of the converter output voltage in a negative-sequence rotating coordinate system. This represents the voltage drop across the equivalent resistance along the q-axis in a negative-sequence rotating coordinate system. This represents the d-axis filter inductance flux linkage in a negative-order rotating coordinate system.

[0136] Step 4.3: Based on the positive sequence voltage component of the DSOGI-PLL phase-locked loop input, obtain the accurate positive and negative sequence coordinate transformation and the phase of the current inner loop control;

[0137] Step 4.4: Using the negative-sequence component of the load current obtained from DSOGI separation as the reference quantity for unbalanced compensation current, establish positive and negative sequence dual-current inner-loop control models in both positive and negative sequence rotating coordinate systems, and perform feedforward decoupling compensation on the cross-coupling terms of the current inner loop. The positive sequence current inner-loop control equation is as follows:

[0138] ;

[0139] In the formula: This represents the d-axis component of the converter output modulation reference voltage in a positive-sequence rotating coordinate system. This indicates the proportional adjustment parameter of the inner-loop PI controller for the current. This represents the integral adjustment parameter of the inner-loop PI controller. Represents the Laplace transform operator. This represents the d-axis current reference value given by the inner loop of the positive sequence current. This represents the d-axis component of the actual converter current in the positive-sequence rotating coordinate system. This represents the d-axis component of the load-side voltage in the positive-sequence rotating coordinate system. Indicates the fundamental angular frequency of the power grid. This represents the q-axis filter inductance flux linkage in a positive-sequence rotating coordinate system. This represents the q-axis component of the converter output modulation reference voltage in the positive-sequence rotating coordinate system. This represents the q-axis current reference value given by the inner loop of the positive sequence current. This represents the q-axis component of the actual converter current in the positive-sequence rotating coordinate system. This represents the d-axis filter inductance flux linkage in the positive-sequence rotating coordinate system.

[0140] The inner-loop control equation for negative-sequence current is:

[0141] ;

[0142] In the formula: This represents the d-axis component of the converter output modulation reference voltage in a negative-sequence rotating coordinate system. This represents the q-axis component of the converter output modulation reference voltage in a negative-sequence rotating coordinate system.

[0143] Step 4.5: Extract the negative sequence component from the load current as a reference quantity for unbalanced compensation current, and use the inner loop feedforward decoupling to cancel the inherent coupling.

[0144] Step 5: Obtain the current reference value in the negative-sequence rotating coordinate system as the compensation quantity. Perform positive and negative-sequence dual-current inner-loop feedforward decoupling control in both the positive-sequence and negative-sequence rotating coordinate systems. Transform the compensation quantity in the negative-sequence rotating coordinate system into the positive-sequence control quantity in the positive-sequence coordinate system and superimpose them to generate the AC-side modulation reference voltage of the flexible multi-state switch. The generation process is as follows:

[0145] Step 5.1: Obtain the current reference value in the negative sequence rotating coordinate system as the compensation quantity and transform it to the positive sequence rotating coordinate system to obtain the transformed current reference value. The formula for the coordinate system transformation matrix is ​​as follows:

[0146] ;

[0147] In the formula: This represents the coordinate transformation matrix from a negative-order rotating coordinate system to a positive-order rotating coordinate system. Indicates the voltage phase angle;

[0148] Step 5.2: Obtain the superposition of the transformation current reference value and the positive sequence control quantity to obtain the AC side modulation reference voltage of the flexible multi-state switch;

[0149] Step 5.3: Input the AC side modulation reference voltage of the flexible multi-state switch into the modulation circuit and apply negative sequence compensation current.

[0150] Step 6: Extract the second harmonic ripple component from the DC bus voltage deviation, convert the second harmonic ripple component into second harmonic pulsating power based on the power formula, and buffer the second harmonic pulsating power through a Buck-type active power decoupling circuit (APD).

[0151] Step 7: The difference between the actual capacitor voltage and the capacitor reference voltage of the Buck-type active power decoupling circuit (APD) is calculated to obtain the capacitor voltage deviation. A DC current reference value is generated based on the capacitor voltage deviation, and an AC compensation current reference value is generated based on the second harmonic ripple component. The DC current reference value and the AC compensation current reference value are superimposed to obtain the inductor current reference value of the Buck-type active power decoupling circuit (APD). A PWM drive signal is then generated based on the inductor current reference value to cause the Buck-type active power decoupling circuit (APD) to absorb or release the second harmonic ripple power. The process of the Buck-type active power decoupling circuit (APD) absorbing or releasing the second harmonic ripple power is as follows:

[0152] Step 7.1: The Buck-type active power decoupling circuit (APD) includes a decoupling inductor. Decoupling capacitors and switching transistors, among which, decoupling inductors With decoupling capacitor Series, decoupling capacitors The voltage is lower than the DC bus voltage, reducing the voltage stress on the switching transistor;

[0153] Step 7.2, based on decoupling capacitor voltage The second harmonic power and fourth harmonic component are calculated from the second harmonic pulsation power of the buffer. The calculation process for the second harmonic power and fourth harmonic component is as follows:

[0154] First, preset the decoupling capacitor current. With decoupling inductor current They are equal, as shown in the following formula:

[0155] ;

[0156] In the formula: This represents the decoupling capacitor current. This indicates the decoupling inductor current. This indicates the current amplitude of the APD circuit. Indicates the phase of the decoupling capacitor current;

[0157] Since the decoupling capacitor voltage consists of an AC component and a DC bias component, the calculation formula for the decoupling capacitor voltage is as follows:

[0158] ;

[0159] In the formula: This represents the actual instantaneous voltage across the decoupling capacitor. This indicates the capacitance value of the decoupling capacitor. Describes the differential operator. Indicates time, This represents the DC bias voltage component of the decoupling capacitor. Indicates the fundamental angular frequency of the power grid. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. This represents the decoupling capacitor current;

[0160] The buffer power in a Buck-type active power decoupling circuit (APD) consists of capacitor power and inductor power, and the formula for calculating the buffer power is as follows:

[0161] ;

[0162] In the formula, This indicates the instantaneous total buffer power of the Buck-type active power decoupling circuit (APD). This represents the instantaneous power of the decoupling capacitor. This represents the instantaneous power of the decoupling inductor. This represents the actual instantaneous voltage across the decoupling capacitor. This represents the decoupling capacitor current. This represents the instantaneous voltage of the decoupling inductor. To represent the decoupled inductor current, we can obtain:

[0163] ;

[0164] The formulas for calculating the second harmonic power and the accompanying fourth harmonic component are as follows:

[0165] Second harmonic power component The calculation formula is as follows:

[0166] ;

[0167] In the formula: Represents the second harmonic power component. This represents the voltage across the decoupling energy storage capacitor in the Buck-type active power decoupling circuit (APD). This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates the fundamental angular frequency of the power grid. Indicates time, Indicates the voltage phase angle;

[0168] Fourth harmonic component The calculation formula is as follows:

[0169] ;

[0170] The total buffer power of the APD is the sum of the second harmonic power and the fourth harmonic component: .

[0171] In other words, the Buck-type active power decoupling circuit (APD) outputs second-harmonic power while also including a fourth-harmonic component. With proper parameter design, the amplitude of the fourth-harmonic component is small, and its impact on the DC bus is negligible. The appropriate parameter design is as follows: when the amplitude of the fourth-harmonic component is small and its impact on the DC bus is negligible, and when the system grid fundamental frequency... That is, the fundamental angular frequency DC bus reference voltage The DC bias voltage of the decoupling capacitor is set to hour;

[0172] Based on the required second-harmonic pulsation power and the allowable range of capacitor voltage fluctuations, select the decoupling capacitor value. Based on the allowable inductor current ripple and the dynamic response requirements for second harmonic power tracking, the decoupling inductor value is selected. ;

[0173] Under these parameters, the inductance term in the fourth harmonic component coefficient is: The capacitance term is After the two cancel each other out, the difference coefficient is only about The amplitude coefficient of the DC bias voltage providing the second harmonic compensation power is... The amplitude of the fourth harmonic ripple power is much smaller than that of the second harmonic main compensation power, so its impact on the DC bus voltage stability can be basically ignored.

[0174] Step 7.3: When the second harmonic power generated by the Buck-type active power decoupling circuit APD has the same amplitude and opposite phase to the second harmonic pulsating power transmitted from the AC side to the DC side, the second harmonic ripple of the DC bus can be suppressed.

[0175] like Figure 3 As shown, this invention employs a control structure combining a parallel dual-voltage outer loop and a comprehensive current inner loop. The upper voltage outer loop is used to maintain the DC bias voltage of the decoupling capacitor in the Buck-type active power decoupling circuit (APD), and to set the reference bias voltage of the decoupling capacitor. With actual sampling voltage After comparison, a DC current reference value is generated by the PI controller. .

[0176] The lower voltage outer loop is used to suppress DC bus second-harmonic ripple. Specifically, the actual DC bus voltage is obtained. With reference voltage The deviation signal between them was separated by SOGI to obtain a frequency of ripple component ; set the second harmonic ripple reference value Set as The error signal is then input into the QPR controller to generate an AC compensation current reference value. DC current reference value AC compensation current reference value The reference value of the APD inductor current of the Buck-type active power decoupling circuit is obtained by superposition. And the actual current of the APD inductor in the Buck-type active power decoupling circuit. After comparison, the inner loop controller of the input current generates a switching transistor drive signal by the PWM module, thereby controlling the Buck-type active power decoupling circuit APD to absorb or release double frequency pulsating power.

[0177] The selection of parameters for the Buck-type active power decoupling circuit (APD) follows these principles: First, determine the decoupling capacitor based on the second harmonic pulsating power to be compensated. The energy buffering capacity; secondly, the decoupling inductor is determined based on the allowable current ripple. Finally, the switching frequency is determined by considering the switching device losses and current tracking accuracy. To evaluate the feeder imbalance compensation effect, a three-phase imbalance index can be used:

[0178] ;

[0179] In the formula: This indicates the three-phase imbalance index. This represents the imbalance quantity being evaluated. This represents the average value of the unbalanced quantity;

[0180] To evaluate the DC second harmonic ripple suppression effect, the DC side voltage fluctuation rate index can be used:

[0181] ;

[0182] In the formula: This represents the DC-side voltage fluctuation index. This represents the actual voltage of the DC bus. Indicates the DC bus reference voltage;

[0183] Based on the above indicators, the suppression effects of the present invention on AC three-phase imbalance and DC second harmonic voltage ripple can be quantified respectively.

[0184] To further illustrate the effectiveness of the compensation method described in this invention under unbalanced load conditions, this embodiment establishes a flexible multi-state switch unbalanced compensation control model in the MATLAB / Simulink simulation platform. The simulation model includes a three-phase AC power supply, a three-phase unbalanced load, a flexible multi-state switch port converter, an AC-side filter inductor, a DC bus capacitor, and a Buck-type active power decoupling circuit (APD) connected in parallel to the DC port. During the simulation, a three-phase load unbalanced condition is first set up, resulting in significant three-phase current imbalance, active power imbalance, and reactive power imbalance on the feeder side. Subsequently, the positive and negative sequence dual-current inner loop compensation method described in this invention is implemented, and the Buck-type active power decoupling circuit (APD) second-harmonic ripple suppression method is implemented on the DC side.

[0185] like Figure 4 As shown, under three-phase unbalanced operating conditions, DSOGI can separate the positive-sequence and negative-sequence components in voltage and current.

[0186] Simulation results show that when the three-phase load is unbalanced, the negative sequence component can be accurately extracted, providing a basis for generating the reference value of the subsequent negative sequence compensation current. Furthermore, by using the DSOGI-PLL, the phase-locked loop output phase is more stable, avoiding the problem of second-harmonic oscillations caused by the negative sequence component under unbalanced voltage conditions in traditional phase-locked loops.

[0187] like Figures 5 to 7 As shown, before the implementation of the imbalance compensation method of this invention, there was a significant imbalance in the three-phase current on the feeder side. The peak values ​​of the three-phase currents (a, b, and c) were 29A, 121A, and 101A, respectively; the active power transmitted by the three-phase currents (a, b, and c) were 4.5kW, 16.8kW, and 4.0kW, respectively; and the reactive power transmitted by the three-phase currents (a, b, and c) were 0.8kW, 8.4kW, and 15.2kW, respectively. Therefore, it can be seen that before compensation, there was a significant imbalance in the three-phase current, active power, and reactive power on the feeder side, with the three-phase transmission current imbalance at 65.33%, the active power imbalance at 99.29%, and the reactive power imbalance at 86.96%.

[0188] like Figures 8 to 10 As shown, after the positive and negative sequence dual current inner loop imbalance compensation method of the present invention is applied, the flexible multi-state switch port can inject negative sequence compensation current into the AC side, so that the amplitude of the three-phase current on the feeder side tends to be consistent and the phase difference of the three-phase current is 120°.

[0189] After compensation, the distribution of three-phase active and reactive power on the feeder side became significantly more balanced. The maximum imbalance in active power decreased from 12.8kW before compensation to 0.3kW, and the maximum imbalance in reactive power decreased from 14.4kW before compensation to 0.3kW. Figures 5 to 7 and Figures 8 to 10The comparison shows that the present invention can effectively reduce the degree of imbalance of three-phase current on the feeder side and improve the problem of unbalanced three-phase power distribution.

[0190] like Figure 11 and Figure 12 As shown, when only unbalance compensation is performed without the Buck-type active power decoupling circuit (APD), the AC side double-frequency pulsating power is transferred to the DC side, causing the DC bus voltage to fluctuate significantly at double frequency.

[0191] At this time, the reference value of the DC bus voltage is 750V, and the actual DC bus voltage fluctuates in the range of 731V to 769V, with a DC side voltage fluctuation rate of 2.53%.

[0192] With the further addition of a Buck-type active power decoupling circuit (APD), the APD can absorb or release second-harmonic pulsating power, thereby reducing DC bus voltage fluctuations. Figure 7 It can be seen that after the Buck-type active power decoupling circuit (APD) is put into operation, the DC bus voltage fluctuation range is narrowed to 746V to 754V, and the DC side voltage fluctuation rate is reduced to 0.53%.

[0193] Compared with the case without Buck-type active power decoupling circuit (APD), the DC bus voltage fluctuation range is significantly reduced, indicating that the Buck-type active power decoupling circuit (APD) described in this invention can effectively suppress the DC second-harmonic voltage ripple generated during the unbalance compensation process.

[0194] In conclusion, Figures 4 to 12 Simulation results show that the method described in this invention can accurately extract the positive and negative sequence components under three-phase unbalanced conditions and achieve three-phase unbalance compensation on the feeder side through positive and negative sequence dual-current inner loop control. Simultaneously, the Buck-type active power decoupling circuit (APD) can effectively buffer the second-harmonic ripple power, reducing the DC bus voltage fluctuation rate from 2.53% to 0.53%. Therefore, this invention can improve the three-phase imbalance on the AC side while suppressing the second-harmonic ripple on the DC side, thus enhancing the operational stability of the flexible multi-state switch under unbalanced load conditions.

[0195] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A flexible multi-state switch compensation method under unbalanced load, characterized in that, Includes the following steps: Step 1: Collect the three-phase load voltage, three-phase load current, three-phase line current, DC bus voltage, and active and reactive power output from the converter at the flexible multi-state switch port. Convert the three-phase load voltage and three-phase load current to... The coordinate system was used, and the positive-order components, negative-order components, and zero-order components were obtained by processing it with a double second-order generalized integrator. Step 2: Obtain the positive sequence component and build a DSOGI-PLL phase-locked loop to obtain the voltage phase angle. ; Step 3: Based on the voltage phase angle Transform the positive-sequence components to a positive-sequence rotating coordinate system and the negative-sequence components to a negative-sequence rotating coordinate system; Step 4: Using the negative sequence component as the unbalanced compensation current reference, perform positive and negative sequence dual current inner loop feedforward decoupling control respectively, and obtain the DC current reference value based on the outer loop PI controller. Step 5: Obtain the current reference value in the negative sequence rotating coordinate system as the compensation quantity, perform dual current inner loop feedforward decoupling control, and generate a flexible multi-state switch AC side modulation reference voltage. Step 6: Extract the second harmonic ripple component from the DC bus voltage deviation, convert the second harmonic ripple component into second harmonic pulsating power based on the power formula, and buffer the second harmonic pulsating power. Step 7: Collect the difference between the actual capacitor voltage and the capacitor reference voltage of the Buck-type active power decoupling circuit APD to obtain the capacitor voltage deviation. Generate a DC current reference value based on the capacitor voltage deviation, and generate an AC compensation current reference value based on the second harmonic ripple component. Superimpose the DC current reference value and the AC compensation current reference value to obtain the inductor current reference value of the Buck-type active power decoupling circuit APD. Generate a PWM drive signal based on the inductor current reference value to drive the Buck-type active power decoupling circuit APD to absorb or release the second harmonic pulsating power.

2. The flexible multi-state switch compensation method under unbalanced load according to claim 1, characterized in that, In step 1, the process of obtaining the positive-order components and the negative-order components is as follows: Step 1.1: Use Clark transformation to convert the three-phase load voltage and three-phase load current to... In a stationary coordinate system; Step 1.2: Use a double second-order generalized integrator to... In a stationary coordinate system, the three-phase load voltage is decomposed into positive sequence voltage components, negative sequence voltage components, and zero sequence voltage components; Step 1.3: Use a dual second-order generalized integrator to decompose the three-phase load current into positive-sequence current components, negative-sequence current components, and zero-sequence current components.

3. The flexible multi-state switch compensation method under unbalanced load according to claim 1, characterized in that, The transformation formula for transforming the positive-sequence components to the positive-sequence rotated coordinate system is as follows: ； In the formula, Indicates the voltage phase angle. Represents the Park transformation matrix. Represents the inverse transformation matrix of Park; The transformation formula for transforming negative-order components to a negative-order rotating coordinate system is as follows: 。 4. The flexible multi-state switch compensation method under unbalanced load according to claim 2, characterized in that, In step 2, the voltage phase angle The calculation process is as follows: Obtain the positive-sequence voltage component and negative-sequence voltage component from step 1, transform them to a synchronous rotating coordinate system using Park transform, and obtain the positive-sequence voltage component. shaft and Axis voltage components , The transformation formula is as follows: ； In the formula: , These represent the positive sequence load voltages in the two-phase stationary coordinate system. shaft and Axial components, Indicates the voltage phase angle; In ascending order Axis voltage components As a phase detection error signal, it is input to the PI controller for closed-loop adjustment calculation to obtain the angular frequency deviation. : ； In the formula: This represents the proportional adjustment parameter of the phase-locked loop PI controller. This represents the integral adjustment parameter of the phase-locked loop PI controller. Represents the Laplace transform operator; angular frequency deviation With the rated resonant angular frequency of the power grid The voltage phase angle is obtained by superposition and then integration. : ； In the formula: Indicates the resonant angular frequency. Represents the time infinitesimal element; The calculated voltage phase angle Then, the feedback is sent to the Park transformation stage to form a closed-loop phase-locked loop, and the output is used as the reference phase for subsequent positive and negative sequence coordinate transformations.

5. The flexible multi-state switch compensation method under unbalanced load according to claim 1, characterized in that, In step 4, the negative sequence component is used as a reference quantity for the unbalanced compensation current. The process of feedforward decoupling control for the cross-coupling term of the current inner loop is as follows: Step 4.1: Obtain the phase angle The positive sequence voltage component obtained by the separation of the two second-order generalized integrators is used as the input of the phase-locked loop of the synchronous rotating coordinate system to suppress the phase double frequency fluctuation caused by the three-phase imbalance. Step 4.2: Extract the actual and reference values ​​of DC bus voltage, active power and reactive power, and generate positive sequence d-axis current reference value and positive sequence q-axis current reference value through the outer loop PI controller; Step 4.3: Based on the positive sequence voltage component of the DSOGI-PLL phase-locked loop input, obtain the accurate positive and negative sequence coordinate transformation and the phase of the current inner loop control; Step 4.4: Using the negative sequence component of the load current obtained by DSOGI separation as the reference quantity of the unbalanced compensation current, establish positive and negative sequence dual current inner loop control models in the positive sequence rotating coordinate system and the negative sequence rotating coordinate system respectively, and perform feedforward decoupling compensation on the cross-coupling terms of the current inner loop. Step 4.5: Extract the negative sequence component from the load current as a reference quantity for unbalanced compensation current, and use the inner loop feedforward decoupling to cancel the inherent coupling.

6. The flexible multi-state switch compensation method under unbalanced load according to claim 1, characterized in that, The process of obtaining the modulation reference voltage in step 5 is as follows: Step 5.1: Obtain the current reference value in the negative sequence rotating coordinate system as the compensation quantity and transform it to the positive sequence rotating coordinate system to obtain the transformed current reference value. The formula for the coordinate system transformation matrix is ​​as follows: ； In the formula: This represents the coordinate transformation matrix from a negative-order rotating coordinate system to a positive-order rotating coordinate system. Indicates the voltage phase angle; Step 5.2: Obtain the superposition of the transformation current reference value and the positive sequence control quantity to obtain the AC side modulation reference voltage of the flexible multi-state switch; Step 5.3: Input the AC side modulation reference voltage of the flexible multi-state switch into the modulation circuit and apply negative sequence compensation current.

7. The flexible multi-state switch compensation method under unbalanced load according to claim 1, characterized in that, In step 7, the process by which the Buck-type active power decoupling circuit (APD) absorbs or releases second-harmonic pulsating power is as follows: Step 7.1: The Buck-type active power decoupling circuit (APD) includes a decoupling inductor. Decoupling capacitors and switching transistors, among which, decoupling inductors With decoupling capacitor Series, decoupling capacitors The voltage is lower than the DC bus voltage, reducing the voltage stress on the switching transistor; Step 7.2, based on decoupling capacitor voltage The second harmonic power and the fourth harmonic component are calculated from the second harmonic pulsation power of the buffer. Step 7.3: When the second harmonic power generated by the Buck-type active power decoupling circuit APD has the same amplitude and opposite phase to the second harmonic pulsating power transmitted from the AC side to the DC side, the second harmonic ripple of the DC bus can be suppressed.

8. The flexible multi-state switch compensation method under unbalanced load according to claim 7, characterized in that, The calculation process for the second harmonic power and the fourth harmonic component is as follows: First, preset the decoupling capacitor current. With decoupling inductor current They are equal, as shown in the following formula: ； In the formula: This represents the decoupling capacitor current. This indicates the decoupling inductor current. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates the phase of the decoupling capacitor current; Since the decoupling capacitor voltage consists of an AC component and a DC bias component, the calculation formula for the decoupling capacitor voltage is as follows: ； In the formula: This represents the actual instantaneous voltage across the decoupling capacitor. This indicates the capacitance value of the decoupling capacitor. Describes the differential operator. Indicates time, This represents the DC bias voltage component of the decoupling capacitor. Indicates the angular frequency of the power grid. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. This represents the decoupling capacitor current; The buffer power in a Buck-type active power decoupling circuit (APD) consists of capacitor power and inductor power, and the formula for calculating the buffer power is as follows: ； In the formula, This indicates the instantaneous total buffer power of the Buck-type active power decoupling circuit (APD). This represents the instantaneous power absorbed or released by the decoupling capacitor. This represents the instantaneous power absorbed or released by the decoupling inductor. This represents the actual instantaneous voltage across the decoupling capacitor. This represents the decoupling capacitor current. This represents the instantaneous voltage of the decoupling inductor. To represent the decoupled inductor current, we can obtain: ； The formulas for calculating the second harmonic power and the accompanying fourth harmonic component are as follows: Second harmonic power component The calculation formula is as follows: ； In the formula: Represents the second harmonic power component. This represents the voltage across the decoupling energy storage capacitor in the Buck-type active power decoupling circuit (APD). This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates the fundamental angular frequency of the power grid. Indicates time, Indicates the voltage phase angle; Fourth harmonic component The calculation formula is as follows: ； In the formula: This represents the fourth harmonic power component. Indicates decoupling inductance. This indicates the APD current amplitude of the Buck-type active power decoupling circuit. Indicates time, Indicates the voltage phase angle; The total buffer power of the Buck-type active power decoupling circuit (APD) is the sum of the second harmonic power and the fourth harmonic component. .

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