A phase-locked method, device, equipment and medium based on multi-step time delay estimation

Abstract

The application discloses a kind of based on multi-step time delay estimation phase-locked method, device, equipment and medium, belong to power electronic converter grid synchronization control technical field, for the low problem of time delay identification precision in prior art, a kind of based on multi-step time delay estimation phase-locked method of the present application will digital control total time delay as to be identified parameter, constructs N step rolling prediction model, builds multi-step time delay observer, utilizes the error between q axis actual voltage and predicted value, solves optimal time delay and angular frequency estimation value in limited time domain rolling, realizes the online real-time identification and adaptive tracking of system total time delay;By constructing multi-objective cost function and imposing upper and lower limit constraints, suppresses estimation jitter, improves identification precision and robustness under complex power grid conditions;Utilize optimal estimation value to calculate phase lag compensation angle, and the phase of basic phase-locked loop is superposed to obtain accurate synchronous phase, eliminate phase-locked loop lag error, improve grid synchronization precision.

Description

Technical Field

[0001] This invention relates to the field of grid-connected synchronous control technology for power electronic converters, and in particular to a phase-locked loop method, apparatus, equipment, and medium based on multi-step time delay estimation. Background Technology

[0002] As the core interface for new energy power generation, energy storage, and flexible power transmission systems, the stable operation of grid-connected converters highly depends on the precise tracking of the grid voltage phase and frequency by a phase-locked loop (PLL). Ideally, a synchronous rotating coordinate system PLL (SRF-PLL) achieves zero steady-state error phase locking by orienting the grid voltage along the d-axis, making the q-axis voltage component zero. However, in actual digital control systems, a total system delay inevitably exists due to the superposition of A / D sampling and holding, control algorithm calculations, PWM modulation updates, and communication transmission.

[0003] The total time delay of this system introduces a non-negligible phase lag in the synchronous rotating coordinate system, leading to a steady-state deviation in the q-axis voltage. This deviation not only reduces phase-locked loop accuracy but also acts as a disturbance injection current control loop, inducing grid-connected current harmonics and degrading power quality. Especially under weak grid conditions, the interaction between grid impedance and converter output impedance is amplified by the time delay, easily inducing subsynchronous oscillations, seriously threatening the stability of the grid-connected system, and even causing the converter to disconnect from the grid.

[0004] To address the aforementioned latency issues, existing technologies primarily employ the following two types of compensation or suppression strategies: 1. Fixed Delay Feedforward Compensation: This method uses a fixed delay value preset based on the nominal control cycle for phase compensation. However, the computational load in a real system fluctuates dynamically (e.g., as more control functions are implemented, the DSP computation time increases), and the switching frequency may also adjust, resulting in a non-constant total system delay. Fixed compensation strategies cannot adapt to time-varying system delays; once the actual delay deviates from the preset value, the compensation effect will be greatly reduced or even have a negative impact.

[0005] 2. Model-Based Parameter Identification: Some schemes attempt to identify time delay parameters by establishing system models. However, existing identification methods are mostly based on single-step prediction models, using only voltage information from the current and next time steps for calculation. This single-step prediction method is extremely sensitive to sampling noise and grid background harmonics, resulting in low data utilization and severe fluctuations and insufficient accuracy in the identified time delay values. Furthermore, existing schemes often lack dedicated observer structures and rolling optimization mechanisms to smooth the identification results, making it difficult to achieve a balance between dynamic response speed and steady-state accuracy.

[0006] In summary, existing technologies have drawbacks such as the inability to identify the total time delay of time-varying systems online in real time, low accuracy and poor stability of single-step prediction models, poor dynamic phase compensation effect, and difficulty in adapting to complex operating conditions of strong / weak power grids. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a phase-locked loop method, apparatus, device and medium based on multi-step delay estimation to improve the above-mentioned problems.

[0008] This invention provides a phase-locked loop method based on multi-step delay estimation, comprising: S1. Three-phase voltage acquisition and coordinate transformation: Real-time acquisition of three-phase grid voltage, generation of uncompensated synchronous phase using integral recursion, and obtaining the actual voltage of the d and q axes in the synchronous rotating coordinate system through coordinate transformation. The actual voltage of the q axis is used as the time delay deviation observation input. S2. Establish a discrete multi-step prediction model for grid voltage with system time delay: take the total digital control time delay as the parameter to be identified, establish a discrete expression for the q-axis component, and construct an N-step rolling prediction model based on the discrete expression to predict the q-axis voltage prediction value at the next N time points in sequence. S3. Construct a multi-step time delay observer: Using the error between the actual q-axis voltage value and the predicted q-axis voltage value as the observer input, and the total digital control delay and real-time angular frequency as the state variables to be identified, a multi-step time delay observer is constructed. The observer filters out harmonic disturbances by optimizing the rolling time domain. Specifically, this includes: constructing a cost function that takes into account q-axis tracking error, time delay stability, and angular frequency smoothness; solving the optimal total digital control delay estimate and the optimal real-time angular frequency estimate that minimize the cost function in a finite time domain; and applying upper and lower limit constraints to the optimal total digital control delay estimate and the optimal real-time angular frequency estimate to avoid meaningless identification results. S4. Calculation of phase lag compensation angle: The phase lag compensation angle is obtained by multiplying the optimal total delay estimate of the digital control and the optimal real-time angular frequency estimate. S5. Basic phase-locked phase update: The basic phase-locked phase is updated by integral recursion using the optimal real-time angular frequency estimate. S6. Precise Synchronous Phase Synthesis and Output: The phase lag compensation angle is superimposed with the basic phase-locked phase to obtain a precise synchronous phase, which is used for synchronous control output; the optimal digital control total delay estimate is fed back to S2, and the optimal real-time angular frequency estimate is fed back to S4 for phase-locking in the next cycle.

[0009] As an improvement of the present invention, in S1, the specific steps of three-phase voltage acquisition and coordinate transformation are as follows: real-time acquisition of three-phase grid voltage, obtaining the voltage in the two-phase stationary coordinate system through Clark transformation; generating uncompensated synchronous phase using an integral recursive method, and based on the uncompensated synchronous phase, transforming the voltage in the two-phase stationary coordinate system into the actual voltage of the d-axis and the actual voltage of the q-axis in the synchronous rotating coordinate system through Park transformation.

[0010] As an improvement of the present invention, in S2, the discrete expression of the q-axis component is established based on the actual voltages of the d and q axes. This expression characterizes the sinusoidal function relationship between the q-axis voltage and the grid voltage amplitude, the estimated real-time angular frequency, the sampling period, and the estimated total delay of digital control as a parameter to be identified. The N-step rolling prediction model is constructed as follows: based on the estimated total digital control delay, the estimated real-time angular frequency, and the grid voltage amplitude at time k, the predicted q-axis voltage value within the next N control cycles is recursively predicted using the sinusoidal function relationship; where k is the index of the current sampling time, N is the number of rolling prediction steps, and its value ranges from 3 to 10.

[0011] As an improvement of the present invention, in S3, the multi-step delay observer adopts a recursive update rule, including: After each N-step rolling prediction is completed, the multi-step prediction average error is calculated. The multi-step prediction average error represents the cumulative deviation between the actual sampled value and the predicted value of the q-axis voltage at the next N time points. Based on the multi-step prediction average error, real-time angular frequency estimate, and grid voltage amplitude, the total time delay estimate of digital control is calculated through the time delay observation equation. The estimated total delay value of the digital control is used to iteratively update the delay observation value to adapt to the dynamically changing system delay.

[0012] As an improvement of the present invention, in S3, the cost function includes three indicators, which are: an indicator characterizing the target with zero steady-state error tracking on the q-axis, used to constrain the predicted q-axis voltage value in the next N steps to approach zero, so as to ensure phase-locked loop accuracy; an indicator characterizing the rate of change of time delay estimation, used to suppress time delay estimation jitter caused by noise; and an indicator characterizing the smoothness of angular frequency, used to adapt to the dynamic fluctuations of the power grid frequency and prevent non-physical jumps in the time delay observation value caused by small frequency changes. The indicators representing the rate of change of time delay estimation and the indicators representing the smoothness of angular frequency are each configured with weight coefficients, the values ​​of which range from 0.01 to 0.1. A rolling optimization algorithm is used to solve for the digital control total time delay estimate and the real-time angular frequency estimate that minimize the cost function, and these are used as the optimal estimates at time k to complete the iterative update of the observations. During the process of solving for the digital control total time delay estimate and the real-time angular frequency estimate that minimize the cost function using the rolling optimization algorithm, upper and lower limit constraints are applied to the total time delay estimate and the angular frequency estimate to ensure the rationality of the physical meaning and improve the stability of the optimization solution. Specifically, the lower limit of the total time delay estimate is 0.5 sampling periods, and the upper limit is 2 sampling periods; the lower limit of the angular frequency estimate is 1-p times the rated angular frequency of the power grid, and the upper limit is 1+p times the rated angular frequency of the power grid; where p is the frequency fluctuation margin percentage, ranging from 1% to 3%.

[0013] As an improvement of the present invention, in S5, the specific method for updating the basic phase-locked phase is as follows: the basic phase-locked phase at time k-1 is added to the step size term to obtain the basic phase-locked phase at time k; wherein, the step size term is the product of the optimal real-time angular frequency estimate and the sampling period.

[0014] As an improvement of the present invention, in S6, the synthesis and output of the precise synchronization phase is specifically as follows: the basic phase-locked phase at time k is superimposed with the phase lag compensation angle to obtain the precise synchronization phase at time k; the precise synchronization phase is used to generate inverse Park transformation and SVPWM modulation signals to drive the inverter power transistors; the optimal real-time angular frequency estimate is fed back to S4, and the optimal digital control total delay estimate is fed back to S2, for use in the generation of phase reference and delay estimation in the next control cycle.

[0015] The present invention also provides a phase-locked loop device based on multi-step delay estimation, comprising: The actual voltage acquisition unit is used to collect the three-phase grid voltage in real time. It generates the uncompensated synchronous phase using an integral recursive method, and obtains the actual voltage of the d and q axes in the synchronous rotating coordinate system through coordinate transformation. The actual voltage of the q axis is used as the time delay deviation observation input. The prediction model building unit is used to take the total digital control delay as the parameter to be identified, establish a discrete expression for the q-axis component, and build an N-step rolling prediction model based on the discrete expression to predict the q-axis voltage prediction value at the next N time points in sequence. The time delay observer building unit is used to build a multi-step time delay observer by taking the error between the actual q-axis voltage value and the predicted q-axis voltage value as the observer input, and taking the total digital control time delay and real-time angular frequency as the state variables to be identified. The observer filters out harmonic disturbances by optimizing the rolling time domain, specifically including: constructing a cost function that takes into account q-axis tracking error, time delay stability and angular frequency smoothness, solving the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate that minimize the cost function in the finite time domain, and applying upper and lower limit constraints to the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate to avoid meaningless identification results. The phase lag compensation angle calculation unit is used to multiply the optimal digital control total delay estimate and the optimal real-time angular frequency estimate to obtain the phase lag compensation angle. The basic phase-locked phase update unit is used to update the basic phase-locked phase by integral recursion using the optimal real-time angular frequency estimate. The precise synchronization phase synthesis and output unit is used to superimpose the phase lag compensation angle with the basic phase-locked phase to obtain a precise synchronization phase for synchronous control output; and to feed back the optimal total digital control delay and the optimal real-time angular frequency estimate to the phase lag compensation angle calculation unit for the next cycle of phase-locking.

[0016] The present invention also provides a phase-locked device based on multi-step delay estimation, including a memory and a processor. The memory stores a computer program that can be executed by the processor to implement the phase-locked method based on multi-step delay estimation as described above.

[0017] The present invention also provides a computer-readable storage medium storing a computer program that can be executed by a processor of the device in which the computer-readable storage medium is located, to implement a phase-locked loop method based on multi-step delay estimation as described above.

[0018] Compared with the prior art, the present invention has at least the following advantages: 1. This invention uses the total digital control delay as the parameter to be identified, builds a multi-step delay observer, establishes a mapping relationship using the error between the actual voltage and the predicted value on the q-axis, and solves the optimal delay estimate in a rolling manner within a finite time domain. This achieves online real-time identification of the total system delay without the need for pre-calibration or offline measurement, and can adaptively track the dynamic changes in delay, thus solving the problem that existing technologies cannot identify the total delay of time-varying systems online in real time.

[0019] 2. This invention establishes a discrete expression for q-axis voltage with system time delay, and builds an N-step rolling prediction model based on this expression to make forward predictions of q-axis voltage for multiple future control cycles. Compared with the traditional single-step prediction method, this invention effectively overcomes the shortcomings of single-step prediction, such as sensitivity to noise and large estimation fluctuations, and improves the identification accuracy and stability.

[0020] 3. This invention calculates the phase lag compensation angle by using the optimal total delay estimate and the optimal real-time angular frequency estimate for digital control, and superimposes it with the basic phase-locked phase to obtain a precise synchronization phase. This achieves accurate compensation for the total delay introduced by sampling, calculation, modulation and other links in the digital control link, effectively eliminates the phase-locked lag error caused by control delay, and solves the problem of poor dynamic phase compensation effect in the prior art.

[0021] 4. In the rolling optimization process, this invention constructs a multi-objective cost function that takes into account q-axis tracking error, time delay stability and angular frequency smoothness, and applies upper and lower limit constraints to the estimated value to limit the identification result to a physically reasonable range. This not only ensures the phase-locked loop accuracy, but also effectively suppresses estimation jitter and non-physical jumps caused by noise, and enhances the algorithm's adaptability and anti-interference ability under complex working conditions such as strong / weak power grids. Attached Figure Description

[0022] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a phase-locked loop method based on multi-step delay estimation according to the present invention; Figure 2 This is a block diagram of a phase-locked loop (PLL) algorithm based on multi-step delay estimation according to the present invention. Figure 3 This is a comparative schematic diagram of the ideal grid voltage, the actual sampled voltage including system time delay, and the output reference signals of the two phase-locked loop methods provided in the embodiments of the present invention; Figure 4 This is a schematic diagram comparing the output phase angle of the two phase-locked loop methods provided in the embodiments of the present invention with the actual power grid phase in the range of 0~2π. Figure 5 This is a comparative schematic diagram of the phase errors of the two phase-locked loop methods provided in the embodiments of the present invention; Figure 6 This is a schematic diagram comparing the estimated system delay and the actual system delay provided by the method of the present invention in an embodiment of the present invention. Figure 7This is a schematic diagram of the system delay identification and phase compensation convergence process during the startup phase provided in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Example 1 like Figures 1-2 As shown, this embodiment provides a phase-locked loop method based on multi-step delay estimation, including: S1. Three-phase voltage acquisition and coordinate transformation.

[0026] The system acquires the three-phase grid voltage u in real time through a voltage Hall sensor. a u b u c The voltage u in the two-phase stationary coordinate system is obtained by Clark transformation. α u β Uncompensated synchronization phase is generated using an integral recursive method. The recursive formula is:

[0027] in, This is the real-time angular frequency estimate output by S3. =100μs is the control period. Initial phase Then with For the rotation angle relative to u α u β Perform the Park transformation to obtain the voltage u along the d and q axes of the synchronously rotating coordinate system. d u q The actual voltage u along the q-axis q As an input quantity for time delay deviation observation; S2. Establish a discrete multi-step prediction model for grid voltage that includes system time delay.

[0028] Digital control total delay As the parameter to be identified, let the grid voltage amplitude be... =311V, control cycle =100μs. The discrete expression for the q-axis voltage acquired at time k is:

[0029] In this embodiment, the prediction step number N=5 is selected to construct a 5-step rolling prediction model. At time k, the q-axis voltage prediction values ​​at times k+1 to k+5 are predicted sequentially. Where i = 1, 2, 3, ..., 5. The N-step rolling prediction model is: .

[0030] S3. Build a multi-step delay observer.

[0031] The multi-step delay observer employs a recursive update rule, including: After each N-step rolling prediction is completed, the multi-step prediction average error is calculated. The multi-step prediction average error represents the cumulative deviation between the actual sampled value and the predicted value of the q-axis voltage at the next N time points. Based on the multi-step prediction average error, real-time angular frequency estimate, and grid voltage amplitude, the total time delay estimate of digital control is calculated through the time delay observation equation. The estimated total delay value of the digital control is used to iteratively update the delay observation value to adapt to the dynamically changing system delay.

[0032] By utilizing the error between the actual q-axis voltage value obtained in S1 and the predicted q-axis voltage value in S2, a mapping relationship between voltage error and time delay is established, and harmonic disturbances are filtered out by optimizing the rolling time domain. In each control cycle, the system acquires the actual q-axis voltage sample value u. q (k+1) to u q (k+5), and compare it with the corresponding predicted value to calculate the average error of multi-step prediction:

[0033] By utilizing the mapping relationship between voltage error and time delay, a time delay observation equation is constructed:

[0034] By using rolling time-domain averaging, this observer can effectively filter out power grid harmonic disturbances and output an online real-time estimate of the equivalent total time delay. The observer uses a recursive update rule, iteratively updating the delay observations after each 5-step rolling prediction to adapt to dynamically changing system delays.

[0035] Construct a cost function that simultaneously represents the target with zero steady-state error on the q-axis, the rate of change of time delay estimation, and the smoothness of angular frequency:

[0036] in, To track targets with zero steady-state error on the q-axis, even if the q-axis voltage is constrained to approach 0, phase-locked accuracy is guaranteed. To constrain the jump amplitude of the time delay estimate and avoid drastic fluctuations in the time delay estimate due to noise interference; An angular frequency smoothing constraint is used to adapt to dynamic fluctuations in the power grid frequency (typically 49.8Hz to 50.2Hz), preventing non-physical jumps in time delay observations caused by minute frequency changes. In this embodiment, a time delay weighting coefficient λ=0.05 and a smoothing weighting coefficient γ=0.05 are selected, and a rolling optimization solution is used to achieve... smallest and As the optimal time delay estimate and the optimal real-time angular frequency estimate, upper and lower limits are set simultaneously: ,Right now ; In this embodiment, p=2% is used to avoid meaningless identification results.

[0037] S4. Calculation of phase lag compensation angle.

[0038] The optimal total time delay estimate obtained using S3 and optimal real-time angular frequency estimate Multiplying them yields the phase lag compensation angle: .

[0039] S5, Basic phase-locked loop phase update.

[0040] Using the optimal real-time angular frequency estimate obtained from S3, the basic phase-locked loop phase is updated recursively through integration: ; S6, Precise Synchronous Phase Synthesis and Output.

[0041] By superimposing the phase lag compensation angle of S4 with the basic phase-locked phase of S5, a precise synchronization phase is obtained: , Used for synchronous control output; the precise synchronization phase is used to generate inverse Park transform and SVPWM modulation signals to drive the inverter power transistors; the real-time angular frequency estimate is used to... and delay estimate Feedback is sent to S4 and S2 to participate in the generation of phase reference and time delay estimation in the next control cycle.

[0042] This embodiment verifies the time delay identification and phase compensation effects of the above method through simulation. The simulation conditions are: grid rated frequency 50Hz, grid voltage amplitude Um=311V, control period Ts=100μs, multi-step prediction steps N=5, time delay weighting coefficient λ=0.05, frequency smoothing weighting coefficient γ=0.05; the system time delay is set to Tsys=0.5ms and kept constant. It should be noted that 0.5ms is equivalent to 5 control cycles, which is an amplified operating condition set to intuitively show the impact of system time delay on the phase-locked loop (PLL) phase. In practical applications, the system time delay usually falls within the range of 0.5Ts~2Ts (50μs~200μs in this embodiment), and the upper and lower limits of time delay identification can be extended by multiples of the control period to adapt to applications with larger total system time delays. For ease of comparison, the simulation also provides the corresponding results of the traditional phase-locked loop method based on a synchronous rotating coordinate system (SRF-PLL). The following is combined with... Figures 3 to 7 Explain the simulation results.

[0043] Figure 3 This paper presents a comparison of the ideal grid voltage, the actual sampled voltage including the system delay, and the output reference signals of two phase-locked loop (PLL) methods under a system delay of 0.5 ms. The ideal grid voltage is the grid voltage waveform without delay, and the actual sampled voltage is the waveform of the ideal grid voltage after the system delay. For ease of observation, Figure 3 The x-axis is taken as the steady-state interval from 120ms to 170ms. Figure 3 It is evident that the actual sampled voltage has a significant phase lag relative to the ideal grid voltage; the output reference signal of the SRF-PLL is locked to the actual sampled voltage with time delay, thus maintaining a fixed phase difference with the ideal grid voltage; the output reference signal of the method of this invention coincides with the ideal grid voltage, indicating that the phase-locked output phase after time delay compensation is consistent with the real grid phase.

[0044] Figure 4 This demonstrates a comparison between the output phase angles of two phase-locked loop (PLL) methods and the actual grid phase within the range of 0–2π. Figure 4 It can be seen that the output phase angle of the SRF-PLL has a significant and constant lag relative to the actual power grid phase, and this lag persists in steady state; the output phase angle of the method of the present invention deviates only slightly from the actual power grid phase.

[0045] Figure 5 This paper compares the phase errors of two phase-locked loop (PLL) methods, where the phase error is the difference between the PLL output phase and the actual grid phase. Figure 5As can be seen, the phase error of SRF-PLL is a constant value of approximately -7.2°, which is caused by system time delay and cannot be eliminated on its own in steady state. The phase error of the method of the present invention approaches zero after the time delay identification converges, and the steady-state root mean square error is less than 0.1°. This indicates that the present invention effectively eliminates the steady-state phase deviation caused by time delay by identifying system time delay online and calculating the phase lag compensation angle.

[0046] Figure 6 This demonstrates a comparison between the estimated system delay provided by the method of this invention and the actual system delay. (By...) Figure 6 As can be seen, the estimated delay value converges from the initial value of 0.1ms (i.e., one control cycle) to the true value of 0.5ms within about 10ms, and remains stable thereafter. This shows that the method of the present invention can identify the total delay of the digital control link online based solely on the grid voltage sampling information when the system delay is unknown.

[0047] Figure 7 The delay identification and phase compensation convergence process of the method of this invention during the startup phase is demonstrated. Figure 7 As can be seen, in the initial stage of startup, the estimated time delay gradually increases from its initial value and converges to the true value within approximately 10ms. Correspondingly, the phase error of the method of this invention rapidly converges from the initial deviation to zero; while the phase error of SRF-PLL remains at approximately -7.2° throughout, without any convergence process. The above process demonstrates that the method of this invention achieves synchronization between the phase-locked output phase and the actual power grid phase by first identifying the time delay and then compensating for the phase.

[0048] In summary, the simulation results show that the method described in this embodiment can identify the total delay of digital control online under the condition that the system delay is unknown and constant, and accordingly perform dynamic compensation on the phase-locked output phase, reducing the phase-locked output phase error from a constant deviation of about 7.2° in the traditional method to within 0.1°; at the same time, the delay estimate remains stable after convergence and does not produce non-physical jumps with small changes in the grid frequency.

[0049] Example 2 The present invention also provides a phase-locked loop device based on multi-step delay estimation, comprising: The actual voltage acquisition unit is used to collect the three-phase grid voltage in real time. It generates the uncompensated synchronous phase using an integral recursive method, and obtains the actual voltage of the d and q axes in the synchronous rotating coordinate system through coordinate transformation. The actual voltage of the q axis is used as the time delay deviation observation input. The prediction model building unit is used to take the total digital control delay as the parameter to be identified, establish a discrete expression for the q-axis component, and build an N-step rolling prediction model based on the discrete expression to predict the q-axis voltage prediction value at the next N time points in sequence. The time delay observer building unit is used to build a multi-step time delay observer by taking the error between the actual q-axis voltage value and the predicted q-axis voltage value as the observer input, and taking the total digital control time delay and real-time angular frequency as the state variables to be identified. The observer filters out harmonic disturbances by optimizing the rolling time domain, specifically including: constructing a cost function that takes into account q-axis tracking error, time delay stability and angular frequency smoothness, solving the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate that minimize the cost function in the finite time domain, and applying upper and lower limit constraints to the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate to avoid meaningless identification results. The phase lag compensation angle calculation unit is used to multiply the optimal digital control total delay estimate and the optimal real-time angular frequency estimate to obtain the phase lag compensation angle. The basic phase-locked phase update unit is used to update the basic phase-locked phase by integral recursion using the optimal real-time angular frequency estimate. The precise synchronization phase synthesis and output unit is used to superimpose the phase lag compensation angle with the basic phase-locked phase to obtain a precise synchronization phase for synchronous control output; and to feed back the optimal total digital control delay and the optimal real-time angular frequency estimate to the phase lag compensation angle calculation unit for the next cycle of phase-locking.

[0050] Example 3 This embodiment provides a phase-locked device based on multi-step delay estimation, including a memory and a processor. The memory stores a computer program, which can be executed by the processor to implement a phase-locked method based on multi-step delay estimation as described in Embodiment 1.

[0051] Example 4 This embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor of the device in which the computer-readable storage medium is located, to implement a phase-locked loop method based on multi-step delay estimation as described in Embodiment 1.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A phase-locked loop method based on multi-step time delay estimation, characterized in that, include: S1. Three-phase voltage acquisition and coordinate transformation: Real-time acquisition of three-phase grid voltage, generation of uncompensated synchronous phase using integral recursion, and obtaining the actual voltage of the d and q axes in the synchronous rotating coordinate system through coordinate transformation. The actual voltage of the q axis is used as the time delay deviation observation input. S2. Establish a discrete multi-step prediction model for grid voltage with system time delay: take the total digital control time delay as the parameter to be identified, establish a discrete expression for the q-axis component, and construct an N-step rolling prediction model based on the discrete expression to predict the q-axis voltage prediction value at the next N time points in sequence. S3. Construct a multi-step delay observer: Use the error between the actual q-axis voltage value and the predicted q-axis voltage value as the observer input, and use the total digital control delay and real-time angular frequency as the state variables to be identified to construct a multi-step delay observer. The observer filters out harmonic disturbances by optimizing the rolling time domain, specifically by: constructing a cost function that takes into account q-axis tracking error, time delay stability and angular frequency smoothness; solving the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate that minimize the cost function in a finite time domain; and applying upper and lower limits to the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate to avoid meaningless identification results. S4. Calculation of phase lag compensation angle: The phase lag compensation angle is obtained by multiplying the optimal total delay estimate of the digital control and the optimal real-time angular frequency estimate. S5. Basic phase-locked phase update: The basic phase-locked phase is updated by integral recursion using the optimal real-time angular frequency estimate. S6. Precise Synchronous Phase Synthesis and Output: The phase lag compensation angle is superimposed with the basic phase-locked phase to obtain a precise synchronous phase, which is used for synchronous control output; the optimal digital control total delay estimate is fed back to S2, and the optimal real-time angular frequency estimate is fed back to S4 for phase-locking in the next cycle.

2. The method according to claim 1, characterized in that, In S1, the specific steps for three-phase voltage acquisition and coordinate transformation are as follows: real-time acquisition of three-phase grid voltage, obtaining the voltage in the two-phase stationary coordinate system through Clark transformation; generating uncompensated synchronous phase using an integral recursive method, and transforming the voltage in the two-phase stationary coordinate system into the actual voltage on the d-axis and the actual voltage on the q-axis in the synchronous rotating coordinate system through Park transformation based on the uncompensated synchronous phase.

3. The method according to claim 1, characterized in that, In S2, the discrete expression of the q-axis component is established based on the actual voltages of the d and q axes. This expression characterizes the sinusoidal function relationship between the q-axis voltage and the grid voltage amplitude, the estimated real-time angular frequency, the sampling period, and the estimated total delay of digital control as a parameter to be identified. The N-step rolling prediction model is constructed as follows: based on the estimated total digital control delay, the estimated real-time angular frequency, and the grid voltage amplitude at time k, the predicted q-axis voltage value within the next N control cycles is recursively predicted using the sinusoidal function relationship; where k is the index of the current sampling time, N is the number of rolling prediction steps, and its value ranges from 3 to 10.

4. The method according to claim 1, characterized in that, In S3, the multi-step delay observer uses a recursive update rule, including: After each N-step rolling prediction is completed, the multi-step prediction average error is calculated. The multi-step prediction average error represents the cumulative deviation between the actual sampled value and the predicted value of the q-axis voltage at the next N time points. Based on the multi-step prediction average error, real-time angular frequency estimate, and grid voltage amplitude, the total time delay estimate of digital control is calculated through the time delay observation equation. The estimated total delay value of the digital control is used to iteratively update the delay observation value to adapt to the dynamically changing system delay.

5. The method according to claim 1, characterized in that, In S3, the cost function includes three indicators, which are: an indicator characterizing the target with zero steady-state error in q-axis tracking, used to constrain the predicted q-axis voltage value in the next N steps to approach zero, so as to ensure phase-locked loop accuracy; The index characterizing the rate of change of time delay estimation is used to suppress time delay estimation jitter caused by noise; the index characterizing the smoothness of angular frequency is used to adapt to the dynamic fluctuations of power grid frequency and prevent non-physical jumps in time delay observations caused by small frequency changes. The indicators representing the rate of change of time delay estimation and the indicators representing the smoothness of angular frequency are each configured with weight coefficients, the values ​​of which range from 0.01 to 0.

1. A rolling optimization algorithm is used to solve for the digital control total time delay estimate and the real-time angular frequency estimate that minimize the cost function, and these are used as the optimal estimates at time k to complete the iterative update of the observations. During the process of solving for the digital control total time delay estimate and the real-time angular frequency estimate that minimize the cost function using the rolling optimization algorithm, upper and lower limit constraints are applied to the total time delay estimate and the angular frequency estimate to ensure the rationality of the physical meaning and improve the stability of the optimization solution. Specifically, the lower limit of the total time delay estimate is 0.5 sampling periods, and the upper limit is 2 sampling periods; the lower limit of the angular frequency estimate is 1-p times the rated angular frequency of the power grid, and the upper limit is 1+p times the rated angular frequency of the power grid; where p is the frequency fluctuation margin percentage, ranging from 1% to 3%.

6. The method according to claim 1, characterized in that, In S5, the specific method for updating the basic phase-locked phase is as follows: the basic phase-locked phase at time k-1 is added to the step size term to obtain the basic phase-locked phase at time k; wherein, the step size term is the product of the optimal real-time angular frequency estimate and the sampling period.

7. The method according to claim 1, characterized in that, In S6, the synthesis and output of the precise synchronization phase are specifically as follows: the basic phase-locked phase at time k is superimposed with the phase lag compensation angle to obtain the precise synchronization phase at time k; the precise synchronization phase is used to generate inverse Park transformation and SVPWM modulation signals to drive the inverter power transistors; the optimal real-time angular frequency estimate is fed back to S4, and the optimal digital control total delay estimate is fed back to S2, which are used to participate in the generation of the phase reference and delay estimation in the next control cycle.

8. A phase-locked loop device based on multi-step time delay estimation, characterized in that, include: The actual voltage acquisition unit is used to collect the three-phase grid voltage in real time. It generates the uncompensated synchronous phase using an integral recursive method, and obtains the actual voltage of the d and q axes in the synchronous rotating coordinate system through coordinate transformation. The actual voltage of the q axis is used as the time delay deviation observation input. The prediction model building unit is used to take the total digital control delay as the parameter to be identified, establish a discrete expression for the q-axis component, and build an N-step rolling prediction model based on the discrete expression to predict the q-axis voltage prediction value at the next N time points in sequence. The time delay observer building unit is used to build a multi-step time delay observer by taking the error between the actual q-axis voltage value and the predicted q-axis voltage value as the observer input, and using the total digital control time delay and real-time angular frequency as the state variables to be identified. The observer filters out harmonic disturbances by optimizing the rolling time domain, specifically by: constructing a cost function that takes into account q-axis tracking error, time delay stability and angular frequency smoothness; solving the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate that minimize the cost function in a finite time domain; and applying upper and lower limits to the optimal total digital control time delay estimate and the optimal real-time angular frequency estimate to avoid meaningless identification results. The phase lag compensation angle calculation unit is used to multiply the optimal digital control total delay estimate and the optimal real-time angular frequency estimate to obtain the phase lag compensation angle. The basic phase-locked phase update unit is used to update the basic phase-locked phase by integral recursion using the optimal real-time angular frequency estimate. The precise synchronization phase synthesis and output unit is used to superimpose the phase lag compensation angle with the basic phase-locked phase to obtain a precise synchronization phase for synchronous control output; and to feed back the optimal total digital control delay and the optimal real-time angular frequency estimate to the phase lag compensation angle calculation unit for the next cycle of phase-locking.

9. A phase-locked loop device based on multi-step time delay estimation, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program that can be executed by the processor to implement a phase-locked loop method based on multi-step delay estimation as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The device contains a computer program that can be executed by a processor of the device in which the computer-readable storage medium is located, to implement a phase-locked loop method based on multi-step delay estimation as described in any one of claims 1 to 7.

Images