A method and system for fault ride-through control of a grid-forming converter

Abstract

A kind of network type converter fault ride-through control method and system, the method includes: based on preset virtual impedance, the maximum current limiting value of allowing and voltage deviation amplitude, virtual impedance proportional gain is calculated;According to the asymmetric gain coefficient of negative sequence voltage component, the virtual impedance proportional gain is corrected, and the virtual impedance proportional gain after correction is obtained, and it is limited to amplitude, and the final virtual impedance proportional gain is output;It is mapped with real-time current vector, current differential vector and preset virtual impedance parameter into internal potential correction vector U , and it is superimposed to the virtual internal potential instruction vector generated by voltage source control loop under normal condition E * , form internal potential instruction vector during fault E * + U ;Further conversion generates three-phase PWM Switching signal.The present application realizes dynamic adjustment of virtual impedance intensity during fault, smooth recovery after fault, maintains voltage source type control structure throughout, without any control loop coordination or mode switching.

Description

Technical Field

[0001] This invention belongs to the field of power electronics and new energy grid-connected power generation technology. More specifically, it relates to a fault ride-through control method and system suitable for grid-type converters to achieve rapid current limiting and voltage support during symmetrical / asymmetrical grid faults, and in particular, a method and system for generating internal potential correction based on virtual impedance proportional gain adaptive adjustment. Background Technology

[0002] Grid-type converters have become a key technology for high-proportion renewable energy power systems due to their advantages such as simulating the external characteristics of synchronous generators, autonomously establishing voltage frequency, and not requiring phase-locked loops. However, grid-type converters face severe challenges during grid faults: their voltage source characteristics mean that fault currents lack inherent limitations, making them highly susceptible to overcurrent-triggered protection shutdowns and even damage to power devices.

[0003] Existing fault ride-through strategies for grid-type converters are mainly divided into two categories: Switching control mode: During a fault, a forced switch to current source mode (i.e., grid-based control) is performed, directly limiting the fault current using the inner current loop. This method disrupts voltage source characteristics, leading to the loss of grid-based advantages, and mode switching is prone to transient impacts.

[0004] Virtual impedance method: A fixed virtual impedance is connected in series in the internal potential control loop to indirectly limit current through voltage feedback. Although this method maintains the voltage source structure, the fixed virtual impedance value is difficult to balance current limiting effect and voltage support strength: if the impedance is too small, the current limiting is insufficient; if the impedance is too large, it will cause a serious drop in port voltage and a decrease in reactive power support capability; moreover, the fixed impedance cannot adapt to the severity of the fault and the symmetrical / asymmetrical type.

[0005] For example, but not limited to, prior art document 1 ( CN 120955826 A A hierarchical control method for fault ride-through in a grid-type converter is disclosed in existing technical document 2 ( CN 121055388 A The paper discloses a fault ride-through method and system for grid-type converters based on dynamic virtual resistance control. However, this technical solution has the following drawbacks: First, it still employs a control method with an inner current loop. The inner current loop determines the control characteristics of its current source, making it impossible to achieve the voltage source characteristics of a grid-type converter. Second, the virtual impedance only includes virtual point resistance, not virtual reactance, and the dynamic adjustment of the virtual impedance is nonlinear, which does not conform to the inductive fault characteristics of synchronous machines. Third, some technical requirements necessitate coordinated control between the inner current loop and the outer grid power loop, making the implementation complex, and multi-loop coordination cannot guarantee the reliability of control under rapid fault conditions.

[0006] Therefore, there is an urgent need for a fault ride-through method for grid-type converters that can maintain the voltage source control structure, dynamically adjust the virtual impedance strength according to the fault severity, and achieve smooth recovery after a fault. Summary of the Invention

[0007] To address the shortcomings of existing technologies and overcome the defects of existing fault ride-through strategies for grid-connected converters, this invention provides a fault ride-through control method and system based on adaptive adjustment of virtual impedance proportional gain. By calculating the vector deviation between the virtual electromotive force and the grid connection point electromotive force in real time, and combining the preset virtual impedance, current limit value, and real-time current, a virtual impedance proportional gain is generated. This results in an internal potential correction amount that is superimposed on the virtual internal potential command, enabling dynamic adjustment of the virtual impedance strength during a fault and smooth recovery after a fault. The voltage source control structure is maintained throughout the process without any control loop coordination or mode switching.

[0008] The present invention adopts the following technical solution.

[0009] A first aspect of the present invention provides a fault ride-through control method for a grid-type converter, the method comprising the following steps: Real-time acquisition of positive and negative sequence voltage and current components at the converter grid connection point, synchronous rotating coordinate system components, and virtual electromotive force command values ​​for grid control. E * Calculate the voltage deviation amplitude Δ U m ; Based on the preset virtual impedance, the maximum allowable current limit, and the voltage deviation amplitude Δ U m Calculate the virtual impedance proportional gain K v ; Determine the asymmetric gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v After correction, the virtual impedance proportional gain is obtained. K v,out ; and the corrected virtual impedance scaling gain K v,out Limiting is applied to output the final virtual impedance proportional gain. K v,out,final ; The final virtual impedance scaling gain K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E* The internal potential command vector is formed during the fault period. E * + U According to the corrected internal potential command vector E * + U Transformation to generate three phases PWM Switch signal.

[0010] Preferably, the calculated voltage deviation amplitude Δ U m include: Taking into account the primary filter reactance X f The resulting voltage drop will convert the positive and negative sequence voltages at the grid connection point to the virtual electromotive force at the midpoint of the converter bridge arm; Based on virtual electromotive force command value E * orthogonal order d Axial components E dp And the virtual electromotive force on the converter bridge arm side, calculate the voltage deviation amplitude Δ between the virtual electromotive force and the grid connection point electromotive force. U m .

[0011] Preferably, the calculation of virtual impedance proportional gain K v include: The virtual impedance amplification factor is obtained by dividing the voltage deviation amplitude by the amplitude of the preset virtual impedance and then normalizing it using the maximum allowable current limit. K v .

[0012] Preferably, the step of determining the asymmetric gain coefficient based on the negative sequence voltage component... γ include: Based on the negative sequence voltage at the grid connection point d Axial components U dn and q Axial components U qn Calculate the negative sequence voltage amplitude at the grid connection point. U nm ; Set threshold U th If the negative sequence voltage amplitude at the grid connection point U nm Threshold U th When the power grid is experiencing an asymmetrical fault, the ability to suppress negative sequence voltage is enhanced. At this time, the gain coefficient is set... γ= γ set, γ set >1; otherwise γ set =1; The virtual impedance scaling gain K v The corrections include: With gain coefficient γ Multiplied by the virtual impedance scaling gain K v The corrected virtual impedance proportional gain is obtained. K v,out .

[0013] Preferably, the corrected virtual impedance proportional gain K v,out Limiting the amplitude includes: The corrected virtual impedance scaling gain K v,out Perform state-dependent dynamic descent rate limiting, where: Based on the corrected virtual impedance proportional gain K v,out Total amplitude of port voltage U pnm A fault ride-through state machine is established, comprising normal state, low-susceptibility state, high-susceptibility state, and recovery timing state. Fault ride-through states are identified, and state transition conditions are based on the modified virtual impedance proportional gain. K v,out Total amplitude of port voltage U pnm A judgment will be rendered.

[0014] Preferably, the fault-crossing state machine includes: Set up state variables with memory functionality Flag ,in: Flag =0 represents the normal state, and the entry condition is: K v,out ≤1 and 0.95≤ U pnm ≤1.05 and I pnm ≤2 I lim and U nm ≤0.05, steady-state operation is achieved under this condition, and the network control virtual internal potential command is used. E * No need to stack U ; Flag=1 represents the low-penetration state, and the entry condition is: K v,out >1 and U pnm <0.9, in this state, low voltage ride-through is performed, and virtual impedance is applied according to the calculation; Flag =2 represents a high-penetration state, and the entry condition is: K v,out >1 and U pnm >1.1, under this condition, high voltage ride-through is performed, and virtual impedance is applied according to the calculation; The entry condition for the recovery state is Flag ≠0 and K v,out ≤1 and 0.95≤ U pnm ≤1.05 and I pnm ≤2 I lim and U nm ≤0.05, the timer is started in this state. T rec After the timer expires Flag =0.

[0015] Preferably, the corrected virtual impedance proportional gain K v,out State-dependent dynamic descent rate limits include: Low-suspension state: Under fault conditions, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the first set value D lvrt ; Recovery state: During the fault recovery process, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the second set value D norm And the second setting value D norm <First setting value D lvrt .

[0016] Preferably, the corrected virtual impedance proportional gain K v,out Limiting the amplitude includes: For the corrected virtual impedance proportional gain K v,out Implement upper limit limiting, corrected virtual impedance proportional gain K v,out≤ Virtual impedance ratio increases to upper limit K lim Output the final virtual impedance proportional gain K v,out,final .

[0017] Preferably, the final virtual impedance is proportional to the gain. K v,out,final The four components of the internal potential correction vector, which are mapped to the real-time current vector, the differential current vector, and the preset virtual impedance parameters, are expressed by the following formula:

[0018] In the formula: U dp , U qp , U dn and U qn These represent the positive sequence of the internal potential correction vector. d Axis components, positive sequence q Axis components, negative order d Axial components and negative sequence q Axial components; I dp , I qp , I dn and I qn These represent the positive sequence current at the grid connection point, respectively. d Axis component, positive sequence current q Axial component, negative sequence current d Axial components and negative sequence currents q Axial components; R v To preset the virtual resistance, X v To preset virtual reactance, L v = X v / ω 0 represents virtual inductance. ω 0 is the rated angular frequency. dI dp , dI qp , dI dn and dI qnThis corresponds to the differential component of the current.

[0019] A second aspect of the present invention provides a fault ride-through control system for a grid-connected converter, comprising the fault ride-through control method for a grid-connected converter as described in the first aspect, including: The grid voltage control module is used to calculate the virtual electromotive force command value and for positive and negative sequence. dq Angular velocity of component decomposition; The electrical quantity acquisition and calculation module is used to obtain the positive and negative sequence. dq Voltage and current components; The virtual impedance proportional gain calculation module is used to calculate the virtual impedance proportional gain based on the preset virtual impedance, the maximum allowable current limit, and the voltage deviation amplitude. K v ; The correction and dynamic limiting module is used to determine the asymmetric gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v After correction, the virtual impedance proportional gain is obtained. K v,out ; and the corrected virtual impedance scaling gain K v,out Limiting is applied to output the final virtual impedance proportional gain. K v,out,final ; The virtual internal potential command correction module is used to adjust the final virtual impedance proportional gain. K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E * The internal potential command vector is formed during the fault period. E * + U ; PWM The modulation module is used to adjust the internal potential command vector. E * + U Transformation to generate three phases PWM Switch signal.

[0020] Compared with the prior art, the beneficial effects of the current impedance mapping method adopted in this invention include at least the following: It directly utilizes the current and its differential information, which is in high agreement with the virtual impedance physical model; Virtual impedance adaptive adjustment to adapt to the voltage support requirements of grid-type converters under different fault conditions; proportional gain K v,out It is associated with the converter current limit value, which facilitates engineering tuning. Attached Figure Description

[0021] Figure 1 This is a general block diagram of fault ride-through control for a grid-type converter provided according to an embodiment of the present invention; Figure 2 This is a flowchart of the virtual internal potential correction vector calculation according to an embodiment of the present invention; Figure 3 This is a fault-crossing state transition diagram provided according to an embodiment of the present invention; Figure 4 The waveform diagram for three-phase fault low-voltage simulation verification provided in accordance with the embodiments of the present invention; Figure 5 The waveform diagram for low-voltage simulation verification of a two-phase fault provided in accordance with the embodiments of the present invention is shown below. Figure 6 The waveform diagram for high-voltage simulation verification of three-phase faults provided in accordance with the embodiments of the present invention; Figure 7 The waveform diagram is provided for high-voltage simulation verification of two-phase faults according to the embodiments of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0023] Embodiment 1 of the present invention provides a fault ride-through control method for a grid-type converter, based on, for example, Figure 1 The grid-type converter control system shown employs single-loop voltage source control under normal operating conditions, such as, but not limited to, droop control and virtual synchronous machine control, directly generating virtual internal potential commands. E * = [ E dp, E qp, E dn, E qn ] T , E qp =E dn = E qn = 0.

[0024] During the fault, the original virtual internal potential command E * An internal potential correction is superimposed on top. U = [ U dp, U qp, U dn, U qn ] T The internal potential command during the fault period is obtained. This internal potential correction amount... U The physical essence of it is the dynamic voltage drop on the virtual impedance. By adaptively adjusting the proportional gain of the virtual impedance, the coordinated control of fault current suppression and voltage support can be achieved.

[0025] It is worth noting that, such as Figure 2 As shown, the most prominent substantive features of this invention include at least the internal potential correction amount. U The generation method first calculates the virtual impedance proportional gain. K v,out Then compare it with the preset virtual impedance. Z v and real-time grid connection point positive and negative sequence dq Current component mapped to internal potential correction U .

[0026] The fault ride-through control method for the grid-type converter is based on real-time calculation of positive and negative sequence components in a synchronous rotating coordinate system, and includes the following steps: Step 1: Collect and calculate electrical quantities and system parameters, including: real-time acquisition of positive and negative sequence voltages and current components at the converter grid connection point in a synchronous rotating coordinate system, and virtual internal potential commands for grid control. E * Calculate the real-time AC bus current amplitude I pnm .

[0027] Specifically, the positive and negative sequence of data collection and grid connection points dq Component voltage, positive and negative sequence of grid connection point dq Component current, virtual internal potential command generated by grid-type voltage source control E* Real-time AC current amplitude at grid connection point I pnm Preset virtual impedance Z v Primary filter reactance X f Maximum permissible current limit I lim .

[0028] More specifically, the positive and negative sequence of the grid connection points dq Component voltages include: positive sequence voltage at the grid connection point. d Axial components U dp The positive sequence voltage at the grid connection point q Axial components U qp The negative sequence voltage at the grid connection point d Axial components U dn The negative sequence voltage at the grid connection point q Axial components U qn ; The positive and negative sequence of the grid connection points dq The component current includes: the positive sequence current at the grid connection point. d Axial components I dp The positive sequence current at the grid connection point q Axial components I qp The negative sequence current at the grid connection point d Axial components I dn The negative sequence current at the grid connection point q Axial components I qn ; The virtual internal potential command generated by the grid-type voltage source control E * Expressed as follows:

[0029] In the formula: E dp This represents the positive sequence of the virtual internal potential generated by the grid voltage source control loop. d Axial components; The amplitude of the real-time grid-connected AC current is expressed by the following formula:

[0030] In the formula: I pnm Indicates the real-time AC current amplitude at the grid connection point; The preset virtual impedance Z v Expressed as follows:

[0031] In the formula: R v Indicates virtual resistance. X v This represents virtual reactance.

[0032] Step 2: Based on the virtual electromotive force command value E * Primary filter reactance X f Positive and negative sequence of grid connection points dq Component voltage, grid connection point positive and negative sequence dq Component current calculation of voltage deviation amplitude Δ U m .

[0033] Preferably, but not limitingly, step 2 specifically includes: Step 2.1, based on the positive and negative sequence of the grid connection point dq Component voltage, positive and negative sequence of grid connection point dq Component current and primary filter reactance X f The virtual electromotive force is converted to the converter bridge arm side.

[0034] Specifically, considering the primary filter reactance X f The resulting voltage drop, which translates the port voltage to the virtual electromotive force at the midpoint of the converter bridge arm, is expressed by the following formula:

[0035] In the formula: U tdp, U tqp, U tdn and U tqn These represent the positive sequence of the virtual electromotive force at the midpoint of the converter bridge arm, respectively. d Axis components, positive sequence q Axial components, negative sequence d Axial components and negative sequence q Axial components.

[0036] Step 2.2: Based on the virtual electromotive force command value E * orthogonal order d Axial components Edp And the virtual electromotive force on the converter arm side obtained in step 2.1, the voltage deviation between the virtual electromotive force and the grid connection point electromotive force is calculated and expressed by the following formula:

[0037] In the formula: Δ U m This represents the magnitude of the voltage deviation between the virtual electromotive force and the electromotive force at the grid connection point.

[0038] It is worth noting that the voltage deviation amplitude Δ U m The physical meaning is: during fault ride-through, under the current current amplitude, the converter still needs to output an additional voltage vector amplitude to maintain the port voltage.

[0039] Step 3: Based on the preset virtual impedance Z v Maximum permissible current limit I lim and the vector deviation amplitude Δ U m Calculate the virtual impedance proportional gain K v ; Specifically, the voltage deviation amplitude Δ U m With the maximum allowable current limit I lim and preset virtual impedance Z v Correlation, defining the virtual impedance proportional gain, is expressed by the following formula:

[0040] In the formula: K v This represents the virtual impedance proportional gain.

[0041] It is worth noting that the physical meaning of this gain is that, in order to overcome the current voltage deviation, the preset virtual impedance needs to be... Z v enlarge K v The actual virtual impedance value is times, that is, the virtual impedance value actually invested. K v Z v This corresponds to the virtual impedance voltage. Current limiting value is used. I limInstead of normalizing the real-time current, the gain directly reflects the ratio of the fault severity to the system's rated capacity, thus avoiding the impact of real-time current fluctuations on gain calculation.

[0042] Step 4: Introduce the asymmetric fault gain coefficient, including: determining the asymmetric fault gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v The correction is then performed to obtain the corrected virtual impedance proportional gain.

[0043] Preferably, but not limitingly, step 4 specifically includes: Step 4.1: Calculate the negative sequence voltage amplitude at the grid connection point, expressed by the following formula:

[0044] In the formula: U nm It represents the negative sequence voltage amplitude at the grid connection point.

[0045] Step 4.2: Set the threshold U th If the negative sequence voltage amplitude at the grid connection point U nm Threshold U th It is believed that the power grid is in an asymmetrical fault state, and the ability to suppress negative sequence voltage should be enhanced. In this case, the gain coefficient is set to... γ = γ set, γ set >1; otherwise γ set =1.

[0046] Preferably, but not limitingly, the threshold U th The typical value is 0.05. p . u Gain coefficient setting value γ set When the value is greater than 1, the typical value is 1.3.

[0047] Step 4.3: Correct the virtual impedance proportional gain, expressed by the following formula:

[0048] In the formula: K v,out This represents the corrected virtual impedance proportional gain.

[0049] Step 5: Establish a fault-crossing state machine and adjust the modified virtual impedance proportional gain.K v,out Perform state-dependent dynamic descent rate limiting and physical upper limit limiting, and output the final virtual impedance proportional gain. K v,out,final .

[0050] Preferably, but not limitingly, step 5 specifically includes: Step 5.1: Based on the corrected virtual impedance proportional gain K v,out Total amplitude of port voltage U pnm Establish a fault-crossing state machine to identify fault-crossing states. Specifically, establish a state machine that includes at least a normal state, a low-throughput state, a high-throughput state, and a recovery timing state. The state transition conditions are based on the virtual impedance proportional gain. K v,out Total amplitude of port voltage U pnm The judgment is as follows: Table 1 Fault Trip State Machine

[0051] It is worth noting that, as one of the prominent substantive features of this invention, the technical concept of establishing a fault-crossing state machine lies in avoiding the modified virtual impedance proportional gain. K v,out Unnecessary abrupt changes cause drastic shifts in the internal potential correction vector; therefore, setting up state variables with memory functionality is necessary. Flag And based on the corrected virtual impedance proportional gain K v,out Total amplitude of port voltage U pnm Perform state transitions, such as Figure 3 As shown.

[0052] The total amplitude of the port voltage is expressed by the following formula:

[0053] In the formula: U pnm This indicates the total amplitude of the port voltage.

[0054] Step 5.2: Adjust the virtual impedance scaling gain according to the current state. K v,out Implement dynamic descent rate limiting, specifically: Low-suspension state: Under fault conditions, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the first set value D lvrtOne of the most prominent and essential features of this invention is that it prevents rapid shutdown due to brief fluctuations in fault conditions, which could lead to insufficient reactive power support. Recovery state: During the fault recovery process, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the second set value D norm And the second setting value D norm <First setting value D lvrt One of the most prominent features of this invention is that it achieves a smooth recovery of the internal potential correction after fault clearance, thus avoiding transient over / under voltage phenomena during faults.

[0055] Step 5.3: Adjust the virtual impedance proportional gain. K v,out Implement upper limit limiting, corrected virtual impedance proportional gain K v,out ≤ Virtual impedance ratio increases to upper limit K lim .

[0056] It is worth noting that, as one of the prominent substantive features of this invention, the technical concept of output upper limit limiting lies in the fact that it is a proportional gain of the corrected virtual impedance. K v,out Excessive size leads to internal potential correction vector U Setting an upper limit for virtual impedance proportional gain beyond the converter's maximum output voltage capability. K lim The upper limit of this virtual impedance proportional gain. K lim The system impedance and primary filter reactance X f and the maximum allowable current limit I lim A joint decision is made to ensure that the virtual impedance proportional gain corresponds to the actual virtual impedance. K v,out Z v Within the physically achievable range.

[0057] Step 5.4: Adjust the virtual impedance proportional gain. K v,out After dynamic limiting, the final virtual impedance proportional gain is obtained, and the final output is:

[0058] In the formula: K v,out,final This represents the final virtual impedance proportional gain.

[0059] Step 6, Internal potential correction vector U The generation includes: adjusting the final virtual impedance scaling gain. K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E * The internal potential command vector is formed during the fault period. E * + U .

[0060] Preferably, but not limitingly, step 6 specifically includes: The final virtual impedance scaling gain K v,out,final The four components of the internal potential correction vector, which are mapped to the real-time current vector, the differential current vector, and the preset virtual impedance parameters, are expressed by the following formula:

[0061] In the formula: U dp, U qp, U dn and U qn These represent the positive sequence of the internal potential correction vector. d Axis components, positive sequence q Axis components, negative order d Axial components and negative sequence q Axial components; R v To preset the virtual resistance, X v To preset virtual reactance, L v = X v / ω 0 represents virtual inductance. ω 0 is the rated angular frequency. dI dp , dIqp , dI dn , dI qn This corresponds to the differential component of the current.

[0062] It is worth noting that when the final virtual impedance is proportional to the gain K v,out,final When = 0, the correction is zero, and the system returns to the normal internal potential command; when the final virtual impedance proportional gain K v,out,final When the voltage is greater than 0, the equivalent amplified virtual impedance actively raises the internal potential to compensate for the impedance voltage drop, thereby suppressing the current and supporting the grid connection point voltage.

[0063] Therefore, it can be understood that, as one of the prominent substantive features of this invention, the current-impedance mapping method adopted in this invention has the following advantages: It directly utilizes the current and its differential information, which is in high agreement with the virtual impedance physical model; Virtual impedance adaptive adjustment to adapt to the voltage support requirements of grid-type converters under different fault conditions; Final virtual impedance proportional gain K v,out,final It is associated with the converter current limit value, which facilitates engineering tuning.

[0064] Step 7, forming the final internal potential command, includes: based on the modified internal potential command vector E * + U Transformation to generate three phases PWM Switch signal.

[0065] Preferably, but not limitingly, step 7 specifically includes: The final virtual impedance scaling gain K v,out,final Substituting into the formula for calculating the internal potential correction vector, we get U This is superimposed on the virtual internal potential command vector generated by the grid-type voltage source control loop: E * + U .in E * =[ E dp, E qp, E dn, E qn ] T This is the internal potential command under normal operating conditions. It can be understood that, typically, the positive sequence...q The axis and negative sequence components are both zero. The corrected internal potential command is then transformed and... PWM Modulation drives the converter switch.

[0066] Embodiment 2 of the present invention provides a fault ride-through control system for a grid-type converter, which implements the fault ride-through control method for a grid-type converter described in Embodiment 1, including: The grid voltage control module is used to calculate the virtual electromotive force command value and for positive and negative sequence. dq angular velocity of component decomposition The electrical quantity acquisition and calculation module is used to obtain the positive and negative sequence. dq Voltage and current components; The virtual impedance proportional gain calculation module is used to calculate the virtual impedance proportional gain based on the preset virtual impedance, the maximum allowable current limit, and the voltage deviation amplitude. K v ; The correction and dynamic limiting module is used to determine the asymmetric gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v After correction, the virtual impedance proportional gain is obtained. K v,out ; and the corrected virtual impedance scaling gain K v,out Limiting is applied to output the final virtual impedance proportional gain. K v,out,final ; The virtual internal potential command correction module is used to adjust the final virtual impedance proportional gain. K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E * The internal potential command vector is formed during the fault period. E * + U ; PWM The modulation module is used to adjust the internal potential command vector. E * + U Transformation to generate three phases PWM Switch signal.

[0067] Embodiment 3 of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded onto the processor, it implements the fault ride-through control method for a grid-type converter according to Embodiment 1.

[0068] Embodiment 4 of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the fault ride-through control method for a grid-type converter according to Embodiment 1.

[0069] To illustrate the beneficial technical effects of the present invention, Figures 4 to 7 The following are illustrated: three-phase fault low-through simulation verification waveforms, two-phase fault low-through simulation verification waveforms, three-phase fault high-through simulation verification waveforms, and two-phase fault high-through simulation verification waveforms provided in accordance with embodiments of the present invention.

[0070] like Figure 4 The simulation waveform diagram of the three-phase fault low-through shows that the reactive power before the fault is close to 1 pu capacitive. When the fault is set at t=1.0s, the three-phase symmetrical voltage at the grid connection point drops to 0.05 pu through impedance voltage division, lasting for 1.0s. At t=2.0s, the fault is cleared, and the voltage returns to the rated value. At the moment the fault occurs, the method of this invention responds rapidly, and the three-phase current rises quickly to the maximum capacity of 3.0 pu, giving full play to the voltage source characteristics to provide reactive power support to the grid and effectively suppressing further voltage drops. During the fault, the current waveform is sinusoidal and symmetrical without distortion. After the fault is cleared, the control algorithm uses a state machine and dynamic limiting to ensure a smooth current exit, without causing overvoltage in any phase, achieving safe and stable operation throughout the fault ride-through process.

[0071] like Figure 5 The simulation waveform diagram of a two-phase fault low-voltage operation shown indicates that the reactive power before the fault is close to 1 pu capacitive. When the fault is set to t=1.0s, the voltage of the two phases (B and C phases) at the grid connection point drops to 0.05 pu through impedance voltage division, while the voltage of phase A remains at its rated value for 1.0s. At t=2.0s, the fault is cleared, and the voltage returns to its rated value. The simulation waveform is as follows. Figure 5 As shown, when a fault occurs, the fault phase current rapidly reaches the 3.0 pu limit, and the non-fault phase current adjusts accordingly, effectively limiting the overall three-phase current within a safe range. The asymmetric gain coefficient introduced in this invention actively suppresses negative sequence voltage, and the two fault phase currents work together to support the grid voltage, significantly improving voltage balance under asymmetrical faults. After the fault ends, the current smoothly exits, and there is no overshoot in any phase voltage, verifying the excellent performance of this method under asymmetrical faults.

[0072] like Figure 6The simulation waveform diagram of the three-phase fault high-voltage transmission shown shows that the reactive power before the fault is close to 1 pu (inductive power). When the fault is set to t=1.0s, the three-phase symmetrical voltage at the grid connection point is raised to 1.30 pu (inductive power) through impedance voltage division, lasting for 1.0s. The fault is cleared at t=2.0s, and the voltage returns to its rated value. The simulation waveform is as follows. Figure 6 As shown, when a fault occurs, the three-phase current rapidly rises to 2.0 pu (according to the high-voltage surge strategy, full support is not required). By absorbing a small amount of reactive power, the grid connection point voltage is stabilized near the rated value, effectively suppressing the voltage surge. During the fault, the voltage waveform is stable, and the current does not exceed the limit. After the fault is cleared, the control logic smoothly restores the current to its initial state, without causing any phase voltage drop, demonstrating the adaptive adjustment capability of this method in high-voltage surge scenarios.

[0073] like Figure 7 The simulation waveform diagram for a two-phase fault high-voltage transmission shows that the reactive power before the fault is close to 1 pu (inductive power). When the fault is set to t=1.0s, the voltage of the two phases (B and C phases) at the grid connection point is raised to 1.30 pu (inductive power) through impedance voltage division. The voltage of phase A remains at its rated value for 1.0s. At t=2.0s, the fault is cleared, and the voltage returns to its rated value. The simulation waveform is as follows: Figure 7 As shown, when a fault occurs, the currents of the two faulty phases are rapidly adjusted to 2.0 pu. Inductive reactive power is injected to suppress voltage rise, and the currents of the non-faulty phases cooperate accordingly, pulling the overall grid connection point voltage back to near its rated value. During the asymmetrical high-voltage surge, the negative sequence component is effectively suppressed, and the three-phase voltage asymmetry is significantly reduced. After the fault is cleared, the current smoothly exits, and no voltage drop occurs in any phase, demonstrating the robustness and reliability of this method under complex fault conditions.

[0074] It is worth noting that in the embodiments of the present invention, "steps + numbers" is only an expression for clearly describing the specific implementation method of the fault ride-through control method for grid-type converters, and not an absolute restriction on the order of the steps. Under the guidance of the core concept of the present invention, changing the order of these steps to achieve the same or similar technical effects all fall within the scope of the present invention.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A fault ride-through control method for a grid-type converter, characterized in that, The method includes the following steps: Real-time acquisition of positive and negative sequence voltage and current components at the converter grid connection point, synchronous rotating coordinate system components, and virtual electromotive force command values ​​for grid control. E * Calculate the voltage deviation amplitude Δ U m ; Based on the preset virtual impedance, the maximum allowable current limit, and the voltage deviation amplitude Δ U m Calculate the virtual impedance proportional gain K v ; Determine the asymmetric gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v After correction, the virtual impedance proportional gain is obtained. K v,out ; and the corrected virtual impedance proportional gain K v,out Limiting is applied to output the final virtual impedance proportional gain. K v,out,final ; The final virtual impedance scaling gain K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E * The internal potential command vector is formed during the fault period. E * + U According to the corrected internal potential command vector E * + U Transformation to generate three phases PWM Switch signal.

2. The fault ride-through control method for a grid-type converter according to claim 1, characterized in that: The calculated voltage deviation amplitude Δ U m include: Taking into account the primary filter reactance X f The resulting voltage drop will convert the positive and negative sequence voltages at the grid connection point to the virtual electromotive force at the midpoint of the converter bridge arm; Based on virtual electromotive force command value E * orthogonal order d Axial components E dp And the virtual electromotive force on the converter bridge arm side, calculate the voltage deviation amplitude Δ between the virtual electromotive force and the grid connection point electromotive force. U m .

3. The fault ride-through control method for a grid-type converter according to claim 1, characterized in that: The calculation of virtual impedance proportional gain K v include: The virtual impedance amplification factor is obtained by dividing the voltage deviation amplitude by the amplitude of the preset virtual impedance and then normalizing it using the maximum allowable current limit. K v .

4. A fault ride-through control method for a grid-type converter according to any one of claims 1 to 3, characterized in that: The asymmetric gain coefficient is determined based on the negative sequence voltage component. γ include: Based on the negative sequence voltage at the grid connection point d Axial components U dn and q Axial components U qn Calculate the negative sequence voltage amplitude at the grid connection point. U nm ; Set threshold U th If the negative sequence voltage amplitude at the grid connection point U nm Threshold U th When the power grid is experiencing an asymmetrical fault, the ability to suppress negative sequence voltage is enhanced. At this time, the gain coefficient is set... γ = γ set, γ set >1; otherwise γ set =1; The virtual impedance scaling gain K v The corrections include: With gain coefficient γ Multiplied by the virtual impedance scaling gain K v The corrected virtual impedance proportional gain is obtained. K v,out .

5. The fault ride-through control method for a grid-type converter according to claim 4, characterized in that: The corrected virtual impedance proportional gain K v,out Limiting the amplitude includes: The corrected virtual impedance proportional gain K v,out Perform state-dependent dynamic descent rate limiting, where: Based on the corrected virtual impedance proportional gain K v,out Total amplitude of port voltage U pnm A fault ride-through state machine is established, comprising normal state, low-susceptibility state, high-susceptibility state, and recovery timing state. Fault ride-through states are identified, and state transition conditions are based on the modified virtual impedance proportional gain. K v,out Total amplitude of port voltage U pnm A judgment will be rendered.

6. The fault ride-through control method for a grid-type converter according to claim 5, characterized in that: The fault-crossing state machine includes: Set up state variables with memory functionality Flag ,in: Flag =0 represents the normal state, and the entry condition is: K v,out ≤1 and 0.95≤ U pnm ≤1.05 and I pnm ≤2 I lim and U nm ≤0.05, steady-state operation is achieved under this condition, and the network control virtual internal potential command is used. E * No need to stack U ; Flag =1 represents the low-penetration state, and the entry condition is: K v,out >1 and U pnm <0.9, in this state, low voltage ride-through is performed, and virtual impedance is applied according to the calculation; Flag =2 represents a high-penetration state, and the entry condition is: K v,out >1 and U pnm >1.1, under this condition, high voltage ride-through is performed, and virtual impedance is applied according to the calculation; The entry condition for the recovery state is Flag ≠0 and K v,out ≤1 and 0.95≤ U pnm ≤1.05 and I pnm ≤2 I lim and U nm ≤0.05, the timer is started in this state. Trec After the timer expires Flag =0.

7. A fault ride-through control method for a grid-type converter according to claim 5 or 6, characterized in that: The corrected virtual impedance proportional gain K v,out State-dependent dynamic descent rate limits include: Low-suspension state: Under fault conditions, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the first set value D lvrt ; Recovery state: During the fault recovery process, limit the proportional gain of the corrected virtual impedance. K v,out The descent rate does not exceed the second set value D norm And the second setting value D norm <First setting value D lvrt .

8. A fault ride-through control method for a grid-type converter according to claim 5 or 6, characterized in that: The corrected virtual impedance proportional gain K v,out Limiting the amplitude includes: For the corrected virtual impedance proportional gain K v,out Implement upper limit limiting, corrected virtual impedance proportional gain K v,out ≤ Virtual impedance ratio increases to upper limit K lim Output the final virtual impedance proportional gain K v,out,final .

9. A fault ride-through control method for a grid-type converter according to any one of claims 1 to 3, characterized in that: The final virtual impedance scaling gain K v,out,final The four components of the internal potential correction vector, which are mapped to the real-time current vector, the differential current vector, and the preset virtual impedance parameters, are expressed by the following formula: In the formula: U dp , U qp , U dn and U qn These represent the positive sequence of the internal potential correction vector. d Axis components, positive sequence q Axis components, negative order d Axial components and negative sequence q Axial components; I dp , I qp , I dn and I qn These represent the positive sequence current at the grid connection point, respectively. d Axis component, positive sequence current q Axial component, negative sequence current d Axial components and negative sequence currents q Axial components; R v To preset the virtual resistance, X v To preset virtual reactance, L v = X v / ω 0 represents virtual inductance. ω 0 is the rated angular frequency. dI dp , dI qp , dI dn and dI qn This corresponds to the differential component of the current.

10. A fault ride-through control system for a grid-connected converter, comprising the fault ride-through control method for a grid-connected converter as described in any one of claims 1 to 9, characterized in that, include: The grid voltage control module is used to calculate the virtual electromotive force command value and for positive and negative sequence. dq Angular velocity of component decomposition; The electrical quantity acquisition and calculation module is used to obtain the positive and negative sequence. dq Voltage and current components; The virtual impedance proportional gain calculation module is used to calculate the virtual impedance proportional gain based on the preset virtual impedance, the maximum allowable current limit, and the voltage deviation amplitude. K v ; The correction and dynamic limiting module is used to determine the asymmetric gain coefficient based on the negative sequence voltage component. γ For the virtual impedance proportional gain K v After correction, the virtual impedance proportional gain is obtained. K v,out ; and the corrected virtual impedance proportional gain K v,out Limiting is applied to output the final virtual impedance proportional gain. K v,out,final ; The virtual internal potential command correction module is used to adjust the final virtual impedance proportional gain. K v,out,final Mapped to the internal potential correction vector by real-time current vector, current differential vector, and preset virtual impedance parameters. U And superimpose it onto the virtual internal potential command vector generated by the voltage source control loop under normal operating conditions. E * The internal potential command vector is formed during the fault period. E * + U ; PWM The modulation module is used to adjust the internal potential command vector. E * + U Transformation to generate three phases PWM Switch signal.

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