A three-level power supply priority management circuit, system and switching method

Abstract

The application discloses a three-stage power supply priority management circuit, system and switching method, and relates to the technical field of power supply management. The circuit comprises a state detection logic module, an RS flip-flop circuit and a fast-on slow-off circuit. The state detection logic module is used for priority management and fault condition hardware judgment on AC power supply, DC power supply and battery power supply, and outputs a control signal; the RS flip-flop circuit receives an instruction, locks and maintains the switch state of each channel, and prevents false triggering; the fast-on slow-off circuit is used for realizing fast access of a new power supply channel and slow closing of a fault power supply channel during switching, realizing seamless transition of fast connection and slow switching, ensuring uninterrupted power supply, and having strong anti-interference ability of the circuit, avoiding the test non-covering problem of using a large-scale logic gate circuit or the risk of program control crash caused by using a single-chip microcomputer for program control, and greatly improving the reliability and safety of the system.

Description

Technical Field

[0001] This invention relates to the field of power supply management technology, specifically to a multi-level power supply priority management and seamless switching circuit that is purely hardware-driven and requires no microprocessor intervention. Background Technology

[0002] In applications with extremely high power supply reliability requirements, such as modern industrial control, specialized equipment, and medical support, systems are typically configured with multi-level redundant power supplies (such as AC mains, DC backup power, and batteries). In this architecture, how to perform real-time status monitoring and intelligent priority allocation of various power supplies to ensure that the load receives continuous and stable power under any unexpected conditions is a core issue in the field of power management technology.

[0003] Existing power priority switching schemes generally use digital circuit controllers (such as FPGAs, microcontrollers (MCUs), and digital signal processors (DSPs) as the control core. Their basic principle is to collect the status signals of the front-end power supply through sampling circuits and process them through an internal processor. The processor relies heavily on pre-written software programs and algorithms to perform periodic logical polling and priority judgment, and then outputs digital instructions to drive relays or switching devices, thereby completing the switching control of each power supply channel.

[0004] However, the aforementioned control methods based on software code and microprocessors are highly susceptible to external noise coupling interference in complex environments such as those with strong electromagnetic interference, posing a fatal risk of controller crashes and program malfunctions. Once the digital controller fails, the entire power management system will be completely paralyzed. Furthermore, when switching from the main power supply to the backup power supply in a traditional switching method, the superposition of software execution cycle and mechanical switching delay often results in a significant switching dead time, causing bus voltage drops and brief interruptions in load power supply. This simply cannot meet the stringent requirements of high-reliability equipment for zero-dropout uninterrupted power supply. Summary of the Invention

[0005] To address the problems existing in the prior art, the purpose of this invention is to overcome the shortcomings of existing digital program-controlled power switching schemes, such as the risk of system crashes, poor anti-interference capabilities, and susceptibility to power interruptions. This invention provides a three-level power priority management circuit, system, and switching method built entirely with analog gate circuits. This circuit utilizes hardware logic gates to achieve absolutely reliable priority judgment and innovatively employs an asymmetric delay trigger circuit to achieve a "first-connect, then-disconnect" mechanism that rapidly connects to the new power supply and slowly shuts down the faulty power supply, ensuring zero-interruption power switching.

[0006] This invention is achieved through the following technical solution: A three-level power supply priority management circuit includes: The status detection logic module is used to judge the fault conditions of each level of power supply and output control signals. Its priority is set from high to low as AC power supply first priority, DC power supply second priority and battery power supply third priority. The logic setting of the status detection logic module is as follows: when any level of power supply has a fault, output a shutdown command for the power supply of the fault level; when a higher priority level power supply is normal, output a start command for the higher priority power supply and output a shutdown command for the lower priority power supply. The RS flip-flop circuit includes an RS flip-flop; the set and reset terminals of the RS flip-flop receive power-on / off commands, and after receiving the commands, send the command signals to the next stage fast-on / slow-off circuit. The fast-on, slow-off circuit receives the command signal output by the RS trigger circuit. The fast-on, slow-off circuit includes a delayed shutdown circuit, which is composed of a PNP transistor, a diode, a resistor, and a capacitor. It is used to quickly connect the start command of the new power supply channel and delay the shutdown command of the fault power supply channel to output a slow shutdown signal, thereby forming a seamless transition during power switching where the new power supply is connected first and the fault power supply is disconnected later.

[0007] Preferably, the preset fault conditions monitored by the state detection logic module specifically include: For the AC power supply, the preset fault conditions include input over / under voltage, input overcurrent, output overcurrent, input phase loss, and AC internal auxiliary power supply abnormality; For the DC power supply and the battery power supply, the preset fault conditions include input over / under voltage, input overcurrent, output overcurrent, and internal auxiliary power supply abnormality.

[0008] Preferably, the state detection logic module is constructed using logic gate devices, which include one or more combinations of AND gates, OR gates, NAND gates, NOR gates, and inverters.

[0009] Preferably, the RS flip-flop in the RS flip-flop circuit is composed of two NOR gates with cross-feedback coupling.

[0010] Preferably, in the selection logic for the third priority battery power supply, the reset terminal of the RS flip-flop is connected to ground level; when both the AC power supply and the DC power supply fail, causing the main power supply of the system to fail, a supercapacitor is used to supply power to the auxiliary source for the battery power supply, and the RS flip-flop outputs an on signal based on the maintained power-on output state, so as to avoid the RS flip-flop from entering an illegal double high-level logic state when the auxiliary source for the battery power supply experiences overvoltage.

[0011] Preferably, for the third priority battery-powered external ground switch control command, the state detection logic module includes an instruction conversion unit; the instruction conversion unit uses NAND gates and NOT gates to perform logical processing on the input first ground switch control command and second ground switch control command to eliminate the all-high level state, and then performs Schmitt delay processing to form a power supply status signal which is sent to the judgment logic for source selection control.

[0012] Preferably, the status detection logic module is further configured to generate a system power-on signal; when a signal indicating that the AC power supply or the DC power supply is normal is received, the system power-on signal is generated; the system power-on signal participates in the control logic of the third priority battery power supply, and if the system power-on signal is not generated, it is determined that the battery power supply is unavailable.

[0013] A highly reliable three-level power supply system includes: a first-priority AC power supply, a second-priority DC power supply, a third-priority battery, and a three-level power supply priority management circuit as described in any one of claims 1 to 7. The status detection logic module of the three-level power supply priority management circuit is connected to the output status monitoring terminals of the AC power supply, DC power supply and battery, respectively.

[0014] Preferably, the power supply system further includes: Power execution switches are connected in series in the AC power supply, DC power supply and battery output main circuit respectively; The controlled terminal of each power execution switch is respectively connected to the output terminal of each level of the RS trigger circuit in the three-level power supply priority management circuit.

[0015] A method for seamless switching of three power supply priorities includes the following steps: The fault status conditions of each level of power supply are acquired in real time, and the start and stop instructions are generated through the hardware logic gates of the status detection logic module. When the status detection logic module determines that the low-priority power supply channel is faulty and the high-priority power supply channel is normal, the fast-on slow-off circuit built by the PNP transistor immediately executes the fast-on of the high-priority power supply channel. When the shutdown command of the fault channel passes through the fast-open-slow-close circuit, the diode in the fast-open-slow-close circuit prevents the RC network from discharging, thus executing the slow shutdown of the fault channel. By utilizing the time difference between the rapid closure of the new channel and the slow opening of the old channel, an overlapping power supply window is forced to be generated, which achieves zero voltage drop of the system bus during priority switching.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: This invention provides a three-level power supply priority management circuit. By using a state detection logic module built with pure analog gate circuits, it eliminates the need for digital controllers or software programs, fundamentally avoiding the risk of program crashes or errors, and achieving highly reliable power supply management. By setting three priority levels—AC power supply, DC power supply, and battery power supply—in descending order, and with the state detection logic module automatically outputting start and stop commands based on the fault status of each power supply level and the status of the higher-priority power supply, it achieves autonomous priority determination based on hardware logic, enabling automatic switching of power supply channels without external intervention. Furthermore, by employing a fast-on, slow-off circuit composed of PNP transistors, diodes, resistors, and capacitors, the fast conduction characteristics of PNP transistors enable the new power supply channel to be rapidly turned on within microseconds, while the diodes... By reverse-blocking the capacitor discharge circuit and allowing the capacitor to discharge slowly only through the resistor, a millisecond-level shutdown delay is generated for the fault-level power supply channel. This ensures that the system bus voltage is uninterrupted and does not drop during the switching process, while avoiding the risk of power conflict caused by the simultaneous long-term conduction of the old and new power supplies. By setting an RS trigger execution circuit, the final switching state of each power supply channel is locked and maintained, ensuring that the power supply channel state remains stable after the set or reset signal is removed. This prevents high-frequency oscillation at the power supply voltage critical point of the power supply channel control terminal, further improving the system's stability and anti-interference capability. The combined effect of the above technologies makes this circuit a complete replacement for digital control schemes, and it has significant practical value in high-reliability power supply applications such as communication base stations, data centers, and industrial control. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a simplified control diagram of the PWR_ON system power-on signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 2 This is a control principle diagram of the PWR_ON system power-on signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 3 This is a simplified control diagram of the PMGSELSSPC AC power selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 4This is a control principle diagram of the PMGSELSSPC AC power selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 5 This is a simplified control diagram of the SECSELSSPC DC power supply selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 6 This is a control principle diagram of the SECSELSSPC DC power supply selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 7 This is a simplified control diagram of the BATSELSSPC battery power selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention; Figure 8 This is a schematic diagram of the control principle of the BATSELSSPC battery power selection signal in the three-level power supply priority management circuit provided in this embodiment of the invention.

[0019] The above Figures 1 to 8 In the figures, the same or corresponding reference numerals indicate the same or corresponding components. The meanings of the logic gate symbols shown in each figure are common knowledge in the art, where: "&" represents an AND gate, "≥1" represents an OR gate, "1" represents a NOT gate / inverter, "&" with a circle represents a NAND gate, and "≥1" with a circle represents a NOR gate. The "E" section shown in each figure represents a fast-on, slow-off execution circuit, which internally contains a PNP transistor, diode, resistor, and capacitor.

[0020] in, Figure 1 and Figure 2 The main illustration shows the generation logic of the system power-on signal PWR_ON. This signal is generated only by the status availability signals of the first priority AC power supply and the second priority DC power supply through OR gate logic. The third priority battery power supply does not participate in the generation of PWR_ON. Figure 3 and Figure 4 The main illustration shows the control logic of the first priority AC power supply selection signal PMGSELSSPC. Various fault signals of AC power supply are judged by the status detection logic module and then sent to the RS flip-flop. The drive signal is then output through the fast-opening and slow-closing circuit (E part). Figure 5 and Figure 6 The main illustration shows the control logic of the second priority DC power supply selection signal SECSELSSPC. The DC power supply can be connected to the power supply system at any time when the AC power supply is abnormal. Its control signal is also latched by the RS flip-flop and then sent to the fast-opening and slow-closing circuit (E part) for output. Figure 7 and Figure 8This mainly illustrates the control logic of the third priority battery power selection signal BATSELSSPC. The DISC1 and DISC2 ground switch control commands are processed by NOT and NAND gates into set and reset signals that can be safely used with standard RS flip-flops. After Schmitt delay processing, these signals are sent to the judgment logic and output as drive signals through a fast-opening, slow-closing circuit (section E). Figure 8 The diagram also shows an optimized connection method where the reset terminal R of the RS flip-flop is permanently pulled down to ground. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] RS flip-flop: A basic bistable flip-flop with a set terminal (S terminal) and a reset terminal (R terminal). The output state is locked and toggled by the combination of signals at the S and R terminals.

[0023] RC charging and discharging network: A resistor-capacitor network consisting of a resistor (R) and a capacitor (C) connected in series. It uses the charging and discharging characteristics of the capacitor to achieve a time delay of the signal. The delay time is determined by the product constant of the resistor value and the capacitor value (RC time constant).

[0024] Power supply path: refers to the complete power transmission path of a certain priority power source (AC power supply, DC power supply or battery power supply) from the power input terminal to the system bus.

[0025] Power execution switch: A controllable switching device (such as a relay, MOSFET, IGBT, etc.) connected in series on the main power supply channel. Its conduction and turn-off are controlled by the switching control signal output by the RS flip-flop.

[0026] Fast-on, slow-off circuit: A power switching execution circuit characterized by fast response to the turn-on command and slow response to the turn-off command. That is, when the control signal jumps from an invalid level to an effective level, the output terminal quickly establishes the drive voltage / current; while when the control signal jumps from an effective level to an invalid level, the output terminal slowly decays the drive voltage / current.

[0027] Supercapacitors, also known as electric double-layer capacitors or farad capacitors, are energy storage devices with high power density, fast charge-discharge characteristics, and long cycle life. In this application, supercapacitors are used to provide temporary power to the auxiliary power source of the battery in extreme cases where both AC and DC power supplies fail simultaneously, so that the RS trigger in the control circuit can maintain correct state memory.

[0028] Air-to-ground switch control commands: In avionics, these are switch control signals used to distinguish whether the aircraft is in the air or on the ground. Different DISC1 / DISC2 combinations correspond to different operating modes of the battery busbar (Continuous mode / Momentary mode / Remaining on last valid state).

[0029] Example 1: Basic Architecture of a Three-Level Power Supply Priority Management Circuit See Figures 1 to 8 This invention provides a three-level power supply priority management circuit. It constructs a power supply priority switching selection logic using pure analog gate circuits and a fast-on, slow-off circuit built with transistors, achieving a seamless transition between fast on and slow off, ensuring uninterrupted power supply. The circuit also exhibits strong anti-interference capabilities, avoiding the test coverage issues associated with using large-scale logic gate circuits (FPGAs) or the risk of program control crashes introduced by microcontrollers. This significantly improves the reliability and security of the system. It enables automatic seamless switching between AC power supply (first priority), DC power supply (second priority), and battery power supply (third priority), ensuring stable output from the power bus in the event of a power supply failure or recovery at any level.

[0030] like Figures 1 to 8 As shown, this three-level power supply priority management circuit mainly consists of three parts: a status detection logic module, an RS flip-flop circuit, and a fast-on, slow-off circuit. Among them: The status detection logic module is used to monitor various power supply statuses and fault signals from external inputs in real time, and generates power-on or power-off commands for each level of power supply according to preset priority rules and fault judgment conditions. In a preferred embodiment, the status detection logic module is built using logic gate devices, including one or more combinations of AND gates, OR gates, NAND gates, NOR gates, and inverters. The advantages of using discrete logic gate devices to build the status detection logic module are: compared with using microprocessors or programmable logic devices, pure hardware logic gate circuits have outstanding advantages such as fast response speed (nanosecond level), no risk of program runaway, strong anti-electromagnetic interference capability, and high reliability under extreme temperature conditions, making them particularly suitable for high-reliability applications such as aviation. The input terminal of the status detection logic module is connected to the output status monitoring terminal of each level of power supply, receiving various fault detection signals from external inputs (including but not limited to input undervoltage, input overvoltage, input overcurrent, output overcurrent, input phase loss, internal auxiliary power supply abnormality, etc.), and its output terminal is connected to the first input terminal (set terminal) and the second input terminal (reset terminal) of the RS flip-flop circuit. In the state detection logic module, the priorities of each power supply level are set from high to low as follows: AC power supply with the first priority, DC power supply with the second priority, and battery power supply with the third priority.

[0031] The state detection logic module is configured as follows: When a preset fault condition exists in any power supply level, the state detection logic module outputs a shutdown command for that fault level. This shutdown command is output as a valid level (e.g., high level) to the reset terminal of the corresponding RS flip-flop, resetting the RS flip-flop and thus shutting down the power supply channel for that level. When a high-priority power supply is functioning normally, the state detection logic module outputs an enable command for the high-priority power supply and simultaneously outputs a shutdown command for the low-priority power supply, thereby ensuring that at any given time, the currently powered channel is the highest available priority power supply channel.

[0032] In one specific implementation, such as Figure 2As shown, the status detection signals (PMG_OK, AC_DC_OK, PMG_MP, PMG_BIAS_OVP_OFF, SEC_OK, DC1_OK, DC1_BIAS_OVP_OFF, etc.) of the first priority AC power supply (PMG) and the second priority DC power supply (DC1) are processed by AND gate / OR gate combination logic to output PMG_AVAIL and SEC_SRC_AVAIL signals, which are then passed through an OR gate to generate the PWR_ON system power-on signal. In this embodiment, each fault signal is a fault indication signal that is active low (i.e., outputting a low level when there is a fault). Therefore, it is necessary to first invert the signal by an inverter before sending it to an AND gate for logical AND operation to obtain an active high-level usable status signal. However, those skilled in the art should understand that if the fault signal is designed to be active high, the connection method of the corresponding logic gate should be adjusted accordingly, which does not exceed the protection scope of this invention.

[0033] The RS flip-flop circuit includes at least one RS flip-flop. The set (S) and reset (R) terminals of the RS flip-flop receive enable and disable command signals from the state detection logic module. After receiving these signals, the module performs state retention processing and sends them to the subsequent fast-on, slow-off circuit. The purpose of using an RS flip-flop is to latch and continuously output the command state when the enable or disable command output by the state detection logic module is a momentary pulse signal (e.g., during power state switching, the logic transition may be accompanied by glitches or brief disturbances). This prevents the power switch from being mistakenly turned off immediately after being enabled due to the momentary disappearance of the command signal, thus ensuring that the power supply channel maintains a stable on or off state during the valid command period, improving the system's anti-interference capability and operational stability.

[0034] In a preferred embodiment of the present invention, such as Figure 4 , Figure 6 and Figure 8 As shown, the RS flip-flop in the described RS flip-flop circuit is composed of two NOR gates cross-feedback coupled together (i.e., the outputs of the two NOR gates are respectively connected to one input of the other NOR gate, forming a standard RS flip-flop structure). Compared to the scheme using NAND gates, the set and reset terminals of the RS flip-flop constructed with NOR gates are both active high, which facilitates direct matching with the active high-level instruction signal output by the state detection logic module, eliminating the need for additional level conversion circuitry. The construction method of the RS flip-flop for the second-priority DC power supply and the third-priority battery power supply selection logic is similar and will not be elaborated further here.

[0035] The fast-on, slow-off circuit receives the command signal output by the RS flip-flop circuit. The fast-on, slow-off circuit includes a delay-off circuit, which is constructed using a PNP transistor, a diode, a resistor, and a capacitor. See also... Figure 4 , Figure 6 and Figure 8 In section E, the fast-on, slow-off circuit is used to quickly connect the start command of the new power supply channel (i.e., quickly turn on the newly selected power supply channel) and delay the shutdown command of the faulty power supply channel to output a slow shutdown signal (i.e., delay the shutdown of the replaced old power supply channel). This creates an overlapping power supply window during power switching, where the new power supply connects first and the faulty power supply is disconnected later, achieving a seamless transition of Make-before-Break. Specifically, when the fast-on, slow-off circuit receives a high-level start signal from the RS flip-flop, it uses the fast conduction characteristic of the PNP transistor to pull up the control terminal voltage of the power switch in microseconds, causing it to quickly enter the saturation conduction state. When it receives a low-level shutdown signal, the reverse blocking characteristic of the diode isolates the discharge circuit of the capacitor, which can only discharge slowly through a large-value resistor. This causes the control terminal voltage of the power switch to decrease slowly, and the power switch slowly transitions from the saturation region to the cutoff region, achieving a shutdown delay of milliseconds or even hundreds of milliseconds. The significant technical effect of this "make-before-break" mechanism is that the voltage on the system bus remains stable during the power supply switching instant, and there will be no voltage drop or spike pulse caused by power supply interruption. This ensures the normal operation of downstream loads (especially avionics equipment that is sensitive to voltage transients) and improves the reliability and power quality of the entire power supply system.

[0036] Example 2: Specific Implementation of Fault Detection Conditions Based on the three-level power supply priority management circuit described in Embodiment 1 above, this embodiment further elaborates on the preset fault conditions monitored by the state detection logic module.

[0037] In one specific implementation, the preset fault conditions for the first priority AC power supply include, but are not limited to, the following five: (1) Input undervoltage protection signal (corresponding to external input signal PMG_OK): When the input voltage of the AC power supply is lower than the preset undervoltage threshold, the PMG_OK signal becomes active (e.g., low level). The status detection logic module determines that there is an input undervoltage fault in this power supply level and outputs the corresponding shutdown command. The setting of this undervoltage threshold can be determined by those skilled in the art based on the normal operating voltage range of the AC power supply system in the actual application scenario. For example, the undervoltage threshold can be set to 80% to 90% of the rated input voltage, but it is not limited to this.

[0038] (2) Output overvoltage protection signal and output undervoltage protection signal (corresponding to external input signal AC_DC_OK): When the DC output voltage after internal rectification of the AC power supply is higher than the preset overvoltage threshold or lower than the preset undervoltage threshold, the AC_DC_OK signal becomes active, and the status detection logic module determines that there is an output overvoltage or undervoltage fault in this power supply stage. The setting of the overvoltage threshold and undervoltage threshold can be determined by those skilled in the art based on the allowable input voltage range of the downstream load. For example, the overvoltage threshold can be set to 110% to 120% of the rated output voltage, and the undervoltage threshold can be set to 80% to 90% of the rated output voltage, but it is not limited to this.

[0039] (3) Input phase loss protection signal (corresponding to external input signal PMG_MP): When any phase is missing or the three phases are severely unbalanced in the three-phase AC input of the AC power supply, the PMG_MP signal becomes active, and the status detection logic module determines that there is an input phase loss fault in this power supply stage. The phase loss detection of the three-phase AC input can be implemented using a conventional phase sequence detection circuit or a phase loss detection circuit. The specific circuit structure is common knowledge in this field and will not be described in detail here.

[0040] (4) Internal auxiliary power supply abnormality signal (corresponding to the external input signal PMG_BIAS_OVP_OFF): When an overvoltage occurs in the auxiliary source (which provides working power for the control circuit, drive circuit, etc.) inside the AC power supply, the PMG_BIAS_OVP_OFF ​​signal becomes active, and the status detection logic module determines that there is an internal auxiliary power supply abnormality fault in this stage of the power supply. The advantage of including the internal auxiliary power supply abnormality in the preset fault conditions is that even if the main power conversion part of the AC power supply is working normally, if the auxiliary power supply of its internal control circuit is abnormal, the entire AC power supply module cannot guarantee reliable operation and must be disconnected in time to prevent more serious faults caused by the loss of control of the control circuit.

[0041] For the second priority DC power supply and the third priority battery power supply, the preset fault conditions include, but are not limited to, the following four: (1) Input undervoltage protection signal (corresponding to external input signals SEC_OK, DC2IN_SELECT): When the input voltage of DC power supply / battery power supply is lower than the preset undervoltage threshold, the corresponding input undervoltage protection signal becomes effective, and the status detection logic module determines that there is an input undervoltage fault in this power supply level.

[0042] (2) Output overvoltage protection signal (corresponding to external input signals DC1_OK, DC2OUT_SELECT): When the output voltage of the DC power supply / battery power supply is higher than the preset overvoltage threshold, the corresponding output overvoltage protection signal becomes active, and the status detection logic module determines that there is an output overvoltage fault in this power supply stage. It should be noted that for battery power supply, its output undervoltage protection is not indicated by the DC2OUT_SELECT signal, but by the DC2IN_SELECT input undervoltage protection signal. When the battery output voltage is too low (i.e., the voltage input to the power conversion module is too low), the input undervoltage protection is triggered. Therefore, the battery power supply does not have a separate output undervoltage fault condition. For the main DC DC1, both its output undervoltage and overvoltage faults are indicated by the DC1_OK signal.

[0043] (3) Internal auxiliary power supply abnormal signal (corresponding to external input signals DC1_BIAS_OVP_OFF, DC2_BIAS_OVP_OFF): When the auxiliary source of DC power supply / battery power supply is overvoltaged, the corresponding auxiliary source overvoltage protection signal becomes effective, and the status detection logic module determines that there is an internal auxiliary power supply abnormal fault in this power supply level.

[0044] (4) Input overcurrent and output overcurrent (not directly listed in the external signal list, but can be implemented by an external current detection and comparison circuit connected to the status detection logic module): When the input current or output current of the DC power supply / battery power supply exceeds the preset overcurrent threshold, the status detection logic module determines that there is an overcurrent fault in the power supply level and outputs the corresponding shutdown command. The introduction of overcurrent protection further improves the safety of the system and prevents catastrophic failures caused by load short circuits or internal power supply short circuits.

[0045] In one specific embodiment of the present invention, all of the above-mentioned fault detection signals are active low (i.e., the signal is low when a fault occurs). The state detection logic module inverts each fault detection signal and then feeds it into an AND gate for logical operation. When all AND gate inputs are high (i.e., no faults exist), the AND gate output is high, indicating that the power supply for that stage is available. When any AND gate input is low (i.e., the corresponding fault exists), the AND gate output is low, indicating that the power supply for that stage is unavailable. This available state signal is then sent to the set or reset terminal of the RS flip-flop for power supply priority selection control.

[0046] Example 3: Specific circuit implementation of RS flip-flops Based on the above Embodiment 1 or Embodiment 2, this embodiment further defines and explains the specific implementation of the RS flip-flop in the RS flip-flop circuit.

[0047] In a preferred embodiment of the present invention, such as Figure 4 , Figure 6 and Figure 8 As shown in the internal RS flip-flop structure, the RS flip-flop in the circuit is composed of two NOR gates cross-feedback coupled together. Specifically, the output of the first NOR gate serves as the Q terminal (positive output) of the RS flip-flop, which is simultaneously connected to the first input of the second NOR gate; the output of the second NOR gate serves as the Q-inverted terminal (inverting output) of the RS flip-flop, which is simultaneously connected to the first input of the first NOR gate; the second input of the first NOR gate serves as the set terminal S of the RS flip-flop, and the second input of the second NOR gate serves as the reset terminal R of the RS flip-flop. When S is high and R is low, Q outputs a high level and is latched; when S is low and R is high, Q outputs a low level and is latched; when both S and R are low, Q maintains the output of the previous state; when both S and R are high, the output states of Q and Q-inverted terminals are uncertain, which is an illegal prohibited state.

[0048] In the selection logic for the third priority battery power supply, in order to completely eliminate the illegal double high-level state that may occur in the aforementioned RS flip-flop, the present invention, in its optimized design in version V2, see [link to relevant documentation]. Figure 8 As shown, the reset terminal R of the RS flip-flop is connected to ground through a resistor (i.e., R is permanently pulled down to a low level). In this case, the RS flip-flop actually operates by outputting a high level and holding it when the S terminal is active, and maintaining the previous state when the S terminal is inactive (because R is always low, the reset function is permanently disabled). The principle and operation of this design are as follows: When both AC and DC power supplies are normal, the system is powered by the high-priority AC or DC power supply, which also provides starting power to the battery's auxiliary power source, keeping the battery in standby mode. At this time, the supercapacitor is fully charged due to the presence of the main power supply. When both AC and DC power supplies fail, causing a power outage, the battery's auxiliary power source is temporarily powered by the supercapacitor (or the battery's own energy storage). As long as the AC or DC power supply has been applied, the supercapacitor has stored enough energy to provide short-term power to the battery's auxiliary power source and control circuit. At this time, since both PMG and DC1 are faulty, the signal output from the status detection logic module to the battery RS flip-flop set terminal S is low (no start command), while the reset terminal R is permanently pulled down to low. The RS flip-flop is in a state of S=0, R=0, and according to the characteristics of the RS flip-flop, its output terminal Q retains the previous state. Since the battery selection signal was set to high level when the main power supply of the system was normal (the battery was in standby and enabled state), the Q output of the RS flip-flop continued to maintain a high level output, so that the battery power supply channel could be turned on normally and provide backup power for the downstream load.

[0049] The significant technical advantages of this RS flip-flop reset terminal R being permanently grounded are as follows: First, it completely eliminates the output uncertainty problem that may occur in the illegal state of S=1 and R=1 of traditional RS flip-flops. Since the R terminal is always at a low level, the state of S=1 and R=1 will never occur, fundamentally eliminating the risk of logic competition and output oscillation. Second, when the battery auxiliary power source experiences overvoltage (corresponding to the external input signal DC2_BIAS_OVP_OFF ​​becoming effective), since the selection logic of PWR_ON signal and PMG / DC1 has higher priority than the battery selection logic, the system will not mistakenly turn on or off the battery regardless of the output state of the battery's RS flip-flop, further improving the system's fault tolerance. Third, through the coordinated operation of supercapacitor energy storage and RS flip-flop state retention function, reliable access to battery power supply is achieved in the extreme case of complete loss of main power, ensuring continuous power supply to the system.

[0050] It should be noted that the above-mentioned optimized scheme of permanently grounding the reset terminal R of the RS trigger is a special design for third-priority battery power supply, and is not applicable to RS triggers for first-priority AC power supply and second-priority DC power supply. This is because for high-priority power supply, the RS trigger must retain complete set and reset functions to achieve reliable shutdown in the event of a high-priority power failure and restart during recovery.

[0051] Example 4: Processing of Battery Ground Switch Control Commands Based on any of the above embodiments one to three, this embodiment provides a more detailed description of the processing of the air-to-ground switch control command unique to the third priority battery power supply station.

[0052] See Figure 7 and Figure 8 As shown, for the third-priority battery power supply, it needs to respond not only to basic fault detection signals but also to externally input air-to-ground switch control commands DISC1 and DISC2 (corresponding to external input signals DISC1 and DISC2, respectively). In a specific application scenario, DISC1 and DISC2 are generated by the air-to-ground status sensor on the aircraft or a ground maintenance switch to indicate whether the aircraft is currently in the air or on the ground, thereby controlling the operating mode of the battery busbar to adapt to the needs of different flight phases. The correspondence between the combined logic states of DISC1 and DISC2 and the operating modes of the battery busbar is as follows: When DISC1=1 and DISC2=0, the battery busbar status is Continuous, indicating that the battery busbar remains connected during continuous operation of the aircraft.

[0053] When DISC1=0 and DISC2=1, the battery busbar status is Momentary (instantaneous working mode), indicating that the battery busbar is only connected under certain instantaneous operating conditions.

[0054] When DISC1=1 and DISC2=1, the battery busbar state remains the last valid state, that is, the Continuous or Momentary state determined in the previous timing cycle remains unchanged.

[0055] When DISC1=0 and DISC2=0, the battery busbar state remains the last valid state, that is, the Continuous or Momentary state determined in the previous timing cycle remains unchanged.

[0056] Since the combined logic of DISC1 and DISC2 is not the standard RS flip-flop input logic, it cannot be directly used to drive the RS flip-flop (because the RS flip-flop requires that S and R cannot be high at the same time, and when DISC1=1 and DISC2=1, S and R being high at the same time will result in an illegal state). Therefore, the state detection logic module includes an instruction conversion unit. This instruction conversion unit uses NAND gates and NOT gates to perform logical processing on the input first empty-ground switch control instruction DISC1 and the second empty-ground switch control instruction DISC2 to eliminate the all-high-level state and convert DISC1 and DISC2 into standard RS flip-flop logic signals BATT_S and BATT_R that can be safely used.

[0057] In one specific implementation, the instruction conversion unit is implemented as follows: the DISC1 signal is split into two paths, one of which is directly used as the BATT_S signal (S terminal), and the other is inverted by a NOT gate and input to one input terminal of a NAND gate; the DISC2 signal is also split into two paths, one of which is directly used as the BATT_R signal (R terminal), and the other is inverted by a NOT gate and input to the other input terminal of a NAND gate; the output terminal of the NAND gate is connected to an additional reset control terminal, which is used to force the state of the RS flip-flop to be locked in the hold state when DISC1=1 and DISC2=1.

[0058] Its truth table logic is shown in Table 1:

[0059] Through the processing of the instruction conversion unit, no matter how DISC1 and DISC2 are combined, the S and R signals input to the RS flip-flop will not be in an illegal state where they are both high at the same time, thus ensuring the deterministic operation of the RS flip-flop.

[0060] Subsequently, the BATT_S and BATT_R signals, processed by the command conversion unit, drive the RS flip-flop to generate the intermediate state signal BATT_DISC_BDE_STATUS1. This intermediate state signal is then subjected to a Schmitt delay of 500ms ± 250ms (i.e., within the range of 250ms to 750ms), forming the final BATT_DISC_BDE_STATUS signal, which is then sent to the subsequent judgment logic for source selection control. The advantages of using a 500ms ± 250ms Schmitt delay are twofold: First, this delay time is much longer than the mechanical jitter time (typically a few milliseconds to tens of milliseconds) that may occur in the external air-to-ground switch command signal, effectively filtering out jitter and glitches generated by the command signal during the switchover process, preventing frequent transitions in the battery busbar state between Continuous and Momentary states, and improving the system's operational stability. Second, the 500ms delay time is sufficiently short compared to the rapid response requirements (millisecond level) for power supply switching, and will not have a substantial impact on the switching response speed of the aircraft between different flight phases, ensuring the system's rapid response capability. The Schmitt delay circuit can be implemented using a conventional Schmitt trigger integrated circuit (such as 74HC14) in conjunction with an RC delay network.

[0061] Example 5: Generation and Control of System Power-On Signal Based on any of the embodiments one to four above, this embodiment provides a more detailed description of the system power-on signal PWR_ON generated by the state detection logic module.

[0062] like Figure 1 and Figure 2 As shown, in one specific embodiment of the present invention, the state detection logic module is further used to generate a system power-on signal PWR_ON. When the state detection logic module receives a signal indicating normal AC power supply of the first priority or normal DC power supply of the second priority (i.e., PMG_AVAIL is high or SEC_SRC_AVAIL is high), it generates the system power-on signal PWR_ON as high through an OR gate logic. In other words, the PWR_ON signal indicates that the first or second level of power supply is available in the system, that is, the system has received mains power. The third priority battery power supply does not participate in the generation of the PWR_ON signal. Even if the battery power supply is completely normal and available, if both AC and DC power supplies are unavailable, the PWR_ON signal will still be low.

[0063] The system power-on signal PWR_ON participates in the third-priority battery power supply control logic. Specifically, the PWR_ON signal and the output signal of the battery RS flip-flop are logically ANDed through an AND gate. The battery power supply channel is only allowed to be turned on when the PWR_ON signal is high and the battery RS flip-flop output is high. If the system power-on signal PWR_ON is not generated (i.e., it is low), the battery power supply is forcibly turned off regardless of the output state of the battery RS flip-flop, meaning the battery power supply is deemed unavailable.

[0064] Another important function of the PWR_ON signal is that its logic design provides protection for the initial use of the battery. Specifically, when the system is initially off-power, the PWR_ON signal is an invalid low level, forcibly shutting off the battery power supply channel and preventing the battery from being turned on upon initial system power-up. Only after at least one of the AC or DC power supplies is powered on normally will the PWR_ON signal become an effective high level, allowing the battery power supply channel to be turned on. This logical constraint ensures that the battery can only be connected after the main power supply has been properly established, avoiding the risk of over-discharge or malfunction caused by the battery being accidentally turned on in an unknown initial state where the auxiliary power source has not yet been established and the supercapacitor has no energy storage. This effectively protects the battery's cycle life and system safety.

[0065] The physical meaning of this logic is as follows: When the system has never been powered on (neither AC nor DC power supply has ever been properly established), the supercapacitor has no stored energy, the battery's auxiliary power source cannot start, and the battery's control circuit has no working power. Even if the battery cells themselves have charge, they cannot be connected to the power supply system because battery connection requires the controller to issue enable signals such as BATT_INTLK, which cannot be provided when the controller is not powered on. Therefore, forcibly determining the battery as unusable when PWR_ON=0 is a safety design that conforms to the actual physical constraints of the system.

[0066] In specific circuit implementations, such as Figure 2As shown, the PWR_ON signal is generated by an OR gate from the PMG_AVAIL and SEC_SRC_AVAIL signals. The PMG_AVAIL signal is derived from the various fault detection signals of the AC power supply through combinational logic, and the SEC_SRC_AVAIL signal is derived from the various fault detection signals of the DC power supply through combinational logic. When either PMG_AVAIL or SEC_SRC_AVAIL is high, PWR_ON outputs a high level, indicating that the system power-on is complete. This PWR_ON signal is then sent to the battery selection logic and ANDed with the output Q of the battery RS flip-flop. Only when PWR_ON is high and the Q output of the battery RS flip-flop is high is the battery power switch allowed to conduct.

[0067] Example 6: Complete Implementation of the Power Supply System Based on the three-level power supply priority management circuit described in any one of the embodiments 1 to 5 above, the present invention also provides a highly reliable three-level power supply system, including: an AC power supply with first priority, a DC power supply with second priority, a battery with third priority, and a three-level power supply priority management circuit as described in any one of the embodiments 1 to 5 above.

[0068] The status detection logic module of the three-level power supply priority management circuit is connected to the output status monitoring terminals of the AC power supply, DC power supply, and battery, respectively, for real-time acquisition of fault detection signals of each power supply level. Specifically, the output status monitoring terminal of the AC power supply outputs at least four types of signals: PMG_OK (input undervoltage protection), AC_DC_OK (output over / undervoltage protection), PMG_MP (input phase loss protection), and PMG_BIAS_OVP_OFF ​​(auxiliary source overvoltage protection); the output status monitoring terminal of the DC power supply outputs at least three types of signals: SEC_OK (input undervoltage protection), DC1_OK (output over / undervoltage protection), and DC1_BIAS_OVP_OFF ​​(auxiliary source overvoltage protection); the output status monitoring terminal of the battery outputs at least three types of signals: DC2IN_SELECT (input undervoltage protection), DC2OUT_SELECT (output overvoltage protection), and DC2_BIAS_OVP_OFF ​​(auxiliary source overvoltage protection). In addition, it also needs to receive external control command signals such as DISC1, DISC2, and BATT_INTLK.

[0069] In one specific embodiment of the present invention, combined with Figures 1 to 8As shown, the power supply system further includes: a first power execution switch (such as a PMG power switch) connected in series on the AC power output main line, a second power execution switch (such as a DC1 power switch) connected in series on the DC power output main line, and a third power execution switch (such as a battery power switch) connected in series on the battery output main line. The controlled terminal of each power execution switch is respectively connected to the output terminal of each level of the RS trigger circuit in the three-level power supply priority management circuit after passing through the fast-on, slow-off circuit. Specifically, the controlled terminal of the first power execution switch corresponding to the AC power supply is connected to the PMG SELSSPC signal terminal (i.e., the AC power supply selection signal output terminal, see...). Figure 3 and Figure 4 The controlled terminal of the second power execution switch corresponding to the DC power supply is connected to the SECSELSSPC signal terminal (i.e., the DC power supply selection signal output terminal, see...). Figure 5 and Figure 6 The controlled terminal of the third power actuator switch corresponding to the battery is connected to the BATSELSSPC signal terminal (i.e., the battery selection signal output terminal, see...). Figure 7 and Figure 8 ).

[0070] In specific hardware selection, the power execution switch can be a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a solid-state relay. An N-channel enhancement-mode power MOSFET is preferred due to its advantages such as low on-resistance, fast switching speed, and simple drive circuit. When the fast-on, slow-off circuit outputs a high level, the power MOSFET is turned on, and the corresponding power supply is connected to the system bus. When the fast-on, slow-off circuit outputs a low level, the power MOSFET is turned off, and the corresponding power supply is disconnected from the system bus.

[0071] The system operates as follows: Under normal operating conditions, the first-priority AC power supply prioritizes powering downstream loads, while simultaneously providing power to the second-priority DC power supply and the third-priority battery auxiliary power supply, ensuring all power supplies are in standby mode. When the status detection logic module detects a fault in the AC power supply, it outputs a shutdown command for the AC power supply channel. Simultaneously, since the DC power supply is functioning normally, the status detection logic module outputs an activation command for the DC power supply channel, achieving seamless switching from AC to DC power supply through a fast-on, slow-off circuit. When the AC power supply returns to normal, the status detection logic module re-outputs the activation command for the AC power supply channel and the shutdown command for the DC power supply channel, and the system automatically switches back to AC power. When both the AC and DC power supplies fail simultaneously, the status detection logic module outputs an activation command for the battery power supply channel, allowing the battery to provide backup power to downstream loads and ensuring continuous system operation.

[0072] Example 7: Seamless Switching Method for Three-Level Power Supply Priority Based on the management circuit and power supply system described in any of the embodiments one to six above, the present invention also provides a method for seamless switching of three-level power supply priorities, comprising the following steps: Step 1: Real-time acquisition of fault status conditions for each power supply level. The status detection logic module receives various fault detection signals in real time from the output status monitoring terminals of the AC power supply, DC power supply, and battery through its input terminals. These signals include, but are not limited to, input undervoltage, output overvoltage, output undervoltage, input phase loss, input overcurrent, output overcurrent, and auxiliary source overvoltage. Upon receiving the aforementioned fault detection signals, the status detection logic module uses internally preset logic gate circuits (a combination of AND gates, OR gates, NAND gates, NOR gates, and inverters) to comprehensively determine the various fault signals and generate real-time available status signals (PMG_AVAIL, SEC_SRC_AVAIL, BATT_AVAIL) for each power supply level. Based on the combination of available status signals at each level, the hardware logic gates of the status detection logic module generate start-up and shutdown commands for each power supply level. Specifically, when a high-priority power supply is available, the status detection logic module outputs an enable command for the high-priority power supply and simultaneously outputs a disable command for all power supplies with lower priority than the high-priority power supply; when all high-priority power supplies are unavailable, the status detection logic module outputs an enable command for the currently highest available priority power supply.

[0073] Step Two: Rapid Enabling of the High-Priority Power Supply Channel. When the status detection logic module determines that the low-priority power supply channel is faulty (or the high-priority power supply has been restored), and the high-priority power supply channel is normal, the high-priority power supply enable command output by the status detection logic module is latched by an RS flip-flop and sent to the fast-on, slow-off circuit built with a PNP transistor. In the fast-on, slow-off circuit, the enable command signal responds rapidly through the base-emitter junction of the PNP transistor, causing the PNP transistor to quickly enter the saturation conduction state. The control terminal voltage of the power execution switch is quickly pulled up to above the drive voltage threshold, and the power execution switch completes conduction within microseconds. Simultaneously, the enable command signal also rapidly charges the capacitor through a diode. This diode has extremely low forward conduction resistance, allowing the voltage across the capacitor to build up rapidly, further accelerating the conduction speed of the power switch. Through the above mechanism, the fast-on, slow-off circuit immediately executes the rapid enabling of the high-priority power supply channel, with an enable response time typically less than 100 microseconds.

[0074] Step 3: Slow shutdown of the low-priority power supply channel in case of fault. When the shutdown command for the fault channel passes through the fast-on, slow-off circuit, the diode in the circuit is reverse-biased (i.e., the diode is cut off), hindering the discharge of the RC network (i.e., the resistor-capacitor charging and discharging network). Specifically, the shutdown command signal causes the base of the PNP transistor to go low, and the PNP transistor exits the saturation state. However, because the diode is reverse-biased, the charge stored in the capacitor cannot be quickly released through the diode, but can only be slowly discharged through the large-value resistor connected in parallel across the capacitor. The voltage across the capacitor slowly decreases as the discharge time progresses, causing the control terminal voltage of the power execution switch to gradually decrease. The power execution switch slowly transitions from the saturation conduction region to the linear region and then to the cutoff region. The duration of the entire shutdown process is determined by the RC time constant, and the required shutdown delay can be set by adjusting the resistor and capacitor values. The typical delay range is 10 milliseconds to 500 milliseconds. Through this mechanism, the fast-on, slow-off circuit performs the slow shutdown of the fault channel.

[0075] Step 4: Creating an Overlapping Power Supply Window for Zero-Drop Switching. By utilizing the time difference between the rapid closing of the new channel and the slow opening of the old channel—that is, on the timeline, the opening time of the high-priority channel is earlier than the complete shutdown time of the low-priority channel—an "overlapping window" is formed where both high-priority and low-priority power supply channels are simultaneously active. The duration of this overlapping window is equal to the shutdown delay of the low-priority channel minus the opening response time of the high-priority channel (since the opening response time is much shorter than the shutdown delay, the duration of the overlapping window is approximately equal to the shutdown delay). During this overlapping window, the system bus is jointly powered by the newly connected high-priority power supply and the soon-to-be-departed low-priority power supply, ensuring continuous power supply without interruption. Through this Make-before-Break switching mechanism, a Make-before-Break overlapping power supply window is forcibly generated, achieving zero voltage drop (i.e., the voltage drop is close to 0 and negligible) on the system bus during priority switching, ensuring the continuous and stable operation of downstream loads during power supply switching.

[0076] In a preferred embodiment of the present invention, the turn-off delay parameters of the fast-on, slow-off circuit can be configured independently for different power supply switching scenarios (AC to DC, DC to AC, AC to battery, DC to battery, etc.) to adapt to the output impedance characteristics and bus capacitance of different power modules. For example, for high-power power modules, which have larger output bus capacitance, a longer turn-off delay (e.g., 200ms to 500ms) can be set to ensure that the overlapping window sufficiently covers the bus capacitance discharge time; for low-power power modules, a shorter turn-off delay (e.g., 10ms to 50ms) can be set to reduce energy return and circulating current losses during the overlapping window. The specific value of the turn-off delay can be optimized and adjusted by those skilled in the art according to actual application conditions, which does not exceed the protection scope of the present invention.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Those skilled in the art can readily implement the present invention based on the accompanying drawings and the above description. However, any modifications, alterations, or variations made by those skilled in the art without departing from the scope of the present invention, utilizing the disclosed technical content, are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, or variations made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the present invention.

Claims

1. A three-level power supply priority management circuit, characterized in that, include: The status detection logic module is used to judge the fault conditions of each level of power supply and output control signals. Its priority is set from high to low as AC power supply first priority, DC power supply second priority and battery power supply third priority. The logic setting of the status detection logic module is as follows: when any level of power supply has a fault, output a shutdown command for the power supply of the fault level; when a higher priority level power supply is normal, output a start command for the higher priority power supply and output a shutdown command for the lower priority power supply. The RS flip-flop circuit includes an RS flip-flop; the set and reset terminals of the RS flip-flop receive power-on / off commands, and after receiving the commands, send the command signals to the next stage fast-on / slow-off circuit. The fast-on, slow-off circuit receives the command signal output by the RS trigger circuit. The fast-on, slow-off circuit includes a delayed shutdown circuit, which is composed of a PNP transistor, a diode, a resistor, and a capacitor. It is used to quickly connect the start command of the new power supply channel and delay the shutdown command of the fault power supply channel to output a slow shutdown signal, thereby forming a seamless transition during power switching where the new power supply is connected first and the fault power supply is disconnected later.

2. The three-level power supply priority management circuit according to claim 1, characterized in that, The preset fault conditions monitored by the state detection logic module specifically include: For the AC power supply, the preset fault conditions include input over / under voltage, input overcurrent, output overcurrent, input phase loss, and AC internal auxiliary power supply abnormality; For the DC power supply and the battery power supply, the preset fault conditions include input over / under voltage, input overcurrent, output overcurrent, and internal auxiliary power supply abnormality.

3. The three-level power supply priority management circuit according to claim 1, characterized in that, The state detection logic module is built using logic gate devices, which include one or more combinations of AND gates, OR gates, NAND gates, NOR gates, and inverters.

4. The three-level power supply priority management circuit according to claim 1, characterized in that, The RS flip-flop in the RS flip-flop circuit is composed of two NOR gates with cross-feedback coupling.

5. The three-level power supply priority management circuit according to claim 4, characterized in that, In the selection logic for the third priority battery power supply, the reset terminal of the RS flip-flop is connected to ground. When both the AC power supply and the DC power supply fail, causing the main power supply of the system to fail, a supercapacitor is used to supply power to the auxiliary source for the battery power supply. The RS flip-flop outputs an on signal based on the maintained power-on output state to avoid the RS flip-flop from entering an illegal double high-level logic state when the auxiliary source for the battery power supply experiences overvoltage.

6. The three-level power supply priority management circuit according to claim 1, characterized in that, For the third priority battery-powered external ground switch control command, the state detection logic module includes an instruction conversion unit. The instruction conversion unit uses NAND gates and NOT gates to perform logical processing on the input first and second ground switch control commands to eliminate the all-high level state. Then, after Schmitt delay processing, a power supply status signal is formed and sent to the judgment logic for source selection control.

7. The three-level power supply priority management circuit according to claim 1, characterized in that, The status detection logic module is also used to generate a system power-on signal; when a signal indicating that the AC power supply or the DC power supply is normal is received, the system power-on signal is generated; the system power-on signal participates in the control logic of the third priority battery power supply, and if the system power-on signal is not generated, it is determined that the battery power supply is unavailable.

8. A highly reliable three-level power supply system, characterized in that, include: The first priority AC power supply, the second priority DC power supply, the third priority battery, and the three-level power supply priority management circuit as described in any one of claims 1 to 7. The status detection logic module of the three-level power supply priority management circuit is connected to the output status monitoring terminals of the AC power supply, DC power supply and battery, respectively.

9. The high-reliability three-level power supply system according to claim 8, characterized in that, The power supply system also includes: Power execution switches are connected in series in the AC power supply, DC power supply and battery output main circuit respectively; The controlled terminal of each power execution switch is respectively connected to the output terminal of each level of the RS trigger circuit in the three-level power supply priority management circuit.

10. A method for seamless switching of three power supply priorities based on the management circuit described in any one of claims 1 to 7, characterized in that, Includes the following steps: The fault status conditions of each level of power supply are acquired in real time, and the start and stop instructions are generated through the hardware logic gates of the status detection logic module. When the status detection logic module determines that the low-priority power supply channel is faulty and the high-priority power supply channel is normal, the fast-on slow-off circuit built by the PNP transistor immediately executes the fast-on of the high-priority power supply channel. When the shutdown command of the fault channel passes through the fast-open-slow-close circuit, the diode in the fast-open-slow-close circuit prevents the RC network from discharging, thus executing the slow shutdown of the fault channel. By utilizing the time difference between the rapid closure of the new channel and the slow opening of the old channel, an overlapping power supply window is forced to be generated, which achieves zero voltage drop of the system bus during priority switching.

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