DC power supply and its method

Abstract

This disclosure relates to a DC power supply and a method thereof. A DC power supply includes: a power stage for outputting an output voltage; a differential block for comparing a feedback signal corresponding to the output voltage with a reference voltage to generate an error signal; and a controller for generating a control signal based on the error signal to control the power stage to reach the output voltage, the controller including an integer determination block for determining an integer based on the error signal; wherein the control signal has a switching frequency; wherein the system operates at a system operating frequency; and wherein the switching frequency is an integer multiple of the system operating frequency.

Description

Technical Field

[0001] This invention relates to a DC power supply, and more particularly to a DC power supply that is synchronized with the applied system. Background Technology

[0002] Unless otherwise specified, the practices described below are not prior art within the scope of this application's patents, and the contents of this paragraph should not be included in the prior art.

[0003] Direct current (DC) power supplies or switching mode power supplies (SMPS) are used in a variety of systems, including sound systems. During the operation of a DC power supply or SMPS, ripple noise or other types of noise can easily be introduced into the system.

[0004] For sound-generating systems, especially those that generate sound by producing ultrasonic pulses, (ripple) noise may beat with the operating frequency, and one beat of the noise may fall into the audible spectrum, thereby reducing sound performance.

[0005] Therefore, existing technologies urgently need improvement. Summary of the Invention

[0006] Therefore, the main objective of this invention is to provide a DC power supply that is synchronized with the applied system, thereby overcoming the shortcomings of the prior art.

[0007] This invention provides a DC power supply for providing an output voltage to a system. The DC power supply includes a power stage for outputting the output voltage; a differential block for comparing a feedback signal corresponding to the output voltage with a reference voltage to generate an error signal; and a controller for generating a control signal based on the error signal to control the power stage to reach the output voltage. The controller includes an integer determination block for determining an integer based on the error signal. The control signal has a switching frequency. The system operates at a system operating frequency. The switching frequency is an integer multiple of the system operating frequency.

[0008] This invention provides a DC power supply for providing an output voltage to a system. The DC power supply includes a power stage for outputting the output voltage and includes multiple sub-power stages; a differential block for comparing a feedback signal corresponding to the output voltage with a reference voltage to generate an error signal; and a controller for generating a control signal based on the error signal to control the power stage to reach the output voltage. The controller includes a percentage determination block for determining a percentage of an active sub-power stage based on the error signal.

[0009] This invention provides a method for a switching mode power supply, wherein the switching mode power supply is used to provide an output voltage to a system, the method comprising generating an error signal based on the output voltage; and adjusting a switching frequency of the switching mode power supply based on the error signal; wherein the switching frequency is synchronized with a system operating frequency of the system. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a DC power supply according to an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram of a DC power supply according to an embodiment of the present invention.

[0012] Figure 3 It corresponds to Figure 2 A waveform diagram of a DC power supply.

[0013] Figure 4 This is a schematic diagram of an integer determination block according to an embodiment of the present invention.

[0014] Figure 5 This is a schematic diagram of a power stage according to an embodiment of the present invention.

[0015] Figure 6 This is a schematic diagram of a power stage according to an embodiment of the present invention.

[0016] Figure 7 This is a schematic diagram of a power stage according to an embodiment of the present invention.

[0017] Figure 8 This is a schematic diagram of a percentage-determined block according to an embodiment of the present invention.

[0018] Figure 9 This is a schematic diagram of a clamping circuit according to an embodiment of the present invention.

[0019] Figure 10 This is a schematic diagram of a clamping circuit according to an embodiment of the present invention.

[0020] Figure 11 This is a schematic diagram of a clamping circuit according to an embodiment of the present invention.

[0021] Figure 12 This is a schematic diagram of an amplifier circuit according to an embodiment of the present invention.

[0022] Figure 13 This is a schematic diagram of an amplifier circuit according to an embodiment of the present invention.

[0023] Figure 14This is a schematic diagram of an air pulse generating device according to an embodiment of the present invention.

[0024] Figure 15 yes Figure 14 A schematic diagram of the drive signal waveform of the air pulse generating device.

[0025] Symbol Explanation

[0026] 10: DC Power Supply

[0027] 12: Controller

[0028] 14: Power Stage

[0029] 16: Feedback Network

[0030] 18: Differential partitioning

[0031] 11: Feedback control loop

[0032] Vout: Output voltage

[0033] F sys System operating frequency

[0034] FB: Feedback Signal

[0035] V REF Reference voltage

[0036] e Error signal

[0037] ct: control signal

[0038] F SW Switching frequency

[0039] N: Integer

[0040] 20: DC power supply

[0041] 22: Controller

[0042] 24: Power Stage

[0043] 26: Feedback Network

[0044] 28: Difference Block

[0045] ct_PWM: PWM control signal

[0046] 222: Switching the clock generator

[0047] CLK: Switch clock

[0048] 224: Sawtooth Signal Generator

[0049] SAW: Sawtooth signal

[0050] 226: Pulse Width Modulator

[0051] LV: Level

[0052] 220: Integers determine blocks

[0053] PDV1: First Critical Value

[0054] PDV2: Second Critical Value

[0055] PDV0: Third Critical Value

[0056] n1: First increment

[0057] n2: Second increment

[0058] 320: Integers determine blocks

[0059] 420: Integers determine blocks

[0060] 3202, 4202: Error signal classification blocks

[0061] 3204, 4204: Determine the block

[0062] 34: Power Stage

[0063] L BB Inductor

[0064] S1~S4: Switches

[0065] 44: Power Stage

[0066] 54: Power Stage

[0067] 441~443: Sub-power stages

[0068] S 11 - S 13 S 21 -S 23 S 31 -S 33 S 41 -S 43 :switch

[0069] 228: Percentage determines block size

[0070] PC: Percentage

[0071] N L1 N L2 :node

[0072] Nin, Nout: Endpoints

[0073] 328: Percentage determines block size

[0074] 428: Percentage determines block size

[0075] 3282, 4282: Error signal classification blocks

[0076] 3284, 4284: Determine the block

[0077] 35: Clamping circuit

[0078] 45: Clamping circuit

[0079] 55: Clamping circuit

[0080] V1: Voltage

[0081] PM: PMOS

[0082] PB: PNP BJT

[0083] 450, 550: Amplifier

[0084] CLP: Clamping Signal

[0085] V REF ':Voltage

[0086] R1, R2, R1': Resistors

[0087] 37: Amplifier Circuit

[0088] 47: Amplifier Circuit

[0089] 370, 470: Differential input stage

[0090] 372, 472: First amplifier output stage

[0091] 374, 474: Second amplifier output stage

[0092] 471: Compensation Circuit

[0093] P1, N1, P2, N2: Transistors

[0094] 1: Air Pulse Generation System

[0095] 13: Air pulse generating device

[0096] 130: Membrane Structure

[0097] 132: Lobe Pair

[0098] 101: First petal

[0099] 103: Second lobe

[0100] 15: Drive circuit

[0101] SV1, SV2: Valve drive signals

[0102] SM: Pressure Drive Signal

[0103] Fv: Valve drive frequency

[0104] F M Pressure-driven frequency

[0105] T V Valve drive cycle

[0106] T M Pressure-driven cycle

[0107] S IN Input signal Detailed Implementation

[0108] The technical features described in the following embodiments can be mixed or combined in various ways as long as they do not conflict with each other.

[0109] In this invention, the term "coupled to" can refer to a direct or indirect connection. "Component A is coupled to component B" can mean that component A is directly connected to component B, or that component A is connected to component B through some component C.

[0110] A DC power supply or switching mode power supply (SMPS) is used to provide DC power / voltage to a system (such as a sound system), wherein the DC power supply operates at a switching frequency and the system operates at a system operating frequency.

[0111] In this invention, the terms "DC power supply" and "mode switching power supply" can be used interchangeably.

[0112] In this invention, the switching frequency of the DC power supply is limited to be synchronized with the system operating frequency. Under this condition, no beat frequencies fall into the audible frequency band, thus improving sound performance.

[0113] Furthermore, this invention limits the switching frequency to an integer multiple of the system operating frequency and utilizes a feedback control loop to determine / adjust this integer multiple. Therefore, the DC power supply can operate at various switching frequencies, and all switching frequencies are synchronized with the system operating frequency.

[0114] In this invention, the synchronization of two frequencies refers to the first frequency. f 1 For the second frequency f 2 A rational multiple of, i.e. f 1 =(N / M) × f2 Where N and M are integers. In the special case where M=1, the first frequency... f 1 With the second frequency f 2 Synchronization refers to the first frequency f 1 For the second frequency f 2 A multiple of an integer.

[0115] Figure 1 This is a schematic diagram of a DC power supply 10 according to an embodiment of the present invention. The DC power supply 10 is an SMPS used to provide an output voltage Vout to a system (e.g., an air pulse generation system). The (air pulse generation) system can operate at a system frequency F. sys The operation can be at an ultrasonic frequency. The DC power supply 10 includes a controller 12, a power stage 14, a feedback network 16, and a differential block 18, forming a feedback control loop 11. The power stage 14 can be considered as the controlled object (plant) of the feedback control loop, its output current to a load (not shown). Figure 1 The load can be the system's drive circuit to output the output voltage Vout. In one embodiment, the power stage 14 can be a DC-DC converter / circuit (e.g., a buck-boost converter) controlled by a pulse width modulation (PWM) control signal.

[0116] The output voltage Vout is fed back to the differential block 18 via feedback network 16 as a feedback signal FB. Differential block 18 then compares the feedback signal FB with a reference voltage Vout. REF Compare and generate an error signal. e Controller 12 determines the error signal based on the error signal. e A control signal ct is generated to control the controlled object, namely power stage 14, so that the output voltage Vout reaches a specified target voltage V. TARGET .

[0117] For example, controller 12 can base its decisions on error signals. e A PWM control signal is generated to control the controlled object, namely power stage 14. Note that the PWM control signal has a switching frequency F. SW This refers to the frequency of the pulses in the PWM control signal. Simultaneously, the output voltage Vout will be proportional to the charge injected into the load. With other conditions remaining constant, the switching frequency F... SW The higher the value, the higher the expected output voltage Vout. In this regard, controller 12 can determine the switching frequency F. SW And generate a switching frequency F SWThe PWM control signal is used to control the output voltage Vout to reach the specified target voltage V. TARGET .

[0118] Furthermore, to mitigate the impact of ripple noise and other types of noise on the system, it is recommended in this invention to switch the frequency F. SW The system operating frequency F sys A multiple of an integer, i.e., F SW = N × F sys , where N is an integer.

[0119] In one embodiment, the controller 12 can determine the error signal based on the error signal. e Determine the integer N, thereby generating a switching frequency F. SW The PWM control signal is used to achieve the specified target voltage V. TARGET F SW = N × F sys .

[0120] Furthermore, power stage 14 may include multiple sub-power stages, wherein the sum of multiple sub-currents from these sub-power stages may be the output current from the entire power stage 14.

[0121] In one embodiment, the controller 12 can determine the error signal based on the error signal. e Determine one percentage point of the active / enabler power stage so that the output voltage Vout can reach the specified target voltage V. TARGET .

[0122] Specifically, Figure 2 This is a schematic diagram of a DC power supply 20 according to an embodiment of the present invention. The DC power supply 20 is also an SMPS, which includes a controller 22, a power stage 24, a feedback network 26, and a differential block 28.

[0123] The difference block 28 can be an operational amplifier.

[0124] Feedback network 26 can be a voltage divider or a resistor divider network, where FB = Vout. In this case, the target voltage V TARGET It can be regarded as V TARGET = (1 + R1 / R2) V REF .

[0125] Controller 22 is used to determine the error signal e A PWM control signal ct_PWM (a type of control signal ct) is generated. The controller 22 includes a switching clock generator 222, a sawtooth signal generator 224, and a pulse width modulator 226. The switching clock generator 222 is used to generate a PWM signal with a switching frequency F.SW All clock changes CLK, where F SW = N × F sys The sawtooth signal generator 224 is used to generate a signal with a switching frequency F based on the switching clock CLK. SW A sawtooth signal SAW. Pulse width modulator 226 is used to adjust the signal based on the sawtooth signal SAW and the error signal. e Generate the PWM control signal ct_PWM.

[0126] The waveforms of switching clock CLK, sawtooth signal SAW, and PWM control signal ct_PWM are displayed in... Figure 3 Specifically, in Figure 3 In the middle, CLK (N) SAW (N) and ct_PWM (N) Let F represent the signal corresponding to the integer N, where F SW = N × F sys or F SW,(N) = N×F sys And F SW,(N) This represents the switching frequency corresponding to the integer N.

[0127] In other words, the switching clock generator 222 and the sawtooth signal generator 224 respectively generate signals with a switching frequency F. SW,(N) Switching clock CLK (N) and sawtooth signal SAW (N) The pulse width modulator 226 generates a PWM control signal ct_PWM based on a level LV. (N) The level LV is related to the error signal. e Related or proportional (e.g.) Figure 1 or Figure 2 (As shown). In one embodiment, the error signal e The larger the value, the lower the LV level, and the wider the PWM control signal width; therefore, more charge is transferred to the load.

[0128] To adjust the charge transferred to the load, in addition to adjusting the pulse width modulator 226 according to the error signal... e Besides the LV level, another factor determining the voltage level is the switching frequency. Furthermore, in F... SW ,(N) = N × F sys Under the constraint, the factor used to adjust the charge transferred to the load is an integer N.

[0129] In this invention, the controller 22 includes an integer decision block 220 to determine the error signal. e The integer N is determined. Generally speaking, when the error signal... eis excessively large or greater than a first threshold (for example, denoted as PDV1), the integer determination block 220 may increase the integer N; on the other hand, when the error signal e is excessively small or less than a second threshold (for example, denoted as PDV2, and PDV2 < PDV1), the integer determination block 220 may decrease the integer N.

[0130] Furthermore, in an embodiment, when the error signal e is greater than the first threshold (PDV1), the integer determination block 220 may increase the integer N by at least a first increment n1; when the error signal e is greater than a third threshold (for example, denoted as PDV0), the integer determination block 220 may increase the integer N by a second increment n2, where PDV0 > PDV1 and n2 > n1.

[0131] Figure 4 is a schematic diagram of an integer determination block according to an embodiment of the present invention. Specifically, (a) and (b) therein are respectively a schematic diagram of an integer determination block 320 and an integer determination block 420 according to the embodiments of the present invention. The integer determination block 320 / 420 may be used to implement the above-mentioned integer determination block 220.

[0132] The integer determination block 320 / 420 may include an error signal classification block 3202 / 4202 and a determination block 3204 / 4204. The error signal classification block 3202 / 4202 includes two / three comparators, and outputs two / three comparison results (UP, DOWN) / (UP, DOWN, TOP). According to the two / three comparison results (UP, DOWN) / (UP, DOWN, TOP), the determination block 3204 / 4204 may determine whether to increase / decrease the integer N according to the comparison results.

[0133] The integer determination block of the present invention may be implemented by an analog circuit or a digital circuit, or both. In Figure 4 , the error signal classification block 3202 / 4202 shows an analog part (which includes a comparator or an operational amplifier (op-amp)), and the determination block 3204 / 4204 shows a logic / control part (which may be implemented by a digital synthesis circuit, but is not limited thereto).

[0134] It should be noted that the integer determination block 420 with segmented / stepwise adjustment has better tracking capability than the integer determination block 320, especially when the feedback signal FB lags far behind / is much lower than the reference voltage V REF . Therefore, the DC power supply equipped with the integer determination block with segmented / stepwise adjustment has a faster transient response to changes in Vout.

[0135] It should be noted that Figure 4 The segmented / gradual adjustment shown in (b) is performed in the increasing direction; however, it is not limited thereto. The adjustment can also be performed in the opposite decreasing direction, which also falls within the scope of the invention.

[0136] For the reduction direction, in addition to reducing the integer N, the percentage of the output current of the output stage can also be reduced. Note that the power stage (or buck-boost converter) can be implemented by multiple sub-segments or multiple sub-power stages. Controlling the percentage of the active / enabled sub-power stage will provide finer granularity to adjust the output current, thereby affecting the output voltage Vout.

[0137] The basic structure of the power stage is explained below. Figure 5 This is a schematic diagram of a power stage 34 according to an embodiment of the present invention. Power stage 34 is a four-switch buck-boost converter, which includes an inductor L. BB and switches S1-S4. Switches S1-S4 are controlled by or according to PWM control signals (e.g., ct_PWM and its derivative signals) generated from pulse width modulator 226. The details of the control mechanism between the PWM control signal and the buck-boost converter are known in the art and will not be elaborated here for the sake of brevity.

[0138] As mentioned earlier, the power stage can be further segmented / implemented into multiple sub-segments or multiple sub-power stages. Figure 6 and Figure 7 Schematic diagrams of power stages 44 and 54 according to embodiments of the present invention are shown respectively. Power stage 44 can be considered as an abstract representation of power stage 54. Power stage 44 includes sub-power stages 441-443 connected in parallel. Power stage 54 has the basic circuit structure of a four-switch buck-boost converter or power stage 44. Power stage 54 can be considered as a segmented four-switch buck-boost converter, which includes switches S 11 -S 13 S 21 -S 23 S 31 -S 33 S 41 -S 43 .

[0139] From an abstract perspective, sub-power stages 441-443 are connected in parallel to... Figure 6 The two representative endpoints Nin and Nout shown are located between them. In fact, Figure 7 Interconnection node (N) between switch and inductor L1 N L2 ) and inductor L BB exist Figure 6 The middle part is omitted.

[0140] The term “segmentation” refers to a configuration that divides a power stage into multiple parallel-connected sub-units, allowing the system to selectively enable a specific number of units to achieve finer control resolution.

[0141] Sub-power stage 441 can be considered as including the first set of switches S 11 S 21 S 31 and S 41 The sub-power stage 442 can be considered as including a second set of switches S 12 S 22 S 32 and S 42 The sub-power stage 443 can be considered as containing a third set of switches S. 13 S 23 S 33 and S 43 .

[0142] A set of switches (i.e., the first / second / third set of switches) and inductor L BB Form an individual buck-boost converter. Combine / aggregate all groups of switches, i.e., combine / aggregate the first, second, and third groups of switches to form an aggregated buck-boost converter. The aggregated current generated by the aggregated buck-boost converter is the sum of the currents of all individual buck-boost converters.

[0143] From another perspective, the total current of the converged buck-boost converter (i.e., power stage 44 / 54) can be controlled by appropriate control switch S. 11 -S 13 S 21 -S 23 S 31 -S 33 S 41 -S 43 To lower or adjust (become lower).

[0144] In other words, the percentage of active / enabled sub-power stages in a power stage can be controlled by the controller. For example, controller 22 can control power stage 44 such that only sub-power stage 441 is active / enabled (meaning that some switches within sub-power stage 441 are turned on and current flows through sub-power stage 441), while the remaining sub-power stages 442 and 443 are inactive / disabled (meaning that no switches within sub-power stages 442 and 443 are turned on and no current flows through sub-power stages 442 and 443). In this case, assuming that the switches within sub-power stages 441-443 have the same size, the percentage of active / enabled sub-power stages in the power stage can be considered as 1 / 3.

[0145] In the above example, the percentage of active / enabled sub-power stages in the power stage can be related to the number of active / enabled sub-power stages, but is not limited to this. Switches within different sub-power stages can have different switch sizes and different current drive capabilities, providing additional degrees of freedom to adjust the percentage.

[0146] Specifically, the switches within sub-power stages 441, 442, and 443 can have power switch sizes PSS1, PSS2, and PSS3, respectively. Power switch size refers to the width of the power metal-oxide-semiconductor field-effect transistor (MOSFET). A larger size / width allows for greater current conduction.

[0147] In one embodiment, the power switch dimensions PSS1, PSS2, and PSS3 can be the same, i.e., PSS1 = PSS2 = PSS3.

[0148] In one embodiment, the power switch sizes PSS1, PSS2, and PSS3 may have a binary relationship, for example, PSS1:PSS2:PSS3 = 1:2:4. The initiative of the control sub-power stages can be represented using or related to a binary percentage, and several different percentages can be achieved by having fewer sub-power stages or fewer control signals.

[0149] In one embodiment, the percentage of active / enabled sub-power levels can be the ratio of the current supplied by the active sub-power level to the total current capacity when all sub-power levels are enabled. In other words, the percentage of active sub-power levels can be represented by the ratio of a first current (related to the active sub-power level) to a second current (corresponding to the state where all sub-power levels are active).

[0150] In one embodiment, the controller 22 can determine the error signal based on the error signal. e The controller 22 determines a percentage PC of the active / enabling sub-power level. Specifically, the controller 22 may include a percentage determination block 228.

[0151] It should be noted that Figure 2 The controller 22 simultaneously displays both the integer decision block 220 and the percentage decision block 228. Preferably, the controller 22 includes both the integer decision block 220 and the percentage decision block 228, but is not limited thereto. In one embodiment, the controller or DC power supply of the present invention may include only one of the integer decision block and the percentage decision block, which also falls within the scope of the present invention.

[0152] Figure 8 This is a schematic diagram of a percentage-determining block according to an embodiment of the present invention. Specifically, Figure 8(a) and (b) are schematic diagrams of percentage determination block 328 and percentage determination block 428 according to embodiments of the present invention.

[0153] The percentage determination block 328 / 428 may include an error signal classification block 3282 / 4282 and a determination block 3284 / 4284. The error signal classification block 3282 / 4282 contains two / three comparators and outputs two / three comparison results (UP, DOWN) / (UP, DOWN, TOP). Based on the two / three comparison results (UP, DOWN) / (UP, DOWN, TOP), the determination block 3284 / 4284 can determine whether to increase / decrease the percentage PC of the active / enabler power stage.

[0154] The percentage determines the block 328, which can be used in error signals. e When the value is too large or greater than a first threshold (e.g., PDV1), the percentage PC is increased; on the other hand, the percentage-determining block 328 can be used in error signal... e Reduce the percentage PC when it is too small or less than a second threshold (e.g., PDV2, and PDV2 < PDV1).

[0155] Furthermore, the percentage-determining block 428 can be used in error signals. e When the value exceeds the first threshold (PDV1), the percentage PC is increased by at least a first increment pc1; and this can be achieved through the error signal. e When the value is greater than a third threshold (e.g., denoted as PDV0), the percentage PC is increased by a second increment pc2, where PDV0 > PDV1 and pc2 > pc1.

[0156] The percentage-determining blocks 328 / 428 can have a similar circuit structure to the integer-determining blocks 320 / 420, which will not be described in detail here for the sake of simplicity.

[0157] In one embodiment, the integer determination block and the percentage determination block may share hardware circuitry. For example, error signal classification blocks 3202 / 4202 may share hardware circuitry (e.g., a comparator) with error signal classification blocks 3282 / 4282.

[0158] exist Figure 4 and Figure 8 In this context, "TOP", "UP", and "DOWN" indicate the comparison results based on the integer N and percentage PC determined by them.

[0159] Because the switching frequency of the DC power supply is limited to be synchronized with the operating frequency of the (ultrasonic) system, or more specifically, F SW = N × F sys The beat frequency between the DC power supply and the applied system will bef = 0 or outside the audible frequency band, will not fall into the audible frequency band.

[0160] In addition, to prevent overshoot (i.e., the output voltage Vout exceeds the target voltage V), TARGET (Too many), a clamping circuit may be included in the DC power supply.

[0161] Figure 9 , Figure 10 and Figure 11 These are schematic diagrams of clamping circuits 35, 45, and 55 according to embodiments of the present invention.

[0162] The clamping circuit 35 includes a Zener diode, whose cathode is coupled to one terminal of the output voltage Vout and whose anode is coupled to one terminal of a voltage V1, where V1 can represent a constant voltage or ground voltage. When the voltage Vout is significantly higher than the voltage V1, the Zener diode enters its breakdown region and conducts a breakdown current, thereby reducing the output voltage Vout.

[0163] Clamping circuits 45 and 55 include a transistor whose control terminal is coupled to the output terminal of an amplifier. Figure 10 and Figure 11 In the illustrated embodiment, the transistor is a P-type transistor (but not limited to this), which is turned on when the voltage at the control terminal is sufficiently low. Specifically, the clamping circuit 45 includes a P-channel MOSFET (PMOS) PM, and the clamping circuit 55 includes a PNP bipolar junction transistor (BJT) PB, but is not limited to this.

[0164] An amplifier 450 / 550 is coupled to a P-type transistor PM / PB. Figure 10 and Figure 11 In the illustrated embodiment, the positive terminal of amplifier 450 / 550 receives a first signal, and the negative terminal receives a second signal, wherein the first signal includes a reference voltage V. REF The second signal is proportional to the output voltage Vout. Amplifiers 450 / 550 generate a clamping signal CLP to P-type transistors PM / PB. When the output voltage Vout is too high / large or higher / greater than a threshold value, amplifiers 450 / 550 generate a low-voltage clamping signal CLP, turning on P-type transistors PM / PB, thereby reducing the output voltage Vout.

[0165] In one embodiment, the first signal received by amplifier 450 may be a reference voltage V. REF Or a voltage V REF ', where V REF ' = V REF + VOS V OS This represents the offset voltage of amplifier 450, used to compensate for actual mismatches within the amplifier.

[0166] In one embodiment, Figure 11 The resistor R1' shown can be expressed as R1' = R1 + R1a, where R1a represents an additional resistor to compensate for actual imperfections, which is optional.

[0167] It should be noted that unavoidable mismatches exist between different (two) amplifiers. This mismatch may cause transistors (such as PM or PB) in the clamping circuit to turn on at the wrong time. Specifically, there may be an unavoidable mismatch between amplifier 28 in the feedback control loop and amplifiers 450 / 550 in the clamping circuits 45 / 55.

[0168] One remedy for this mismatch is to share a differential input stage between the two amplifiers. Note that an operational amplifier includes a differential input stage, an intermediate stage, and an amplifier output stage. An amplifier circuit may include a differential input stage, an intermediate stage, and multiple (e.g., two) amplifier output stages, one of which outputs the error signal. e Meanwhile, the output stage of another amplifier outputs a clamping signal CLP.

[0169] For example, Figure 12 This is a schematic diagram of an amplifier circuit 37 according to an embodiment of the present invention. The amplifier circuit 37 includes a differential input stage 370 and two amplifier output stages 372 and 374 (intermediate stages are omitted for simplicity). The two amplifier output stages 372 and 374 are coupled to the differential input stage 370, wherein amplifier output stage 372 outputs an error signal. e The amplifier output stage 374 outputs the clamping signal CLP.

[0170] Specifically, Figure 13 This is a schematic diagram of an amplifier circuit 47 according to an embodiment of the present invention. The amplifier circuit 47 is shown in transistor hierarchy and can be used to implement amplifier circuit 37. Similarly, amplifier circuit 47 includes a differential input stage 470 and two amplifier output stages 472 and 474 (intermediate stages are also shown and shared). The two amplifier output stages 472 and 474 are coupled to the differential input stage 470, wherein amplifier output stage 472 outputs an error signal. e The amplifier output stage 474 outputs the clamping signal CLP.

[0171] It should be noted that the offset voltage can be mitigated by adjusting the ratio of the transistor's transconductance. For example, the transistor's conductance can be adjusted so that (gmp2 / gmn2) > (gmp1 / gmn1) to reduce the offset voltage, where gmp1, gmn1, gmp2, and gmn2 represent the transconductances of transistors P1, N1, P2, and N2, respectively.

[0172] In the embodiment shown for amplifier circuit 47, a compensation circuit 471 (including a capacitor and a resistor, functioning as a low-pass filter) is included, coupled to the output terminal of the output voltage Vout. The compensation circuit 471 can filter out / average error signals. e The high-frequency changes in the system stabilize its performance.

[0173] Figure 14 A schematic diagram of an air pulse generation system 1 according to an embodiment of the present invention is shown. The air pulse generation system 1 includes an air pulse generating device 13 and a driving circuit 15. The pulse generating device 13 includes a membrane structure 130. The membrane structure 130 includes a first lobe 101 and a second lobe 103, forming a lobe pair 132.

[0174] The first lobe 101 is driven by a first valve drive signal SV1, and the second lobe 103 is driven by a second valve drive signal SV2, so that the lobe performs differential mode movement on 132 to form a virtual valve 112.

[0175] At the same time, both lobes 101 and 103 are driven by a pressure drive signal SM, causing the lobes to perform common-mode motion on 132 to form an amplitude-modulated air pressure change.

[0176] The drive circuit 15 is used to generate the pressure drive signal SM and the valve drive signals SV1 and SV2. The DC power supply 10 (generally referring to all types of DC power supplies in this invention) is used to provide the voltage Vout to the drive circuit 15.

[0177] The waveforms of drive signals SV1, SV2, and SM are displayed on Figure 15 Generally speaking, valve drive signals SV1 and SV2 correspond to a valve drive frequency Fv, while pressure drive signal SM corresponds to a pressure drive frequency F. M . Figure 15 (a) shows F M = 2. Fv's scheme (see U.S. Patent No. 11,943,585). Figure 15 (b) shows F M = Fv scheme (see U.S. Patent Application No. 19 / 424,094). In any case, the system operating frequency F of the air pulse generating system 1 is... sys The pressure drive frequency F can be selected.M Or valve drive frequency Fv.

[0178] Assume F sys = F M The switching frequency F of the switching mode power supply (SMPS) or DC power supply (e.g., 10) is... SW Will be F SW = N. F M Therefore, the switching ripples and other noise generated by SMPS are related to the system operating frequency F. sys Or pressure drive frequency F M Synchronization. The impact of switching noise extends across multiple system operating cycles (regardless of the valve actuation cycle T). V Or pressure-driven cycle T M (During this period) Maintain consistency in time.

[0179] In this invention, the multiplication symbol “×” and “.” can be used interchangeably.

[0180] In other words, make the switching frequency F SW With system operating frequency F sys Synchronization does not essentially eliminate switching noise in SMPS, but rather ensures that switching ripples remain consistent across system operating cycles. This is achieved by using F... SW Restricted to F sys From the perspective of system synchronization operation or sampling, the impact of switching noise is significantly and effectively reduced. Therefore, system performance is improved.

[0181] When the air pulse generation system 1 is applied to sound generation, the switching frequency F is... SW With the (ultrasound) system operating frequency F sys Synchronization does not produce beat frequencies within the audible frequency band, thus improving sound quality.

[0182] In summary, by synchronizing the switching frequency with the system operating frequency, the disclosed DC power supply effectively mitigates the effects of switching noise. This synchronization method ensures a stable power supply, thereby improving the overall performance of the applied system.

[0183] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A DC power supply for providing an output voltage to a system, the DC power supply comprising: A power stage is used to output this output voltage; A difference block is used to compare a feedback signal corresponding to the output voltage with a reference voltage to generate an error signal; and A controller is used to generate a control signal based on the error signal to control the power stage to achieve the output voltage. The controller includes: An integer determines the block, which is used to determine an integer based on the error signal; The control signal has a switching frequency; The system operates at a system operating frequency; The switching frequency is an integer multiple of the system's operating frequency.

2. The DC power supply as described in claim 1, The integer determines the block to increment the integer when the error signal is greater than a first threshold value; The integer determines the block to decrease the integer when the error signal is less than a second threshold value.

3. The DC power supply as described in claim 2, The first critical value is greater than the second critical value.

4. The DC power supply as described in claim 2, The integer determines that the block increases by at least a first increment when the error signal is greater than the first threshold value; The integer determines the block by increasing the integer by a second increment when the error signal is greater than a third threshold value; The second increment is greater than the first increment; The third critical value is greater than the first critical value.

5. The DC power supply as described in claim 1, This power stage contains multiple sub-power stages; The controller includes a percentage determination block used to determine the percentage of an active sub-power stage based on the error signal.

6. The DC power supply as described in claim 5, This percentage determines the percentage by which the active sub-power stage is increased when the error signal is greater than a first threshold. This percentage determines the percentage by which the block reduces the active sub-power stage when the error signal is less than a second threshold value; The first critical value is greater than the second critical value.

7. The DC power supply as described in claim 6, The percentage determines the percentage by which the active sub-power level is increased by at least a first increment when the error signal is greater than the first threshold. The percentage determines the percentage by which the active sub-power stage is increased by a second increment when the error signal is greater than a third threshold. The second increment is greater than the first increment; The third critical value is greater than the first critical value.

8. The DC power supply as claimed in claim 1, comprising a clamping circuit coupled to an output terminal of the DC power supply.

9. The DC power supply of claim 8, wherein the clamping circuit includes a Zener diode.

10. The DC power supply as described in claim 8, The clamping circuit includes a first switch; The first switch is turned on when the output voltage is greater than a critical value.

11. The DC power supply as claimed in claim 10, One of the control terminals of the first switch is coupled to an amplifier.

12. The DC power supply as described in claim 11, The amplifier receives a first signal and a second signal; The first signal includes the reference voltage; The second signal is proportional to the output voltage.

13. The DC power supply as described in claim 12, The first switch is a P-type switch; The amplifier includes a positive input terminal, a negative input terminal, and an output terminal; The amplifier receives the first signal at the positive input terminal and the second signal at the negative input terminal; The output terminal of the amplifier is coupled to a control terminal of the P-type switch; The amplifier generates a clamping signal to the control terminal of the P-type switch.

14. The DC power supply as described in claim 12, The first signal includes the reference voltage and an offset voltage.

15. The DC power supply as claimed in claim 1, further comprising: An amplifier circuit includes a differential input stage, a first amplifier output stage, and a second amplifier output stage; The first amplifier output stage outputs the error signal; The switching frequency is determined based on the error signal; The output stage of the second amplifier outputs a clamping signal for a switch in a clamping circuit.

16. The DC power supply as described in claim 15, The difference block includes a first amplifier used to compare a feedback signal with the reference voltage and generate the error signal; The first amplifier includes the differential input stage and the first amplifier output stage; The DC power supply includes the clamping circuit, which includes a second amplifier, and the second amplifier includes the differential input stage and the second amplifier output stage.

17. The DC power supply as claimed in claim 1, The difference block contains an amplifier.

18. The DC power supply of claim 1, wherein the controller comprises: A switching clock generator is used to generate all switching clocks with the switching frequency, wherein the switching frequency is an integer multiple of the system operating frequency; A sawtooth signal generator is used to generate a sawtooth signal having the switching frequency according to the switching clock; and A pulse width modulator is used to generate a pulse width modulation control signal based on the sawtooth signal and the error signal; The pulse width modulation control signal has the switching frequency; The power stage is controlled by the pulse width modulation control signal to output the output voltage.

19. The DC power supply of claim 1, wherein the controller includes an error signal classification block, the error signal classification block comprising: A first comparator is used to compare the error signal with a first threshold value and generate a first comparison result; and A second comparator is used to compare the error signal with a second threshold value and generate a second comparison result; The controller determines the integer or an active sub-power level percentage based on the first comparison result and the second comparison result.

20. The DC power supply of claim 19, wherein the error signal classification block comprises: A third comparator is used to compare the error signal with a third threshold value and generate a third comparison result; The controller determines the integer or the percentage of the active sub-power level based on the first comparison result, the second comparison result, and the third comparison result.

21. The DC power supply as claimed in claim 1, The system is an air pulse generation system, which includes a drive circuit and an air pulse generation device, and the pulse generation device includes a membrane structure. The DC power supply provides the output voltage for the drive circuit. The driving circuit drives the membrane structure to operate at the system's operating frequency.

22. The DC power supply as claimed in claim 21, The membrane structure includes a first lobe and a second lobe; The driving circuit generates a first valve driving signal to drive the first valve flap, and generates a second valve driving signal to drive the second valve flap. The first and second lobes perform differential mode motion to form a virtual valve; The first valve drive signal and the second valve drive signal are synchronized with the operating frequency of the system. The switching frequency is an integer multiple of the system's operating frequency.

23. A DC power supply for providing an output voltage to a system, the DC power supply comprising: A power stage is used to output the output voltage, and it contains multiple sub-power stages; A difference block is used to compare a feedback signal corresponding to the output voltage with a reference voltage to generate an error signal; and A controller is used to generate a control signal based on the error signal to control the power stage to achieve the output voltage. The controller includes: A percentage-determining block is used to determine the percentage of an active power level based on the error signal.

24. The DC power supply as described in claim 23, These multiple sub-power stages correspond to multiple switch sizes; The dimensions of these multiple switches have a binary relationship.

25. A method for use with a switching mode power supply, wherein the switching mode power supply is used to provide an output voltage to a system, the method comprising: An error signal is generated based on the output voltage; and Adjust a switching frequency of the switching mode power supply according to the error signal; The switching frequency is synchronized with the system's operating frequency.

26. The method of claim 25, comprising: An integer is determined based on the error signal; The switching frequency is an integer multiple of the system's operating frequency; The system operates at its operating frequency.

27. The method of claim 25, wherein the switching mode power supply includes a power stage comprising a plurality of sub-power stages, and the method comprises: The percentage of an active power level is determined based on this error signal.

28. The method of claim 25, The system is an air pulse generation system, which includes a drive circuit and an air pulse generation device, and the pulse generation device includes a membrane structure. The driving circuit drives the membrane structure to operate at the system's operating frequency.

29. The method of claim 28, The membrane structure includes a pair of lobes, which are driven by a valve drive signal to perform differential mode movement and by a pressure drive signal to perform common mode movement. The valve drive signal has a valve drive frequency, and the pressure drive signal has a pressure drive frequency. The switching frequency is an integer multiple of the valve drive frequency or an integer multiple of the pressure drive frequency.

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