A multi-parallel silicon carbide drive improvement circuit and control method

Abstract

The application relates to the technical field of power electronic conversion and control, and discloses a multi-channel parallel silicon carbide driving improvement circuit and a control method, which comprises a plurality of parallelly connected silicon carbide MOS tubes; the gates of the plurality of parallelly connected silicon carbide MOS tubes are electrically connected with gate resistors; the Kelvin sources of the plurality of parallelly connected silicon carbide MOS tubes are electrically connected with Kelvin source resistors; one end of the gate resistor is electrically connected with the gates of the plurality of parallelly connected silicon carbide MOS tubes, and the other end of the gate resistor is connected to a driving signal input end through a common driving resistor; one end of the Kelvin source resistor is electrically connected with the Kelvin source resistors of the plurality of parallelly connected silicon carbide MOS tubes, and the other end of the Kelvin source resistor is connected to a driving voltage negative electrode. The common driving resistor is used for realizing impedance matching of the driving signal, and the switching synchronism of the multi-channel parallel silicon carbide device is improved.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion and control technology, and in particular to a multi-channel parallel silicon carbide drive improvement circuit and control method. Background Technology

[0002] Silicon carbide MOSFETs, as third-generation wide-bandgap semiconductor devices, offer advantages such as high switching speed, low on-resistance, and high temperature resistance. However, with increasing power demands, the current carrying capacity of a single silicon carbide device often falls short of application requirements. Therefore, a multi-parallel connection is necessary to improve the system's current handling capability. Multi-parallel silicon carbide drive circuits connect multiple silicon carbide MOSFET devices in parallel, allowing each device to share the load current, thereby achieving high current output. However, due to limitations in silicon carbide device manufacturing processes, even devices from the same batch can vary in parameters such as threshold voltage, gate capacitance, and switching characteristics.

[0003] In existing technologies, multi-parallel silicon carbide devices are typically driven by directly connecting the gate drive ports of each device in parallel. However, this connection method can lead to mutual interference between the parallel devices. When a device experiences a switching time deviation due to parameter differences or PCB layout differences, its gate-source voltage change will affect the gate-source voltage of other devices through the common drive path, causing inconsistent switching times among the parallel devices. This, in turn, leads to uneven current distribution among the devices, local device overload, and decreased system efficiency, severely affecting the reliability and stability of the parallel system. Summary of the Invention

[0004] In view of this, the present invention proposes a multi-channel parallel silicon carbide drive improvement circuit and control method, which solves the problem of mutual interference between parallel devices caused by the existing technology of directly connecting the gate drive ports of each device in parallel. When a device has a switching time deviation due to parameter differences or PCB layout differences, the change of its gate source voltage will affect the gate source voltage of other devices through the common drive path, resulting in inconsistent switching times of the parallel devices, which in turn causes uneven current distribution among devices, local device overload, and reduced system efficiency.

[0005] The technical solution of the present invention is implemented as follows: On the one hand, the present invention provides a multi-channel parallel silicon carbide drive improvement circuit, including multiple silicon carbide MOS transistors connected in parallel; The gates of the plurality of parallel-connected silicon carbide MOS transistors are electrically connected to the gate resistors. The Kelvin source of the plurality of parallel-connected silicon carbide MOS transistors is electrically connected to the Kelvin source resistor. One end of the gate resistor is electrically connected to the gate of the plurality of parallel-connected silicon carbide MOS transistors, and the other end of the gate resistor is connected to the drive signal input terminal through a common drive resistor. One end of the Kelvin source resistor is connected in parallel with the Kelvin source resistors of the plurality of silicon carbide MOS transistors, and the other end of the Kelvin source resistor is connected to the negative terminal of the drive voltage.

[0006] Based on the above technical solutions, preferably, the gate resistor electrically isolates the gates of each silicon carbide MOS transistor, reducing the impact of PCB wiring differences, and the Kelvin source resistor electrically isolates the Kelvin sources of each silicon carbide MOS transistor, reducing circulating current and suppressing source current.

[0007] Based on the above technical solutions, preferably, the gate resistors of the multiple parallel-connected silicon carbide MOS transistors are combined to form a total driving resistor, wherein the single-transistor driving resistor accounts for 50% of the total driving resistor, and the single-transistor driving resistor includes a gate resistor and an internal driving resistor.

[0008] Based on the above technical solutions, preferably, the multi-parallel silicon carbide drive improvement circuit is applied to the power converter of the energy storage system to form the upper or lower bridge arm of the half-bridge circuit or the full-bridge circuit, and the multiple parallel-connected silicon carbide MOS transistors include three silicon carbide MOS transistors connected in parallel.

[0009] On the other hand, the present invention also provides a control method for a multi-channel parallel silicon carbide drive improvement circuit, comprising the following steps: The lower limit of the gate drive resistor is determined based on the damping condition of the drive circuit, and the upper limit of the gate drive resistor is determined based on the anti-misoperation turn-on condition. The single-transistor drive resistor is set to account for 50% of the total drive resistor; The values ​​of each resistance are calculated according to the total driving resistance formula and the set proportion. The total driving resistance consists of the common driving resistance, the gate resistance, the internal driving resistance and the Kelvin source resistance. A PWM control signal is input to the drive signal input terminal and transmitted to the gate of each silicon carbide MOSFET through the common drive resistor and each gate resistor.

[0010] Based on the above technical solutions, preferably, the setting of the single-transistor drive resistor to account for 50% of the total drive resistor includes: The single-transistor drive resistor is set to the sum of the gate resistor and the internal drive resistor, and the proportion of the single-transistor drive resistor in the total drive resistor is set to 50% to suppress the circulating current between parallel silicon carbide MOS transistors.

[0011] Based on the above technical solutions, preferably, the step of determining the lower limit value of the gate drive resistor according to the damping condition of the drive circuit includes: setting the gate resistor to provide damping to dampen the oscillation of the drive current at the moment of turn-on of the silicon carbide MOS transistor; The step of determining the upper limit of the gate drive resistor based on the anti-misoperation turn-on condition includes: preventing excessive voltage change rate when the silicon carbide MOSFET is turned off, so as to avoid the silicon carbide MOSFET being mistakenly turned on again.

[0012] Based on the above technical solutions, preferably, the PWM control signal is two mutually opposite PWM signals, which respectively control the multi-parallel silicon carbide drive improvement circuits of the upper and lower bridge arms, and ensure that the upper and lower bridge arms will not be turned on at the same time through the mutually opposite control method.

[0013] Based on the above technical solutions, preferably, the step of determining the lower limit value of the gate drive resistance according to the driving circuit damping condition includes: The lower limit of the gate drive resistor is determined based on the parasitic capacitance of the silicon carbide MOSFET and the parasitic inductance of the drive circuit. The step of determining the upper limit of the gate drive resistor based on the anti-misoperation conditions includes: determining the upper limit of the gate drive resistor based on the gate-source threshold voltage and switching speed requirements of the silicon carbide MOSFET.

[0014] Based on the above technical solutions, preferably, the step of calculating the resistance values ​​according to the total driving resistance formula and the set proportion includes: Using the lower and upper limits of the gate drive resistor as constraints, the specific values ​​of the common drive resistor, gate resistor, and Kelvin source resistor are calculated within the range of the constraints, based on the setting that the single-transistor drive resistor accounts for 50%.

[0015] The multi-channel parallel silicon carbide drive improvement circuit and control method of the present invention have the following advantages over the prior art: (1) By connecting gate resistors in series with the gates of multiple parallel silicon carbide MOS transistors and Kelvin source resistors in series with the Kelvin source, and connecting each gate resistor to the drive signal input terminal through a common drive resistor, the gate resistors are used to achieve effective isolation between the parallel devices to prevent mutual interference during the switching process. The Kelvin source resistors are used to compensate for the inconsistency of drive circuit impedance caused by PCB wiring differences. The common drive resistors are used to achieve impedance matching of the drive signal, thereby improving the switching synchronization of multiple parallel silicon carbide devices. (2) The gates of each parallel silicon carbide MOS transistor are electrically isolated by the gate resistor and the Kelvin source resistor is electrically isolated by the Kelvin source resistor. The gate isolation reduces the impact of inconsistent drive path impedance caused by PCB wiring differences. The Kelvin source isolation reduces the circulating current between parallel devices and suppresses source current fluctuations, improving the synchronicity of switching action and the balance of current distribution of each parallel device. At the same time, it reduces circulating current loss and gate-source voltage oscillation risk, and enhances the stability and reliability of the multi-parallel system. (3) By determining the lower limit of the gate drive resistor based on the damping condition of the drive circuit and the upper limit of the gate drive resistor based on the anti-misoperation turn-on condition, the range of resistor values ​​is established. By using the principle that the single-tube drive resistor accounts for 50% of the total drive resistor, the common drive resistor, gate resistor, internal drive resistor and Kelvin source resistor are systematically calculated and configured in combination with the total drive resistor formula. The PWM control signal is input through the drive signal input terminal and transmitted to the gate of each silicon carbide MOS tube through the common drive resistor and each gate resistor, so as to achieve balanced matching of drive impedance and optimized balance of drive capability of each parallel device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a topology diagram of a multi-channel parallel silicon carbide drive improvement circuit according to the present invention; Figure 2 This is the actual topology applied to the PCS power supply according to an embodiment of the present invention; Figure 3 This is a comparison diagram of the effects of the embodiments of the present invention and the conventional circuit; Figure 4 This is a flowchart of a control method for a multi-channel parallel silicon carbide drive improvement circuit according to the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 The present invention provides a multi-parallel silicon carbide drive improvement circuit, comprising multiple silicon carbide MOS transistors connected in parallel; The gates of the plurality of parallel-connected silicon carbide MOS transistors are electrically connected to the gate resistors. The Kelvin source of the plurality of parallel-connected silicon carbide MOS transistors is electrically connected to the Kelvin source resistor. One end of the gate resistor is electrically connected to the gate of the plurality of parallel-connected silicon carbide MOS transistors, and the other end of the gate resistor is connected to the drive signal input terminal through a common drive resistor. One end of the Kelvin source resistor is connected in parallel with the Kelvin source resistors of the plurality of silicon carbide MOS transistors, and the other end of the Kelvin source resistor is connected to the negative terminal of the drive voltage.

[0020] Specifically, this embodiment employs a circuit structure where gate resistors are connected in series with the gates of multiple parallel-connected silicon carbide MOSFETs, and Kelvin source resistors are connected in series with their respective Kelvin sources. These gate resistors are then connected to the drive signal input via a common drive resistor. This structure effectively isolates the parallel devices using the gate resistors to prevent mutual interference during switching. The Kelvin source resistors compensate for impedance inconsistencies in the drive circuit caused by PCB layout differences, and the common drive resistor achieves impedance matching for the drive signal. This embodiment solves the problems of inconsistent switching times, uneven dynamic current distribution, and gate-source voltage oscillations caused by device parameter dispersion and layout differences in existing multi-parallel silicon carbide drive circuits, thus improving the switching synchronization of multi-parallel silicon carbide devices.

[0021] The gate resistor electrically isolates the gates of each silicon carbide MOSFET, reducing the impact of PCB wiring differences. The Kelvin source resistor electrically isolates the Kelvin sources of each silicon carbide MOSFET, reducing circulating current and suppressing source current.

[0022] Specifically, this embodiment electrically isolates the gates of each parallel silicon carbide MOSFET using gate resistors and electrically isolates the Kelvin sources of each silicon carbide MOSFET using Kelvin source resistors. Gate isolation reduces the impact of inconsistent drive path impedance caused by PCB wiring differences, while Kelvin source isolation reduces circulating current between parallel devices and suppresses source current fluctuations. This embodiment solves the problem of mutual interference between parallel devices caused by wiring differences and device parameter dispersion, improves the synchronization of switching actions and the balance of current distribution among parallel devices, reduces circulating current losses and the risk of gate-source voltage oscillation, and enhances the stability and reliability of the multi-parallel system.

[0023] The gate resistors of the multiple parallel-connected silicon carbide MOS transistors are combined to form the total driving resistance, wherein the single-transistor driving resistance accounts for 50% of the total driving resistance, and the single-transistor driving resistance includes the gate resistor and the internal driving resistance.

[0024] Specifically, this embodiment sets the proportion of the single-transistor drive resistor in the total drive resistor to 50%. The single-transistor drive resistor includes both a gate resistor and an internal drive resistor. This ensures a balanced configuration between the single-transistor drive resistor and the common drive resistor. By utilizing this ratio, it guarantees sufficient drive capability from the common drive resistor while ensuring effective electrical isolation between the single-transistor drive resistors. This embodiment solves the problems of balancing drive strength and isolation effect, and the lack of quantitative basis for drive resistor configuration. It achieves impedance optimization configuration of a multi-parallel silicon carbide MOSFET drive system, improving the synchronization of switching actions of each parallel device and the stability of the drive circuit.

[0025] The multi-parallel silicon carbide drive improvement circuit is applied in the power converter of the energy storage system to form the upper or lower bridge arm of the half-bridge circuit or the full-bridge circuit. The multiple parallel-connected silicon carbide MOSFETs include three silicon carbide MOSFETs connected in parallel.

[0026] Specifically, this embodiment applies a multi-parallel silicon carbide drive improvement circuit to the power converter of an energy storage system. Three silicon carbide MOSFETs are connected in parallel to form the upper or lower arm of a half-bridge or full-bridge circuit. This three-MOSFET parallel configuration triples the current handling capacity of a single transistor. Combined with optimized drive design of the improvement circuit, synchronous switching and current sharing control of the parallel devices are achieved. This embodiment solves the problems of insufficient single-transistor current handling capacity and difficulty in guaranteeing bridge arm switching characteristics in high-power applications of energy storage system power converters. It achieves high current handling capacity and high reliability operation of the energy storage system power converter, improving the power density, conversion efficiency, and overall performance of the energy storage system.

[0027] In one specific embodiment, the external gate drive resistor plays a crucial role in limiting noise and ringing in the gate drive path. Without a properly sized gate resistor, parasitic inductance and capacitance, high dv / dt and di / dt, and reverse recovery of the body diode can lead to undesirable behavior.

[0028] The design of the drive resistor mainly follows two principles: The drive resistor must provide sufficient damping in the drive circuit to dampen the oscillation of the drive current at the moment the MOSFET is turned on.

[0029] ; To prevent the MOSFET from generating a large dV / dt when it is turned off, which could cause the MOSFET to turn on again unintentionally.

[0030] ; Experimental calculations show that in a silicon carbide parallel circuit, the driving resistance of a single transistor (i.e., In total drive resistance When the proportion of the transistor is 50%, circulating current can be suppressed better. The formula for the driving resistor of a single transistor is as follows:

[0031] ; in, Total driving resistance; For common driving resistor; It is a single silicon carbide driving resistor; For internal driving resistors; This is the K-pole resistor.

[0032] Among the PCS products used in this invention, the following are selected: It is 6Ω. It is 12Ω. It is 0.5Ω. The actual effect is as follows. Figure 2 As shown.

[0033] The product driver used in this invention is as follows: Figure 3 As shown, the control is achieved by two PWM waves. The upper and lower transistors use the same set of PWM waves to control each other in opposite directions, ensuring that the upper and lower transistors will not be turned on at the same time, making the control more reliable and stable.

[0034] Product topology as follows Figure 3 As shown, it consists of a DC / AC circuit. Its working principle is as follows: when the battery pack discharges, the energy stored in it is converted from DC to AC by a converter, feeding the stored DC power back to the grid; when the battery is charging, the AC power from the grid is rectified by the converter, converting AC to DC and storing it in the battery. Compared to traditional three-level inverters, the silicon carbide two-level inverter in this application example has a simpler power circuit, higher operating efficiency, and a smaller size.

[0035] Please see Figure 4 The present invention also provides a control method for a multi-channel parallel silicon carbide drive improvement circuit, applied to a multi-channel parallel silicon carbide drive improvement circuit, comprising the following steps: The lower limit of the gate drive resistor is determined based on the damping condition of the drive circuit, and the upper limit of the gate drive resistor is determined based on the anti-misoperation turn-on condition. The single-transistor drive resistor is set to account for 50% of the total drive resistor; The values ​​of each resistance are calculated according to the total driving resistance formula and the set proportion. The total driving resistance consists of the common driving resistance, the gate resistance, the internal driving resistance and the Kelvin source resistance. A PWM control signal is input to the drive signal input terminal and transmitted to the gate of each silicon carbide MOSFET through the common drive resistor and each gate resistor.

[0036] Specifically, this embodiment establishes a resistance range by determining the lower limit of the gate drive resistor based on the drive circuit damping condition and the upper limit of the gate drive resistor based on the anti-false turn-on condition. Utilizing the principle of setting the single-transistor drive resistor to account for 50% of the total drive resistance, and combining this with the total drive resistance formula, the common drive resistor, gate resistor, internal drive resistor, and Kelvin source resistor are systematically calculated and configured. The PWM control signal is input through the drive signal input terminal and transmitted to the gate of each silicon carbide MOSFET via the common drive resistor and each gate resistor. This embodiment solves the problems of difficult-to-configure drive resistor parameters and the difficulty in balancing insufficient drive circuit damping with the risk of false turn-on in multi-parallel silicon carbide drive systems, achieving balanced matching of drive impedances and optimized balance of drive capabilities for each parallel device.

[0037] The setting that the single-transistor drive resistor accounts for 50% of the total drive resistor includes: The single-transistor drive resistor is set to the sum of the gate resistor and the internal drive resistor, and the proportion of the single-transistor drive resistor in the total drive resistor is set to 50% to suppress the circulating current between parallel silicon carbide MOS transistors.

[0038] Specifically, this embodiment defines the single-transistor drive resistor as the sum of the gate resistance and the internal drive resistance, and sets the proportion of this single-transistor drive resistor in the total drive resistance to 50%. This ratio ensures a 1:1 balanced configuration between the single-transistor drive resistor and the common drive resistance, providing sufficient electrical isolation impedance between devices while guaranteeing adequate drive capability. This embodiment solves the problem of inter-device circulating current caused by differences in device parameters and switching timing deviations in parallel silicon carbide MOSFETs, effectively suppressing circulating current in parallel devices, reducing circulating current losses and uneven thermal stress, and improving the current distribution balance and long-term operational reliability of multi-parallel systems.

[0039] The step of determining the lower limit of the gate drive resistor based on the damping condition of the drive circuit includes: setting the gate resistor to provide sufficient damping to dampen the oscillation of the drive current at the moment of turn-on of the silicon carbide MOS transistor; The step of determining the upper limit of the gate drive resistor based on the anti-misoperation turn-on condition includes: preventing excessive voltage change rate when the silicon carbide MOSFET is turned off, so as to avoid the silicon carbide MOSFET being mistakenly turned on again.

[0040] Specifically, this embodiment establishes a reasonable range for the gate resistance by determining the lower limit of the gate drive resistance based on the driving circuit damping condition and the upper limit of the gate drive resistance based on the anti-false turn-on condition. The lower limit ensures sufficient damping from the gate resistance to suppress the oscillation of the drive current during the turn-on of the silicon carbide MOSFET, while the upper limit limits the risk of false turn-on caused by an excessively large gate resistance leading to an excessive voltage change rate during turn-off. This embodiment solves the problems of lacking quantitative design basis for gate resistance parameter selection and the difficulty in simultaneously meeting the requirements for insufficient driving circuit damping and anti-false turn-on. It achieves optimized configuration of the gate drive resistance, effectively suppressing drive current oscillations during turn-on and avoiding false turn-on during turn-off.

[0041] The PWM control signal consists of two mutually opposite PWM signals, which control the multi-parallel silicon carbide drive improvement circuits of the upper and lower bridge arms respectively. The mutually opposite control method ensures that the upper and lower bridge arms will not be turned on at the same time, thereby achieving reliable control of the half-bridge circuit or the full-bridge circuit.

[0042] Specifically, this embodiment employs two mutually opposing PWM signals to control the multi-parallel silicon carbide drive improvement circuit of the upper and lower bridge arms respectively. By utilizing mutually opposing control logic at the signal source, it ensures that the switching states of the upper and lower bridge arms are always complementary, fundamentally avoiding shoot-through short circuits caused by simultaneous activation of both arms. This embodiment solves the risk of bridge arm shoot-through caused by control timing errors or interference during switching of half-bridge or full-bridge circuits, achieving safe and reliable control of half-bridge or full-bridge circuits. It effectively prevents device damage and system failure caused by shoot-through short circuit faults, improving the operational safety and system reliability of the power converter.

[0043] The step of determining the lower limit value of the gate drive resistance based on the drive circuit damping condition includes: The lower limit of the gate drive resistor is determined based on the parasitic capacitance of the silicon carbide MOSFET and the parasitic inductance of the drive circuit. The step of determining the upper limit of the gate drive resistor based on the anti-misoperation conditions includes: determining the upper limit of the gate drive resistor based on the gate-source threshold voltage and switching speed requirements of the silicon carbide MOSFET.

[0044] Specifically, this embodiment determines the lower limit of the gate drive resistor based on the parasitic capacitance of the silicon carbide MOSFET and the parasitic inductance of the drive circuit, and determines the upper limit of the gate drive resistor based on the gate-source threshold voltage and switching speed requirements of the silicon carbide MOSFET. A lower limit constraint is established by utilizing the matching relationship between the device parasitic parameters and the drive circuit parasitic parameters to ensure sufficient drive circuit damping. An upper limit constraint is established by utilizing the gate-source threshold voltage characteristics and switching speed requirements to ensure that switching performance requirements are met and false turn-on is avoided. This embodiment solves the problem of lacking quantitative basis for the design of gate drive resistor parameters based on the physical characteristics of the device and the actual characteristics of the circuit, making it difficult to accurately match specific application scenarios. It achieves precise design of the gate drive resistor based on device parameters and circuit characteristics, improving the damping characteristics and switching performance of the drive circuit.

[0045] The calculation of each resistance value based on the total driving resistance formula and the set proportion includes: Using the lower and upper limits of the gate drive resistor as constraints, the specific values ​​of the common drive resistor, gate resistor, and Kelvin source resistor are calculated within the range of the constraints, based on the setting that the single-transistor drive resistor accounts for 50%.

[0046] Specifically, this embodiment uses the lower and upper limits of the gate drive resistor as constraints. Within these constraints, and considering the 50% proportion of the single-transistor drive resistor, it systematically calculates the specific resistance values ​​of the common drive resistor, gate resistor, and Kelvin source resistor using the total drive resistor formula. This establishes a multi-parameter collaborative calculation method based on dual constraints. This embodiment solves the problems in multi-parameter parallel silicon carbide drive systems, such as the lack of a systematic calculation method for the design of each drive resistor parameter, the difficulty in coordinating the configuration of each resistor value, and the inability to simultaneously meet damping conditions and anti-false turn-on requirements. It achieves accurate calculation and optimized configuration of drive resistor parameters, ensuring that each resistor value achieves optimal matching while meeting the drive circuit damping requirements and anti-false turn-on requirements.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel parallel silicon carbide drive improvement circuit, characterized in that, Includes multiple silicon carbide MOSFETs connected in parallel; The gates of the plurality of parallel-connected silicon carbide MOS transistors are electrically connected to the gate resistors. The Kelvin source of the plurality of parallel-connected silicon carbide MOS transistors is electrically connected to the Kelvin source resistor. One end of the gate resistor is electrically connected to the gate of the plurality of parallel-connected silicon carbide MOS transistors, and the other end of the gate resistor is connected to the drive signal input terminal through a common drive resistor; One end of the Kelvin source resistor is connected in parallel with the Kelvin source resistors of the plurality of silicon carbide MOS transistors, and the other end of the Kelvin source resistor is connected to the negative terminal of the drive voltage.

2. The multi-channel parallel silicon carbide drive improvement circuit as described in claim 1, characterized in that, The gate resistor electrically isolates the gates of each silicon carbide MOSFET, reducing the impact of PCB wiring differences. The Kelvin source resistor electrically isolates the Kelvin sources of each silicon carbide MOSFET, reducing circulating current and suppressing source current.

3. The multi-channel parallel silicon carbide drive improvement circuit as described in claim 1, characterized in that, The gate resistors of the multiple parallel-connected silicon carbide MOS transistors are combined to form the total driving resistance, wherein the single-transistor driving resistance accounts for 50% of the total driving resistance, and the single-transistor driving resistance includes the gate resistor and the internal driving resistance.

4. The multi-channel parallel silicon carbide drive improvement circuit as described in claim 1, characterized in that, The multi-parallel silicon carbide drive improvement circuit is applied in the power converter of the energy storage system to form the upper or lower bridge arm of the half-bridge circuit or the full-bridge circuit. The multiple parallel-connected silicon carbide MOSFETs include three silicon carbide MOSFETs connected in parallel.

5. A control method for a multi-channel parallel silicon carbide drive improvement circuit, applied to a multi-channel parallel silicon carbide drive improvement circuit as described in any one of claims 1-4, characterized in that, Includes the following steps: The lower limit of the gate drive resistor is determined based on the damping condition of the drive circuit, and the upper limit of the gate drive resistor is determined based on the anti-misoperation turn-on condition. The single-transistor drive resistor is set to account for 50% of the total drive resistor; The values ​​of each resistance are calculated according to the total driving resistance formula and the set proportion. The total driving resistance consists of the common driving resistance, the gate resistance, the internal driving resistance and the Kelvin source resistance. A PWM control signal is input to the drive signal input terminal and transmitted to the gate of each silicon carbide MOSFET through the common drive resistor and each gate resistor.

6. The control method for a multi-channel parallel silicon carbide drive improvement circuit as described in claim 5, characterized in that, The setting that the single-transistor drive resistor accounts for 50% of the total drive resistor includes: The single-transistor drive resistor is set to the sum of the gate resistor and the internal drive resistor, and the proportion of the single-transistor drive resistor in the total drive resistor is set to 50% to suppress the circulating current between parallel silicon carbide MOS transistors.

7. The control method for a multi-channel parallel silicon carbide drive improvement circuit as described in claim 6, characterized in that, The step of determining the lower limit of the gate drive resistor based on the damping condition of the drive circuit includes: setting the gate resistor to provide damping to dampen the oscillation of the drive current at the moment of turn-on of the silicon carbide MOS transistor; The step of determining the upper limit of the gate drive resistor based on the anti-misoperation turn-on condition includes: preventing excessive voltage change rate when the silicon carbide MOSFET is turned off, so as to avoid the silicon carbide MOSFET being mistakenly turned on again.

8. The control method for a multi-channel parallel silicon carbide drive improvement circuit as described in claim 6, characterized in that, The PWM control signal consists of two mutually opposite PWM signals, which control the multi-parallel silicon carbide drive improvement circuits of the upper and lower bridge arms respectively. The mutually opposite control method ensures that the upper and lower bridge arms will not be turned on at the same time.

9. The control method for a multi-channel parallel silicon carbide drive improvement circuit as described in claim 5, characterized in that, The step of determining the lower limit value of the gate drive resistance based on the drive circuit damping condition includes: The lower limit of the gate drive resistor is determined based on the parasitic capacitance of the silicon carbide MOSFET and the parasitic inductance of the drive circuit. The step of determining the upper limit of the gate drive resistor based on the anti-misoperation conditions includes: determining the upper limit of the gate drive resistor based on the gate-source threshold voltage and switching speed requirements of the silicon carbide MOSFET.

10. The control method for a multi-channel parallel silicon carbide drive improvement circuit as described in claim 9, characterized in that, The calculation of each resistance value based on the total driving resistance formula and the set proportion includes: Using the lower and upper limits of the gate drive resistor as constraints, the specific values ​​of the common drive resistor, gate resistor, and Kelvin source resistor are calculated within the range of the constraints, based on the setting that the single-transistor drive resistor accounts for 50%.

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