Drive circuit and control method for an ANPC three-level circuit
Patent Information
- Application Number
- CN202611133319.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-28
- Publication Date
- 2026-10-27
AI Technical Summary
在实际运行中，当进行封波（即封锁所有开关脉冲）时，由于各开关器件关断特性的不一致，封波过程中可能出现电压尖峰或直通短路等情况，进而造成开关器件甚至整个设备的损坏
[0005]根据本申请的ANPC型三电平电路的驱动电路，通过设定开关器件的关断时序，由第一驱动模块先关断内管，第二驱动模块再关断外管，最后由第三驱动模块关断钳位管，完成封波操作，可以有效减小开关器件电压应力，降低封波过程出现电压尖峰或短路的概率，避免损坏开关器件或设备。
Smart Images
Figure CN122993420A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power electronics technology, and in particular relates to a driving circuit and control method for an ANPC type three-level circuit. Background Technology
[0002] Active Neutral Point Clamped (ANPC) three-level topologies are widely used in photovoltaic inverters, energy storage converters, and other fields due to their advantages such as uniform loss distribution and high conversion efficiency. ANPC topologies typically employ various types of switching devices, each with inherent differences in turn-off and turn-on times. In actual operation, when pulse blocking (i.e., blocking all switching pulses) is performed, voltage spikes or shoot-through short circuits may occur during the blocking process due to the inconsistency in the turn-off characteristics of each switching device, potentially causing damage to the switching devices or even the entire equipment. Summary of the Invention
[0003] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a driving circuit and control method for an ANPC-type three-level circuit, which can reduce the voltage stress on the switching devices, reduce the probability of voltage spikes or short circuits during the blocking process, and avoid damage to the switching devices or equipment.
[0004] In a first aspect, this application provides a driving circuit for an ANPC-type three-level circuit, comprising: The first driving module is used to respond to the blocking signal and output a first driving pulse to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state. The second driving module is used to output the first driving pulse to the external transistor in the ANPC type three-level circuit that is in the conducting state when all the internal transistors of the ANPC type three-level circuit are in the off state, so as to turn off the external transistor in the conducting state. The third driving module is used to output the first driving pulse to the clamping transistor in the ANPC type three-level circuit that is in the conducting state when all the external transistors of the ANPC type three-level circuit are in the off state, so as to turn off the clamping transistor in the conducting state.
[0005] According to the driving circuit of the ANPC type three-level circuit of this application, by setting the turn-off sequence of the switching devices, the first driving module turns off the inner tube first, the second driving module turns off the outer tube, and finally the third driving module turns off the clamping tube to complete the wave blocking operation. This can effectively reduce the voltage stress of the switching devices, reduce the probability of voltage spikes or short circuits during the wave blocking process, and avoid damage to the switching devices or equipment.
[0006] According to one embodiment of this application, the second driving module is used to output the first driving pulse to the outer tube in the ANPC type three-level circuit that is in the conducting state when all the inner tubes of the ANPC type three-level circuit are in the off state and there is a clamping tube in the conducting state.
[0007] According to one embodiment of this application, after the first driving module outputs the first driving pulse to the inner tube in the ANPC type three-level circuit that is in the conducting state and delays for a first preset time, the second driving module outputs the first driving pulse to the outer tube in the ANPC type three-level circuit that is in the conducting state.
[0008] According to one embodiment of this application, after the second driving module outputs the first driving pulse to the external tube in the ANPC type three-level circuit that is in the conducting state and delays for a second preset time, the third driving module outputs the first driving pulse to the clamping tube in the ANPC type three-level circuit that is in the conducting state.
[0009] According to one embodiment of this application, the third driving module is further configured to output a second driving pulse to the target clamping transistor of the ANPC type three-level circuit in response to an enable signal, so as to turn on the target clamping transistor; The first driving module is further configured to output the second driving pulse to the target inner tube of the ANPC type three-level circuit when the target clamping tube is in the conducting state, so as to conduct the target inner tube; The second driving module is further configured to output the second driving pulse to the target outer tube of the ANPC type three-level circuit when the target inner tube is in a conducting state, so as to conduct the target outer tube.
[0010] According to one embodiment of this application, after the third driving module outputs the second driving pulse to the target clamping tube and delays for a third preset time, the first driving module outputs the second driving pulse to the target inner tube.
[0011] According to one embodiment of this application, after the first driving module outputs the second driving pulse to the target inner tube and delays for a fourth preset time, the second driving module outputs the second driving pulse to the target outer tube.
[0012] Secondly, this application provides a control method for an ANPC-type three-level circuit, including: In response to the blocking signal, a first driving pulse is output to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state. When all the internal transistors of the ANPC-type three-level circuit are in the off state, the first driving pulse is output to the external transistors in the ANPC-type three-level circuit that are in the on state to turn off the external transistors in the on state. When all the external transistors of the ANPC type three-level circuit are in the off state, the first driving pulse is output to the clamping transistor in the ANPC type three-level circuit that is in the on state, so as to turn off the clamping transistor in the on state.
[0013] Thirdly, this application provides a power conversion device, comprising: ANPC type three-level circuit; The driving circuit of the ANPC type three-level circuit as described in the first aspect above is connected to the ANPC type three-level circuit.
[0014] Fourthly, this application provides a power supply system, comprising: The power conversion equipment described in the third aspect above.
[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the driving circuit of the ANPC type three-level circuit provided in the embodiments of this application; Figure 2 This is a flowchart illustrating the control method for the ANPC-type three-level circuit provided in the embodiments of this application; Figure 3 This is one of the topological schematic diagrams of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 4 This is the second topology diagram of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 5 This is the third schematic diagram of the topology of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the blocking process of the ANPC type three-level circuit provided in the embodiments of this application; Figure 7 This is the fourth topology diagram of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 8 This is the fifth schematic diagram of the topology of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 9 This is the sixth schematic diagram of the topology of the ANPC-type three-level circuit provided in the embodiments of this application; Figure 10 This is one of the signal timing diagrams for the ANPC-type three-level circuit blocking provided in the embodiments of this application; Figure 11 This is the second signal timing diagram of the ANPC-type three-level circuit blocking provided in the embodiments of this application; Figure 12 This is the third of the signal timing diagrams for the ANPC-type three-level circuit blocking provided in the embodiments of this application; Figure 13 This is the fourth of the signal timing diagrams for the ANPC-type three-level circuit blocking provided in the embodiments of this application; Figure 14 This is a schematic diagram of the open-wave process of the ANPC type three-level circuit provided in the embodiments of this application; Figure 15 This is one of the signal timing diagrams of the ANPC type three-level circuit open wave provided in the embodiments of this application; Figure 16 This is the second signal timing diagram of the ANPC type three-level circuit open wave provided in the embodiments of this application; Figure 17 This is the third of the signal timing diagrams for the ANPC-type three-level circuit open-wave provided in the embodiments of this application; Figure 18 This is the fourth of the signal timing diagrams for the open-wave ANPC type three-level circuit provided in the embodiments of this application. Detailed Implementation
[0017] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0018] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0019] The following description, in conjunction with the accompanying drawings, details specific embodiments and application scenarios of the ANPC-type three-level circuit driving circuit 100, the ANPC-type three-level circuit control method, the power conversion equipment, and the power supply system provided in this application.
[0020] like Figure 3 As shown, the ANPC type three-level circuit includes a DC positive bus. V pos DC negative bus V neg And the neutral point N located between the two, each phase bridge arm of the circuit contains six power switching devices and corresponding freewheeling diodes. The six switching devices are the outer tube (T1, T4), the inner tube (T2, T3) and the clamping tube (T5, T6).
[0021] in, C inv A This refers to the inverter filter capacitor for phase A. L inv A This represents the inverter filter inductor of phase A.
[0022] The modulation truth table of the ANPC type three-level circuit is shown in Table 1. By time-division conduction of the six power switching devices, the ANPC type three-level circuit can realize three-level output, which can output three level states: +1 level, 0 level (i.e., zero level) and -1 level.
[0023] When the modulating wave is greater than 0, i.e., the polarity of the modulating wave is positive, T1 and T6 remain on, while T4 and T5 remain off. At this time, when T2 is on and T3 is off, the circuit outputs a +1 level. When T2 is off and T3 is on, the circuit outputs a 0 level. Here, to distinguish the polarity, this is recorded as +0 level. When the modulating wave is less than 0, i.e., the polarity of the modulating wave is negative, T1 and T6 remain off, while T4 and T5 remain on. At this time, when T2 is off and T3 is on, the circuit outputs a -1 level. When T2 is on and T3 is off, the circuit outputs a 0 level. This is recorded as -0 level.
[0024] ANPC-type three-level circuits can be used in power conversion equipment such as photovoltaic inverters and energy storage converters to optimize loss distribution and improve system efficiency.
[0025] In an ANPC-type three-level circuit, the modulation method can be to use the inner transistors (T2, T3) as high-frequency switching devices and the outer transistors (T1, T4) and clamping transistors (T5, T6) as low-frequency (also known as power frequency) switching devices. There are inherent differences in the turn-off and turn-on times between high-frequency and low-frequency switching devices. In actual operation, when pulse blocking (i.e., blocking all switching pulses) is performed, due to the inconsistency in the turn-off characteristics of each switching device, voltage spikes or short circuits may occur during the pulse blocking process, potentially causing damage to the switching devices or even the entire equipment.
[0026] Table 1
[0027] Taking modulation wave > 0 and modulation wave < 0 as examples, we will explain the abnormal states that may occur during the wave blocking process.
[0028] When the modulated wave > 0 and the ANPC type three-level circuit is at +1 level, T1, T2, and T6 are turned on, while T3 and T4 are turned off. In this case, wave blocking requires turning off T1, T2, and T6. For example... Figure 4 As shown, if T2 and T6 are turned off, but T1 is still in the conducting state (represented by a wire in the figure), the inverter current... i inv The direction is positive, and the current is... i inv After the freewheeling diodes of T3 and T4 provide freewheeling current, the potential at point A of T2 is now... V pos The potential at point B is - V neg T2 bears the voltage drop of the entire rectifier bus, which can easily lead to overvoltage damage to T2.
[0029] When the modulated wave > 0 and the ANPC type three-level circuit is in the +0 state, T1, T2, and T6 are turned on, and T3, T4, and T5 are turned off. In this case, wave blocking requires turning off T1, T3, and T6. If T3 and T6 are already turned off, but T1 is still turned on, the inverter current... i inv If the direction is positive, the same pattern will appear. Figure 4 Under the same abnormal wave blocking condition, T2 bears the voltage drop of the entire rectifier bus, which can easily lead to overvoltage damage to T2.
[0030] When the modulated wave is less than 0 and the ANPC three-level circuit is at -1 level, T3, T4, and T5 are turned on, while T1, T2, and T6 are turned off. In this case, wave blocking requires turning off T3, T4, and T5. For example... Figure 5 As shown, if T3 and T5 are turned off, but T4 is still in the conducting state (represented by a wire in the figure), the inverter current... i inv The direction is negative, and the current is negative. iinv After the diodes in T1 and T2 freewheel to the DC positive bus, the potential at point A of T3 is... V pos The potential at point B is - V neg T3 bears the voltage drop of the entire rectifier bus, which can easily lead to overvoltage damage to T3.
[0031] When the modulated wave is less than 0 and the ANPC three-level circuit is at -1 level, T2, T4, and T5 are turned on, while T1, T3, and T6 are turned off. In this case, wave blocking requires turning off T2, T4, and T5. If T2 and T5 are turned off, but T4 is still on, the inverter current... i inv If the direction is negative, the same will occur. Figure 5 Under the same abnormal wave blocking condition, T3 bears the voltage drop of the entire rectifier bus, which can easily lead to overvoltage damage to T3.
[0032] This application provides a driving circuit 100 for an ANPC type three-level circuit, which can reduce the voltage stress on the switching devices, reduce the probability of voltage spikes or short circuits during the semaphore process, and avoid damage to the switching devices or equipment.
[0033] like Figure 1 As shown, the driving circuit 100 of the ANPC type three-level circuit includes a first driving module 110, a second driving module 120 and a third driving module 130. The first driving module 110 is used to drive the inner transistor in the ANPC type three-level circuit to turn on or off, the second driving module 120 is used to drive the outer transistor in the ANPC type three-level circuit to turn on or off, and the third driving module 130 is used to drive the clamping transistor in the ANPC type three-level circuit to turn on or off.
[0034] It is understood that the driving circuit 100 of the ANPC type three-level circuit may include circuit components such as isolation devices, driving stages and power supplies. After receiving control signals (such as blocking signals, enable signals, etc.), the driving circuit 100 drives the switching transistors in the ANPC type three-level circuit to operate.
[0035] The first driving module 110 can be a circuit unit in the driving circuit 100 that drives the inner tube to turn on or off, the second driving module 120 can be a circuit unit in the driving circuit 100 that drives the outer tube to turn on or off, and the third driving module 130 can be a circuit unit in the driving circuit 100 that drives the clamping tube to turn on or off.
[0036] The first driving module 110 is used to respond to the blocking signal and output a first driving pulse to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state. The second driving module 120 is used to output a first driving pulse to the external transistor in the ANPC type three-level circuit that is in the conducting state when all the internal transistors of the ANPC type three-level circuit are in the off state, so as to turn off the external transistor in the conducting state. The third driving module 130 is used to output a first driving pulse to the clamping transistor in the ANPC type three-level circuit that is in the conducting state when all the external transistors of the ANPC type three-level circuit are in the off state, so as to turn off the clamping transistor in the conducting state.
[0037] It is understandable that the blocking signal is a control signal used to block the drive pulses of power switching devices.
[0038] For example, the system containing the ANPC type three-level circuit is equipped with a protection circuit. When the system detects faults such as overcurrent, overvoltage, or short circuit, the protection circuit sends a blocking signal to the drive circuit 100.
[0039] For example, during normal shutdown, the control unit (such as a system-level main controller independent of the inverter body, or a control module integrated inside the inverter) generates a blocking signal and sends the blocking signal to the drive circuit 100.
[0040] The first drive pulse is a drive signal issued by the drive module to control the power switching device to turn off. It can be in the form of a level signal, pulse width modulation (PWM) waveform, or pulse sequence to drive the corresponding power switching device to perform a turn-off action.
[0041] In this embodiment, when the blocking signal is received, the first driving module 110 first outputs a first driving pulse to the inner tube in the conducting state. After turning off the inner tube in the conducting state, the second driving module 120 outputs a first driving pulse to the outer tube in the conducting state. After turning off the outer tube in the conducting state, the third driving module 130 finally outputs a first driving pulse to the clamping tube in the conducting state to turn off the clamping tube in the conducting state. The driving circuit 100 turns off all power switching devices (T1 to T6) of the ANPC type three-level circuit according to the turn-off sequence of turning off the inner tube first, then the outer tube, and finally the clamping tube, thus completing the blocking operation.
[0042] In some embodiments, the second driving module 120 is used to output a first driving pulse to the outer tube in the ANPC type three-level circuit that is in the conducting state when all the inner tubes of the ANPC type three-level circuit are in the off state and there is a clamping tube in the conducting state.
[0043] In this embodiment, the first driving module 110 first turns off all the internal transistors of the ANPC type three-level circuit. At this time, there are clamping transistors and external transistors in the conducting state. The second driving module 120 can output the first driving pulse to the external transistors in the conducting state to turn off the external transistors in the conducting state first. After all the external transistors of the ANPC type three-level circuit are turned off, the third driving module 130 turns off the clamping transistors in the conducting state.
[0044] In some embodiments, after the first driving module 110 outputs a first driving pulse to the inner tube in the ANPC type three-level circuit that is in the conducting state and delays for a first preset time, the second driving module 120 outputs a first driving pulse to the outer tube in the ANPC type three-level circuit that is in the conducting state.
[0045] The first preset duration is the preset waiting time.
[0046] In this embodiment, after the first driving module 110 sends out the first driving pulse, timing begins. When the timing reaches the first preset duration, it indicates that the inner tube that received the first driving pulse has been reliably turned off and can safely perform the subsequent wave blocking operation. The second driving module 120 then outputs the first driving pulse to the outer tube that is in the conducting state.
[0047] It is understandable that the first preset duration can be set according to the characteristics of the switching device in actual application. Its value is related to factors such as the turn-off delay time, drive response speed, operating temperature and bus voltage of the switching device. By reasonably setting the first preset duration, it can be ensured that the inner tube that receives the first drive pulse has completed reliable turn-off within the first preset duration, avoiding short circuit or device damage caused by premature execution of subsequent actions.
[0048] In some embodiments, after the second driving module 120 outputs a first driving pulse to the external tube in the ANPC type three-level circuit that is in the conducting state and delays for a second preset time, the third driving module 130 outputs a first driving pulse to the clamping tube in the ANPC type three-level circuit that is in the conducting state.
[0049] The second preset duration is the preset waiting time.
[0050] In this embodiment, after the second drive module 120 sends out the first drive pulse, a timer is started. When the timer reaches the second preset duration, it indicates that the outer tube that received the first drive pulse has been reliably turned off, and the subsequent wave blocking operation can be safely performed. The third drive module 130 then outputs the first drive pulse to the clamping tube that is in the conducting state.
[0051] It is understandable that the second preset duration can be set according to the characteristics of the switching device in actual application. Its value is related to factors such as the turn-off delay time, drive response speed, operating temperature and bus voltage of the switching device. By reasonably setting the second preset duration, it can be ensured that the outer tube that receives the first drive pulse has completed reliable turn-off within the second preset duration, avoiding short circuit or device damage caused by premature execution of subsequent actions.
[0052] In actual operation, the first preset duration and the second preset duration can be equal or unequal, and can be flexibly configured according to the actual working conditions.
[0053] For example, such as Figure 6 As shown, when the blocking signal is valid, the first drive module 110 first turns off the inner tubes T2 and T3, and then delays for a first preset time t. off_delay1 Then, the second drive module 120 shuts off the external tubes T1 and T4, delaying for a second preset time t. off_delay2 Finally, the third drive module 130 shuts off clamping transistors T5 and T6, where t off_delay1 =t off_delay2 =1μs-10μs.
[0054] The working principle and technical effects of the wave-blocking process in the embodiments of this application will be described in detail below. It should be noted that this description is only used to explain the technical essence of this application so that those skilled in the art can understand it, and should not be regarded as any limitation on the scope of protection of this application.
[0055] like Figure 7 As shown, when the modulation wave > 0, the inner tube is turned off first, and T1 and T6 remain on. At this time, T2 and T3 share half of the bus voltage, and T3 and T5 also share half of the bus voltage. Only when T6 is turned off will the voltage change. Figure 4 The abnormal state shown.
[0056] When all the internal transistors of the ANPC-type three-level circuit are in the off state, there is a clamping transistor in the on state. The second drive module 120 outputs the first drive pulse to the external transistor in the ANPC-type three-level circuit that is in the on state, which can effectively prevent the switching device from being damaged by overvoltage.
[0057] For example, during wave blocking, the circuit is at +0 level, and transistors T1, T3, and T6 are conducting, with current flowing through them. i When the direction is negative, turning off T3 first can suppress the current as soon as possible, avoid voltage spikes or shoot-through short circuits, and prevent device damage.
[0058] like Figure 8 As shown, if T1 is turned off first, the current can still continue from T3 and T6, and the current will continue to increase.
[0059] like Figure 9As shown, the inner tube T3 is turned off first. The current can only flow through the freewheeling diode of T2 and T1 to the positive busbar. The positive busbar position can effectively suppress the current from continuing to increase.
[0060] The wave blocking process of this application embodiment will be described in detail from four different implementation perspectives below.
[0061] The blocking signal is valid when it is low.
[0062] like Figure 10 As shown, the ANPC type three-level circuit is at +1 level, at t s1 Before time t, T3, T4, and T5 are in the off state, and T1, T2, and T6 are in the on state. s1 When the time-blocking signal goes low, T2 is first turned off, and after a delay (the first preset duration), at t... s2 Turn off T1 at any time, and after a delay of a certain period of time (the second preset duration), at t s3 At time ts3, T6 is turned off, and after time ts3, all power switching devices in the ANPC type three-level circuit are in the off state.
[0063] like Figure 11 As shown, the ANPC type three-level circuit is at +0 level, at t s1 Before time t, T2, T4, and T5 are in the off state, and T1, T3, and T6 are in the on state. s1 When the time-blocking signal goes low, T3 is first turned off, and after a delay, at t... s2 Turn off T1 at any time, and after a delay, at t s3 At time ts3, T6 is turned off, and after time ts3, all power switching devices in the ANPC type three-level circuit are in the off state.
[0064] like Figure 12 As shown, the ANPC type three-level circuit is at level -1, at t s1 Before time t, T1, T2, and T6 are in the off state, and T3, T4, and T5 are in the on state. s1 When the time-blocking signal goes low, T3 is first turned off, and after a delay, at t... s2 T4 is turned off at the beginning, and after a delay, at t s3 At time ts3, T5 is turned off, and after time ts3, all power switching devices in the ANPC type three-level circuit are in the off state.
[0065] like Figure 13 As shown, the ANPC type three-level circuit is at -0 level, at t s1Before time t, T1, T3, and T6 are in the off state, and T2, T4, and T5 are in the on state. s1 When the time-blocking signal goes low, T2 is first turned off, and after a delay, at t... s2 T4 is turned off at the beginning, and after a delay, at t s3 At time ts3, T5 is turned off, and after time ts3, all power switching devices in the ANPC type three-level circuit are in the off state.
[0066] The drive circuit 100 turns off all power switching devices (T1 to T6) of the ANPC type three-level circuit according to the turn-off sequence of first turning off the inner transistor, then the outer transistor, and finally the clamping transistor. No signal interruption will occur during any state of waveform blocking. Figure 4 or Figure 5 The abnormal state shown means that the power switching devices in the ANPC type three-level circuit will not bear the entire bus voltage drop during the wave blocking operation, effectively reducing the voltage stress on the switching devices, reducing the probability of voltage spikes or short circuits during the wave blocking process, and avoiding damage to the switching devices or equipment.
[0067] According to the ANPC type three-level circuit driving circuit 100 provided in the embodiment of this application, by setting the turn-off sequence of the switching devices, the first driving module 110 first turns off the inner tube, the second driving module 120 then turns off the outer tube, and finally the third driving module 130 turns off the clamping tube to complete the wave blocking operation. This can effectively reduce the voltage stress of the switching devices, reduce the probability of voltage spikes or short circuits during the wave blocking process, and avoid damage to the switching devices or equipment.
[0068] This application embodiment also sets the turn-on timing of the switching devices during the opening wave of the ANPC type three-level circuit, so as to reduce the voltage stress during the opening wave process and effectively protect the safety of the switching devices and equipment.
[0069] In some embodiments, the third driving module 130 is further configured to output a second driving pulse to the target clamping transistor of the ANPC type three-level circuit in response to an enable signal, so as to turn on the target clamping transistor. The first driving module 110 is also used to output a second driving pulse to the target inner tube of the ANPC type three-level circuit when the target clamping tube is in the conducting state, so as to conduct the target inner tube. The second drive module 120 is also used to output a second drive pulse to the target outer tube of the ANPC type three-level circuit when the target inner tube is in the conducting state, so as to turn on the target outer tube.
[0070] It is understandable that the enable signal (also known as the open wave signal) is a control signal used to enable the drive circuit 100 to output drive pulses. It can be sent to the drive circuit 100 by the control unit when the system is powered on and started, or it can be generated and sent to the drive circuit 100 by the control unit when the system recovers from the protection state.
[0071] The second drive pulse is a drive signal issued by the drive module to control the power switching device to turn on. It can be in the form of a level signal, pulse width modulation (PWM) waveform, or pulse sequence to drive the corresponding power switching device to perform the turn-on action.
[0072] It should be noted that the target clamping transistor is the clamping transistor that needs to be turned on during the open-wave process, and can be T5 or T6; the target inner transistor is the inner transistor that needs to be turned on during the open-wave process, and can be T2 or T3; and the target outer transistor is the outer transistor that needs to be turned on during the open-wave process, and can be T1 or T4. The drive circuit 100 can select the corresponding target clamping transistor, target inner transistor, and target outer transistor for conduction control according to the required output level.
[0073] In this embodiment of the application, when the enable signal is received, the third drive module 130 first outputs a second drive pulse to the target clamping tube. After the target clamping tube is turned on, the first drive module 110 outputs a second drive pulse to the target inner tube. After the target inner tube is turned on, the second drive module 120 finally outputs a second drive pulse to the target outer tube to turn on the target outer tube and complete the open wave operation.
[0074] In some embodiments, after the third driving module 130 outputs a second driving pulse to the target clamping tube and delays for a third preset time, the first driving module 110 outputs a second driving pulse to the target inner tube.
[0075] The third preset duration is the preset waiting time.
[0076] In this embodiment, after the third drive module 130 sends out the second drive pulse, timing begins. When the timing reaches the third preset duration, it indicates that the target clamping tube has been reliably turned on and can safely perform the subsequent open-wave operation. The first drive module 110 outputs the second drive pulse to the target inner tube to turn on the target inner tube.
[0077] It is understandable that the third preset duration can be set according to the characteristics of the switching device in actual application. Its value is related to factors such as the conduction delay time, drive response speed, operating temperature and bus voltage of the switching device. By reasonably setting the third preset duration, it can be ensured that the target clamping tube that receives the second drive pulse has completed reliable conduction within the third preset duration.
[0078] In some embodiments, after the first driving module 110 outputs a second driving pulse to the target inner tube and delays for a fourth preset time, the second driving module 120 outputs a second driving pulse to the target outer tube.
[0079] The fourth preset duration is the preset waiting time.
[0080] In this embodiment, after the first driving module 110 sends out the second driving pulse, timing begins. When the timing reaches the fourth preset duration, it indicates that the target inner tube has been reliably turned on and can safely perform the subsequent wave opening operation. The second driving module 120 outputs the second driving pulse to the target outer tube to turn on the target outer tube and complete the wave opening operation.
[0081] It is understandable that the fourth preset duration can be set according to the characteristics of the switching device in actual application. Its value is related to factors such as the conduction delay time, drive response speed, operating temperature and bus voltage of the switching device. By reasonably setting the fourth preset duration, it can be ensured that the target inner tube that receives the second drive pulse has completed reliable conduction within the fourth preset duration.
[0082] In actual implementation, the third and fourth preset durations can be equal or unequal, and can be flexibly configured according to the actual working conditions.
[0083] For example, such as Figure 14 As shown, when the open-wave signal is valid, the third drive module 130 first turns on the clamping transistor corresponding to the current level, i.e., the target clamping transistor, and delays for a third preset time t. on_delay1 Then, the first driving module 110 turns on the inner tube corresponding to the current level, i.e., the target inner tube, and delays for a fourth preset time t. on_delay2 Finally, the second drive module 120 turns on the external tube corresponding to the current level, i.e., the target external tube, where t on_delay1 =t on_delay2 =1μs-10μs.
[0084] The wave opening process of this application embodiment will be described in detail from four different implementation perspectives below.
[0085] The open wave signal (i.e., the enable signal) is valid when it is high.
[0086] like Figure 15 As shown, at t s1 Before time t, all time points T1 through T6 were in the off state. s1 When the open-wave signal goes high, T6 is turned on first. After a delay (the third preset duration), at t... s2 When T2 is turned on, after a delay of a certain period (the fourth preset duration), at t s3 At a certain moment, T1 is turned on to complete the open-wave operation and output a +1 level.
[0087] like Figure 16 As shown, at t s1 Before time t, all time points T1 through T6 were in the off state. s1 When the open-wave signal goes high, T6 is turned on first. After a delay, at t... s2 T3 is turned on at the specified time, and after a delay, at t s3 At that moment, T1 is turned on to complete the open-wave operation and output a +0 level.
[0088] like Figure 17 As shown, at t s1 Before time t, all time points T1 through T6 were in the off state. s1 When the open-wave signal goes high, T5 is turned on first. After a delay, at time t... s2 T3 is turned on at the specified time, and after a delay, at t s3 At that moment, T4 is turned on to complete the open-wave operation and output a -1 level.
[0089] like Figure 18 As shown, at t s1 Before time t, all time points T1 through T6 were in the off state. s1 When the open-wave signal goes high, T5 is turned on first. After a delay, at time t... s2 T2 is turned on at the specified time, and after a delay of a certain period of time, at t s3 At that moment, T4 is turned on to complete the open-wave operation and output a -0 level.
[0090] The drive circuit 100 follows the conduction sequence of first opening the clamping transistor, then the inner transistor, and finally the outer transistor to complete the opening operation of the ANPC type three-level circuit, reducing voltage stress during the opening process and effectively protecting the switching devices and equipment.
[0091] This application also provides a control method for an ANPC-type three-level circuit.
[0092] The control method for the ANPC type three-level circuit provided in this application embodiment can be executed by the driving circuit 100 of the ANPC type three-level circuit, an electronic device, or a functional module or functional entity in an electronic device that can implement the control method for the ANPC type three-level circuit.
[0093] like Figure 2 As shown, the control method of the ANPC type three-level circuit includes steps 210, 220 and 230.
[0094] Step 210: In response to the blocking signal, output the first driving pulse to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state.
[0095] Step 220: With all the internal transistors of the ANPC type three-level circuit in the off state, output the first driving pulse to the external transistor in the ANPC type three-level circuit that is in the on state to turn off the external transistor in the on state.
[0096] Step 230: When all the external transistors of the ANPC type three-level circuit are in the off state, output the first drive pulse to the clamping transistor in the ANPC type three-level circuit that is in the on state, so as to turn off the clamping transistor in the on state.
[0097] According to the control method of the ANPC type three-level circuit provided in the embodiments of this application, by setting the turn-off sequence of the switching devices, the inner tube is turned off first, then the outer tube is turned off, and finally the clamping tube is turned off to complete the wave blocking operation. This can effectively reduce the voltage stress of the switching devices, reduce the probability of voltage spikes or short circuits during the wave blocking process, and avoid damage to the switching devices or equipment.
[0098] In some embodiments, outputting a first drive pulse to the external transistor in the on state of the ANPC type three-level circuit may include: When all the internal transistors of the ANPC-type three-level circuit are in the off state and there is a clamping transistor in the on state, the first driving pulse is output to the external transistor in the ANPC-type three-level circuit that is in the on state.
[0099] In some embodiments, after outputting a first driving pulse to the inner tube in the conducting state of the ANPC type three-level circuit and delaying for a first preset time, a first driving pulse is output to the outer tube in the conducting state of the ANPC type three-level circuit.
[0100] In some embodiments, after outputting a first drive pulse to the external transistor in the ANPC type three-level circuit that is in the conducting state and delaying for a second preset time, the first drive pulse is output to the clamping transistor in the ANPC type three-level circuit that is in the conducting state.
[0101] In some embodiments, the control method for the ANPC type three-level circuit may further include: In response to the enable signal, a second drive pulse is output to the target clamping transistor of the ANPC type three-level circuit to turn on the target clamping transistor; When the target clamping transistor is in the on state, a second drive pulse is output to the target inner transistor of the ANPC type three-level circuit to turn on the target inner transistor; When the target inner tube is in the conducting state, a second driving pulse is output to the target outer tube of the ANPC type three-level circuit to turn on the target outer tube.
[0102] In some embodiments, after outputting a second drive pulse to the target clamping tube and delaying for a third preset time, a second drive pulse is output to the target inner tube.
[0103] In some embodiments, after outputting a second driving pulse to the target inner tube and delaying for a fourth preset time, a second driving pulse is output to the target outer tube.
[0104] The control method for the ANPC-type three-level circuit provided in this application embodiment can realize the various processes implemented by the above-described ANPC-type three-level circuit drive circuit 100 embodiment. To avoid repetition, it will not be described again here.
[0105] This application also provides a power conversion device.
[0106] The power conversion device includes an ANPC type three-level circuit and a drive circuit 100 for the ANPC type three-level circuit as described above, the drive circuit 100 being connected to the ANPC type three-level circuit.
[0107] Among them, power conversion equipment can be photovoltaic inverters, energy storage converters, and other equipment used for power conversion.
[0108] The drive circuit 100 turns off all power switching devices (T1 to T6) of the ANPC type three-level circuit according to the turn-off sequence of first turning off the inner transistor, then the outer transistor, and finally the clamping transistor, thus completing the wave blocking operation.
[0109] According to the power conversion equipment provided in the embodiments of this application, by setting the turn-off sequence of the switching devices, the inner tube is turned off first, then the outer tube is turned off, and finally the clamping tube is turned off to complete the wave blocking operation. This can effectively reduce the voltage stress on the switching devices, reduce the probability of voltage spikes or short circuits during the wave blocking process, and avoid damage to the switching devices or equipment.
[0110] This application also provides a power supply system, including the power conversion device as described above.
[0111] This power supply system can be a photovoltaic-storage system or a photovoltaic-storage-charging system, etc., used to supply power to local loads, meet the system's own power needs, or connect to the power grid to achieve grid-connected operation.
[0112] According to the power supply system provided in the embodiments of this application, by setting the turn-off sequence of the switching devices, the inner tube is turned off first, then the outer tube is turned off, and finally the clamping tube is turned off to complete the wave blocking operation. This can effectively reduce the voltage stress on the switching devices, reduce the probability of voltage spikes or short circuits during the wave blocking process, and avoid damage to the switching devices or equipment.
[0113] This application also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described ANPC-type three-level circuit control method embodiment and achieves the same technical effect. To avoid repetition, it will not be described again here.
[0114] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0115] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the control method for the ANPC type three-level circuit described above.
[0116] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0117] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described ANPC-type three-level circuit control method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0118] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.
[0119] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0121] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
[0122] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0123] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A driving circuit for an ANPC-type three-level circuit, characterized in that, include: The first driving module is used to respond to the blocking signal and output a first driving pulse to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state. The second driving module is used to output the first driving pulse to the external transistor in the ANPC type three-level circuit that is in the conducting state when all the internal transistors of the ANPC type three-level circuit are in the off state, so as to turn off the external transistor in the conducting state. The third driving module is used to output the first driving pulse to the clamping transistor in the ANPC type three-level circuit that is in the conducting state when all the external transistors of the ANPC type three-level circuit are in the off state, so as to turn off the clamping transistor in the conducting state.
2. The driving circuit of the ANPC type three-level circuit according to claim 1, characterized in that, The second driving module is used to output the first driving pulse to the external transistor in the ANPC type three-level circuit that is in the conducting state when all the internal transistors of the ANPC type three-level circuit are in the off state and there is a clamping transistor in the conducting state.
3. The driving circuit of the ANPC type three-level circuit according to claim 1, characterized in that, After the first driving module outputs the first driving pulse to the inner tube in the ANPC type three-level circuit that is in the conducting state and delays for a first preset time, the second driving module outputs the first driving pulse to the outer tube in the ANPC type three-level circuit that is in the conducting state.
4. The driving circuit of the ANPC type three-level circuit according to claim 1, characterized in that, After the second driving module outputs the first driving pulse to the external tube in the ANPC type three-level circuit that is in the conducting state and delays for a second preset time, the third driving module outputs the first driving pulse to the clamping tube in the ANPC type three-level circuit that is in the conducting state.
5. The driving circuit of the ANPC type three-level circuit according to claim 1, characterized in that, The third driving module is also used to output a second driving pulse to the target clamping transistor of the ANPC type three-level circuit in response to the enable signal, so as to turn on the target clamping transistor; The first driving module is further configured to output the second driving pulse to the target inner tube of the ANPC type three-level circuit when the target clamping tube is in the conducting state, so as to conduct the target inner tube; The second driving module is further configured to output the second driving pulse to the target outer tube of the ANPC type three-level circuit when the target inner tube is in a conducting state, so as to conduct the target outer tube.
6. The driving circuit of the ANPC type three-level circuit according to claim 5, characterized in that, After the third driving module outputs the second driving pulse to the target clamping tube and delays for a third preset time, the first driving module outputs the second driving pulse to the target inner tube.
7. The driving circuit of the ANPC type three-level circuit according to claim 5, characterized in that, After the first driving module outputs the second driving pulse to the target inner tube and delays for a fourth preset time, the second driving module outputs the second driving pulse to the target outer tube.
8. A control method for an ANPC-type three-level circuit, characterized in that, include: In response to the blocking signal, a first driving pulse is output to the inner tube in the conducting state in the ANPC type three-level circuit to turn off the inner tube in the conducting state. When all the internal transistors of the ANPC-type three-level circuit are in the off state, the first driving pulse is output to the external transistors in the ANPC-type three-level circuit that are in the on state to turn off the external transistors in the on state. When all the external transistors of the ANPC type three-level circuit are in the off state, the first driving pulse is output to the clamping transistor in the ANPC type three-level circuit that is in the on state, so as to turn off the clamping transistor in the on state.
9. A power conversion device, characterized in that, include: ANPC type three-level circuit; The driving circuit of the ANPC type three-level circuit as described in any one of claims 1-7, wherein the driving circuit is connected to the ANPC type three-level circuit.
10. A power supply system, characterized in that, include: The power conversion device as described in claim 9.