Voltage reducing power converter, packaged device and method of controlling a power converter

Abstract

The application relates to a step-down power converter, a packaged device and a control method of the power converter. The step-down power converter comprises an input port, an output port, a first half-bridge power stage, a filter multiplexing unit, a second power stage and a second inductor. The input port receives a direct-current input voltage, and the output port provides a direct-current output voltage to a load. The first half-bridge power stage is connected between the input port and a reference ground, and the output end of the first half-bridge power stage is connected to the filter multiplexing unit. The filter multiplexing unit is composed of a first inductor and a flying capacitor. The second power stage is connected between the output end of the filter multiplexing unit and the second inductor. According to the application, the filter multiplexing unit is simultaneously used as an output filter network of the first half-bridge power stage and an input filter network of the second power stage, so that a high step-down conversion ratio is realized, the number of devices can be effectively reduced, the voltage stress of a switch tube is reduced, the conversion efficiency is improved, and the application is suitable for a high step-down ratio power supply scene with high input voltage and low voltage and large current output.

Description

Technical Field

[0001] This application relates to the field of power converter manufacturing technology, and in particular to a buck power converter, a packaged device, and a control method for the power converter. Background Technology

[0002] As power consumption in AI servers and data centers continues to rise, replacing the traditional 12V bus architecture with a 48V bus has become an industry trend. However, directly stepping down from 48V to 1V processor core voltage faces a significant buck ratio challenge. Traditional single-stage Buck converters have extremely small duty cycles in this scenario, leading to a surge in switching losses, limited minimum on-time, and difficulties in control loop design. While conventional two-stage series solutions can alleviate duty cycle pressure, the serial power paths of multiple stages cause conduction losses to accumulate, and the large size of the intermediate bus capacitor is detrimental to power density improvement. Although existing hybrid converter topologies have made some progress, they generally suffer from problems such as complex power stages, a large number of components, and high control difficulty, making it difficult to achieve both high efficiency and high power density. Summary of the Invention

[0003] To address the above problems, this application provides a step-down power converter, comprising: The input port is used to receive DC input voltage. The output port is used to provide DC output voltage to the load; The first half-bridge power stage includes a first high-side switch and a first low-side switch connected in series between the input port and the reference ground. The common node of the first high-side switch and the first low-side switch is defined as the first switching node. A filtering and multiplexing unit includes a first inductor and a flying capacitor, one end of the first inductor being connected to the first switching node; the flying capacitor is connected between the other end of the first inductor and the reference ground. A second power stage is connected between the other end of the first inductor and the output port, and the second power stage includes a plurality of switching transistors and a switched capacitor network; and The second inductor is connected between a preset node within the second power stage and the output port; The filter multiplexing unit serves as both the output filter network of the first half-bridge power stage and the input filter network of the second power stage, and the steady-state voltage conversion ratio of the power converter satisfies: V0 / V in =D 2 / 2; Where D is the control duty cycle of the switching transistor in the first half-bridge power stage, Vin is the input voltage, and V0 is the output voltage.

[0004] In one embodiment, the second power stage is a subsequent buck converter unit, with its input side connected to the other end of the first inductor and its output side connected to the output port via the second inductor.

[0005] In one embodiment, the first inductor and the second inductor have a 180° phase difference during operation, and the peak-to-peak value of the two inductor current ripples is smaller than that of a single inductor current ripple when they are superimposed at the output port.

[0006] In one embodiment, the inductance ratio L2 / L1 of the second inductor and the first inductor is set based on the duty cycle to satisfy L2 / L1 = (DD) / L1 / L2. 2 / 2) / (1-DD 2 / 2), so that the peak values ​​of the two inductor currents are equal.

[0007] In one embodiment, the duty cycle ranges from 0.15 to 0.25 to accommodate an input voltage range of 36V to 60V.

[0008] In one embodiment, the output voltage V0 ranges from 0.8V to 1.2V, and the power converter is used to provide core power supply voltage for a processor or accelerator chip.

[0009] In one embodiment, the switched capacitor network includes: The first switched capacitor unit has its first end connected to the common terminal of the third and fourth switched transistors, and its second end connected to the common terminal of the fifth and sixth switched transistors; the other end of the current path of the third switched transistor is connected to the other end of the first inductor. The second switched capacitor unit has its first end connected to the common terminal of the seventh and eighth switched transistors, and its second end connected to the common terminal of the ninth and tenth switched transistors, respectively; the other end of the current path of the eighth switched transistor is connected to the first plate of the flying capacitor.

[0010] In one embodiment, the first switched capacitor unit and the second switched capacitor unit form a uniform voltage distribution node within the second power stage to reduce the voltage stress on each switch in the second power stage.

[0011] In one embodiment, both the first high-side switch and the first low-side switch are gallium nitride-based high electron mobility transistors.

[0012] In one embodiment, a flying capacitor voltage balancing control circuit is further included. The flying capacitor voltage balancing control circuit is used to sample the voltage across the flying capacitor. When the deviation between the sampled voltage of the flying capacitor and the target value exceeds a preset threshold, the flying capacitor voltage is restored to the target value by adjusting the duty cycle or the phase distribution within the second power stage.

[0013] In one embodiment, an adaptive mode switching control circuit is further included, which controls the operating phase states of the first inductor and the second inductor based on the load current detection signal. When the load is under heavy load steady state, the two-phase inductors are controlled to operate in a complementary interleaved state to reduce output ripple; and When the load is in a transient state, the two-phase inductors are controlled to operate in the same phase to improve the dynamic response speed.

[0014] This application also provides a packaged device for implementing the power converter mentioned in any of the above embodiments, including: The packaging substrate has vertical power supply vias; A gallium nitride power transistor die is disposed in a first region of the packaging substrate, and at least the first high-side switch and the first low-side switch are integrated therein. A silicon-based control chip is disposed in the second region of the packaging substrate, integrating the switching transistor drive logic and pulse width modulation control circuit of the second power stage; The passive component layer is embedded or mounted inside the packaging substrate and includes at least the first inductor, the second inductor, the flying capacitor, and the output filter capacitor. The packaging substrate electrically interconnects the gallium nitride power transistor chip and the silicon-based control chip through an intermediate bus voltage node, forming a vertical power supply path with high voltage input from the bottom and low voltage output from the top of the packaging substrate.

[0015] In one embodiment, the gallium nitride power transistor die and the silicon-based control die are stacked vertically, and the passive device layer is located in the middle buried region of the packaging substrate.

[0016] In one embodiment, the silicon-based control chip integrates a segmented gate drive circuit, which is used to adjust the magnitude of the drive current in segments during the switching process and introduce a handshake signal in the drive path to prevent the high-side and low-side switching transistors from being turned on simultaneously.

[0017] This application also provides a control method for a buck power converter, including: A pulse width modulation signal with a duty cycle of D is generated to control the complementary conduction of the high-side and low-side switches in the first power stage, so that the ratio of the output voltage to the input voltage of the power converter satisfies V0 / V0. in =D 2 / 2; The currents of the first inductor and the second inductor are controlled to be 180 degrees out of phase and operate alternately. Based on the preset target output voltage or the real-time detected duty cycle, adjust the equivalent inductance ratio of the second inductor to the first inductor or control the timing so that the ripple of the two inductor currents cancels each other out after being superimposed at the output terminal.

[0018] In one embodiment, a flying capacitor voltage balancing step is also included: Detect the voltage of the flying capacitor connected between the first power stage and the second power stage; When the detected flying capacitor voltage deviates from the target value, the duty cycle of the pulse width modulation signal is adjusted or the operating timing of the switched capacitor network in the second power stage is adjusted until the flying capacitor voltage recovers to the target value.

[0019] The technical solutions provided by the embodiments of this application may include the following beneficial effects: As can be seen from the above embodiments, this application provides a buck power converter, a packaged device, and a control method for the power converter. The buck power converter includes an input port, an output port, a first half-bridge power stage, a filter multiplexing unit, a second power stage, and a second inductor. The input port receives a DC input voltage, and the output port provides a DC output voltage to the load. The first half-bridge power stage is connected between the input port and a reference ground, and its output terminal is connected to the filter multiplexing unit. The filter multiplexing unit consists of a first inductor and a flying capacitor. The second power stage is connected between the output terminal of the filter multiplexing unit and the second inductor. This application achieves a high buck conversion ratio by using the filter multiplexing unit simultaneously as the output filter network of the first half-bridge power stage and the input filter network of the second power stage. This effectively reduces the number of components, lowers the voltage stress on the switching transistors, and improves the conversion efficiency, making it suitable for high buck ratio power supply scenarios with high voltage input and low voltage high current output.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the description are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the topology of a buck power converter provided in one embodiment of this application.

[0023] Figures 2-5 This is a schematic diagram of a variant topology of a buck power converter provided in one embodiment of this application.

[0024] Figures 6a-6c This is a schematic diagram of the vertical co-sealing structure provided in one embodiment of this application from multiple perspectives.

[0025] Figures 7-9 This is a schematic diagram of ripples provided in one embodiment of this application. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, descriptions of features known in the art may be omitted for clarity and brevity. The modes described in the following exemplary embodiments do not represent all modes consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0027] As described in the background section, with the rapid development of artificial intelligence technology, the demand for computing power in high-performance data centers is growing exponentially. The power consumption of processors, GPUs, and AI accelerators continues to rise, posing unprecedented challenges to the power supply architecture. To reduce transmission losses in the power distribution network, data centers are gradually adopting 48V power buses to replace the traditional 12V bus architecture. However, the processor core voltage has dropped to 1V or even 0.8V, and the voltage conversion ratio from 48V to the load point is as high as 48:1 or even 60:1, placing extremely high demands on DC-DC power converters.

[0028] In existing technologies, traditional half-bridge Buck converters face severe limitations in high buck ratio scenarios: with a theoretical duty cycle of only about 2% when the input is 48V and the output is 1V, such a narrow turn-on pulse places extremely stringent requirements on the minimum pulse width capability of the gate drive circuit, the response speed of the control loop, and the switching speed of the power switches. At the same time, the high-side switches bear the full input voltage, resulting in significant switching losses, while the low-side switches carry almost all the output current, leading to a sharp increase in conduction losses. Furthermore, the inductor current ripple is large under extreme duty cycles, requiring large inductance values ​​for the inductor and large capacitance values ​​for the output filter capacitor, which severely limits the miniaturization and high power density integration of the power module. To address this, the industry has proposed a two-stage or even multi-stage series converter architecture. This architecture uses a front-end stage to pre-step down 48V to the intermediate bus voltage and then convert it to 1V in the back-end stage to distribute the duty cycle pressure of a single stage. However, in this scheme, the current needs to flow through multiple power stages and inductors in sequence. The conduction losses of each stage are superimposed, making it difficult to improve the efficiency under heavy load. In addition, the large-capacity voltage regulator capacitor required for the intermediate bus is bulky and difficult to integrate. At the same time, the increased number of power devices leads to increased control complexity, material costs, and package size.

[0029] In recent years, researchers have proposed hybrid topologies that combine switched capacitor networks with inductor buck networks. These topologies utilize the charge distribution effect of flying capacitors to generate multiple voltage levels, reducing voltage stress on the switching transistors. This allows for the use of power devices with low withstand voltage and low on-resistance. Related research has demonstrated the potential of hybrid topologies in high buck ratio applications. However, existing hybrid topologies still have several shortcomings: most require a large number of switching transistors and driver circuits, resulting in complex topologies and high bill of materials costs; voltage balance control of flying capacitors relies on complex timing management, and the risk of voltage overshoot during startup and transients cannot be ignored; some topologies still rely on large intermediate or output filter capacitors, failing to fundamentally solve the miniaturization problem of passive devices; in particular, existing hybrid topologies generally combine switched capacitor networks and inductor filter networks as independent functional modules in series, failing to fully exploit the functional reuse potential of passive devices across different power levels, resulting in a still relatively large number of devices and limiting further improvements in monolithic or single-package integration.

[0030] It should be noted that the power converter provided in this application is particularly suitable for applications with input voltages of 36V to 60V (typically 48V) and output voltages of 0.8V to 1.2V, such as AI servers, GPUs / xPUs, data center processors, 3D integrated chips, Chiplet packaged systems, and other scenarios requiring high-efficiency power supply near the load. However, those skilled in the art should understand that the technical solution of this application is not limited to the specific voltage ranges mentioned above, but can be applied to any application requiring high step-down ratio power conversion.

[0031] In this application, the term "high-side switch" refers to a switch connected to a high-potential terminal, such as the input port or between an intermediate voltage node and a switching node. The term "low-side switch" refers to a switch connected between a switching node and reference ground. The term "common terminal" refers to the intermediate node when two switches are connected in series. The term "current path" refers to the path through which current flows when a switch is turned on; for a field-effect transistor, the current path is the channel between its source and drain. Please refer to Figure 1 This application provides a buck power converter, including an input port, an output port, a first half-bridge power stage, a filter multiplexing unit, a second power stage, and a second inductor.

[0032] The input port is used to receive DC input voltage V. in The output port provides a DC output voltage V0 to the load. In practical applications, the load is a core computing unit such as a processor, GPU, or AI accelerator chip that requires low-voltage, high-current power. The input port connects to an external 48V bus, and the output port is positioned close to the load, forming a point-of-load (POW) power supply architecture. By placing the power converter as close to the load as possible, parasitic resistance and inductance in the power supply path can be effectively reduced, thereby reducing power distribution losses and improving overall power supply efficiency.

[0033] The first half-bridge power stage includes a first high-side switch S connected in series between the input port and reference ground. H1 and the first low-side switch S L1 First high-side switch S H1 With the first low-side switch S L1 The common node is defined as the first switch node S. W1 SH1 and S L1 Complementary conduction is achieved under the control of the pulse width modulation signal, i.e., S H1 When conducting S L1 Shutdown, S L1 When conducting S H1 When shutting down, a dead time needs to be set between the two to avoid direct short circuits. (via S) H1 and S L1 The alternating switching action chops the DC high voltage received at the input port into a pulse waveform, and the first switching node S... W1 The amplitude is V at the point. in Or a switching waveform approximately equal to V0, which is used as the input to the subsequent filtering and multiplexing unit.

[0034] It should be understood that in this application, the first high-side switch S... H1 and the first low-side switch S L1 Gallium nitride-based high electron mobility transistors are preferred, taking advantage of their low on-resistance under high voltage conditions to reduce power loss in the front-end stage.

[0035] The filter multiplexing unit includes a first inductor L1 and a flying capacitor C. F One end of the first inductor L1 is connected to the first switching node S. W1 Flying capacitor C F The first inductor L1 is connected between its other end and the reference ground. The second power stage is connected between its other end and the output port. The second power stage includes a network of multiple switching transistors and switched capacitors. The second inductor L2 is connected between a preset node within the second power stage and the output port.

[0036] First inductor L1 and flying capacitor C F This constitutes a filter multiplexing unit. The filter multiplexing unit serves simultaneously as the output filter network of the first half-bridge power stage and the input filter network of the second power stage.

[0037] Specifically, when the first half-bridge power stage is operating, the first inductor L1 and the flying capacitor C F Together against S W1 The pulse voltage at the input stage is filtered to obtain a smoother intermediate voltage. This intermediate voltage then serves directly as the input voltage for the second power stage, eliminating the need for an additional independent input filtering network. Through this functional reuse, this application effectively reduces the number of passive components, lowers material costs and package size, while avoiding the size and integration issues associated with traditional two-stage architectures that require large-capacity voltage regulator capacitors on the intermediate bus.

[0038] Furthermore, the voltage conversion ratio of the power converter in this application during steady-state operation satisfies: V o / V in = D² / 2. Where D is the control duty cycle of the switching transistor in the first half-bridge power stage, i.e., the first high-side switching transistor S. H1 The ratio of the on-time to the switching cycle within a switching cycle.

[0039] Understandably, compared to the traditional single-stage Buck converter V o / V in Based on the linear transformation relationship of D, this application achieves a quadratic step-down gain through a super-superposition topology. Specifically, in a typical application scenario with 48V input and 1V output, the duty cycle required by a traditional Buck converter is only about 2%, while the duty cycle required by this application is about 20% (D≈0.204). This significant increase in duty cycle means a substantial increase in the conduction pulse width of the first high-side switch, which greatly relaxes the limitation on the minimum conduction time capability of the gate drive circuit, reduces the design difficulty of the control loop, and allows for further increases in the switching frequency of the switch, which is beneficial for the miniaturization of passive devices. Furthermore, the voltage stress on the switch is effectively reduced, the distribution of conduction loss and switching loss is more balanced, and the overall conversion efficiency is improved.

[0040] Please continue to refer to Figure 1 In some implementations, the second power stage is a subsequent step-down converter unit, whose input side is connected to the other end of the first inductor L1, and whose output side is connected to the output port via the second inductor L2.

[0041] Understandably, the second power stage receives the intermediate voltage output from the filter multiplexing unit, further steps it down, and then transfers energy to the output port through the second inductor L2. The first half-bridge power stage and the second power stage work together during operation; the former undertakes high-voltage switching, while the latter undertakes low-voltage, high-current power conversion. The two are efficiently coupled through the filter multiplexing unit.

[0042] In some implementations, refer to Figure 1 and combined Figure 7 , Figure 8 and Figure 9 The diagram shows the ripple pattern, where the first inductor L1 and the second inductor L2 have a 180° phase difference during operation.

[0043] Specifically, when the first inductor L1 is charging, the second inductor L2 is discharging; conversely, when the first inductor L1 is discharging, the second inductor L2 is charging. The two inductor currents are staggered in time, causing the peak-to-peak value of the superimposed ripple at the output port to be smaller than the peak-to-peak value of a single inductor current ripple. This characteristic is known as the inductor current ripple cancellation / minimization principle.

[0044] Understandably, a reduction in output current ripple means lower output voltage ripple for the same output capacitor value, or the ability to use a smaller output filter capacitor for the same output voltage ripple requirement, thus helping to reduce the overall size of the power supply module. Furthermore, lower output current ripple also helps reduce power supply noise at the load end, improving system stability.

[0045] In some implementations, the inductance ratio L2 / L1 of the second inductor L2 to the first inductor L1 is set based on the duty cycle D to satisfy: L2 / L1 = (D - D² / 2) / (1 - D - D² / 2), which makes the peak-to-peak values ​​of the two inductor currents tend to be equal.

[0046] It should be noted that "approaching equality" here means that the peak-to-peak values ​​of the two inductor currents are basically the same within the allowable error range of engineering practice, not that they are completely equal in a mathematical sense. When the peak-to-peak values ​​of the two inductor currents approach equality and their phase difference is 180°, the superimposed ripple at the output reaches a minimum.

[0047] Specifically, the derivation of the inductor current ripple cancellation is as follows: Under steady-state operating conditions, the first inductor L1 and the second inductor L2 experience different voltage stresses during their respective conduction and turn-off phases. To minimize the output current ripple, the circuit needs to operate in two complementary states, i.e., the currents of L1 and L2 have a 180° phase difference. According to the inductor volt-second balance principle, the peak-to-peak values ​​of the two inductor currents are related to the voltage across their respective inductors and their conduction time. By adjusting the inductance ratio of L1 and L2, the ripple amplitudes of the two inductor currents can be matched. The derivation is as follows: When the peak-to-peak values ​​of L1 and L2 are equal, the following must be satisfied: (V in - V CF - V o ) / L1 = (V CF - V o ) / L2.

[0048] Substitute V CF = D·V in and V o = (D² / 2)·V in And after simplification, the above sensitivity ratio formula can be obtained. When the conversion ratio V CR =V o / V in When L = 1 / 48, D ≈ 20.41%, L2 / L1 ≈ 1 / 4.

[0049] Figure 7 This is a schematic diagram of ripple cancellation when L1 = L2 and the amplitudes of the two ripple paths are perfectly matched. The superimposed output ripple approaches zero. Figure 8 and Figure 9 The superimposed ripple states are shown for ripple mismatches of 25% and 75%, respectively. It can be seen that the greater the ripple mismatch, the greater the superimposed output ripple. Therefore, configuring L2 / L1 to approximate the values ​​calculated by the above formula can achieve a better ripple cancellation effect.

[0050] In some implementations, the duty cycle D ranges from 0.15 to 0.25 to accommodate an input voltage range of 36V to 60V.

[0051] Specifically, when the input voltage varies between 36V and 60V and the output voltage is between 0.8V and 1.2V, according to V o / V in =D² / 2 can be used to calculate the corresponding duty cycle range.

[0052] With V in =48V, V oTaking 1V as an example, D≈0.204, which is within the above range. This duty cycle range ensures that the conduction pulse width of the first high-side switch is moderate, so that the drive is not difficult due to an excessively small duty cycle, nor is the discharge time of the first inductor L1 insufficient due to an excessively large duty cycle.

[0053] In some implementations, the output voltage V o The range is 0.8V to 1.2V. The power converter is used to provide the core power supply voltage for processor or accelerator chips. Currently, the core voltage of mainstream high-performance processors and AI accelerator chips is typically 0.8V or 1V. Using the above output voltage range allows this application to adapt to the power supply needs of the vast majority of processors.

[0054] Please combine Figure 1 In some embodiments, the switched capacitor network includes a first switched capacitor unit C. 21 Second switched capacitor unit C 22 .

[0055] Specifically, the first switched capacitor unit C 21 One end (i.e., one of its plates) is connected to the third switch S. H21 and the fourth switch S L21 The common terminal is connected, and the other end (i.e., its other plate) is connected to the fifth switch S. H22 and the sixth switch S L22 The common terminal is connected. The third switch S... H21 The other end of the current path is connected to the other end of the first inductor L1. The second switched capacitor unit C 22 One end (i.e., one of its plates) is connected to the seventh switch S. H23 and the eighth switch S L23 The common terminal is connected, and the other end (i.e., its other plate) is connected to the ninth switch S. H24 and the tenth switch S L24 The common terminal is connected. The eighth switch S... L23 The other end of the current path is connected to the flying capacitor C. F The first plate.

[0056] It should be understood that, in this embodiment, the first switched capacitor unit C 21 With the third to sixth switching transistors (S) H21 S L21 S H22 S L22 This constitutes the first set of topology units in the second power stage, and the second switched capacitor unit C 22 With the seventh to tenth switching transistors (S) H23 S L23 S H24 S L24This constitutes the second set of topology units in the second power stage. The two sets of units are cascaded, with the third switch S... H21 The eighth switch S is connected to the other end of the first inductor L1 to receive the intermediate voltage. L23 With flying capacitor C F The positive plate is connected to achieve electrical coupling. The connections between the remaining switching transistors are defined in the claims and will not be repeated here.

[0057] This application forms multiple voltage distribution nodes within the second power stage by setting up a switched capacitor network with the aforementioned specific connection relationship. The voltage stress on each switching transistor is effectively clamped to a fraction of the intermediate voltage, thereby enabling the use of switching devices with low withstand voltage and low on-resistance, and reducing conduction losses.

[0058] In some implementations, refer to Figures 2 to 5 The circuit topology proposed in this application has several variations. Figures 2 to 5 Four topology variations based on the same inventive concept are shown, with differences in the specific connection methods of the switched capacitor networks in the first half-bridge power stage, the filter multiplexing unit, and the second power stage, but all including a filter multiplexing unit (i.e., the first inductor L1 and the flying capacitor C). F The core architecture consists of a multiplexed structure and a switched capacitor network for voltage distribution.

[0059] Specifically, Figure 2 In the variant shown, the first half-bridge power stage includes two half-bridge units, the filter multiplexing unit includes a corresponding combination of inductors and flying capacitors, and the switched capacitor network is symmetrically connected. Figure 3 In the variant shown, the flying capacitor connection position in the filter multiplexing unit is different from... Figure 1 The number of capacitors and the connection method of the switching transistors in the switched capacitor network are adjusted accordingly. Figure 4 and Figure 5 The variations shown differ in the number of first half-bridge units and the connection topology of the inductors in the filter multiplexing units. All of these variations fall within the protection scope of this application. Those skilled in the art should understand that the above variations are merely illustrative, and other equivalent modifications based on the core architecture of this application do not depart from the spirit and scope of this application.

[0060] In some implementations, the first switched capacitor unit C 21 Second switched capacitor unit C 22 A uniform voltage distribution node is formed within the second power stage to reduce the voltage stress on each switch in the second power stage.

[0061] Specifically, through the flying capacitor C F First switched capacitor unit C 21Second switched capacitor unit C 22 Due to the charge distribution effect, the voltages of multiple nodes within the second power stage are clamped to the input voltage V. in Several proportional values. For example, C F The voltage across the terminals is D·V in C 21 The voltage across C is allocated to an intermediate level according to the switching timing. This ensures that the voltage difference across either switch in the second power stage is lower than the input voltage V when either switch is turned on. in Even lower than V in / 2 or V in / 3, the specific voltage stress depends on the duty cycle D and the charge distribution coefficient of the capacitor network. Lower voltage stress means that power switches with lower on-resistance can be used, thereby reducing conduction losses and improving conversion efficiency.

[0062] In some implementations, the first high-side switch S H1 and the first low-side switch S L1 All are gallium nitride-based high electron mobility transistors.

[0063] Understandably, gallium nitride (GaN)-based high electron mobility transistors possess excellent characteristics such as wide bandgap, high critical electric field, and high carrier mobility. At the same voltage rating, GaN devices have significantly lower on-resistance than silicon-based devices, and their gate charge and output capacitance are smaller, which helps reduce switching losses.

[0064] In this application, the first high-side switch S H1 and the first low-side switch S L1 Direct connection to the 48V input port requires withstanding high voltage stress. Using GaN devices allows for extremely low on-resistance while maintaining high voltage withstand capability, significantly reducing power loss in the front-end. For the switches in the second power stage, since the voltage stress they experience is reduced to a lower level through the switched capacitor network, low-voltage silicon-based devices can be used to achieve a balance between cost and performance. This heterogeneous integration approach addresses both high efficiency and low cost requirements.

[0065] Please combine Figure 1 In some implementations, the buck power converter also includes a flying capacitor voltage balancing control circuit. The flying capacitor voltage balancing control circuit is used to sample the flying capacitor C. F The voltage across the capacitor C F The sampled voltage and the target value D·V in When the deviation exceeds a preset threshold, the flying capacitor voltage is restored to the target value D·V by adjusting the duty cycle D or the phase distribution within the second power stage. in .

[0066] Specifically, the flying capacitor C F It is the key energy node connecting the first half-bridge power stage and the second power stage, and its ideal steady-state voltage should be D·V. in In practical circuits, due to factors such as inconsistent parasitic parameters of the switching transistor, dead time deviation, load transient changes, drive delay, and uncertainty of the initial voltage of the flying capacitor, C F The voltage may deviate from the target value. If C F Excessive or insufficient voltage can lead to changes in voltage stress on the switching transistors in the second power stage, decreased output voltage regulation accuracy, and inductor current ripple imbalance. In severe cases, it may even cause overvoltage or overcurrent in the switching transistors.

[0067] To address the aforementioned issues, this application incorporates a flying capacitor voltage balancing control circuit. This control circuit detects C in real time using a resistor divider network or a capacitively coupled sampling method. F The voltage across the terminals, and the target value D·V in Compare them.

[0068] When the deviation exceeds a preset threshold (e.g., ±5% of the target value), the control circuit adjusts the duty cycle D to adjust the input to C. F The amount of charge changes until C F Voltage recovery; or, by adjusting the operating timing of the switched capacitor network within the second power stage, so that C F The discharge or charging rate changes, thereby achieving voltage balance. Through the above feedback control mechanism, this application can effectively maintain C. F Voltage stability ensures that the power converter can operate reliably under various operating conditions.

[0069] In some implementations, the voltage balancing control circuit also includes a pre-charge function. During the power converter startup process, the flying capacitor C is first charged via the pre-charge path. F Pre-charge the transistor to near the target value before activating the pulse width modulation switch, thus avoiding the impact of C during startup. F Protects the switching transistor from damage caused by large current surges and voltage overshoots resulting from zero or uncertain initial voltage.

[0070] In some implementations, the buck power converter further includes an adaptive mode switching control circuit. The adaptive mode switching control circuit controls the operating phase state of the first inductor L1 and the second inductor L2 based on the load current detection signal.

[0071] Specifically, when the load is under heavy load steady state, the two-phase inductors are controlled to operate in a complementary interleaved state to reduce output ripple. In this operating mode, the currents of L1 and L2 are 180° out of phase, resulting in minimal output ripple, which helps reduce the capacitance requirement of the output filter capacitor and reduce output voltage ripple.

[0072] In one embodiment, when the load experiences a transient change, the two-phase inductors are controlled to operate in phase to improve dynamic response speed. In phase operation mode, L1 and L2 charge or discharge simultaneously, reducing the equivalent inductance value to half that of a single-channel inductance value. This significantly increases the rate of change of inductor current, enabling faster energy delivery to or release from the load, reducing the undershoot or overshoot of the output voltage, and improving transient response performance.

[0073] Understandably, both operating modes have their advantages: in complementary interleaved mode, the output ripple is small but the dynamic response speed is relatively slow, while in in-phase mode, the dynamic response is fast but the output ripple is large. This application uses an adaptive mode-switching control circuit to determine the load operating state in real time based on the load current detection signal. When the load current is detected to be basically stable or changing slowly, it is judged as steady state; when the load current change rate is detected to exceed a preset threshold, it is judged as transient change. The circuit automatically switches between the two modes, thus enabling the power converter to balance steady-state efficiency and transient response performance under all operating conditions.

[0074] Furthermore, based on the capacitor charge balance and inductor volt-second balance equations, the steady-state conversion relationship of the power converter of this application under different duty cycles can be derived. When the duty cycle D is greater than or less than 50%, the circuit experiences different operating states within one switching cycle, but the final conversion ratio conclusion remains consistent.

[0075] Specifically, when D < 50%, there are four operating states within one switching cycle, and the voltage stress of the two inductors in each state is shown in Table 1 below.

[0076] Table 1 The four states are, in order: State I, State II, State III, and State IV. By applying the volt-second balance principle to the inductor voltage in each state, the flying capacitor voltage V can be obtained. CF = 2V o / D, and thus V is derived. o / V in = D² / 2.

[0077] Specifically, when D > 50%, there are still four operating states. The expression for the inductor voltage stress in each state is different from that when D < 50%, but the conclusion obtained after applying the volt-second balance is completely consistent: V CF = 2V o / D,V o / V in = D² / 2.

[0078] It is understandable that the above derivation shows that the secondary buck characteristic of the power converter of this application has a wide duty cycle adaptability. Whether the duty cycle is less than or greater than 50%, it can maintain a stable square buck conversion ratio, thus ensuring the universality of the topology of this application.

[0079] In some implementations, the power converter operates in two modes depending on the load conditions: a two-phase inductor in-phase operating mode and a two-phase inductor complementary interleaved operating mode. To improve the circuit's dynamic response to rapid load changes, in addition to increasing the output capacitance or improving the loop bandwidth, the circuit can be switched to the two-phase inductor in-phase operating mode. In this mode, both inductors charge or discharge simultaneously, reducing the equivalent inductance value and increasing the rate of change of inductor current. This allows for a faster response to load changes, suppressing output voltage drops or overshoots, and improving dynamic response performance.

[0080] Understandably, the output current ripple increases relatively in in-phase mode, but the resulting improvement in dynamic response speed is valuable for loads such as processors that require rapid, high-current switching. This configuration allows the power converter to flexibly switch between low ripple and high dynamic response based on actual operating conditions, balancing steady-state efficiency and transient performance.

[0081] Please refer to Figure 6a , Figure 6b and Figure 6c This application also provides a heterogeneous integrated package device for implementing the power converter as described in any of the above embodiments. The package device includes a package substrate (sub), a gallium nitride power transistor die (DIE), a silicon-based control die, and a passive device layer.

[0082] The packaging substrate has vertically oriented power supply vias. A gallium nitride power transistor die is disposed in a first region of the packaging substrate, such as the left side region or the lower layer region of the packaging substrate, and integrates at least a first high-side switching transistor S. H1 and the first low-side switch S L1 The silicon-based control chip is disposed in the second region of the packaging substrate, such as the right side region or the upper region of the packaging substrate, integrating the switching transistor drive logic and pulse width modulation control circuit of the second power stage. A passive component layer is embedded or mounted inside the packaging substrate, and includes at least a first inductor L1, a second inductor L2, and a flying capacitor C. F and output filter capacitor.

[0083] The packaging substrate electrically interconnects the gallium nitride power transistor chip and the silicon-based control chip through an intermediate bus voltage node, forming a vertical power supply path with high voltage input from the bottom and low voltage output from the top of the packaging substrate.

[0084] Understandably, compared to traditional horizontal power supply schemes, the vertical power supply path of this application significantly shortens the physical distance of current flow from the power converter to the load, reduces parasitic resistance and inductance on the power supply path, and lowers power distribution losses. Simultaneously, embedding passive components within the packaging substrate effectively utilizes vertical space, improving overall power density. The heterogeneous integration of the front-end high-voltage GaN device and the back-end low-voltage Si control chip fully leverages the dual advantages of GaN devices' high voltage withstand capability and low on-resistance, as well as Si devices' high integration and low cost, providing a mass-producible technical solution for high-density 48V-PoL power supply.

[0085] In some implementations, gallium nitride power transistor chips and silicon-based control chips are stacked vertically, with the passive device layer located in the buried region of the package substrate. This vertically stacked chip layout further reduces the footprint of the packaged device, allowing the entire power conversion module to be positioned close to the processor or accelerator chip, or even directly integrated beneath the processor substrate. The buried passive device layer in the middle of the substrate shortens the interconnection distance between the passive devices and the switching transistors, reducing parasitic parameters. Furthermore, the inductors and capacitors embedded within the substrate can achieve high device density and consistency through advanced packaging processes.

[0086] In some implementations, a segmented gate drive circuit is integrated within the silicon-based control chip.

[0087] The segmented gate drive circuit is used to adjust the magnitude of the drive current in segments during the switching process and introduces a handshake signal in the drive path to prevent the high-side and low-side switches from turning on simultaneously. This application adopts a segmented drive strategy, using different drive intensities at different stages of the switching process and employing a larger drive current to quickly charge and discharge the gate charge, thereby suppressing voltage overshoot.

[0088] Secondly, a handshake signal is introduced into the drive circuit to ensure that the low-side switch can only be turned on after the high-side switch is completely turned off, and vice versa, thus fundamentally eliminating the risk of shoot-through short circuit caused by the simultaneous conduction of the upper and lower switches.

[0089] Furthermore, the drive circuit features an adjustable dead-time function. Based on the actual drive loop impedance and switching characteristics, the dead time between the high-side switch turn-off and the low-side switch turn-on is adjusted to optimize the body diode's conduction time. When the dead time is too long, the body diode's conduction time increases, leading to higher conduction losses; conversely, when the dead time is too short, the switch may not be fully turned off before being turned on by the other diode, resulting in significant switching losses or even device damage. Through this adjustable dead-time function, this application enables the power converter to maintain high conversion efficiency across the entire load range.

[0090] This application also provides a control method for a buck power converter. The power converter includes a first power stage and a second power stage cascaded through a filter multiplexing unit, and a first inductor L1 and a second inductor L2 connected in parallel to transfer energy. The control method includes the following steps S100 to S300.

[0091] Step S100: Generate a pulse width modulation signal with a duty cycle of D to control the high-side switch S in the first power stage. H1 With low-side switching transistor S L1 The complementary conduction ensures that the ratio of the output voltage to the input voltage of the power converter satisfies V o / V in = D² / 2.

[0092] Specifically, the pulse width modulation signal is generated by a digital pulse width modulator within the silicon-based control chip. This signal is then applied to the S... after level conversion and driving circuitry. H1 and S L1 The gates of the two circuits are alternately switched on and off. The output voltage V can be adjusted by regulating the duty cycle D of the PWM signal. o The magnitude of the output voltage V. o The voltage is sampled by the feedback loop and compared with the reference voltage. The error is processed by the compensation network and the duty cycle D is adjusted to form a closed-loop voltage regulation control.

[0093] Step S200: Control the current of the first inductor L1 and the second inductor L2 to work alternately with a phase difference of 180 degrees.

[0094] Specifically, the control chip generates two drive signals with a 180° phase difference, which control the switching transistors associated with L1 and L2 respectively. At higher switching frequencies, the interleaved control causes the two inductor currents to alternately provide energy to the output, resulting in an output equivalent current ripple frequency that is twice that of a single-channel switching frequency, and a significant reduction in ripple amplitude.

[0095] Step S300: According to the preset target output voltage or the real-time detected duty cycle, adjust the equivalent inductance ratio of the second inductor L2 and the first inductor L1 or control the timing so that the ripple of the two inductor currents cancels each other out after being superimposed at the output.

[0096] Specifically, in actual mass production, the inductance values ​​of L1 and L2 may have manufacturing tolerances. The control method in this application can, based on the real-time detected duty cycle D, adjust the control timing of the switching transistor within the second power stage to effectively change the ripple amplitude ratio of the two inductor currents, thereby minimizing the superimposed ripple at the output. This adjustment process can be fixed through tuning during the chip factory testing phase, or it can be adjusted in real-time using an adaptive algorithm when the load changes.

[0097] In some implementations, the control method further includes a flyover capacitor voltage balancing step.

[0098] Step S400: Detect the flying capacitor C connected between the first power stage and the second power stage. F The voltage.

[0099] Step S500: When the detected flying capacitor voltage is different from the target value D·V in When the deviation exceeds the preset threshold, adjust the duty cycle D of the pulse width modulation signal or adjust the operating timing of the switching capacitor network in the second power stage until the flying capacitor voltage recovers to the target value D·Vin.

[0100] Specifically, the flying capacitor C F The voltage is sampled and quantized via an analog-to-digital converter. The digital compensator within the control chip compares the sampled value with the D·V value. in The comparison is performed, and the deviation is calculated. When the deviation exceeds the preset dead zone range, the compensator outputs an adjustment amount, changing the PWM duty cycle or adjusting the conduction timing of the switching transistor in the second power stage, so that C... F Charge or discharge until its voltage returns to near the target value.

[0101] During startup, a pre-charging step for the flying capacitor can be performed first: before the switching transistor begins its switching action, the C capacitor is pre-charged by the pre-charging circuit. F Charge to near D·V in The voltage value is then gradually increased, and the duty cycle D is gradually increased to make the output voltage V... o The current rises smoothly to the target value while limiting inrush current during startup. The soft-start process effectively avoids the large current surge during startup, protecting the switching transistors and load from damage.

[0102] In some implementations, the control method further includes a dead time adaptive adjustment step: detecting the rate of change of the switching node voltage of the switching transistor in the first power stage or the second power stage, and adaptively adjusting the dead time between the high-side switching transistor being turned off and the low-side switching transistor being turned on based on the rate of change of the voltage, so as to minimize the conduction time of the body diode of the switching transistor.

[0103] Specifically, when a rapid drop in the switching node voltage is detected, it indicates a light load or a high input voltage, and the dead time can be appropriately shortened to reduce the conduction loss of the body diode. When a slow drop in the switching node voltage is detected, the dead time needs to be appropriately extended to ensure safe commutation of the switching transistor. Through adaptive dead time adjustment, this application can maintain optimal efficiency under different load conditions and process angles.

[0104] It is understood that the above control steps can be executed in parallel or in a preset scheduling order, and this application does not impose any restrictions on this.

[0105] In summary, this application achieves a voltage-to-square ratio step-down conversion through a unique filter multiplexing unit architecture, achieves ripple cancellation through dual-inductor interleaving control and inductance ratio optimization, and achieves stable and efficient operation under all operating conditions through flying capacitor voltage balance control and adaptive mode switching. Furthermore, it transforms the above circuit scheme into a mass-producible high-power-density product through heterogeneous integrated packaging devices. The technical solution of this application provides a comprehensive solution for high-step-down ratio, high-current power supply scenarios such as AI servers and data centers.

[0106] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0107] In the above detailed description, reference has been made to the accompanying drawings, which illustrate specific aspects of how this disclosure can be practiced. In this regard, terms indicating direction or positional relationship, such as “thickness,” “upper,” “lower,” “top,” “bottom,” “inner,” and “outer,” can be used with reference to the orientation of the described figures. Since components of the described device can be positioned in several different orientations, these directional terms are for illustrative purposes and not for limitation. It should be understood that other aspects can be utilized and structural or logical changes can be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0108] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0109] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.

[0110] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A step-down power converter, characterized in that, include: The input port is used to receive DC input voltage. The output port is used to provide DC output voltage to the load; The first half-bridge power stage includes a first high-side switch and a first low-side switch connected in series between the input port and the reference ground. The common node of the first high-side switch and the first low-side switch is defined as the first switching node. A filter multiplexing unit includes a first inductor and a flying capacitor, with one end of the first inductor connected to the first switching node; The flying capacitor is connected between the other end of the first inductor and the reference ground; The second power stage is connected between the other end of the first inductor and the output port, and the second power stage includes a network of multiple switching transistors and switched capacitors; as well as The second inductor is connected between a preset node within the second power stage and the output port; The filter multiplexing unit serves simultaneously as the output filter network of the first half-bridge power stage and the input filter network of the second power stage, and the steady-state voltage conversion ratio of the power converter satisfies: V0 / V in =D 2 / 2; Where D is the control duty cycle of the switching transistor in the first half-bridge power stage, and V in V is the input voltage, and V0 is the output voltage.

2. The power converter according to claim 1, characterized in that, The second power stage is a subsequent step-down converter unit, whose input side is connected to the other end of the first inductor, and whose output side is connected to the output port via the second inductor.

3. The power converter according to claim 1, characterized in that, The first inductor and the second inductor have a 180° phase difference during operation. When the current ripple of the two inductors is superimposed at the output port, the peak-to-peak value of the two current ripples is smaller than that of a single inductor current ripple.

4. The power converter according to claim 3, characterized in that, The inductance ratio L2 / L1 of the second inductor and the first inductor is set based on the duty cycle to satisfy L2 / L1 = (DD) / L1 / L2. 2 / 2) / (1-DD 2 / 2), so that the peak values ​​of the two inductor currents are equal.

5. The power converter according to claim 1, characterized in that, The duty cycle ranges from 0.15 to 0.25 to accommodate an input voltage range of 36V to 60V.

6. The power converter according to claim 1, characterized in that, The output voltage V0 ranges from 0.8V to 1.2V, and the power converter is used to provide core power supply voltage for processor or accelerator chips.

7. The power converter according to claim 1, characterized in that, The switched capacitor network includes: The first switched capacitor unit has its first end connected to the common terminal of the third and fourth switched transistors, and its second end connected to the common terminal of the fifth and sixth switched transistors; the other end of the current path of the third switched transistor is connected to the other end of the first inductor. The second switched capacitor unit has its first end connected to the common terminal of the seventh and eighth switched transistors, and its second end connected to the common terminal of the ninth and tenth switched transistors, respectively; the other end of the current path of the eighth switched transistor is connected to the first plate of the flying capacitor.

8. The power converter according to claim 7, characterized in that, The first switched capacitor unit and the second switched capacitor unit form a uniform voltage distribution node within the second power stage to reduce the voltage stress on each switch in the second power stage.

9. The power converter according to claim 1, characterized in that, Both the first high-side switch and the first low-side switch are gallium nitride-based high electron mobility transistors.

10. The power converter according to claim 1, characterized in that, It also includes a flying capacitor voltage balancing control circuit, which is used to sample the voltage across the flying capacitor. When the deviation between the sampled voltage of the flying capacitor and the target value exceeds a preset threshold, the flying capacitor voltage is restored to the target value by adjusting the duty cycle or the phase distribution within the second power stage.

11. The power converter according to claim 1, characterized in that, It also includes an adaptive mode switching control circuit, which controls the operating phase state of the first inductor and the second inductor based on the load current detection signal. When the load is under heavy load steady state, the two-phase inductors are controlled to operate in a complementary interleaved state to reduce output ripple; and When the load is in a transient state, the two-phase inductors are controlled to operate in the same phase to improve the dynamic response speed.

12. A packaged device for implementing the power converter as claimed in any one of claims 1 to 11, characterized in that, include: The packaging substrate has vertical power supply vias; A gallium nitride power transistor die is disposed in a first region of the packaging substrate, and at least the first high-side switch and the first low-side switch are integrated therein. A silicon-based control chip is disposed in the second region of the packaging substrate, integrating the switching transistor drive logic and pulse width modulation control circuit of the second power stage; The passive component layer is embedded or mounted inside the packaging substrate and includes at least the first inductor, the second inductor, the flying capacitor, and the output filter capacitor. The packaging substrate electrically interconnects the gallium nitride power transistor chip and the silicon-based control chip through an intermediate bus voltage node, forming a vertical power supply path with high voltage input from the bottom and low voltage output from the top of the packaging substrate.

13. The packaged device according to claim 12, characterized in that, The gallium nitride power transistor die and the silicon-based control die are stacked vertically, and the passive device layer is located in the middle buried region of the packaging substrate.

14. The packaged device according to claim 12, characterized in that, The silicon-based control chip integrates a segmented gate drive circuit, which is used to adjust the magnitude of the drive current in segments during the switching process and introduce a handshake signal in the drive path to prevent the high-side and low-side switching transistors from being turned on simultaneously.

15. A control method for a buck power converter, the power converter comprising a first power stage and a second power stage cascaded through a filter multiplexing unit, and a first inductor and a second inductor connected in parallel for energy transmission, characterized in that, The control method includes: A pulse width modulation signal with a duty cycle of D is generated to control the complementary conduction of the high-side and low-side switches in the first power stage, so that the ratio of the output voltage to the input voltage of the power converter satisfies V0 / V0. in =D 2 / 2; The currents of the first inductor and the second inductor are controlled to be 180 degrees out of phase and operate alternately. Based on the preset target output voltage or the real-time detected duty cycle, adjust the equivalent inductance ratio of the second inductor to the first inductor or control the timing so that the ripple of the two inductor currents cancels each other out after being superimposed at the output.

16. The control method according to claim 15, characterized in that, It also includes a flying capacitor voltage balancing step: Detect the voltage of the flying capacitor connected between the first power stage and the second power stage; When the detected flying capacitor voltage deviates from the target value, the duty cycle of the pulse width modulation signal is adjusted or the operating timing of the switched capacitor network in the second power stage is adjusted until the flying capacitor voltage recovers to the target value.

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