Balancing bridge circuit and control method thereof, and inverter system

Abstract

The application discloses a balanced bridge circuit, a control method thereof and an inverter system. The balanced bridge circuit comprises: voltage division capacitors and a balanced bridge group. The voltage division capacitors are connected in series between the positive terminal and the negative terminal of an input power supply. The connection points of two adjacent voltage division capacitors are voltage division nodes. The voltage division capacitors on the two sides of the voltage division nodes are upper voltage division capacitors and lower voltage division capacitors, respectively. The balanced bridge group comprises at least two balanced bridges. Each balanced bridge comprises an upper bridge arm, a lower bridge arm and an inductive energy storage arm. The upper bridge arm is used for charging and discharging the upper voltage division capacitors through the inductive energy storage arm. The lower bridge arm is used for charging and discharging the lower voltage division capacitors through the inductive energy storage arm. The inductive energy storage arm is used for storing and releasing energy. The inductive currents of the balanced bridges in the balanced bridge group are out of phase. The application can suppress the bus high-frequency current ripple.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and in particular to a balanced bridge circuit and its control method, and an inverter system. Background Technology

[0002] In high-voltage inverter scenarios, the power supply voltage is typically high, such as in photovoltaic power generation, battery energy storage, or other power generation methods. However, converters generally have lower voltage withstand capabilities, requiring voltage division of the power supply before further use.

[0003] Figure 1 This is a circuit diagram of an existing voltage divider for a power supply. For example... Figure 1 As shown, capacitors C01 and C02 are used to divide the input power supply by half. Capacitors C01 and C02 are the buses of two loads, respectively. The loads may be isolated DC / DC converters, isolated DC / AC converters, non-isolated DC / DC converters, or non-isolated DC / AC converters. Among them, for loads such as DC / AC converters that vary with the power frequency (e.g., 50Hz), capacitors C01 and C02 will usually experience half-bus power frequency fluctuations due to the fluctuations in the power frequency.

[0004] Existing technology uses a balanced bridge for half-bus clamping control to make the voltage Vc01 of capacitor C01 equal to the voltage Vc02 of capacitor C02, i.e., Vc01=Vc02. However, the high-frequency switching of the switching devices (switching transistors Q01 and Q02) in the balanced bridge generates high-frequency current ripple, which is then transmitted to the buses of the two loads. Summary of the Invention

[0005] This invention provides a balanced bridge circuit and its control method, as well as an inverter system, to suppress high-frequency current ripple on the bus.

[0006] According to one aspect of the present invention, a balanced bridge circuit is provided, comprising: The voltage divider capacitor is connected in series between the positive and negative terminals of the input power supply. The connection point of two adjacent voltage divider capacitors is a voltage divider node. The voltage divider capacitors located on both sides of the voltage divider node are the upper voltage divider capacitor and the lower voltage divider capacitor, respectively. A balanced bridge group, comprising at least two balanced bridges; each balanced bridge includes an upper bridge arm, a lower bridge arm, and an inductor energy storage arm. The upper bridge arm is used to charge and discharge the upper voltage divider capacitor through the inductor energy storage arm, and the lower bridge arm is used to charge and discharge the lower voltage divider capacitor through the inductor energy storage arm. The inductor energy storage arm is used to store and release energy. The inductor currents of each balanced bridge in the balanced bridge group are output in out-of-phase.

[0007] Optionally, the number of balanced bridges in a balanced bridge group is M, and the phase difference of the inductor current of each balanced bridge is 360° / M; wherein, M≥2.

[0008] Optionally, the number of voltage dividing capacitors is two, namely a first voltage dividing capacitor and a second voltage dividing capacitor; In the balanced bridge, the first end of the upper bridge arm, the first end of the lower bridge arm, and the first end of the inductive energy storage arm are electrically connected. The second end of the upper bridge arm is the upper bridge arm connection end of the balanced bridge. The second end of the lower bridge arm is the lower bridge arm connection end of the balanced bridge. The second end of the inductive energy storage arm is the inductive connection end of the balanced bridge. In this configuration, the upper bridge arm connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the positive terminal of the input power supply, the lower bridge arm connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the negative terminal of the input power supply, and the inductor connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the voltage divider node.

[0009] Optionally, the balanced bridge includes: a first switching transistor, a second switching transistor, and an inductor; Wherein, the first end of the first switch transistor serves as the first end of the upper bridge arm, and the second end of the first switch transistor serves as the second end of the upper bridge arm; the first end of the second switch transistor serves as the first end of the lower bridge arm, and the second end of the second switch transistor serves as the second end of the lower bridge arm; the first end of the inductor serves as the first end of the inductor energy storage arm, and the second end of the inductor serves as the second end of the inductor energy storage arm.

[0010] Optionally, the balanced bridge circuit further includes: a control module and a drive module; the drive module is connected between the control module and the control terminal of the balanced bridge. The control module generates PWM signals required for each balanced bridge based on the collected voltages of each voltage divider capacitor and the inductor current of each balanced bridge; the drive module drives the switching transistors in each balanced bridge according to the PWM signals.

[0011] Optionally, the control module includes: The voltage outer loop control unit is connected to the voltage of each voltage divider capacitor in the balance bridge group. The voltage outer loop control unit calculates the voltage difference between the voltage of the upper voltage divider capacitor and the voltage of the lower voltage divider capacitor, and performs PI regulation on the voltage difference to obtain a current reference value. At least two current inner loop control units, each corresponding to one of the at least two balanced bridges, are connected to the current reference value and the inductor current of the balanced bridge corresponding to the current inner loop control unit; the current inner loop control unit calculates the difference between the current reference value and the inductor current to obtain the current difference, and performs PI regulation on the current difference to obtain the PWM reference value; At least two PWM signal generation units, each corresponding to one of the at least two balanced bridges, are provided. Each PWM signal generation unit is connected to a corresponding PWM reference value and a carrier signal. The PWM signal generation unit generates a PWM signal based on the PWM reference value and the carrier signal.

[0012] Optionally, the phase difference of the carrier signals corresponding to each of the PWM signal generation units is 360° / M; where M≥2.

[0013] Optionally, the PWM signal generation unit includes: a divider, a comparator, and an inverter; The first input terminal of the divider is connected to the PWM reference value, and the second input terminal of the divider is connected to the sum of the voltages of the upper voltage divider capacitor and the lower voltage divider capacitor. The divider divides the PWM reference value by the sum of the voltages to obtain the carrier comparison value. The first input terminal of the comparator is connected to the carrier comparison value, and the second input terminal of the comparator is connected to the carrier signal. The comparator compares the carrier comparison value and the carrier signal to obtain the upper arm control signal. The input terminal of the inverter is connected to the upper bridge arm control signal, and the inverter inverts the upper bridge arm control signal to obtain the lower bridge arm control signal; wherein, the upper bridge arm control signal and the lower bridge arm control signal constitute the PWM signal output by the PWM signal generation unit.

[0014] According to another aspect of the present invention, a control method for a balanced bridge circuit is provided, applicable to the balanced bridge circuit provided in any embodiment of the present invention, the control method comprising: S1: Collect the voltage of each of the voltage divider capacitors and the inductor current of each of the balance bridges; S2: For one of the balanced bridge groups, based on the voltage of the upper voltage divider capacitor, the voltage of the lower voltage divider capacitor, and the inductor current of each balanced bridge, a PWM signal is generated to control each balanced bridge so that the inductor current of each balanced bridge is output out of phase.

[0015] According to another aspect of the present invention, an inverter system is provided, comprising: an input power supply, a balanced bridge circuit as described in any embodiment of the present invention, and at least two converters, wherein the voltage divider capacitor in the balanced bridge circuit serves as the DC bus capacitor of the converter.

[0016] The balanced bridge circuit provided in this embodiment of the invention includes a balanced bridge group for balancing voltage divider nodes. The balanced bridge group includes at least two balanced bridges with out-of-phase output. On one hand, by setting at least two balanced bridges within a balanced bridge group, compared to setting only one balanced bridge, an additional inductor current is used for voltage balancing, thereby reducing the peak-to-peak value of the inductor current in each balanced bridge and improving the balancing capability of the voltage divider nodes. On the other hand, for balanced bridges, the high-frequency switching of the upper and lower bridge arms causes high-frequency current ripple in the inductor current. This embodiment of the invention provides at least two balanced bridges with out-of-phase output in a balanced bridge group, so that the high-frequency current ripple in the inductor current of each balanced bridge cancels each other out, significantly reducing the high-frequency current ripple for the external circuitry of the balanced bridge group (i.e., the upper and lower voltage divider capacitors).

[0017] Furthermore, the voltage divider capacitor typically consists of two parts: an aluminum capacitor and a film capacitor. The aluminum capacitor provides low-frequency (e.g., 50Hz) energy support, while the film capacitor absorbs the switching ripple from the load switch and the balancing bridge switch. On one hand, embodiments of the present invention balance the voltage divider capacitors by setting a balancing bridge group, ensuring equal voltage across all capacitors and reducing the capacitance of the aluminum capacitor. On the other hand, embodiments of the present invention, by setting the balancing bridge group to include at least two balancing bridges with out-of-phase outputs, can suppress high-frequency current ripple caused by the high-frequency switching of the balancing bridge without increasing the capacitance of the film capacitor.

[0018] In summary, the embodiments of the present invention can achieve at least the following beneficial effects: Firstly, it improves the voltage balancing capability of the voltage divider node and enhances the ability to drive unbalanced loads, thereby reducing the number of aluminum capacitors. Secondly, the reduction of high-frequency ripple in the circuit can reduce the number of film capacitors. Thirdly, the reduced inductance current in each balanced bridge circuit helps to reduce losses and increase frequency.

[0019] Therefore, the embodiments of the present invention are advantageous for achieving long lifespan, lightweight, low cost, high performance and low EMC.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit diagram of an existing power supply voltage divider; Figure 2 A circuit diagram of a balanced bridge circuit provided in an embodiment of the present invention; Figure 3 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention; Figure 4 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention; Figure 5 A comparative waveform diagram of the inductor current in a balanced bridge circuit provided in an embodiment of the present invention and the inductor current in related technologies; Figure 6 for Figure 5 Enlarged schematic diagram of time intervals 1 to 2; Figure 7 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention; Figure 8 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention; Figure 9 A schematic diagram of a control module provided in an embodiment of the present invention; Figure 10 A PWM signal and current waveform diagram of a balanced bridge circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of an inverter system provided in an embodiment of the present invention; Figure 12 This is a flowchart of a control method for a balanced bridge circuit provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 2 A circuit diagram of a balanced bridge circuit provided in an embodiment of the present invention. See also... Figure 2 The balanced bridge circuit includes voltage-dividing capacitors used to divide the input power supply. For example, the balanced bridge circuit includes a first voltage-dividing capacitor C1 and a second voltage-dividing capacitor C2. The connection point of two adjacent voltage-dividing capacitors is a voltage-dividing node O1. The voltage-dividing capacitors located on either side of the voltage-dividing node are the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, respectively. For example, the first voltage-dividing capacitor C1 is the upper voltage-dividing capacitor, and the second voltage-dividing capacitor C2 is the lower voltage-dividing capacitor.

[0026] The balanced bridge circuit also includes a balanced bridge group Z1, which includes at least two balanced bridges. For example, the balanced bridge group Z1 includes balanced bridges Z11, ..., Z1M. Each balanced bridge includes an upper bridge arm B1, a lower bridge arm B2, and an inductor energy storage arm B3. The upper bridge arm B1 is used to charge and discharge the upper voltage divider capacitor through the inductor energy storage arm B3. The lower bridge arm B2 is used to charge and discharge the lower voltage divider capacitor through the inductor energy storage arm B3. The inductor energy storage arm B3 is used to store and release energy.

[0027] In this setup, the number of inductor energy storage arms is equal to the number of balancing bridges. For example, the number of inductor energy storage arms in the balancing bridge group is M. Correspondingly, the inductor currents of the M inductor energy storage arms are iL1, iL2, ..., iLM. The inductor currents (i.e., iL1, iL2, ..., iLM) of each balancing bridge in a balancing bridge group are output in out-of-phase.

[0028] Specifically, on the one hand, by setting at least two balanced bridges in the balanced bridge group, compared with setting only one balanced bridge, at least one more inductor current is used for voltage balancing, thereby reducing the peak-to-peak value of the inductor current of each balanced bridge and improving the balancing capability of the voltage divider node. On the other hand, by controlling the phase-shifted conduction of each balanced bridge circuit in the balanced bridge group, the phase-shifted output of the inductor current of each balanced bridge circuit can be controlled. For the balanced bridge, the high-frequency switching of the upper and lower bridge arms causes high-frequency current ripple in the inductor current of the balanced bridge. In this embodiment of the invention, at least two balanced bridges with phase-shifted output are set in the balanced bridge group, so that the high-frequency current ripple in the inductor current of each balanced bridge cancels each other out, and the high-frequency current ripple is significantly reduced for the external circuit of the balanced bridge group (i.e., the upper voltage divider capacitor and the lower voltage divider capacitor).

[0029] Furthermore, the voltage divider capacitor typically consists of two parts: an aluminum capacitor and a film capacitor. For example, the first voltage divider capacitor C1 includes a first aluminum capacitor and a first film capacitor connected in parallel, and the second voltage divider capacitor C2 includes a second aluminum capacitor and a second film capacitor connected in parallel. The aluminum capacitor provides low-frequency (e.g., 50Hz) energy support, while the film capacitor absorbs the switching ripple of the load switch and the balance bridge switch. On one hand, embodiments of the present invention balance the voltage dividers by setting a balance bridge group, making the voltages of each voltage divider capacitor equal, thus reducing the capacitance of the aluminum capacitor. On the other hand, embodiments of the present invention, by setting the balance bridge group to include at least two balance bridges with out-of-phase outputs, can suppress the high-frequency current ripple caused by the high-frequency switching of the balance bridge without increasing the capacitance of the film capacitor.

[0030] In summary, the embodiments of the present invention can achieve at least the following beneficial effects: Firstly, it improves the voltage balancing capability of the voltage divider node and enhances the ability to drive unbalanced loads, thereby reducing the number of aluminum capacitors. Secondly, the reduction of high-frequency ripple in the circuit can reduce the number of film capacitors. Thirdly, the reduced inductor current in each balancing bridge helps lower losses and increase frequency. Specifically, if only one balancing bridge balances the voltage at the voltage divider node, with an inductor current of I, the circuit loss can be calculated using the power formula I0. 2 R is calculated; if two balanced bridges simultaneously balance the voltage at the same voltage divider node, the inductor current in both balanced bridges is I / 2, and the loss of one balanced bridge circuit becomes I. 2 R / 4, the sum of the losses of the two balanced bridges is I. 2 With R / 2, losses are significantly reduced.

[0031] Therefore, the embodiments of the present invention are advantageous for achieving long lifespan, lightweight, low cost, high performance and low EMC.

[0032] Based on the above embodiments, optionally, the number of balanced bridges in a balanced bridge group is M, and the phase difference of the inductor current of each balanced bridge is 360° / M; where M≥2. This setting can make the high-frequency current ripple in the inductor current of each balanced bridge cancel out to 0, thereby further reducing the high-frequency current ripple of the external circuit of the balanced bridge group.

[0033] In the above embodiments, there are various ways to set the balance bridge group, which will be described in detail below, but this is not intended to limit the present invention.

[0034] See also Figure 2 In one embodiment, optionally, in each balanced bridge, the first end of the upper bridge arm B1, the first end of the lower bridge arm B2, and the first end of the inductive energy storage arm B3 are electrically connected, the second end of the upper bridge arm B1 is the upper bridge arm connection end of the balanced bridge, the second end of the lower bridge arm B2 is the lower bridge arm connection end of the balanced bridge, and the second end of the inductive energy storage arm B3 is the inductive connection end of the balanced bridge.

[0035] In this balanced bridge group, the upper bridge arm connection terminal of each balanced bridge is electrically connected to the positive terminal of the input power supply, the lower bridge arm connection terminal of each balanced bridge is electrically connected to the negative terminal of the input power supply, and the inductor connection terminal of each balanced bridge is electrically connected to the voltage divider node.

[0036] The working principle of this balanced bridge circuit is as follows: when the voltage Vc_UP of the first voltage divider capacitor C1 is greater than the voltage Vc_LOW of the second voltage divider capacitor C2, the conduction time of the upper bridge arm B1 in each balanced bridge is greater than the conduction time of the lower bridge arm B2. Specifically, when the upper bridge arm B1 is on, the lower bridge arm B2 is off, and the first voltage divider capacitor C1 charges the lower bridge arm B2 through the upper bridge arm B1 and the inductor energy storage arm B3. The inductor currents of the inductor energy storage arm B3 of each balanced bridge are iL1, ..., iLM, and the phase difference between the inductor currents iL1, ..., iLM is 360° / M. This setting can make the high-frequency current ripple in the inductor current of each balanced bridge cancel out to zero, reducing the high-frequency current ripple of the external circuit of the balanced bridge group. In addition, the setting of at least two balanced bridges can improve the balancing capability of the voltage divider node O1 and can more effectively suppress the fluctuation of the half bus.

[0037] Figure 3 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention. See also... Figure 3In one embodiment, optionally, the balanced bridge includes: a first switch BG1, a second switch BG2, and an inductor L1; wherein, the first end of the first switch BG1 serves as the first end of the upper bridge arm, and the second end of the first switch BG1 serves as the second end of the upper bridge arm; the first end of the second switch BG2 serves as the first end of the lower bridge arm, and the second end of the second switch BG2 serves as the second end of the lower bridge arm; the first end of the inductor L1 serves as the first end of the inductor energy storage arm, and the second end of the inductor L1 serves as the second end of the inductor energy storage arm.

[0038] Specifically, the first terminal of the first switch BG1, the first terminal of the second switch BG2, and the first terminal of the inductor L1 are electrically connected; the second terminal of the first switch BG1 is electrically connected to the positive terminal of the input power supply, the second terminal of the second switch BG2 is electrically connected to the negative terminal of the input power supply, and the second terminal of the inductor L1 is electrically connected to the voltage divider node O1. This embodiment of the invention provides a balanced bridge consisting of a first switch BG1, a second switch BG2, and an inductor L1, resulting in a simple circuit structure that is easy to implement.

[0039] In the above embodiments, the inductor L1 can be a discrete inductor or a magnetically integrated inductor, or other different forms.

[0040] Figure 4 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention. See also... Figure 4 In one embodiment, optionally, the balanced bridge group Z1 includes two balanced bridges, namely balanced bridges Z11 and Z12. Balanced bridge Z11 includes a first switch BG11, a second switch BG12, and an inductor L11; balanced bridge Z12 includes a first switch BG21, a second switch BG22, and an inductor L21.

[0041] Figure 5 The diagram shows a comparison of the inductor current in a balanced bridge circuit according to an embodiment of the present invention and the inductor current in related technologies. Figure 6 for Figure 5 The waveform diagram of this embodiment of the invention is an enlarged view at time 1 to time 2. See also... Figure 5 and Figure 6 Waveform X1 is the inductor current waveform in related technologies, waveform X2 is the inductor current waveform of the balance bridge Z11 in this embodiment of the invention, and waveform X3 is the inductor current waveform of the balance bridge Z12 in this embodiment of the invention. It should be noted that in... Figure 5 In the middle, waveform X2 covers waveform X3.

[0042] In related technologies, a single balanced bridge is used, where the inductor current varies between approximately -100V and 100V, with a peak-to-peak value reaching nearly 200V. In this embodiment of the invention, a single balanced bridge is used. Figure 4Taking the two balanced bridges shown as an example, the inductor current of each balanced bridge varies between approximately -50V and 50V, with a peak-to-peak value of approximately 100V, and the current amplitude is reduced by nearly 50%. Therefore, the embodiments of the present invention can significantly reduce the inductor current of the balanced bridge, thereby reducing losses.

[0043] In this embodiment of the invention, the inductor currents of the two balanced bridges Z11 and Z12 are output with a 180° phase shift. This configuration ensures that the sum of the inductor currents of inductor L11 and L21 is a constant of 0, meaning that high-frequency ripple is canceled out to zero. Therefore, this embodiment of the invention does not cause high-frequency disturbances to the external components (voltage divider capacitors C1 and C2), achieving its purpose of handling power frequency or low-frequency fluctuations without causing high-frequency disturbances.

[0044] Figure 7 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention. See also... Figure 7 In another embodiment, optionally, the balanced bridge group Z1 includes three balanced bridges, namely balanced bridges Z11, Z12, and Z13. Balanced bridge Z11 includes a first switch BG11, a second switch BG12, and an inductor L11; balanced bridge Z12 includes a first switch BG21, a second switch BG22, and an inductor L21; balanced bridge Z13 includes a first switch BG31, a second switch BG32, and an inductor L31. Similar to the aforementioned embodiment, the inductor currents of the three balanced bridges Z11, Z12, and Z13 are output with a 120° phase shift, which can ensure that the sum of the inductor currents of inductors L11, L21, and L31 is a constant value of 0. Furthermore, compared to two balanced bridges, the amplitude of the inductor current in each of the three balanced bridges is further reduced.

[0045] Figure 8 A circuit diagram of another balanced bridge circuit provided in an embodiment of the present invention. See also... Figure 8Based on the above embodiments, optionally, the balanced bridge circuit further includes: a control module 20 and a drive module 30; the drive module 30 is connected between the control module 20 and the control terminal of the balanced bridge. The control terminal of the balanced bridge is the control terminal of the switching transistors in the balanced bridge. For example, in the case of two balanced bridges Z11 and Z12, the control terminal of balanced bridge Z11 is the control terminal of the first switching transistor BG11 and the control terminal of the second switching transistor BG12; the control terminal of balanced bridge Z12 is the control terminal of the first switching transistor BG21 and the control terminal of the second switching transistor BG22. The control module 20 generates the PWM signal required by each balanced bridge based on the collected voltages of each voltage divider capacitor and the inductor current of each balanced bridge; the drive module 30 drives the switching transistors in each balanced bridge according to the PWM signal. By controlling the conduction state of the switching transistors in each balanced bridge, this embodiment of the invention can achieve the balancing effect of the voltage divider capacitors and control the phase-shifting alternation of the inductor currents of each balanced bridge.

[0046] Figure 9 This is a schematic diagram of a control module provided in an embodiment of the present invention. See also... Figure 9 Based on the above embodiments, optionally, the control module 20 includes a voltage outer loop control unit 21. The voltage outer loop control unit 21 is connected to the voltage of each voltage divider capacitor. The voltage outer loop control unit 21 calculates the voltage difference between the voltage Vcup of the upper voltage divider capacitor (i.e., voltage divider capacitor C1) and the voltage Vclow of the lower voltage divider capacitor (i.e., voltage divider capacitor C2), and performs PI regulation on the voltage difference to obtain a current reference value Iref. This current reference value Iref serves as the control reference for each balanced bridge. For example, the voltage outer loop control unit 21 includes a first subtractor and a first PI controller. The input terminals of the first subtractor are respectively input to the voltage Vcup of the upper voltage divider capacitor and the voltage Vclow of the lower voltage divider capacitor. The output terminal of the first subtractor is connected to the input terminal of the first PI controller. The first PI controller performs PI regulation on the input voltage difference to obtain the current reference value Iref. Optionally, the first PI controller also has a limiting function to limit the PI regulation signal and prevent the current reference value from being too large.

[0047] The control module 21 further includes at least two current inner loop control units corresponding to at least two balanced bridges, and at least two PWM signal generation units corresponding to at least two balanced bridges. For example, there are two balanced bridges, namely balanced bridges Z11 and Z12; correspondingly, there are two current inner loop control units, namely current inner loop control units 22 and 23; and there are two PWM signal generation units, namely PWM signal generation units 24 and 25.

[0048] Specifically, the inner current loop control unit 22 receives the current reference value Iref and the inductor current IBR11 of the balanced bridge Z11. It calculates the difference between the current reference value Iref and the inductor current IBR11 to obtain the current difference, and then applies PI regulation to this current difference to obtain the corresponding PWM reference value for the balanced bridge Z11. For example, the inner current loop control unit 22 includes a second subtractor and a second PI controller. The input terminals of the second subtractor are the current reference value Iref and the inductor current IBR11, respectively. The output terminal of the second subtractor is connected to the input terminal of the second PI controller. The second PI controller applies PI regulation to the input current difference to obtain the corresponding PWM reference value for the balanced bridge Z11. Optionally, the second PI controller also has a limiting function to limit the PI-regulated signal and prevent the current reference value from becoming too large.

[0049] The PWM signal generation unit 24 receives the PWM reference value and carrier signal of the balanced bridge Z11. Based on the PWM reference value and carrier signal of the balanced bridge Z11, the PWM signal generation unit 24 generates PWM signals to control the first switching transistor BG11 and the second switching transistor BG12. For example, the PWM signal generation unit 24 includes: a first divider, a first comparator, and a first inverter; wherein, the first input terminal of the first divider receives the PWM reference value of the balanced bridge Z11, and the second input terminal of the first divider receives the sum of the voltages of the upper and lower voltage divider capacitors. The first divider divides the PWM reference value by the sum of the voltages to obtain the carrier comparison value of the balanced bridge Z11; the first input terminal of the first comparator receives the carrier comparison value of the balanced bridge Z11, and the second input terminal of the first comparator receives the carrier signal. The first comparator divides the carrier signal by the carrier signal. The comparison value is compared with the carrier signal to obtain the upper arm control signal of the balanced bridge Z11, which is used to control the first switch BG11 of the balanced bridge Z11. The input terminal of the first inverter is connected to the upper arm control signal of the balanced bridge Z11. The first inverter inverts the upper arm control signal of the balanced bridge Z11 to obtain the lower arm control signal of the balanced bridge Z11, which is used to control the second switch BG12 of the balanced bridge Z11. The upper arm control signal and the lower arm control signal constitute the PWM signal of the balanced bridge Z11 output by the PWM signal generation unit.

[0050] The current inner loop control unit 22 and PWM signal generation unit 24 corresponding to the balanced bridge Z11 have been specifically described above. The current inner loop control unit 23 and PWM signal generation unit 25 corresponding to the balanced bridge Z12 are configured similarly. Specifically, the current inner loop control unit 23 receives the current reference value Iref and the inductor current IBR12 of the balanced bridge Z12. The difference between the current reference value Iref and the inductor current IBR12 is calculated to obtain the current difference, which is then PI-regulated to obtain the PWM reference value for the corresponding balanced bridge Z12. For example, the current inner loop control unit 23 includes a third subtractor and a third PI controller. The input terminals of the third subtractor are the current reference value Iref and the inductor current IBR12, respectively. The output terminal of the third subtractor is connected to the input terminal of the third PI controller. The third PI controller PI-regulated the input current difference to obtain the PWM reference value for the corresponding balanced bridge Z12. Optionally, the third PI controller also has a limiting function to limit the PI-regulated signal and prevent the current reference value from becoming too large.

[0051] The PWM signal generation unit 25 receives the PWM reference value and carrier signal of the balanced bridge Z12. Based on the PWM reference value and carrier signal of the balanced bridge Z12, the PWM signal generation unit 25 generates PWM signals to control the first switching transistor BG21 and the second switching transistor BG22. For example, the PWM signal generation unit 25 includes: a second divider, a second comparator, and a second inverter. The first input of the second divider receives the PWM reference value of the balanced bridge Z12, and the second input receives the sum of the voltages of the upper and lower voltage divider capacitors. The second divider divides the PWM reference value by the sum of the voltages to obtain the carrier comparison value of the balanced bridge Z12. The first input of the second comparator receives the carrier comparison value of the balanced bridge Z12, and the second input receives the carrier signal. The second comparator divides the carrier signal by the carrier signal. The comparison value is compared with the carrier signal to obtain the upper arm control signal of the balanced bridge Z12, which is used to control the first switch BG21 of the balanced bridge Z12. The input terminal of the first inverter is connected to the upper arm control signal of the balanced bridge Z12, and the second inverter inverts the upper arm control signal of the balanced bridge Z12 to obtain the lower arm control signal of the balanced bridge Z12, which is used to control the second switch BG22 of the balanced bridge Z12. The upper arm control signal and the lower arm control signal constitute the PWM signal of the balanced bridge Z12 output by the PWM signal generation unit.

[0052] Optionally, the control module 21 further includes an adder. The two input terminals of the adder are the voltage Vcup of the upper voltage divider capacitor and the voltage Vclow of the lower voltage divider capacitor, respectively. The output terminal of the adder is the sum of the voltages of the upper and lower voltage divider capacitors. This sum of the voltages of the upper and lower voltage divider capacitors serves as the input signal for each PWM signal generation unit.

[0053] In other embodiments, the sum of the voltages of the upper and lower voltage divider capacitors can also be obtained by acquiring the power supply voltage.

[0054] Optionally, the carrier signal of each PWM signal generation unit is provided by a carrier signal generator. For example, the carrier signal generator can provide a triangular wave or sawtooth wave carrier signal. Specifically, the carrier signal of PWM signal generation unit 24 is provided by a first carrier signal generator, and the carrier signal of PWM signal generation unit 25 is provided by a second carrier signal generator. The carrier signals generated by the first and second carrier signal generators have equal amplitudes and a phase difference of 180°. In an embodiment with M balanced bridges, the phase difference of the carrier signals from each carrier signal generator is 360° / M; where M ≥ 2.

[0055] Optionally, in practical applications, the amplitude of the carrier signal generator can be set, and the amplitude of the carrier signal output by the carrier signal generator can be controlled through a gain module. For example, in... Figure 9 In the middle, the gain of the module is set to 0.5 times.

[0056] Figure 10 The diagram shows the PWM signal and current waveforms of a balanced bridge circuit according to an embodiment of the present invention. See also... Figure 10 Waveform PWM1 is the PWM signal of the first switching transistor BG11 in the balanced bridge Z11, and waveform PWM2 is the PWM signal of the first switching transistor BG21 in the balanced bridge Z12. The two PWM signals PWM1 and PWM2 are 180° out of phase, and the corresponding two inductor currents IBR11 and IBR12 are also 180° out of phase, thus realizing the setting of the interleaved balanced bridge.

[0057] In summary, this embodiment of the invention, by setting at least two balanced bridges within the balanced bridge group, provides an additional inductor current for voltage balancing compared to setting only one balanced bridge. This reduces the peak-to-peak value of the inductor current in each balanced bridge and improves the balancing capability of the voltage divider nodes. Furthermore, by controlling the phase-shifted conduction of each balanced bridge circuit in a balanced bridge group, the phase-shifted output of the inductor current of each balanced bridge circuit can be controlled. For balanced bridges, the high-frequency switching of the upper and lower bridge arms causes high-frequency current ripple in the inductor current. This embodiment of the invention, by setting at least two balanced bridges with phase-shifted output in a balanced bridge group, ensures that the high-frequency current ripple in the inductor current of each balanced bridge cancels each other out, significantly reducing the high-frequency current ripple for the external circuitry of the balanced bridge group (i.e., the upper and lower voltage divider capacitors).

[0058] Furthermore, the voltage divider capacitor typically consists of two parts: an aluminum capacitor and a film capacitor. For example, the first voltage divider capacitor C1 includes a first aluminum capacitor and a first film capacitor connected in parallel, and the second voltage divider capacitor C2 includes a second aluminum capacitor and a second film capacitor connected in parallel. The aluminum capacitor provides low-frequency (e.g., 50Hz) energy support, while the film capacitor absorbs the switching ripple of the load switch and the balance bridge switch. On one hand, embodiments of the present invention balance the voltage dividers by setting a balance bridge group, making the voltages of each voltage divider capacitor equal, thus reducing the capacitance of the aluminum capacitor. On the other hand, embodiments of the present invention, by setting the balance bridge group to include at least two balance bridges with out-of-phase outputs, can suppress the high-frequency current ripple caused by the high-frequency switching of the balance bridge without increasing the capacitance of the film capacitor.

[0059] Therefore, the embodiments of the present invention can achieve at least the following beneficial effects: Firstly, it improves the voltage balancing capability of the voltage divider node and enhances the ability to drive unbalanced loads, thereby reducing the number of aluminum capacitors. Secondly, the reduction of high-frequency ripple in the circuit can reduce the number of film capacitors. Thirdly, the reduced inductance current in each balanced bridge circuit helps to reduce losses and increase frequency.

[0060] This invention also provides an inverter system. Figure 11 This is a schematic diagram of an inverter system provided in an embodiment of the present invention. See also... Figure 11 The inverter system includes a balanced bridge circuit 2 as provided in any embodiment of the present invention, and has corresponding beneficial effects. The inverter system also includes an input power supply 1 and a converter 3, wherein the voltage-dividing capacitor in the balanced bridge circuit 2 serves as the DC bus capacitor of the converter 3. The converter 3 further includes a conversion circuit, which serves as the load of the balanced bridge circuit 2.

[0061] This invention also provides a control method for a balanced bridge circuit. This control method is applicable to the balanced bridge circuit provided in any embodiment of this invention and has corresponding beneficial effects. This control method can be configured in the control module of the balanced bridge circuit, and the control module can be implemented by software and / or hardware. Specifically, Figure 12 A flowchart illustrating a control method for a balanced bridge circuit according to an embodiment of the present invention. See also... Figure 12 The control method includes the following steps: S1: Collect the voltage of each voltage divider capacitor and the inductor current of each balance bridge.

[0062] S2: Based on the voltage of the upper voltage divider capacitor, the voltage of the lower voltage divider capacitor, and the inductor current of each balanced bridge, generate PWM signals to control each balanced bridge so that the inductor current of each balanced bridge is output in phase.

[0063] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0064] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A balanced bridge circuit, characterized in that, include: The voltage divider capacitor is connected in series between the positive and negative terminals of the input power supply. The connection point of two adjacent voltage divider capacitors is a voltage divider node. The voltage divider capacitors located on both sides of the voltage divider node are the upper voltage divider capacitor and the lower voltage divider capacitor, respectively. A balanced bridge group, comprising at least two balanced bridges; each balanced bridge includes an upper bridge arm, a lower bridge arm, and an inductor energy storage arm. The upper bridge arm is used to charge and discharge the upper voltage divider capacitor through the inductor energy storage arm, and the lower bridge arm is used to charge and discharge the lower voltage divider capacitor through the inductor energy storage arm. The inductor energy storage arm is used to store and release energy. The inductor currents of each balanced bridge in the balanced bridge group are output in out-of-phase.

2. The balanced bridge circuit according to claim 1, characterized in that, The number of balance bridges in a balance bridge group is M, and the phase difference of the inductor current of each balance bridge is 360° / M; wherein, M≥2.

3. The balanced bridge circuit according to claim 1, characterized in that, The number of voltage dividing capacitors is two, namely the first voltage dividing capacitor and the second voltage dividing capacitor; In the balanced bridge, the first end of the upper bridge arm, the first end of the lower bridge arm, and the first end of the inductive energy storage arm are electrically connected. The second end of the upper bridge arm is the upper bridge arm connection end of the balanced bridge. The second end of the lower bridge arm is the lower bridge arm connection end of the balanced bridge. The second end of the inductive energy storage arm is the inductive connection end of the balanced bridge. In this configuration, the upper bridge arm connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the positive terminal of the input power supply, the lower bridge arm connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the negative terminal of the input power supply, and the inductor connection terminal of each balanced bridge in the balanced bridge group is electrically connected to the voltage divider node.

4. The balanced bridge circuit according to claim 3, characterized in that, The balanced bridge includes: a first switching transistor, a second switching transistor, and an inductor; Wherein, the first end of the first switch transistor serves as the first end of the upper bridge arm, and the second end of the first switch transistor serves as the second end of the upper bridge arm; the first end of the second switch transistor serves as the first end of the lower bridge arm, and the second end of the second switch transistor serves as the second end of the lower bridge arm; the first end of the inductor serves as the first end of the inductor energy storage arm, and the second end of the inductor serves as the second end of the inductor energy storage arm.

5. The balanced bridge circuit according to any one of claims 1-4, characterized in that, Also includes: A control module and a drive module; the drive module is connected between the control module and the control terminal of the balance bridge; The control module generates PWM signals required by each of the voltage divider capacitors and the inductor current of each of the balance bridges based on the collected voltages of each of the voltage divider capacitors and the inductor current of each of the balance bridges; the drive module drives the switching transistors in each of the balance bridges according to the PWM signals.

6. The balanced bridge circuit according to claim 5, characterized in that, The control module includes: The voltage outer loop control unit is connected to the voltage of each voltage divider capacitor in the balance bridge group. The voltage outer loop control unit calculates the voltage difference between the voltage of the upper voltage divider capacitor and the voltage of the lower voltage divider capacitor, and performs PI regulation on the voltage difference to obtain a current reference value. At least two current inner loop control units, each corresponding to one of the at least two balanced bridges, are connected to the current reference value and the inductor current of the balanced bridge corresponding to the current inner loop control unit; the current inner loop control unit calculates the difference between the current reference value and the inductor current to obtain the current difference, and performs PI regulation on the current difference to obtain the PWM reference value; At least two PWM signal generation units, each corresponding to one of the at least two balanced bridges, are provided. Each PWM signal generation unit is connected to a corresponding PWM reference value and a carrier signal. The PWM signal generation unit generates a PWM signal based on the PWM reference value and the carrier signal.

7. The balanced bridge circuit according to claim 6, characterized in that, The phase difference of the carrier signal corresponding to each PWM signal generation unit is 360° / M; where M≥2.

8. The balanced bridge circuit according to claim 6, characterized in that, The PWM signal generation unit includes: a divider, a comparator, and an inverter; The first input terminal of the divider is connected to the PWM reference value, and the second input terminal of the divider is connected to the sum of the voltages of the upper voltage divider capacitor and the lower voltage divider capacitor. The divider divides the PWM reference value by the sum of the voltages to obtain the carrier comparison value. The first input terminal of the comparator is connected to the carrier comparison value, and the second input terminal of the comparator is connected to the carrier signal. The comparator compares the carrier comparison value and the carrier signal to obtain the upper arm control signal. The input terminal of the inverter is connected to the upper bridge arm control signal, and the inverter inverts the upper bridge arm control signal to obtain the lower bridge arm control signal; wherein, the upper bridge arm control signal and the lower bridge arm control signal constitute the PWM signal output by the PWM signal generation unit.

9. A control method for a balanced bridge circuit as described in any one of claims 1-8, characterized in that, include: S1: Collect the voltage of each of the voltage divider capacitors and the inductor current of each of the balance bridges; S2: Based on the voltage of the upper voltage divider capacitor, the voltage of the lower voltage divider capacitor, and the inductor current of each of the balanced bridges, generate a PWM signal to control each of the balanced bridges so that the inductor currents of each balanced bridge are output in out-of-phase.

10. An inverter system, characterized in that, include: The input power supply, the balanced bridge circuit as described in any one of claims 1-8, and the converter, wherein the voltage divider capacitor in the balanced bridge circuit serves as the DC bus capacitor of the converter.

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