Frequency modulation closed loop control system of isolated non-resonant soft switching DC-DC converter

Abstract

The application discloses a frequency modulation closed loop control system of an isolated non-resonant soft switching DC-DC converter, comprising: a variable definition module for defining global variables, input variables and output variables required by the system; a pre-calculation module for reading input variables and calculating the error between the voltage reference value and the voltage feedback value after starting the current calculation step, and simultaneously performing time-sharing switching judgment of the soft start stage and the normal closed loop control stage according to the running time; a main algorithm module for executing frequency modulation and drive logic generation algorithm, including the soft start stage, the normal closed loop control stage, the sawtooth wave generation stage and the output mapping and logic generation stage; and an output module for real-time updating and outputting the sawtooth wave phase signal, the target switching frequency and the drive signals of the four switching tubes, and ending the current calculation step. The application realizes seamless smooth switching from the soft start to the normal closed loop control, and generates high-precision multi-channel switching tube drive signals.

Description

Technical Field

[0001] This invention relates to the technical field of power electronic control and digital power supply, and in particular to a frequency modulation closed-loop control system for an isolated non-resonant soft-switching DC-DC converter. Background Technology

[0002] In recent years, with the rapid development of data center power supply systems, energy storage boost systems, and high-voltage isolated industrial power supplies, high-gain, high-efficiency, and high-dynamic-response isolated DC-DC converters have become core key equipment for connecting low-voltage DC sources and high-voltage DC buses. In these application scenarios, in order to achieve high power density and high conversion efficiency, increasing the switching frequency to reduce the size of transformers and passive filtering devices is an inevitable technological trend.

[0003] However, the closed-loop control and dynamic response of the converter face severe technical challenges under high-frequency operation:

[0004] 1. Current and frequency surges at the moment of closed-loop switching.

[0005] When a converter transitions from the startup phase to the normal closed-loop control phase, the historical integral state of the closed-loop regulator, such as a PI regulator, is often initially zero or mismatched with the actual operating conditions. This can easily lead to huge frequency and current surges at the moment of switching to the closed loop. Such sudden changes can not only cause severe electrical stress but may also lead to malfunctions of overcurrent protection or damage to semiconductor devices.

[0006] 2. Frequency jitter problem caused by discretization of digital control.

[0007] When using digital microprocessors or digital logic to calculate voltage-controlled oscillators and sawtooth waves, the presence of discrete control step size makes it easy for the sawtooth wave to generate phase truncation error during the zero-crossing reset process. This leads to high-frequency jitter in the output switching frequency, deteriorates the output voltage quality, and increases high-frequency electromagnetic interference.

[0008] 3. The complexity and reliability of driving signal timing generation.

[0009] For a four-switch bridge isolation converter with specific timing requirements, the key to ensuring reliable non-resonant soft-switching operation of the converter is to generate, in real time and accurately, multiple switching transistor drive signals with specific duty cycles and phase differences based on the target switching frequency of the closed-loop output using simplified digital logic.

[0010] Therefore, the industry urgently needs a frequency modulation closed-loop control strategy that can achieve seamless and smooth switching from soft start to closed-loop control, eliminate frequency jitter caused by the discretization of digital control, and accurately generate multi-channel switch drive signals. How to efficiently complete error calculation, PI integral pre-charging, residual retention voltage-controlled oscillation, and gate logic mapping within each control step using a modular control architecture constitutes the research motivation and innovative breakthrough of this invention. Summary of the Invention

[0011] The purpose of this invention is to overcome the shortcomings and deficiencies of the prior art and provide a frequency modulation closed-loop control system for an isolated non-resonant soft-switching DC-DC converter, which realizes seamless and smooth switching from soft start to normal closed-loop control, eliminates frequency mutations and current surges, overcomes the frequency jitter problem under digital discrete control, and generates multi-channel switching transistor drive signals with high precision.

[0012] To achieve the above objectives, the technical solution provided by this invention is: a frequency modulation closed-loop control system for an isolated non-resonant soft-switching DC-DC converter, comprising: a variable definition module, a pre-calculation module, a main algorithm module, and an output module;

[0013] The variable definition module is used to define the global variables, input variables, and output variables required by the system. The global variables include the integral term PI_interal and the sawtooth wave phase Saw_phase. The input variables include the voltage reference value V. ref Voltage feedback value V out The runtime t and control step size Delt, the output variables include the sawtooth wave phase signal v saw Target switching frequency And the drive signals Sp1~Sp4 for the four switching transistors;

[0014] The pre-calculation module is used to read the input variables and calculate the voltage reference value V after starting the current calculation step. ref With voltage feedback value V out The voltage error between them is determined, and the time-sharing switch between the soft start phase and the normal closed-loop control phase is judged based on the running time.

[0015] The main algorithm module is used to execute the frequency modulation and drive logic generation algorithm, including the soft start stage, the normal closed-loop control stage, the sawtooth wave generation stage, and the output mapping and logic generation stage.

[0016] The output module is used to update and output the sawtooth wave phase signal v in real time. saw Target switching frequency And the drive signals Sp1~Sp4 of the four switching transistors, and end the current calculation step.

[0017] Furthermore, the soft-start phase in the main algorithm module takes effect when the running time is less than a set soft-start time threshold. During this phase, the real-time switching frequency f... s As the running time t increases from the initial set frequency f s_start Linearly increasing to the target switching frequency f s_end Meanwhile, based on the current linearly increasing real-time switching frequency f s The integral term PI_interal of the PI regulator used for closed-loop control is dynamically precharged in real time to follow the current switching frequency, so as to achieve a smooth and seamless transition when switching from the soft start stage to the normal closed-loop control stage.

[0018] Furthermore, during the soft-start phase, the real-time switching frequency f s As the running time t increases from the initial set frequency f s_start Linearly increasing to the target switching frequency f s_end The formula is:

[0019] ;

[0020] At this stage, to ensure no sudden changes in current or frequency at the moment of switching to closed loop, the current linearly increasing real-time switching frequency f is used. s Real-time dynamic pre-charge of the integral term PI_interal of the PI controller:

[0021] ;

[0022] In the formula, For proportional gain, The integral gain is achieved through the real-time dynamic pre-charge, ensuring that the integrator state of the PI regulator is precisely matched to the corresponding output state at the moment of switching into the normal closed-loop control phase, thus achieving seamless and smooth switching.

[0023] Furthermore, the normal closed-loop control phase in the main algorithm module takes effect when the running time t is greater than or equal to the set soft-start time threshold. During this phase, the target switching frequency is calculated by performing cumulative integral and proportional calculations based on the voltage error. and the target switching frequency Apply upper and lower limit constraints.

[0024] Furthermore, during the normal closed-loop control phase, pre-charging is stopped and normal closed-loop PI regulation is initiated, as follows:

[0025] First, perform discrete integration and accumulation on the voltage error:

[0026] ;

[0027] Subsequently, the target switching frequency is calculated. :

[0028] ;

[0029] In the formula, For proportional gain, This is the integral gain;

[0030] Finally, the target switching frequency Apply upper and lower limit constraints to restrict it to a set safe frequency range.

[0031] Furthermore, in the sawtooth wave generation stage of the main algorithm module, voltage-controlled oscillator logic is used to generate the sawtooth wave according to the determined target switching frequency. The sawtooth wave phase is incrementally accumulated with the control step size Delt; when the phase accumulation value is greater than or equal to 1.0, zero-crossing reset is performed by subtracting 1.0 to retain the boundary residual, so as to eliminate frequency jitter caused by digital discretization.

[0032] Furthermore, in the sawtooth wave generation stage, according to the determined target switching frequency... Using the control step size Delt, calculate the phase increment Δθ within the current step size. ×Delt, and update the sawtooth wave phase:

[0033] ;

[0034] When Saw_phase ≥ 1.0, a zero-crossing reset is triggered; to eliminate frequency jitter and phase truncation errors caused by digital discretization control, a reset calculation that retains the boundary residuals is used during reset.

[0035] ;

[0036] The retained residuals ensure that the average frequency of the output waveform is equal to the macroscopic period. This effectively suppresses high-frequency digital jitter.

[0037] Furthermore, in the output mapping and logic generation stage of the main algorithm module, a multi-comparator logic operation is performed based on a preset modulation reference and the sawtooth wave phase (Saw_phase) obtained in the sawtooth wave generation stage. Combined with gate logic combination operations, the drive signals Sp1~Sp4 for the four switching transistors are directly generated. The multi-comparator logic operation includes:

[0038] The first comparator logic Cmp1 is generated by comparing the first preset reference with the sawtooth wave phase Saw_phase.

[0039] The second comparator logic Cmp2 is generated by comparing the second preset reference with the sawtooth wave phase Saw_phase.

[0040] The third comparator logic Cmp3 is generated by comparing the sawtooth wave phase Saw_phase with the first preset reference.

[0041] The fourth comparator logic, Cmp4, is generated by comparing the third preset reference with the sawtooth wave phase, Saw_phase.

[0042] Among them, the first driving signal Sp1 of the four switching transistors is taken from the first comparator logic Cmp1, the fourth driving signal Sp4 is taken from the second comparator logic Cmp2, the third driving signal Sp3 is taken from the third comparator logic Cmp3, and the second driving signal Sp2 is taken from the combination gate logic signal obtained by multiplying the inverted signal of the fourth comparator logic Cmp4 with the third comparator logic Cmp3.

[0043] Furthermore, in the output mapping and logic generation stage, a set of fixed modulation references is defined, including a first preset reference mod. 05 = 0.5, Second preset benchmark mod mul1 = 0.25 and the third preset benchmark v tri_mod = 0.75; Perform multiplexer logic operations based on the current sawtooth wave phase (Saw_phase) and the above reference:

[0044] The first comparator logic Cmp1 compares 0.5 with Saw_phase. If 0.5 > Saw_phase, then Cmp1 = 1; otherwise, it is 0.

[0045] The second comparator logic Cmp2: compares 0.25 with Saw_phase. If 0.25 > Saw_phase, then Cmp2 = 1; otherwise, it is 0.

[0046] The third comparator logic Cmp3: compares Saw_phase with 0.5. If 0.5 < Saw_phase, then Cmp3 = 1; otherwise, it is 0.

[0047] The fourth comparator logic Cmp4 compares 0.75 with Saw_phase. If 0.75 < Saw_phase, then Cmp4 = 1; otherwise, it is 0.

[0048] After obtaining the comparator output, the drive signal for the second switch is calculated using combinational gate logic. That is, the driving signal Sp2 is equal to the inverted Cmp4 multiplied by Cmp3, expressed by the formula:

[0049] .

[0050] Furthermore, in the output module, the results generated by the main algorithm module are mapped and assigned to the specified physical or simulation output port in real time to obtain the logical outputs of the drive signals of the four switching transistors. Specifically, the logical output of drive signal Sp1 is equal to Cmp1, the logical output of drive signal Sp2 is equal to the inverted Cmp4 multiplied by Cmp3, the logical output of drive signal Sp3 is equal to Cmp3, and the logical output of drive signal Sp4 is equal to Cmp4. The formulas are expressed as follows:

[0051] ;

[0052] This concludes the current control and simulation step size calculation.

[0053] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0054] 1. This invention achieves a seamless and smooth transition from the soft-start phase to the normal closed-loop control phase. During the soft-start phase, the invention employs dynamic pre-charging of the closed-loop PI integral term, ensuring that the integral term follows the linearly increasing real-time switching frequency. At the instant the soft-start phase ends and the normal closed-loop control phase begins, because the integral term has already been pre-charged to a state perfectly matched to the current frequency, the frequency surge and current spike at the moment of closed-loop transition are completely eliminated, ensuring the safe and stable startup process of the converter.

[0055] 2. This invention significantly eliminates frequency jitter and phase distortion caused by the discretization of digital control. The voltage-controlled sawtooth wave generation logic of this invention employs a reset algorithm that retains the boundary residual during phase reset (Saw_phase -= 1.0), avoiding the phase truncation error caused by direct zeroing. This effectively eliminates high-frequency jitter under digital discrete control, improving the accuracy of frequency modulation control and the electromagnetic compatibility characteristics of modulation.

[0056] 3. This invention achieves efficient and accurate logic mapping of multiple drive signals. This invention achieves this through simple preset benchmark comparison and gate logic combination (such as... It directly generates four-channel switching transistor drive signals with strict timing and duty cycle relationships from the current sawtooth wave phase, without the need for complex hardware timers or multiple nested logic, thus improving the controller's execution efficiency and the reliability of drive control.

[0057] In summary, this invention achieves seamless soft-start switching and low-jitter, precise modulation of voltage-controlled sawtooth waves, ensuring safe and stable operation of the converter across the entire frequency band while improving closed-loop dynamic response performance. This invention is applicable to isolated boost DC power conversion scenarios requiring high gain, high dynamic response, and high reliability, such as data center power supplies, energy storage boost power supplies, and high-boost isolated industrial power supplies. Attached Figure Description

[0058] Figure 1 This is a flowchart of the frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter provided in this embodiment.

[0059] Figure 2 This is the isolated non-resonant soft-switching DC-DC converter topology provided in this embodiment.

[0060] Figure 3 This is the timing logic diagram of the drive signal for the switching transistor of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment.

[0061] Figure 4 This is a simulation result diagram of the drive signal of the switch transistor of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment.

[0062] Figure 5 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment under rated operating conditions.

[0063] Figure 6 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment when the output power is switched from 1kW to 800W.

[0064] Figure 7 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment, showing the dynamic process of the output voltage switching from 1kW to 800W.

[0065] Figure 8 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage during the switching frequency adjustment process of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment when the output power is switched from 1kW to 800W.

[0066] Figure 9 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment when the input voltage switches from 48V to 40V.

[0067] Figure 10 This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment, showing the dynamic process of the output voltage switching from 48V to 40V.

[0068] Figure 11This is a simulation waveform diagram of the switching frequency, output voltage, and input voltage of the isolated non-resonant soft-switching DC-DC converter provided in this embodiment, showing the switching frequency adjustment process when the input voltage switches from 48V to 40V. Detailed Implementation

[0069] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0070] This embodiment discloses a frequency modulation closed-loop control system for an isolated non-resonant soft-switching DC-DC converter, such as... Figure 1 As shown, the system is implemented based on a modular digital control architecture, specifically including: a variable definition module, a pre-calculation module, a main algorithm module, and an output module. The system operates in a microcontroller (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA) with a fixed control step size Delt (e.g., Delt = 1 × 10⁻⁶). -7 s) Execute cyclically. The specific implementation within each control step is as follows:

[0071] a. Variable definition module

[0072] During system initialization, the required global variables, input variables, and output variables are declared and allocated in advance:

[0073] Global variables include the integral term PI_interal (initial value 0.0) used for closed-loop control regulation and the sawtooth phase of the voltage-controlled oscillator Saw_phase (initial value 0.0, range 0.0~1.0).

[0074] Input variables: including voltage reference value V ref Voltage feedback value V out The runtime t and the control step size Delt.

[0075] Output variables: including sawtooth wave phase signal v saw Target switching frequency And the drive signals Sp1~Sp4 for the four switching transistors.

[0076] b. Pre-calculation module

[0077] After the current control step begins, first read the input variable V. ref V out , t and Delt, and calculate the current voltage error error = V ref -V outSubsequently, based on the current running time t and the preset soft start time threshold (set to 0.02s in this embodiment, i.e., soft start lasts for 1000 simulation / control steps), the time-sharing judgment between the soft start stage and the normal closed-loop control stage is performed.

[0078] c. Main Algorithm Module

[0079] Within the current step size, the main algorithm module sequentially executes the soft-start and closed-loop time-sharing switching logic, the sawtooth wave generation logic, and the output mapping and drive gate logic generation logic, including the soft-start phase, the normal closed-loop control phase, the sawtooth wave generation phase, and the output mapping and logic generation phase, as detailed below:

[0080] c1. Soft start and closed-loop time-sharing phase

[0081] Soft start phase (t < 0.02s): Real-time switching frequency f s As the running time t increases from the initial set frequency f s_start (e.g., 10kHz) linearly increase to the target switching frequency f s_end (e.g., 90kHz), the formula is:

[0082] ;

[0083] At this stage, to ensure no sudden changes in current or frequency at the moment of closing the loop, based on the current linearly increasing f... s Real-time dynamic pre-charge of the integral term PI_interal of the PI controller:

[0084] ;

[0085] in, For proportional gain (e.g.) =3000.0), For integral gain (e.g.) =800000.0). Through the above real-time dynamic pre-charge, at the instant of closed-loop cut-in at t=0.02s, the integrator state of the PI regulator is precisely matched with the 90kHz output state, achieving a truly seamless and smooth switching.

[0086] Normal closed-loop control phase (t≥0.02s): Stop pre-charging and switch to normal closed-loop PI regulation, as follows:

[0087] First, the voltage error is discretely integrated and accumulated:

[0088] ;

[0089] The target switching frequency was then calculated. :

[0090] ;

[0091] Finally, Implement safety upper and lower limit constraints to restrict it to a set safety frequency range (e.g., 10 kHz ≤ ≤200kHz).

[0092] c2, Sawtooth Wave Generation Stage

[0093] The target switching frequency determined based on the above steps Using the control step size Delt, calculate the phase increment Δθ within the current step size. ×Delt, and update the sawtooth wave phase:

[0094] ;

[0095] A zero-crossing reset is triggered when Saw_phase ≥ 1.0. To eliminate frequency jitter and phase truncation errors caused by digital discretization control, a reset calculation that retains boundary residuals is used during reset.

[0096] ;

[0097] The retained residuals ensure that the average frequency of the output waveform is strictly equal to the macroscopic period. This effectively suppresses high-frequency digital jitter.

[0098] c3. Output Mapping and Logic Generation Stage

[0099] Define a set of fixed modulation references, including a first preset reference mod. 05 = 0.5, Second preset benchmark mod mul1 =0.25 and the third preset benchmark v tri_mod = 0.75. Perform multiplexer logic operations based on the current sawtooth wave phase (Saw_phase) and the aforementioned reference:

[0100] The first comparator logic Cmp1 compares 0.5 with Saw_phase. If 0.5 > Saw_phase, then Cmp1 = 1; otherwise, it is 0.

[0101] The second comparator logic Cmp2: compares 0.25 with Saw_phase. If 0.25 > Saw_phase, then Cmp2 = 1; otherwise, it is 0.

[0102] The third comparator logic Cmp3: compares Saw_phase with 0.5. If 0.5 < Saw_phase, then Cmp3 = 1; otherwise, it is 0.

[0103] The fourth comparator logic Cmp4 compares 0.75 with Saw_phase. If 0.75 < Saw_phase, then Cmp4 = 1; otherwise, it is 0.

[0104] After obtaining the comparator output, the drive signal for the second switch is calculated using combinational gate logic. That is, the driving signal Sp2 is equal to the inverted Cmp4 multiplied by Cmp3, expressed by the formula:

[0105] ;

[0106] c4, Output Module

[0107] The results generated by the main algorithm module are mapped and assigned in real time to the physical or simulation output ports specified by the system, resulting in the logical outputs of the drive signals for the four switching transistors. Specifically, drive signal Sp1 is logically equal to Cmp1, drive signal Sp2 is logically equal to the inverted Cmp4 multiplied by Cmp3, drive signal Sp3 is logically equal to Cmp3, and drive signal Sp4 is logically equal to Cmp4. The formulas are as follows:

[0108] ;

[0109] At this point, the current control and simulation step size calculation is complete, and we await the next long trigger signal and repeat the above module logic.

[0110] The above embodiments completely solve the sudden impact at the moment of closed-loop switching by dynamically pre-charging the integral term of the closed-loop regulator (i.e., PI regulator) during the soft-start phase; at the same time, by combining sawtooth wave generation logic with residual retention and simplified multi-comparator combination gate logic, the isolated non-resonant soft-switching DC-DC converter has extremely high frequency modulation control accuracy, electromagnetic compatibility and closed-loop response speed over a wide frequency range.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0112] The following simulation verification is performed on the frequency modulation closed-loop control system of the above-mentioned isolated non-resonant soft-switching DC-DC converter. The topology of the isolated non-resonant soft-switching DC-DC converter in this embodiment of the invention is as follows: Figure 2 As shown, the timing logic for driving the switching transistor is as follows: Figure 3 As shown in Table 1 below, a simulation test platform was built to verify its theoretical analysis and non-resonant soft-switching characteristics.

[0113] Table 1 Simulation Parameters of Isolated Non-Resonant Soft-Switching DC-DC Converter

[0114]

[0115] Under the parameters shown in Table 1, the simulation waveforms of the switching transistor drive control of the converter in this embodiment of the invention are as follows: Figure 4 As shown, the four drive signals strictly follow the logical time sequence. Furthermore, the simulated waveforms of the input / output voltages and switching frequencies of the converter in this embodiment are as follows: Figure 5 As shown, the input voltage V in It is 48V, and the output voltage V out With a voltage of 800V, a switching frequency of 80kHz, and a smooth transition from soft start to closed-loop control in 0.02s, the output voltage is very stable and the switching frequency does not fluctuate significantly.

[0116] Figures 6-8 The simulation waveforms of the switching frequency, output voltage, and input voltage of the converter according to an embodiment of the present invention are shown when the output power switches from 1kW to 800W. Figure 6 It can be seen that the output voltage is controlled at 800V during output power switching, and the switching frequency of the converter is adjusted from the original 80kHz to about 98kHz. According to Figure 7 It can be seen that during the dynamic adjustment of the output voltage during output power switching, the output voltage overshoot is within 0.025%, and the dynamic process is only 2ms. Therefore, the output voltage overshoot is small and the dynamic adjustment speed is fast during output power switching. According to Figure 8 It can be seen that when the output power is switched, the switching frequency changes from low to high, and the sawtooth wave changes from sparse to dense.

[0117] Figures 9-11 The simulation waveforms of the switching frequency, output voltage, and input voltage of the converter according to an embodiment of the present invention are shown when the input voltage switches from 48V to 40V. Figure 9 It can be seen that when the input voltage switches, the output voltage is controlled at 800V, and the switching frequency of the converter is adjusted from the original 80kHz to about 42kHz. According to Figure 10 It can be seen that during the dynamic adjustment of the output voltage when the input voltage is switched, the output voltage overshoot is within 0.05%, and the dynamic process is only 2.2ms. Therefore, the output voltage overshoot is small and the dynamic adjustment speed is fast during the input voltage switching process. According to Figure 11 It can be seen that when the output power is switched, the switching frequency changes from high to low, and the sawtooth wave changes from dense to sparse.

[0118] Based on the simulation results above, the frequency modulation closed-loop control system of the isolated non-resonant soft-switching DC-DC converter in this embodiment of the invention is verified. It can improve the closed-loop dynamic response performance while ensuring the safe and stable operation of the converter across the entire frequency band by achieving seamless soft-start switching and low-jitter precise modulation of sawtooth waves.

[0119] In the description of this invention patent, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0120] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0121] In this invention patent, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0122] In this invention patent, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0123] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0124] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A frequency modulation closed-loop control system for an isolated non-resonant soft-switching DC-DC converter, characterized in that, include: The module consists of a variable definition module, a pre-calculation module, a main algorithm module, and an output module. The variable definition module is used to define the global variables, input variables, and output variables required by the system. The global variables include the integral term PI_interal and the sawtooth wave phase Saw_phase. The input variables include the voltage reference value V. ref Voltage feedback value V out The runtime t and control step size Delt, the output variables include the sawtooth wave phase signal v saw Target switching frequency And the drive signals Sp1~Sp4 for the four switching transistors; The pre-calculation module is used to read the input variables and calculate the voltage reference value V after starting the current calculation step. ref With voltage feedback value V out The voltage error between them is determined, and the time-sharing switch between the soft start phase and the normal closed-loop control phase is judged based on the running time. The main algorithm module is used to execute the frequency modulation and drive logic generation algorithm, including the soft start stage, the normal closed-loop control stage, the sawtooth wave generation stage, and the output mapping and logic generation stage. The output module is used to update and output the sawtooth wave phase signal v in real time. saw Target switching frequency And the drive signals Sp1~Sp4 of the four switching transistors, and end the current calculation step.

2. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 1, characterized in that, The soft-start phase in the main algorithm module takes effect when the running time is less than a set soft-start time threshold. During this phase, the real-time switching frequency f... s As the running time t increases from the initial set frequency f s_start Linearly increasing to the target switching frequency f s_end Meanwhile, based on the current linearly increasing real-time switching frequency f s The integral term PI_interal of the PI regulator used for closed-loop control is dynamically precharged in real time to follow the current switching frequency, so as to achieve a smooth and seamless transition when switching from the soft start stage to the normal closed-loop control stage.

3. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 2, characterized in that, During the soft-start phase, the real-time switching frequency f s As the running time t increases from the initial set frequency f s_start Linearly increasing to the target switching frequency f s_end The formula is: ； At this stage, to ensure no sudden changes in current or frequency at the moment of switching to closed loop, the current linearly increasing real-time switching frequency f is used. s Real-time dynamic pre-charge of the integral term PI_interal of the PI controller: ； In the formula, For proportional gain, The integral gain is achieved through the real-time dynamic pre-charge, ensuring that the integrator state of the PI regulator is precisely matched to the corresponding output state at the moment of switching into the normal closed-loop control phase, thus achieving seamless and smooth switching.

4. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 3, characterized in that, The normal closed-loop control phase in the main algorithm module takes effect when the running time t is greater than or equal to the set soft-start time threshold. During this phase, the target switching frequency is calculated by performing cumulative integral and proportional calculations based on the voltage error. and the target switching frequency Apply upper and lower limit constraints.

5. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 4, characterized in that, During the normal closed-loop control phase, pre-charging is stopped and normal closed-loop PI regulation is initiated, as follows: First, perform discrete integration and accumulation on the voltage error: ； Subsequently, the target switching frequency is calculated. : ； In the formula, For proportional gain, For integral gain; Finally, regarding the target switching frequency Apply upper and lower limit constraints to restrict it to a set safe frequency range.

6. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 5, characterized in that, In the sawtooth wave generation stage of the main algorithm module, voltage-controlled oscillator logic is used based on a determined target switching frequency. The sawtooth wave phase is incrementally accumulated with the control step size Delt; when the phase accumulation value is greater than or equal to 1.0, zero-crossing reset is performed by subtracting 1.0 to retain the boundary residual, so as to eliminate frequency jitter caused by digital discretization.

7. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 6, characterized in that, During the sawtooth wave generation stage, according to the determined target switching frequency Using the control step size Delt, calculate the phase increment Δθ within the current step size. ×Delt, and update the sawtooth wave phase: ； When Saw_phase ≥ 1.0, a zero-crossing reset is triggered; to eliminate frequency jitter and phase truncation errors caused by digital discretization control, a reset calculation that retains the boundary residuals is used during reset. ； The retained residuals ensure that the average frequency of the output waveform is equal to the macroscopic period. This effectively suppresses high-frequency digital jitter.

8. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 7, characterized in that, The output mapping and logic generation stage in the main algorithm module performs multi-comparator logic operations based on a preset modulation reference and the sawtooth wave phase (Saw_phase) obtained in the sawtooth wave generation stage, and combines this with gate logic combination operations to directly generate the drive signals Sp1~Sp4 for four switching transistors; wherein, the multi-comparator logic operations include: The first comparator logic Cmp1 is generated by comparing the first preset reference with the sawtooth wave phase Saw_phase. The second comparator logic Cmp2 is generated by comparing the second preset reference with the sawtooth wave phase Saw_phase. The third comparator logic Cmp3 is generated by comparing the sawtooth wave phase Saw_phase with the first preset reference. The fourth comparator logic, Cmp4, is generated by comparing the third preset reference with the sawtooth wave phase, Saw_phase. Among them, the first driving signal Sp1 of the four switching transistors is taken from the first comparator logic Cmp1, the fourth driving signal Sp4 is taken from the second comparator logic Cmp2, the third driving signal Sp3 is taken from the third comparator logic Cmp3, and the second driving signal Sp2 is taken from the combination gate logic signal obtained by multiplying the inverted signal of the fourth comparator logic Cmp4 with the third comparator logic Cmp3.

9. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 8, characterized in that, In the output mapping and logic generation stage, a set of fixed modulation references is defined, including a first preset reference mod. 05 = 0.5, Second preset benchmark mod mul1 = 0.25 and the third preset benchmark v tri_mod = 0.75; Perform multiplexer logic operations based on the current sawtooth wave phase (Saw_phase) and the above reference: The first comparator logic Cmp1 compares 0.5 with Saw_phase. If 0.5 > Saw_phase, then Cmp1 = 1; otherwise, it is 0. The second comparator logic Cmp2: compares 0.25 with Saw_phase. If 0.25 > Saw_phase, then Cmp2 = 1; otherwise, it is 0. The third comparator logic Cmp3: compares Saw_phase with 0.

5. If 0.5 < Saw_phase, then Cmp3 = 1; otherwise, it is 0. The fourth comparator logic Cmp4 compares 0.75 with Saw_phase. If 0.75 < Saw_phase, then Cmp4 = 1; otherwise, it is 0. After obtaining the comparator output, the drive signal for the second switch is calculated using combinational gate logic. That is, the driving signal Sp2 is equal to the inverted Cmp4 multiplied by Cmp3, expressed by the formula: 。 10. The frequency modulation closed-loop control system for the isolated non-resonant soft-switching DC-DC converter according to claim 9, characterized in that, In the output module, the results generated by the main algorithm module are mapped and assigned to the specified physical or simulation output port in real time, resulting in the logical outputs of the drive signals for the four switching transistors. Specifically, drive signal Sp1 is logically equal to Cmp1, drive signal Sp2 is logically equal to the inverted Cmp4 multiplied by Cmp3, drive signal Sp3 is logically equal to Cmp3, and drive signal Sp4 is logically equal to Cmp4. The formulas are expressed as follows: ； This concludes the current control and simulation step size calculation.

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