Symmetric wavelet generation method and apparatus, microcontroller chip and computer readable storage medium

Abstract

The application discloses a symmetrical wave emitting method and device, a microcontroller chip and a computer readable storage medium. The method comprises the following steps: obtaining three-phase current values of a three-phase inverter, performing magnetic field oriented control calculation on the processed three-phase current values to obtain upper bridge arm duty cycles and lower bridge arm duty cycles of the three phases; calling a wave emitting function to execute dead zone variable control logic to dynamically correct the upper bridge arm duty cycles and the lower bridge arm duty cycles of the three phases; setting values of corresponding shadow registers based on the corrected upper bridge arm duty cycles or the corrected lower bridge arm duty cycles; starting a timer output module counter, and matching a counter value of the counter with the values of the shadow registers to output a center-symmetrical pulse width modulation waveform. The method calls the wave emitting function to execute the dead zone variable control logic to dynamically correct the upper bridge arm duty cycles and the lower bridge arm duty cycles of the three phases, ensures that the lower bridge arm is turned on after the upper bridge arm is completely turned off, and fundamentally avoids the short circuit burning risk caused by simultaneous conduction.

Description

Technical Field

[0001] The present invention relates to the field of motor control technology, and in particular to a symmetrical wave generation method, device, microcontroller chip and computer-readable storage medium. Background Technology

[0002] In modern motor control systems, pulse width modulation (PWM) technology is one of the techniques for achieving efficient and precise control.

[0003] In a three-phase inverter, each phase consists of an upper bridge arm switch and a lower bridge arm switch. The switch needs time to go from being turned on to being completely turned off and from being turned off to being fully turned on. In order to prevent the upper and lower bridge arms from being directly short-circuited, a double turn-off time is inserted to ensure that the next switch can only start to conduct after the previous switch has been completely and thoroughly turned off.

[0004] Traditional hardware PWM generation methods rely on counters and comparator registers to achieve edge-aligned or center-aligned pulse width modulation, with hardware inserting a double-off time (dead-time insertion) during complementary PWM channel switching. However, the dead-time insertion in this method applies to all channels, and can only use the dead time required by the worst-case channel as the independent dead time for the upper and lower bridges of all channels. This can easily lead to short circuits and burnout of the upper and lower bridge arms due to simultaneous conduction. Summary of the Invention

[0005] This invention provides a symmetrical wave generation method, apparatus, microcontroller chip, and computer-readable storage medium to solve the technical problem that the prior art can only take the dead time required by the worst channel as the independent dead time of the upper and lower bridges of all channels, which leads to the upper and lower bridge arms being short-circuited and burned out due to simultaneous conduction.

[0006] According to one aspect of the present invention, a symmetrical wave generation method is provided, comprising: Obtain the three-phase current values ​​of the three-phase inverter, perform field-oriented control calculations on the processed three-phase current values, and obtain the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases; The waveform generation function is called to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases; Based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, set the corresponding shadow register values ​​respectively; The counter of the timer output module is started, and the count value of the counter is matched with the value of the shadow register to output a centrally symmetrical pulse width modulation waveform.

[0007] According to another aspect of the present invention, a symmetrical wave transmitting device is provided, comprising: The acquisition module is used to acquire the three-phase current values ​​of the three-phase inverter, perform field-oriented control calculations on the processed three-phase current values, and obtain the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases. The correction module is used to call the waveform generation function to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases; The setting module is used to set the values ​​of the corresponding shadow registers based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, respectively. The timer output module is used to match the counter value with the value of the shadow register and output a centrally symmetrical pulse width modulation waveform.

[0008] According to another aspect of the present invention, a microcontroller chip is provided, the microcontroller chip comprising: at least one processor; and on-chip memory communicatively connected to the at least one processor; The on-chip memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the symmetrical wave generation method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the symmetrical wave generation method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the symmetrical wave generation method described in any embodiment of the present invention.

[0011] The technical solution of this invention solves the technical problem that the existing technology can only take the dead time required by the worst channel as the independent dead time of the upper and lower bridge arms of all channels, which leads to short circuit and burnout of the upper and lower bridge arms due to simultaneous conduction. This is achieved by calling the waveform function to execute the dead time variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart illustrating a symmetrical wave generation method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart illustrating a symmetrical wave generation method provided in Embodiment 2 of the present invention; Figure 3 This is a flowchart illustrating a symmetrical wave generation method provided in Embodiment 3 of the present invention; Figure 4 This is a flowchart illustrating a symmetrical wave generation method provided in Embodiment 4 of the present invention; Figure 5 A flowchart illustrating a symmetrical wave generation method according to a specific embodiment of the present invention; Figure 6 A timing logic diagram of a symmetrical wave generation method provided in another specific embodiment of the present invention; Figure 7 This is a schematic diagram of a symmetrical wave-generating device provided in Embodiment 5 of the present invention; Figure 8 This is a schematic diagram of the structure of a microcontroller chip for a symmetrical wave generation method according to an embodiment of the present invention; Figure 9 This is a structural block diagram of an electrical device provided in Embodiment 7 of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention. It should be understood that the various steps described in the method embodiments of the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0016] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0019] The names of the messages or information exchanged between the multiple devices in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0020] Example 1 Figure 1 This is a flowchart illustrating a symmetrical wave generation method provided in Embodiment 1 of the present invention. This method is applicable to scenarios requiring compatibility with multiple power devices in three-phase inverter drives. The method can be executed by a symmetrical wave generation device and is generally integrated on a microcontroller chip.

[0021] like Figure 1 As shown, the symmetrical wave generation method provided in Embodiment 1 of the present invention includes the following steps: S110. Obtain the three-phase current values ​​of the three-phase inverter, and perform field-oriented control calculations on the processed three-phase current values ​​to obtain the duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm of the three phases.

[0022] It should be noted that several basic steps precede this step, such as system power-on, interrupt triggering, and initiating SPI transmission via the serial peripheral interface. The specific details of these steps are described in the detailed embodiments below and will not be elaborated upon here.

[0023] In this embodiment, after the interrupt triggering step and the SPI transmission step are executed synchronously, the analog-to-digital converter (ADC) module is started to sample the three-phase current to obtain the three-phase current values ​​of the three-phase inverter. Specifically, after the ADC module completes sampling, a callback is triggered to process the three-phase current values ​​(processing includes filtering, unit conversion, etc.); the raw data from the resolver or encoder acquired by SP1 is read and parsed to obtain the rotor electrical angle (used for field-oriented control calculation); and field-oriented control calculations are performed on the processed three-phase current values ​​to obtain the upper and lower bridge arm duty cycles of the three phases.

[0024] The timer output module supports independent configuration of multiple channels, mapping six timer output channels to the upper and lower arms of the U, V, and M phases respectively, with each channel's clock cycle parameter adjustable independently. The duty cycles of the upper and lower arms of the three phases can include those for phase U, phase V, and phase W. The timer output module can be either a TOM (TimerOutput Module) or an ATOM (ARU-connected Timer Output Module). TOM is a basic 16-bit output unit, while ATOM is an enhanced 24-bit output unit with ARU (Advanced Routing Unit) interconnect capability.

[0025] The core algorithm for field-oriented control may include Clarke transform, Park transform, PI controller calculation of three-phase voltage, inverse Park transform, and space vector modulation. This part is existing technology and will not be described in detail.

[0026] S120. Call the waveform generation function to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases.

[0027] In this embodiment, during the process of dynamically correcting the duty cycles of the upper and lower bridge arms of the three phases using the variable dead-time control logic, the dead-time of the upper and lower bridge arms of the three phases is dynamically adjusted according to the current operating conditions. Different calculation methods are used to correct the independent dead-time of the upper and lower bridge arms of the three phases (i.e., to correct the duty cycles of the upper and lower bridge arms) depending on the dead-time control mode. The correction of the independent dead-time of the upper and lower bridge arms is based on the calculated dead-time of the upper and lower bridge arms of the three phases. The dead-time control mode can be selected according to the requirements of the current scenario.

[0028] In this embodiment, the dead-time control mode can include a simultaneous upper and lower bridge dead-time compensation mode and a superimposed upper and lower bridge dead-time mode, and the two modes can be used simultaneously. The simultaneous upper and lower bridge dead-time compensation mode is suitable for scenarios with high duty cycle accuracy requirements, such as low-speed motor control and servo positioning; the superimposed upper and lower bridge dead-time mode is suitable for scenarios with high real-time requirements and low duty cycle accuracy requirements, such as high-speed motor control.

[0029] In the simultaneous dead-zone compensation mode for both upper and lower bridges, the duty cycle of the upper bridge arm is calculated as the upper bridge arm conduction time minus the upper bridge arm dead-zone time, thus achieving the effect of delaying the opening of the upper bridge arm and turning it off in advance. In the simultaneous dead-zone compensation mode for both upper and lower bridges, the duty cycle of the lower bridge arm is calculated as the lower bridge arm conduction time plus the lower bridge arm dead-zone time, thus achieving the same effect of delaying the opening of the lower bridge arm and turning it off in advance, forming a staggered complement with the upper bridge arm.

[0030] In the dead-zone mode of superimposed upper and lower bridges, the duty cycle of the upper bridge arm is directly adopted as the target value, and only the range of the duty cycle of the upper bridge arm is constrained; in the dead-zone mode of superimposed upper and lower bridges, the lower bridge arm superimposes the total time of all dead zones at one time.

[0031] S130. Based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, set the corresponding shadow register values ​​respectively.

[0032] It should be noted that in applications such as motor control, it is necessary to simultaneously control one upper-arm MOSFET and one lower-arm MOSFET. These two MOSFETs must conduct in a complementary manner; when the upper arm is on, the lower arm must be off. Directly using the toggle function of a register to control both pins is unreliable. A more reliable method is to control the upper arm's on-time with a first shadow register and its off-time with a second shadow register, and vice versa. When a dead time needs to be inserted, only the value of one of the shadow registers needs to be modified. To prevent shoot-through between the upper and lower arms, the upper arm needs to be turned on slightly later and the lower arm turned off slightly earlier. Therefore, the on-time of the upper arm is increased by a dead time, which is reflected in the corrected duty cycle of both the upper and lower arms.

[0033] In this embodiment, if a clock cycle parameter is configured and set to operate the upper bridge arm of the timer output module 1, then only the rising edge position and falling edge position of the upper bridge arm need to be calculated, and the pulse width modulation waveform of the lower bridge arm is directly generated by the complementary logic without separate calculation; if a clock cycle parameter is configured and set to operate the lower bridge arm of the timer output module 1, then only the rising edge position and falling edge position of the lower bridge arm need to be calculated, and the pulse width modulation waveform of the upper bridge arm is directly generated by the complementary logic without separate calculation.

[0034] Specifically, the rising edge position A (i.e., the turn-on point) and falling edge position B (i.e., the turn-off point) of the upper bridge arm are calculated using a centrally symmetric formula based on the maximum count value of one clock cycle and the corrected upper bridge arm duty cycle. The rising edge position A of the upper bridge arm is less than half of the maximum count value of one clock cycle (pwmPeriod / 2), and the falling edge position B of the upper bridge arm is greater than half of the maximum count value of one clock cycle.

[0035] Specifically, the rising edge position A (i.e., the turn-on point) and falling edge position B (i.e., the turn-off point) of the lower bridge arm are calculated using a centrally symmetric formula based on the maximum count value of one clock cycle and the corrected duty cycle of the lower bridge arm. The rising edge position A of the lower bridge arm is less than half of the maximum count value of one clock cycle (pwmPeriod / 2), and the falling edge position B of the lower bridge arm is greater than half of the maximum count value of one clock cycle.

[0036] In this embodiment, if the parameter for one clock cycle is set to operate the upper bridge arm, the rising edge position A of the upper bridge arm is written to the first shadow register (SR1) of the timer output channel to control the upper bridge arm to be turned on or the lower bridge arm to be turned off; the falling edge position B of the upper bridge arm is written to the second shadow register (SR0) of the timer output channel to control the upper bridge arm to be turned off or the lower bridge arm to be turned on. The same applies to the lower bridge arm, which will not be described in detail here.

[0037] It should be noted that, according to the characteristics of the shadow register, the newly written value will not take effect immediately. It needs to wait until the current pulse width modulation period ends and then be synchronously loaded at the beginning of the next period, so as to avoid waveform distortion caused by modifying parameters in the middle of the period.

[0038] S140. Start the counter of the timer output module, match the count value of the counter with the value of the shadow register, and output a centrally symmetrical pulse width modulation waveform.

[0039] It should be noted that the timer system (i.e., the GTM module) includes a timer output module. The GTM module is a physical circuit soldered inside the microcontroller chip, which includes: a counter, multiple matching units, a shadow register, flip-flops, and gate circuits. The timer output module can be either TOM or ATOM; no specific restriction is made here.

[0040] The timer output module uses a centrally symmetrical waveform generation method to output a centrally symmetrical pulse width modulation waveform. This centrally symmetrical generation method makes the waveform symmetrical, effectively doubling the switching frequency, improving the inductance filtering effect of the motor, and making the current waveform smoother, thereby reducing torque ripple.

[0041] In this embodiment, within one clock cycle, the counter starts counting from 0 upwards. When the count value reaches the rising edge position A, multiple matching units match the counter value with the value of the shadow register. When the first shadow register value matches, the flip-flop and gate circuits set the pin level high according to the configuration, enabling the rising edge. When the count value reaches pwmPeriod / 2, it continues counting upwards. When it reaches the falling edge position B, the flip-flop and gate circuits execute the action of the second register, setting the pin level low, enabling the falling edge. Therefore, the upper bridge arm is turned on at (pwmPeriod - pwmValue) / 2 and turned off at (pwmPeriod + pwmValue) / 2, and the lower bridge arm is turned on at (pwmPeriod + pwmValue) / 2 and turned off at (pwmPeriod - pwmValue) / 2, outputting a centrally symmetrical pulse width modulation waveform. Here, pwmValue can represent the corrected upper bridge arm duty cycle.

[0042] The present invention provides a symmetrical waveform generation method. First, the three-phase current values ​​of a three-phase inverter are obtained. Field-oriented control calculations are then performed on the processed three-phase current values ​​to obtain the duty cycles of the upper and lower bridge arms. Next, the waveform generation function is called to execute variable dead-time control logic to dynamically correct the duty cycles of the upper and lower bridge arms. Then, based on the corrected upper or lower bridge arm duty cycles, the values ​​of the corresponding shadow registers are set. Finally, the counter of the timer output module is started, and the counter value is matched with the value of the shadow register to output a centrally symmetrical pulse width modulation waveform. This method, by calling the waveform generation function to execute variable dead-time control logic to dynamically correct the duty cycles of the upper and lower bridge arms, solves the technical problem in existing technologies where only the dead time required for the worst-case channel can be used as the independent dead time for the upper and lower bridge arms of all channels, leading to short-circuit burnout due to simultaneous conduction of the upper and lower bridge arms. This method fundamentally avoids the risk of short-circuit burnout caused by simultaneous conduction. In addition, the output center-symmetrical pulse width modulation waveform can ensure the accuracy of the synthesized voltage vector and reduce torque ripple and noise.

[0043] Example 2 Figure 2 This is a flowchart illustrating a symmetrical wave generation method according to Embodiment 2 of the present invention. Embodiment 2 is an optimization based on Embodiment 1. For details not covered in this embodiment, please refer to Embodiment 1.

[0044] like Figure 2 As shown, the symmetrical wave generation method provided in Embodiment 2 of the present invention includes the following steps: S210. Obtain the three-phase current values ​​of the three-phase inverter, and perform field-oriented control calculations on the processed three-phase current values ​​to obtain the duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm of the three phases.

[0045] S220. When the dead zone control mode is determined to be the simultaneous compensation dead zone mode for both upper and lower bridges, the dead zone time of the upper bridge arm and the dead zone time of the lower bridge arm of the three phases are dynamically adjusted according to the working conditions.

[0046] Among them, the dead zone control mode can be determined as the simultaneous compensation dead zone mode for both upper and lower bridges based on the dead zone control mode selection flag. This mode is suitable for scenarios with high duty cycle accuracy requirements, such as low-speed motor control and servo positioning.

[0047] The upper and lower dead time of the three-phase bridge arm are dynamically adjusted based on real-time sampling of motor current, temperature, or load conditions.

[0048] S230. Based on the adjusted upper arm dead time and lower arm dead time of the three phases, correct the upper arm duty cycle and lower arm duty cycle of the three phases.

[0049] It should be noted that the correction of the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases can be performed independently. The correction process of the duty cycle of the upper arm and the duty cycle of the lower arm of each phase is the same. Here, we will take the correction of the duty cycle of the upper arm and the duty cycle of the lower arm of phase U as an example.

[0050] Specifically, for phase U in the three-phase system, correcting the duty cycle of the upper and lower bridge arms of phase U includes: calculating the difference between the duty cycle of the upper bridge arm of phase U and the adjusted dead time of the upper bridge arm of phase U to obtain the corrected duty cycle of the upper bridge arm of phase U; and calculating the sum of the duty cycle of the lower bridge arm of phase U and the adjusted dead time of the lower bridge arm of phase U to obtain the corrected duty cycle of the lower bridge arm of phase U. The duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm are the same value.

[0051] The formula for calculating the corrected upper arm duty cycle is: pwmValueUU=pwmValueU-UBDeadTime, where pwmValueUU represents the corrected upper arm duty cycle, pwmValueU represents the upper arm duty cycle, and UBDeadTime represents the upper arm dead time.

[0052] The formula for calculating the corrected lower arm duty cycle is: pwmValueUL=pwmValueU+LBDeadTime, where pwmValueUL represents the corrected lower arm duty cycle. Since the upper arm duty cycle and the lower arm duty cycle have the same value, pwmValueU can also represent the lower arm duty cycle, and LBDeadTime represents the lower arm dead time.

[0053] It should be noted that if the current current of the electrical equipment is large, UBDeadTime or LBDeadTime can be increased to ensure that the lower bridge arm is turned on again after the upper bridge arm is completely turned off; if the current current of the electrical equipment is small, UBDeadTime or LBDeadTime can be decreased to reduce voltage distortion and losses caused by dead time.

[0054] S240. Based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, set the corresponding shadow register values ​​respectively.

[0055] S250. Start the counter of the timer output module, match the count value of the counter with the value of the shadow register, and output a centrally symmetrical pulse width modulation waveform.

[0056] Embodiment 2 of this invention provides a symmetrical wave generation method, which specifies the process of dynamically correcting the duty cycle of the upper and lower bridge arms of the three phases. This method is suitable for scenarios with high requirements for duty cycle accuracy. In the simultaneous dead-time compensation mode of the upper and lower bridges, the duty cycle of the upper bridge arm is calculated as the upper bridge arm conduction time minus the upper bridge arm dead time, achieving the effect of delayed turn-on and early turn-off of the upper bridge arm; the duty cycle of the lower bridge arm is calculated as the lower bridge arm conduction time plus the lower bridge arm dead time, similarly achieving delayed turn-on and early turn-off of the lower bridge arm, forming a staggered complement with the upper bridge arm.

[0057] Example 3 Figure 3 This is a flowchart illustrating a symmetrical wave generation method according to Embodiment 3 of the present invention. Embodiment 3 is an optimization based on Embodiment 1. For details not covered in this embodiment, please refer to Embodiment 1.

[0058] like Figure 3 As shown, the symmetrical wave generation method provided in Embodiment 3 of the present invention includes the following steps: S310. Obtain the three-phase current values ​​of the three-phase inverter, and perform field-oriented control calculations on the processed three-phase current values ​​to obtain the duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm of the three phases.

[0059] S320. When the dead-time control mode is determined to be the superimposed dead-time mode of upper and lower bridges, the duty cycle of the upper bridge arm of the three phases is corrected to within the maximum count value of the clock cycle.

[0060] Among them, the dead zone control mode can be determined as the upper and lower bridge superimposed dead zone mode based on the dead zone control mode selection flag.

[0061] In this embodiment, when the upper and lower bridge superimposed dead zone mode is adopted, the duty cycle of the upper bridge arm is directly adopted as the target value, and the duty cycle of the upper bridge arm is constrained within the maximum count value of the clock cycle. The maximum count value of the clock cycle is the total width of the pulse.

[0062] S330: Dynamically adjust the dead time of the upper arm and the dead time of the lower arm of the three phases according to the operating conditions.

[0063] Among them, the dead time of the upper arm and the dead time of the lower arm of the three phases can be dynamically adjusted according to the real-time sampled motor current, temperature or load conditions.

[0064] S340. Based on the adjusted upper arm dead time and lower arm dead time of the three phases, the lower arm duty cycle of the three phases is corrected to obtain the corrected lower arm duty cycle.

[0065] Specifically, for phase U in the three phases, the lower arm duty cycle of phase U is corrected to obtain the corrected lower arm duty cycle, which includes: calculating the sum of the lower arm duty cycle of phase U and the adjusted lower arm dead time and upper arm dead time of phase U to obtain the corrected lower arm duty cycle of phase U.

[0066] The formula for calculating the corrected lower arm duty cycle is: pwmValueUL=pwmValueU+UBDeadTime+LBDeadTime, where pwmValueUL represents the corrected lower arm duty cycle, pwmValueU represents the lower arm duty cycle, UBDeadTime represents the adjusted upper arm dead time, and LBDeadTime represents the adjusted lower arm dead time.

[0067] S350: Based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, set the corresponding shadow register values ​​respectively.

[0068] S360. Start the counter of the timer output module, match the counter value with the value of the shadow register, and output a centrally symmetrical pulse width modulation waveform.

[0069] Embodiment 3 of this invention provides a symmetrical wave generation method for dynamically correcting the duty cycle of the upper and lower bridge arms of the three phases. This method is suitable for scenarios with high real-time requirements and low duty cycle accuracy requirements. In the upper and lower bridge superimposed dead-time mode, the duty cycle of the upper bridge arm is directly adopted as the target value, while the lower bridge arm superimposes all the dead times of the upper and lower bridge arms at once, which greatly simplifies the calculation process and improves the response speed.

[0070] Example 4 Figure 4 This is a flowchart illustrating a symmetrical wave generation method according to Embodiment 4 of the present invention. Embodiment 4 is an optimization based on the above embodiments. For details not covered in this embodiment, please refer to the above embodiments.

[0071] like Figure 4As shown, the symmetrical wave generation method provided in Embodiment 4 of the present invention includes the following steps: S410. Obtain the three-phase current values ​​of the three-phase inverter, and perform field-oriented control calculations on the processed three-phase current values ​​to obtain the duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm of the three phases.

[0072] S420: Call the waveform generation function to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases.

[0073] S430: Based on the corrected upper bridge arm duty cycle, set the values ​​of the corresponding shadow registers respectively.

[0074] In this embodiment, for each of the three phases, the rising edge and falling edge of the upper bridge arm are determined according to the maximum count value of the clock cycle and the corrected upper bridge arm duty cycle.

[0075] Specifically, for phase U in the three phases, the rising edge and falling edge corresponding to the upper bridge arm are determined according to the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after correction of phase U; the rising edge and falling edge corresponding to the upper bridge arm are written into different shadow registers respectively.

[0076] Specifically, based on the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after U-phase correction, the rising edge and falling edge corresponding to the upper bridge arm of U-phase are determined respectively, including: taking half of the difference between the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after U-phase correction as the rising edge corresponding to the upper bridge arm of U-phase; and taking the average value of the maximum count value and the duty cycle of the upper bridge arm after U-phase correction as the falling edge corresponding to the upper bridge arm of U-phase.

[0077] It is understandable that for a pulse width modulation waveform with a clock cycle number of pwmPeriod, the goal is to find two comparison values ​​such that the high-level time of the output is exactly the corrected duty cycle of the upper and lower bridge arms, pwmValueUU. The entire pulse is symmetrical about the center of the clock cycle, pwmPeriod / 2. According to the definition of central symmetry, the distance from the rising edge to the starting point 0 of the clock cycle is equal to the distance from the falling edge to the ending point of the clock cycle, i.e., the maximum count value of the clock cycle, pwmPeriod.

[0078] The formula for calculating the rising edge position A is: A = (pwmPeriod - pwmValueUU) / 2; the formula for calculating the falling edge position B is: B = (pwmPeriod + pwmValueUU) / 2; pwmPeriod represents the maximum count value (i.e., the total pulse width) of one clock cycle, and pwmValueUU represents the corrected upper bridge arm duty cycle.

[0079] In another embodiment, the values ​​of the corresponding shadow registers are set based on the corrected lower bridge arm duty cycle, which is the same as the processing method in this embodiment where the values ​​of the corresponding shadow registers are set based on the corrected upper bridge arm duty cycle.

[0080] S440. Write the rising edge and falling edge corresponding to the upper bridge arm into different shadow registers respectively.

[0081] Specifically, the rising edge position A corresponding to the upper bridge arm is written into the SR1 shadow register, and the falling edge position B corresponding to the upper bridge arm is written into the SR0 shadow register.

[0082] S450: Start the counter of the timer output module, match the counter value with the value of the shadow register, and output a centrally symmetrical pulse width modulation waveform.

[0083] Embodiment 4 of this invention provides a symmetrical waveform generation method that decouples complex control algorithms (software) from high-precision timing outputs (hardware). This allows the system to have sufficient time to process complex variable dead-time logic even at high switching frequencies (such as 6kHz or even higher), thereby improving the real-time response bandwidth of the entire system.

[0084] Based on the technical solutions of the above embodiments, this invention provides several specific implementation methods.

[0085] As one specific implementation method of this embodiment. Figure 5 This is a flowchart illustrating a symmetrical wave generation method according to a specific embodiment of the present invention, as shown below. Figure 5 As shown, it includes the following steps: Step 1: Power on the system.

[0086] In this step, the timer system is reset and the microcontroller is started; the clock and hardware peripherals are initialized; the advanced timer output channel (ATOM) is configured as a center-symmetric pulse width modulation mode, the clock period and the initial values ​​of the dead time of the upper and lower bridge arms are set, and the interrupt notification is enabled.

[0087] Step 2: Set the operating frequency of the main control loop to 6kHz.

[0088] Step 3: ATOM07_Notification interrupt triggered.

[0089] In this step, the interrupt is generated by a notification event from the Advanced Timer Output Channel (ATOM). After entering the interrupt service routine, a complete control cycle begins to be executed.

[0090] Step 4: Initiate SPI transmission.

[0091] In this step, external device data is read via the SP1 bus, including angle data from the rotary transformer or magnetic encoder, current sensor data, and fault status. After initiating the SP1 transmission, step 5 can be executed.

[0092] Step 5: ADC current sampling In this step, the ADC module is activated to sample the three-phase current.

[0093] Step 6: Trigger the callback function.

[0094] In this step, a callback is triggered after the ADC current sampling is completed. The current data is processed in this callback, including filtering, unit conversion, and saving to variables.

[0095] Step 7: Analyze the electrical angle and convert it to the latest electrical angle. In this step, the original data of the resolver or encoder acquired by SPI is read and parsed to obtain the rotor electrical angle; the angle value is updated for use in the Park transformation or Clarke transformation in step 8.

[0096] Step 8: Determine the current filtering conversion and overcurrent protection.

[0097] In this step, the sampled current value is digitally filtered and compared with the overcurrent threshold. If the current exceeds the threshold, fault protection is triggered, such as shutting down the pulse width modulation output.

[0098] Step 9: Perform magnetic field orientation control calculations to obtain the three-phase duty cycle.

[0099] Step 10: Call the wave generation function.

[0100] In this step, the three-phase duty cycle is used as input to call a custom waveform generation function, which internally executes dead-zone variable control logic.

[0101] Step 11: Determine the dead zone control mode.

[0102] In this step, the dead zone control mode is selected based on the dead zone control mode flag, which is either the simultaneous dead zone compensation mode for both upper and lower bridges or the superimposed dead zone mode for both upper and lower bridges.

[0103] Step 12: Dynamically correct the independent dead time of the upper and lower bridges.

[0104] This step corresponds to dynamically correcting the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases.

[0105] Step 13: Set the value of the shadow register.

[0106] In this step, based on the corrected duty cycles of the upper and lower bridge arms, the rising edge position A or falling edge position B of the centrally symmetrical pulse width modulation waveform is calculated, the rising edge position is written to the SR1 shadow register, and the falling edge position B is written to the SR0 shadow register. Step 13: Output complementary symmetrical pulse width modulation waveforms.

[0107] The pulse width modulation waveform automatically flips the pin level when matching the rising edge position A or the falling edge position B, generating a centrally symmetrical complementary pulse width modulation waveform with a variable dead time. The waveform is symmetrical about the midpoint of the clock cycle, with low harmonic content and small torque ripple.

[0108] As one specific implementation method of this embodiment. Figure 6 A timing logic diagram of a symmetrical wave generation method provided in another specific embodiment of the present invention. Figure 6 This demonstrates how center-symmetric ripple generation and variable dead-time insertion work together on the timeline within a single clock cycle. To prevent bridge shoot-through, the hardware strictly adheres to the following four phases during a complete on / off switching process: Phase 1 (Rising Edge Approach): The upper bridge arm is turned on with a delay, and the lower bridge arm is turned off in advance, leaving a duty cycle for the lower bridge arm in between; Phase 2 (high level in the middle): The upper bridge arm remains on and the lower bridge arm remains off. At this time, current flows through the upper bridge arm. Phase 3 (falling edge attachment): the upper bridge arm is turned off in advance, the lower bridge arm is turned on with a delay, and the upper bridge arm duty cycle is left in the middle; Phase 4 (low level in the middle): The upper bridge arm remains off, and the lower bridge arm remains on. At this time, current flows through the lower bridge arm.

[0109] Final synthesis as follows Figure 6 The diagram shows a set of smooth, symmetrical, and secure complementary drive waveforms (i.e., centrally symmetrical pulse width modulation waveforms).

[0110] Example 5 Figure 7 This is a schematic diagram of a symmetrical wave-generating device provided in Embodiment 5 of the present invention. The symmetrical wave-generating device can be implemented by software and / or hardware, and is generally integrated on a microcontroller chip.

[0111] like Figure 7 As shown, the device includes: an acquisition module 110, a correction module 120, a setting module 130, and a timer output module 140.

[0112] The acquisition module 110 is used to acquire the three-phase current values ​​of the three-phase inverter, perform field-oriented control calculations on the processed three-phase current values, and obtain the duty cycle of the upper bridge arm and the duty cycle of the lower bridge arm of the three phases. The correction module 120 is used to call the waveform generation function to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases. Setting module 130 is used to set the values ​​of the corresponding shadow registers based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, respectively. The timer output module 140 is used to match the counter value with the value of the shadow register and output a centrally symmetrical pulse width modulation waveform.

[0113] In this embodiment, the device first acquires the three-phase current values ​​of the three-phase inverter through the acquisition module 110, performs field-oriented control calculations on the processed three-phase current values, and obtains the duty cycles of the upper and lower bridge arms of the three phases. Next, the correction module 120 calls the waveform generation function to execute dead-zone variable control logic to dynamically correct the duty cycles of the upper and lower bridge arms of the three phases. Then, the setting module 130 sets the values ​​of the corresponding shadow registers based on the corrected upper or lower bridge arm duty cycles. Finally, the timer output module 140 matches the counter's count value with the value of the shadow registers to output a centrally symmetrical pulse width modulation waveform.

[0114] This embodiment provides a symmetrical wave generator that ensures that the lower bridge arm is turned on again after the upper bridge arm is completely turned off, fundamentally avoiding the risk of short circuit and burnout caused by simultaneous conduction.

[0115] Furthermore, the correction module 120 includes: The adjustment submodule is used to dynamically adjust the dead time of the upper arm and the dead time of the lower arm of the three phases according to the working conditions when the dead zone control mode is determined to be the dead zone compensation mode of both upper and lower bridges. The correction submodule is used to correct the upper arm duty cycle and lower arm duty cycle of the three phases based on the adjusted upper arm dead time and lower arm dead time of the three phases.

[0116] Based on the above optimizations, the revised sub-modules include: The first calculation unit is used to calculate the difference between the upper arm duty cycle of phase U and the adjusted upper arm dead time of phase U in the three phases, so as to obtain the corrected upper arm duty cycle of phase U. The second calculation unit is used to calculate the sum of the duty cycle of the lower arm of phase U and the dead time of the lower arm of phase U after adjustment, so as to obtain the corrected duty cycle of the lower arm of phase U. The duty cycle of the upper bridge arm is the same as that of the lower bridge arm.

[0117] Furthermore, the correction module 120 includes: The first correction submodule is used to correct the duty cycle of the upper bridge arm of the three phases to within the maximum count value of the clock cycle when the dead zone control mode is determined to be the upper and lower bridge superimposed dead zone mode. The adjustment submodule is used to dynamically adjust the dead time of the upper arm and the dead time of the lower arm of the three-phase bridge according to the operating conditions. The second correction submodule is used to correct the lower arm duty cycle of the three phases based on the adjusted upper arm dead time and lower arm dead time, so as to obtain the corrected lower arm duty cycle.

[0118] Based on the above optimizations, the second correction submodule includes: The first calculation submodule is used to calculate the sum of the lower arm duty cycle of phase U and the adjusted lower arm dead time and upper arm dead time of phase U in the three phases, so as to obtain the corrected lower arm duty cycle of phase U.

[0119] Furthermore, the setting module 130 includes: The first setting submodule is used to determine the rising edge and falling edge of the upper bridge arm for the U phase in the three phases according to the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after the U phase is corrected; and write the rising edge and falling edge corresponding to the upper bridge arm into different shadow registers respectively.

[0120] Based on the above technical solution, the first setting submodule includes: The first calculation unit is used to take half of the difference between the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after U-phase correction as the rising edge of the upper bridge arm of U-phase. The second calculation unit is used to take the average of the maximum count value and the duty cycle of the upper arm after U-phase correction as the falling edge corresponding to the upper arm of U-phase.

[0121] The above-described symmetrical wave generation device can execute the symmetrical wave generation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0122] Example 6 Figure 8 A schematic diagram of a microcontroller chip 10, which can be used to implement embodiments of the present invention, is shown. The microcontroller chip 10 is a very large-scale integrated circuit. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0123] like Figure 8As shown, the microcontroller chip 10 includes at least one processor 11 and on-chip memory, such as read-only memory (ROM) 12 and random access memory (RAM) 13, communicatively connected to the at least one processor 11. The on-chip memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the microcontroller chip 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0124] Multiple components in the microcontroller chip 10 are connected to the I / O interface 15, including: an input unit 16, an output unit 17, a storage unit 18, and a communication unit 19.

[0125] Processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Processor 11 executes the various methods and processes described above, such as a symmetric wave generation method.

[0126] In some embodiments, the symmetrical wave generation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on the microcontroller chip 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the symmetrical wave generation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the symmetrical wave generation method by any other suitable means (e.g., by means of firmware).

[0127] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0128] In some embodiments, the symmetrical wave generation method can be implemented as a computer program, which is implicitly included in a computer program product. When executed by a processor, the computer program implements the symmetrical wave generation method of the present invention. The computer program product can be understood as a software product that primarily implements its solution through a computer program. The computer program used to implement the method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer program causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0129] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0130] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0131] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0132] Example 7 Figure 9 This is a structural block diagram of an electrical device provided in Embodiment Seven of the present invention, as shown below. Figure 9 As shown, the electrical equipment includes a microcontroller chip 100. The microcontroller 100 is used to execute the symmetrical wave generation method provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0133] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A symmetrical wave generation method, characterized in that, The method includes: Obtain the three-phase current values ​​of the three-phase inverter, perform field-oriented control calculations on the processed three-phase current values, and obtain the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases; The waveform generation function is called to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases; Based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, set the corresponding shadow register values ​​respectively; The counter of the timer output module is started, and the count value of the counter is matched with the value of the shadow register to output a centrally symmetrical pulse width modulation waveform.

2. The method according to claim 1, characterized in that, The call to the waveform generation function executes the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower arms of the three phases, including: When the dead zone control mode is determined to be the simultaneous compensation dead zone mode for both upper and lower bridges, the dead zone time of the upper bridge arm and the dead zone time of the lower bridge arm of the three phases are dynamically adjusted according to the working conditions. Based on the adjusted upper arm dead time and lower arm dead time of the three phases, the upper arm duty cycle and lower arm duty cycle of the three phases are corrected.

3. The method according to claim 2, characterized in that, The step of correcting the upper arm duty cycle and lower arm duty cycle of the three phases based on the adjusted upper arm dead time and lower arm dead time includes: For phase U in the three phases, calculate the difference between the duty cycle of the upper arm of phase U and the dead time of the upper arm of phase U after adjustment, and obtain the corrected duty cycle of the upper arm of phase U. The corrected lower arm duty cycle of phase U is obtained by summing the lower arm duty cycle of phase U with the adjusted lower arm dead time. The duty cycle of the upper bridge arm is the same as that of the lower bridge arm.

4. The method according to claim 1, characterized in that, The call to the waveform generation function executes the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower arms of the three phases, including: When the dead-time control mode is determined to be the superimposed dead-time mode of upper and lower bridges, the duty cycle of the upper bridge arm of the three phases is corrected to within the maximum count value of the clock cycle. The dead time of the upper arm and the dead time of the lower arm of the three-phase bridge are dynamically adjusted according to the operating conditions. The lower arm duty cycle of the three phases is corrected based on the adjusted upper arm dead time and lower arm dead time to obtain the corrected lower arm duty cycle.

5. The method according to claim 4, characterized in that, The step of correcting the lower arm duty cycle of the three phases based on the adjusted upper arm dead time and lower arm dead time to obtain the corrected lower arm duty cycle includes: For phase U in the three phases, the duty cycle of the lower bridge arm of phase U is calculated as the sum of the adjusted dead time of the lower bridge arm and the dead time of the upper bridge arm of phase U, to obtain the corrected duty cycle of the lower bridge arm of phase U.

6. The method according to claim 1, characterized in that, Based on the corrected upper bridge arm duty cycle, set the values ​​of the corresponding shadow registers, including: For phase U in the three phases, the rising edge and falling edge of the upper bridge arm are determined according to the maximum count value of the clock cycle and the duty cycle of the upper bridge arm after correction of phase U. Write the rising and falling edges corresponding to the upper bridge arm into different shadow registers.

7. The method according to claim 6, characterized in that, The step of determining the rising and falling edges of the upper arm of phase U based on the maximum count value of the clock cycle and the duty cycle of the upper arm after correction of phase U includes: Half of the difference between the maximum count value of the clock cycle and the corrected duty cycle of the upper bridge arm of the U phase is taken as the rising edge of the upper bridge arm of the U phase. The average of the maximum count value and the corrected upper arm duty cycle of the U phase is taken as the falling edge corresponding to the upper arm of the U phase.

8. A symmetrical wave-generating device, characterized in that, The device includes: The acquisition module is used to acquire the three-phase current values ​​of the three-phase inverter, perform field-oriented control calculations on the processed three-phase current values, and obtain the duty cycle of the upper arm and the duty cycle of the lower arm of the three phases. The correction module is used to call the waveform generation function to execute the dead-zone variable control logic to dynamically correct the duty cycle of the upper and lower bridge arms of the three phases; The setting module is used to set the values ​​of the corresponding shadow registers based on the corrected upper arm duty cycle or the corrected lower arm duty cycle, respectively. The timer output module is used to match the counter value with the value of the shadow register and output a centrally symmetrical pulse width modulation waveform.

9. A microcontroller chip, characterized in that, The microcontroller chip includes: At least one processor; and on-chip memory communicatively connected to the at least one processor; The on-chip memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the symmetrical wave generation method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the symmetrical wave generation method according to any one of claims 1-7.

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