Totem-pole bridgeless pfc converter with lc realizing zvs and control method thereof

Abstract

This invention discloses a totem-pole bridgeless PFC converter and its control method for achieving ZVS using LC. The converter includes a main power circuit and a control circuit. The main power circuit includes an input AC voltage source V. in Two switching transistors, two diodes, and main inductor L b ZVS inductor L g ZVS capacitor C g and output capacitor C o The control circuit includes a voltage comparator module, an output voltage comparator module, a PI regulator, a microcontroller, a PWM module, a signal selection module, a current comparator module, an AC input differential sampling circuit, an output voltage sampling circuit, and a current sampling circuit. The LC branch of the main power circuit is connected between the switching node and ground, providing a reverse path for negative current. The converter's main inductor operates in continuous current mode, and only high-frequency triangular ripple current flows through the LC branch inductor. The two currents combine to form the TCM current, which enables ZVS conduction of the switching transistor.

Description

Technical Field

[0001] This invention relates to power electronic power factor correction technology, and in particular to a totem pole bridgeless PFC converter and control method that achieves ZVS using LC. Background Technology

[0002] In recent years, with the rapid development of modern power electronics technology, the requirements of various electrical equipment for power quality have been continuously increasing. In particular, in scenarios that require AC-DC power conversion, such as data center power supplies, new energy charging, industrial switching power supplies, and portable charging equipment, power factor correction circuits must be added to the front end to improve power quality, reduce harmonic pollution, and increase the utilization rate of power.

[0003] Boost PFC converters, as the most traditional power factor correction circuits, are widely used due to their simple design and low cost. However, they suffer from diode reverse recovery issues and the inductor current can only operate in continuous or discontinuous current mode, resulting in the switching transistors generally operating in hard switching mode, leading to high switching losses, low efficiency, and a limited switching frequency. Totem-pole bridgeless PFC is an optimized design based on the traditional Boost PFC converter. It uses two switching transistors instead of the two diodes on the rectifier bridge and places the boost inductor on the input side of the converter, thus eliminating the rectifier bridge used for rectification at the front end of the Boost PFC converter. Although totem-pole bridgeless PFC has advantages over other PFC topologies such as fewer components, higher power density, and lower common-mode noise, its switching transistors still operate in hard switching mode most of the time, resulting in significant switching losses due to voltage and current overlap during switching. Existing methods for achieving soft switching in converters involve controlling the inductor current to allow it to have a negative current. This allows the charge on the junction capacitance of the switching transistor to be carried away before it is turned on, achieving zero-voltage turn-on. However, this method often requires four switching transistors to achieve reverse current flow, which further increases the cost of the converter.

[0004] Therefore, developing a method that can achieve zero-voltage turn-on of the switching transistors across the entire range, ensuring the efficiency of the converter, without excessively increasing the cost of the converter, is a problem that researchers in this field urgently need to solve. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a totem-pole bridgeless PFC converter that achieves ZVS using LC. This converter adds an LC branch to the traditional totem-pole bridgeless PFC converter. This branch is connected between the switching node and ground. When the converter's main transistor is turned on, the negative current can be freewheeled through the LC branch. At the same time, the generated negative current also carries away the charge of the junction capacitance of the switching transistor, enabling the converter to achieve zero-voltage conduction across the entire range. In addition, due to the presence of the LC branch, the boost inductor at the front end can operate in continuous current mode, greatly reducing the impact of high-frequency ripple.

[0006] To achieve the above objectives, the technical solution adopted by this invention is as follows: a totem-pole bridgeless PFC converter that implements ZVS using LC, comprising a main power circuit and a control circuit, wherein the main power circuit includes an input AC voltage source v in First switching transistor Q1, second switching transistor Q2, first diode D1, second diode D2, main inductor L b ZVS inductor L g ZVS capacitor C g The first junction capacitor C1, the second junction capacitor C2, and the output capacitor C o The control circuit includes an input voltage comparison module, an output voltage comparison module, a PI regulator, a microcontroller, a PWM module, a signal selection module, a current comparison module, an AC input differential sampling circuit, an output voltage sampling circuit, and a current sampling circuit.

[0007] The input AC voltage source of the converter v in One end is connected to the main inductor L b One end is connected to the first terminal, and the other end is connected to the negative terminal of the second diode D2. The main inductor L b Connect the source of the first switching transistor Q1 and the drain of the second switching transistor Q2. The drain of the first switching transistor Q1 is connected to the cathode of the first diode D1. The source of the second switching transistor Q2 is connected to the anode of the second diode D2. The source of the first switching transistor Q1 and the drain of the second switching transistor Q2 are connected to switching node A. The anode of the first diode D1 and the cathode of the diode D2 are connected to node B. The ZVS inductor L in the LC branch... g and ZVS capacitor C g The circuit is connected in series, with one end of the LC branch connected to switch node A and the other end connected to the positive terminal of the second diode D2. The first junction capacitance C1 is connected in parallel across the first switch Q1, and the second junction capacitance C2 is connected in parallel across the second switch Q2. The output capacitor C... o One end is connected to the drain of the first switching transistor Q1 and the cathode of the first diode D1, respectively, and the other end is connected to the ZVS capacitor C in the LC branch. g The source of the second switch Q2 is connected to the positive terminal of the second diode D2.

[0008] The AC input differential sampling circuit is connected to the input AC voltage source v respectively. in The input voltage comparison module is connected to the microcontroller, and one end of the output voltage sampling circuit is connected to the output capacitor C. o The other end connects to the output voltage comparison module and the microcontroller. The output voltage comparison module is connected to the reference voltage V. ref The circuit consists of a PI regulator and an output voltage sampling circuit. The PI regulator is connected to a microcontroller. The Mux signal generated by the microcontroller enters the signal selection module. The microcontroller calculates the turn-off time t of the switching transistor. off The signal enters the PWM module to generate the boost diode signal PWM_B and the synchronous rectifier diode signal PWM_SR. PWM_B and PWM_SR then enter the signal selection module to generate the corresponding drive signals for the first switch Q1 and the second switch Q2. The current sampling circuit acquires the signal from the main inductor L. b With ZVS inductor L g The sum of currents i A The output of the current sampling circuit is connected to the input terminals of two current comparison modules, and the other input terminal of each current comparison module is connected to the reference current I. c and-I c The output of the current comparison module is connected to the signal selection module to generate an NCD signal that enters the PWM module.

[0009] A control method for a totem-pole bridgeless PFC converter that implements ZVS using LC is proposed. The control method consists of two parts: digital control and analog control.

[0010] The specific steps of analog control are as follows:

[0011] Step 1: The AC input differential sampling circuit acquires the input AC voltage source V. in live wire voltage and neutral line voltage The input AC voltage is then sent to the input voltage comparison module for comparison. and Perform differential calculations to obtain the input AC voltage. .

[0012] Step 2: The output voltage sampling circuit samples the output capacitor C. o The voltage at both ends is sampled to obtain the output voltage V. o It is then fed into the output voltage comparison module and compared with the reference voltage V. ref By comparison, the error voltage v is obtained. ea .

[0013] Step 3: Set the error voltage v ea Send to the PI controller, based on u in Vo v ea Minimum current I for achieving ZVS zvs ZVS inductor L g The value of L gv and main inductor L b The value of L bv Calculate the turn-off time t of a switching transistor. off The other switch is complementary and conducts.

[0014] Step 4: During the positive half-cycle of the power frequency, sample the current i obtained by the current sampling circuit. A The reference current I generated by the microcontroller c The signal is fed into the current comparison module for comparison. The NCD signal generated by the current comparison module is used to turn off the second switch Q2. During the negative half-cycle of the power frequency, the current i sampled by the current sampling circuit is... A The reference current -I generated by the microcontroller c The signals are compared using a current comparison module. The NCD signal generated by the current comparison module is used to turn off the first switch Q1. During the positive and negative half-cycles, the conduction timing of the first switch Q1 and the second switch Q2 is opposite. During the positive half-cycle, the second switch Q2 acts as a boost switch and the first switch Q1 acts as a synchronous rectifier. During the negative half-cycle, the first switch Q1 acts as a boost switch and the second switch Q2 acts as a synchronous rectifier. Therefore, the selection of the PWM signals for the first switch Q1 and the second switch Q2 is achieved using a signal selection module. During the positive half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_B and the PWM signal for the first switch Q1 is PWM_SR. During the negative half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_SR and the PWM signal for the first switch Q1 is PWM_B.

[0015] The specific steps of digital control are as follows:

[0016] Step 1: The microcontroller's ADC reads the input voltage u collected by the input voltage sampling circuit. in The output voltage V collected by the output voltage sampling circuit o and the error voltage signal v from the PI controller ea .

[0017] Step II: The sampled voltage signal is converted in the microcontroller to obtain a voltage value consistent with the actual voltage signal, which is used to calculate the turn-off time t of the switching transistor. off At the same time, the microcontroller determines the input voltage u in The sign of u in When u > 0, the microcontroller sends a judgment signal Mux=1; when u in When <0, the microcontroller sends a judgment signal Mux=0.

[0018] Step III: Calculate the turn-off time t of the switching transistor based on the result of step 2. off This controls the count of the advanced timer in the microcontroller. The timer is turned off by external triggering of the microcontroller. The NCD signal emitted by the analog current comparator circuit enters the microcontroller and serves as the signal source for external triggering. The timer is turned off after the NCD signal is triggered.

[0019] Step IV, Reference Current I c and-I c The input voltage u is generated by the DAC function of the microcontroller and sampled within the microcontroller. in The signal is converted to a reference current signal and configured as a dual-channel output in the analog circuit to be compared with the current i acquired by the current sampling module. A Compare them.

[0020] The converter operates symmetrically in the positive and negative half-cycles. For the positive half-cycle of the AC input voltage source, the converter's operating modes are as follows:

[0021] Mode 1, time t0 to t1: Second switch Q2 is turned on, first switch Q1 is turned off, main inductor L b and ZVS inductor L g The voltage across the terminals is the input voltage u. in The inductor current increases linearly, and the current i A Main inductor L b and ZVS inductor L g The sum of the currents also increases linearly.

[0022] Mode 2, time t1 to t2: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The first junction capacitance C1 is discharged, and the second junction capacitance C2 is charged. This process takes a very short time, and the current i can be considered as... A Constant.

[0023] Mode 3, time t2 to t3: First switch Q1 turns on with zero voltage, second switch Q2 turns off, main inductor L... b and ZVS inductor L g The voltage across the two ends is u in -V o The inductor current decreases linearly, and at time t3, the current i A It dropped to 0.

[0024] Mode 4, time t3 to t4: Current i A The current flows in reverse, and the negative current forms a loop through the first switch Q1 and the LC branch. At time t4, the first switch Q1 is turned off, and the current drops to its minimum value.

[0025] Mode 5, time t4 to t5: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The second junction capacitor C2 is discharged, and the first junction capacitor C1 is charged. This process is very short, and the current i can be considered as... A Constant.

[0026] Mode 6, time intervals t5 to t6: Due to the reverse current, the charge on the junction capacitance C2 of the second switch Q2 can be completely discharged. Therefore, at time t5, the second switch Q2 turns on with zero voltage, and the main inductor L... b and ZVS inductor L g The voltage across the terminals is the input voltage u. in The inductor current increases linearly, and the next switching cycle begins after this mode ends.

[0027] Compared with the prior art, the significant advantages of this invention are as follows: The totem-pole bridgeless PFC converter with ZVS implemented by LC proposed in this invention reduces the number of switching transistors used while still achieving zero-voltage turn-on across the entire range, thus improving the converter's operating efficiency and reducing its cost. It also significantly reduces the current ripple of the input-side boost inductor and the impact of grid-side current harmonics, making the design of the EMI filter simpler. Attached Figure Description

[0028] Figure 1 This is an overall block diagram of a totem-pole bridgeless PFC converter and its control strategy that implements ZVS using LC.

[0029] Figure 2 This is a schematic diagram of the conduction timing and key waveforms of each switch in a switching cycle of a totem pole bridgeless PFC converter that implements ZVS using LC.

[0030] Figure 3 This is a schematic diagram of the key waveforms of a totem-pole bridgeless PFC converter that implements ZVS using LC within the power frequency cycle.

[0031] Figure 4 This diagram illustrates the operating modes of a totem-pole bridgeless PFC converter with ZVS implemented by LC during one switching cycle. In the diagram, red represents non-conducting and black represents conducting. Detailed Implementation

[0032] The technical solutions of the present invention will be described more comprehensively and completely below with reference to the accompanying drawings of the embodiments of the present invention. The described embodiments are only some embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0033] Combination Figures 1-4 The present invention proposes a totem-pole bridgeless PFC converter with ZVS implemented by LC, comprising a main power circuit and a control circuit, wherein the main power circuit includes an input AC voltage source v in First switching transistor Q1, second switching transistor Q2, first diode D1, second diode D2, main inductor L b ZVS inductor L g ZVS capacitor C g The first junction capacitor C1, the second junction capacitor C2, and the output capacitor C o The control circuit includes an input voltage comparison module, an output voltage comparison module, a PI regulator, a microcontroller, a PWM module, a signal selection module, a current comparison module, an AC input differential sampling circuit, an output voltage sampling circuit, and a current sampling circuit.

[0034] As a specific example, the input AC voltage source v of the converter in One end is connected to the main inductor L b One end is connected to the first terminal, and the other end is connected to the negative terminal of the second diode D2. The main inductor L b The circuit is connected to the source of the first switching transistor Q1 and the drain of the second switching transistor Q2. The drain of the first switching transistor Q1 is connected to the cathode of the first diode D1, and the source of the second switching transistor Q2 is connected to the anode of the second diode D2. The source of the first switching transistor Q1 and the drain of the second switching transistor Q2 are connected to switch node A, and the anode of the first diode D1 and the cathode of the second diode D2 are connected to node B. The ZVS inductor L in the LC branch... g and ZVS capacitor C g The transistors are connected in series, with one end connected to switch node A and the other end connected to the positive terminal of the second diode D2. The first junction capacitance C1 is connected in parallel across the first switch Q1, and the second junction capacitance C2 is connected in parallel across the second switch Q2. The output capacitor C... o One end is connected to the drain of the first switching transistor Q1 and the cathode of the first diode D1, respectively, and the other end is connected to the ZVS capacitor C in the LC branch. g The source of the second switch Q2 is connected to the positive terminal of the second diode D2.

[0035] As a specific example, the key waveforms of this invention during the switching cycle are as follows: Figure 2 As shown, the current flowing through the switching transistor in the totem-pole bridgeless PFC converter with ZVS implemented by LC is i. A The main inductor current is i Lb The current in the LC branch is i Lg The current relationship is as follows:

[0036] ,

[0037] During the dead time interval t1 to t2, the junction capacitance C1 of the first switch Q1 is affected by the peak current i. pk Charging and discharging are performed to achieve soft switching of the first switching transistor Q1. During the dead time t4-t5, the junction capacitance C2 of the second switching transistor Q2 is reduced by the negative peak current I. zvs Charging and discharging are performed to achieve soft switching of the second switching transistor Q2.

[0038] As a specific example, the control method of a totem pole bridgeless PFC converter with ZVS implemented by LC can be divided into two parts: digital control and analog control.

[0039] The specific steps of analog control are as follows:

[0040] Step 1: The AC input differential sampling circuit acquires the input AC voltage source V. in live wire voltage and neutral line voltage The input AC voltage is then sent to the input voltage comparison module for comparison. and Perform differential calculations to obtain the input AC voltage. .

[0041] Step 2: The output voltage sampling circuit samples the output capacitor C. o The voltage at both ends is sampled to obtain the output voltage V. o It is then fed into the output voltage comparison module and compared with the reference voltage V. ref By comparison, the error voltage v is obtained. ea .

[0042] Step 3: Set the error voltage v ea Send to the PI controller, based on u in V o v ea Minimum current I for achieving ZVS zvs ZVS inductor L g The value of L gv and main inductor L b The value of L bv Calculate the turn-off time t of a switching transistor off The other switch is complementary and conducts.

[0043] Step 4: During the positive half-cycle of the power frequency, sample the current i obtained by the current sampling circuit. A The reference current I generated by the microcontroller c The current is fed into the current comparison module for comparison. The NCD signal generated by the current comparison module is used to turn off the second switch Q2. During the negative half-cycle of the power frequency, the current i sampled by the current sampling circuit is...A The reference current -I generated by the microcontroller c The signals are compared using a current comparison module. The NCD signal generated by the current comparison module is used to turn off the first switch Q1. During the positive and negative half-cycles, the conduction timing of the first switch Q1 and the second switch Q2 is opposite. During the positive half-cycle, the second switch Q2 acts as a boost switch and the first switch Q1 acts as a synchronous rectifier. During the negative half-cycle, the first switch Q1 acts as a boost switch and the second switch Q2 acts as a synchronous rectifier. Therefore, the selection of the PWM signals for the first switch Q1 and the second switch Q2 is achieved using a signal selection module. During the positive half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_B and the PWM signal for the first switch Q1 is PWM_SR. During the negative half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_SR and the PWM signal for the first switch Q1 is PWM_B.

[0044] The specific steps of digital control are as follows:

[0045] Step I: The ADC of the microcontroller (STM32G474) reads the input voltage u acquired by the input voltage sampling circuit. in The output voltage V collected by the output voltage sampling circuit o and the error voltage signal v from the PI controller ea .

[0046] Step II: The sampled voltage signal is converted in the microcontroller to obtain a voltage value consistent with the actual voltage signal, which is used to calculate the turn-off time t of the switching transistor. off At the same time, the microcontroller determines the input voltage u in The sign of u in When u > 0, the microcontroller sends a judgment signal Mux=1; when u in When <0, the microcontroller sends a judgment signal Mux=0;

[0047] Step III: Calculate the turn-off time t of the switching transistor based on the result of step 2. off This controls the size of the advanced timer count in the microcontroller. The timer is turned off by external triggering of the microcontroller. The NCD signal emitted by the analog current comparator circuit enters the microcontroller and serves as the signal source for external triggering. The timer is turned off after the NCD signal is triggered.

[0048] Step IV, Reference Current I c and-I c The input voltage u is generated by the DAC function of the microcontroller and sampled within the microcontroller. in The signal is converted to a reference current signal and configured as a dual-channel output in the analog circuit to be compared with the current i acquired by the current sampling module. A Compare them.

[0049] Combination Figure 4 The converter operates symmetrically in the positive and negative half-cycles. For the positive half-cycle of the AC input voltage source, the converter's operating modes are as follows:

[0050] Mode 1, time t0 to t1: Second switch Q2 is turned on, first switch Q1 is turned off, main inductor L b and ZVS inductor L g The voltage across the terminals is the input voltage u. in The inductor current increases linearly, and the current i A Main inductor L b and ZVS inductor L g The sum of the currents also increases linearly.

[0051] Mode 2, time t1 to t2: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The first junction capacitance C1 is discharged, and the second junction capacitance C2 is charged. This process takes a very short time, and the current i can be considered as... A Constant;

[0052] Mode 3, time t2 to t3: First switch Q1 turns on with zero voltage, second switch Q2 turns off, main inductor L... b and ZVS inductor L g The voltage across the two ends is u in -V o The inductor current decreases linearly, and at time t3, the current i A Decreased to 0;

[0053] Mode 4, time t3 to t4: Current i A The current flows in reverse, and the negative current forms a loop through the first switch Q1 and the LC branch. At time t4, the first switch Q1 is turned off, and the current drops to its minimum value.

[0054] Mode 5, time t4 to t5: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The second junction capacitor C2 is discharged, and the first junction capacitor C1 is charged. This process is very short, and the current i can be considered as... A Constant;

[0055] Mode 6, time intervals t5 to t6: Due to the reverse current, the charge on the junction capacitance C2 of the second switch Q2 can be completely discharged. Therefore, at time t5, the second switch Q2 turns on with zero voltage, and the main inductor L... b and ZVS inductor L g The voltage across the terminals is the input voltage u. inThe inductor current increases linearly, and the next switching cycle begins after this mode ends.

[0056] Switch conduction time t on and shutdown time t off The calculation is as follows:

[0057] On-time of the second switch Q2 The expression is:

[0058] ,

[0059] ,

[0060] ,

[0061] ,

[0062] Turn-off time of the second switch Q2 The expression is:

[0063] ,

[0064] Among them, i in For the input current, I zvs To achieve the minimum current required for the switch to turn on in ZVS mode, V o V is the output voltage. m AC input voltage u in peak voltage, L bv Main inductor L b The magnitude of the sensitivity, L gv ZVS inductor L g The magnitude of the sensitivity value, i represents the phase of the AC input voltage at power frequency. pk For i A The peak current.

[0065] Achieving the minimum current I of the ZVS of the switching transistor zvs Obtained under the following conditions:

[0066] ,

[0067] Among them, C oss V represents the value of the junction capacitance of the switching transistor. o For the output voltage, t dead Dead time;

[0068] Peak current comparison signal I from the microcontroller DAC c and-I c It is determined by the following formula:

[0069] ,

[0070] ,

[0071] in, For input current, For output power, This represents the peak value of the AC input voltage.

[0072] Example

[0073] A specific embodiment of the present invention is shown in Table 1 below, which provides the main parameters of a totem-pole bridgeless PFC converter that implements ZVS using LC:

[0074] Table 1. Main parameters of the totem-pole bridgeless PFC converter for ZVS implemented by LC.

[0075]

[0076] according to Figure 3 It can be seen that during the power frequency cycle, the main inductor L b The current waveform operates in continuous current mode, exhibiting only a very small current ripple. (ZVS inductor L) g Because of the capacitor, its current waveform is a pure high-frequency current ripple, and the main inductance L can be calculated separately. b negative peak current and ZVS inductor L g negative peak current :

[0077] ,

[0078] ,

[0079] At this time, the current i A negative peak i A_neg for:

[0080] ,

[0081] To meet the requirement of zero-voltage turn-on of the switching transistor, that is, before the second switching transistor Q2 turns on, there must be a sufficient negative current I to achieve ZVS. zvs The junction capacitance of the switching transistor is fully charged and discharged, so the current i A negative peak i A_neg Must be less than or equal to -1 zvs This is necessary to ensure that the second switch Q2 can be turned on at zero voltage.

[0082] At this point, the minimum conduction time of the switching transistor can be calculated:

[0083] ,

[0084] ,

[0085] The turn-off time of the switching transistor can be calculated using the volt-second balance:

[0086] ,

[0087] The switching frequency of the converter :

[0088] ,

[0089] The calculated on-time and off-time of the switching transistor are used to control the rise and fall of the current. In practical applications, the current rise is controlled by comparing the peak current, while the fall time is controlled by the calculated t. off To control, observe Figure 2 It can be seen that before the second switch Q2 is turned on, the voltage u at its junction capacitance is... c2 The voltage has been reduced to zero, indicating that it can be turned on at zero voltage. Before the first switching transistor Q1 is turned on, because the current is large enough, the voltage u across the junction capacitance of the first switching transistor Q1 is... c1 It will also be set to zero, so all switching transistors can achieve zero-voltage turn-on.

[0090] according to Figure 3 The ZVS capacitor C of the LC branch can be seen. g The ZVS capacitor C needs to be charged or discharged in advance when switching between positive and negative half-cycles, that is, when the input voltage changes from positive to negative. g The ZVS capacitor C needs to be charged in advance when the input voltage changes from negative to positive. g Pre-discharge is necessary because the ZVS capacitor C... g The voltage on follows the input voltage u in Change, when u in When >0, v Cg =u in , when u in When <0, The capacitor C is set to switch from the positive half-cycle to the negative half-cycle. g Starting from 10V, it needs to be charged to 390V during the negative half-cycle. It is assumed that the capacitor voltage V during this charging process... cg If the change is linear, the charging current can be obtained from the following formula. for:

[0091] ,

[0092] Where C gv For capacitor C gThe size of the capacitance, I bias For capacitor C g The amount of current required for pre-charging. Let t be the change in capacitor voltage, and t be time.

[0093] It is assumed that capacitor C g If the charging is constant current charging, then it is only necessary to use u in When the voltage is less than 10V, let the current i A The average value is -I bias This allows the capacitor C to be supplied with power. g Fully charged, at this point calculate the main inductance L. b and ZVS inductor L g positive peak current i b_pk and i g_pk This allows us to obtain the current i flowing through the switching transistor. A positive peak current i A_pk :

[0094] ,

[0095] ,

[0096] ,

[0097] At this time, the current i A negative peak current i A_neg1 It can be represented as:

[0098] ,

[0099] Then the current i A Current change for:

[0100] ,

[0101] During the conduction of switch S1, the main inductor L b The voltage across the terminals is V o -u in ZVS inductor L g The voltage across the terminals is V o -v cg ,in:

[0102] ,

[0103] in, It is the angular frequency at the power frequency.

[0104] Therefore, we can obtain the capacitance C. g The on-time of switch S1 during the charging phase, i.e.:

[0105] ,

[0106] ,

[0107] Calculated t off1 It is in u in When the voltage is less than 10V, in order to provide capacitor C g The on-time of the pre-charge switching transistor Q1.

[0108] The above are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

Claims

1. A totem-pole bridgeless PFC converter implementing ZVS using LC, characterized in that, It includes a main power circuit and a control circuit, wherein the main power circuit includes an input AC voltage source V. in First switching transistor Q1, second switching transistor Q2, first diode D1, second diode D2, main inductor L b ZVS inductor L g ZVS capacitor C g The first junction capacitor C1, the second junction capacitor C2, and the output capacitor C o The control circuit includes an input voltage comparison module, an output voltage comparison module, a PI regulator, a microcontroller, a PWM module, a signal selection module, a current comparison module, an AC input differential sampling circuit, an output voltage sampling circuit, and a current sampling circuit. The input AC voltage source of the converter v in One end is connected to the main inductor L b One end is connected to the first terminal, and the other end is connected to the negative terminal of the second diode D2. The main inductor L b Connect the source of the first switching transistor Q1 and the drain of the second switching transistor Q2. The drain of the first switching transistor Q1 is connected to the cathode of the first diode D1. The source of the second switching transistor Q2 is connected to the anode of the second diode D2. The source of the first switching transistor Q1 and the drain of the second switching transistor Q2 are connected to switching node A. The anode of the first diode D1 and the cathode of the diode D2 are connected to node B. The ZVS inductor L in the LC branch... g and ZVS capacitor C g The circuit is connected in series, with one end of the LC branch connected to switch node A and the other end connected to the positive terminal of the second diode D2. The first junction capacitance C1 is connected in parallel across the first switch Q1, and the second junction capacitance C2 is connected in parallel across the second switch Q2. The output capacitor C... o One end is connected to the drain of the first switching transistor Q1 and the cathode of the first diode D1, respectively, and the other end is connected to the ZVS capacitor C in the LC branch. g The source of the second switch Q2 is connected to the positive terminal of the second diode D2. The AC input differential sampling circuit is connected to the input AC voltage source v respectively. in The input voltage comparison module is connected to the microcontroller, and one end of the output voltage sampling circuit is connected to the output capacitor C. o The other end connects to the output voltage comparison module and the microcontroller. The output voltage comparison module is connected to the reference voltage V. ref The circuit consists of a PI regulator and an output voltage sampling circuit. The PI regulator is connected to a microcontroller. The Mux signal generated by the microcontroller enters the signal selection module. The microcontroller calculates the turn-off time t of the switching transistor. off The signal enters the PWM module to generate the boost diode signal PWM_B and the synchronous rectifier diode signal PWM_SR. PWM_B and PWM_SR then enter the signal selection module to generate the corresponding drive signals for the first switch Q1 and the second switch Q2. The current sampling circuit acquires the signal from the main inductor L. b With ZVS inductor L g The sum of currents i A The output of the current sampling circuit is connected to the input terminals of two current comparison modules, and the other input terminal of each current comparison module is connected to the reference current I. c and-I c The output of the current comparison module is connected to the signal selection module to generate an NCD signal that enters the PWM module.

2. A control method for a totem-pole bridgeless PFC converter with ZVS implemented by LC as described in claim 1, characterized in that: The control methods are divided into two parts: digital control and analog control.

3. The control method for a totem-pole bridgeless PFC converter implementing ZVS using LC as described in claim 2, characterized in that, The specific steps of digital control are as follows: Step 1: The microcontroller's ADC reads the input voltage u collected by the input voltage sampling circuit. in The output voltage V collected by the output voltage sampling circuit o and the error voltage signal v from the PI controller ea ; Step II: The sampled voltage signal is converted in the microcontroller to obtain a voltage value consistent with the actual voltage signal, which is used to calculate the turn-off time t of the switching transistor. off At the same time, the microcontroller determines the input voltage u in The sign of u in When u > 0, the microcontroller sends a judgment signal Mux=1; when u in When <0, the microcontroller sends a judgment signal Mux=0; Step III: Calculate the turn-off time t of the switching transistor based on the result of step 2. off This controls the size of the advanced timer count in the microcontroller. The timer is turned off by external triggering of the microcontroller. The NCD signal emitted by the analog current comparator circuit enters the microcontroller and serves as the signal source for external triggering. The timer is turned off after the NCD signal is triggered. Step IV, Reference Current I c and-I c The input voltage u is generated by the DAC function of the microcontroller and sampled within the microcontroller. in The signal is converted to a reference current signal and configured as a dual-channel output in the analog circuit to be compared with the current i acquired by the current sampling module. A Compare them.

4. The control method for the totem-pole bridgeless PFC converter with ZVS implemented by LC according to claim 3, characterized in that, The converter operates symmetrically in the positive and negative half-cycles. For the positive half-cycle of the AC input voltage source, the converter's operating modes are as follows: Mode 1, time t0 to t1: Second switch Q2 is turned on, first switch Q1 is turned off, main inductor L b and ZVS inductor L g The voltage across the terminals is the input voltage u. in The inductor current increases linearly, and the current i A Main inductor L b and ZVS inductor L g The sum of the currents also increases linearly; Mode 2, time t1 to t2: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The first junction capacitance C1 is discharged, and the second junction capacitance C2 is charged. This process takes a very short time, and the current i can be considered as... A Constant; Mode 3, time t2 to t3: First switch Q1 turns on with zero voltage, second switch Q2 turns off, main inductor L... b and ZVS inductor L g The voltage across the two ends is u in -V o The inductor current decreases linearly, and at time t3, the current i A Decreased to 0; Mode 4, time t3 to t4: Current i A The current flows in reverse, and the negative current forms a loop through the first switch Q1 and the LC branch. At time t4, the first switch Q1 is turned off, and the current drops to its minimum value. Mode 5, time t4 to t5: Dead time, both the second switch Q2 and the first switch Q1 are turned off, current i A The second junction capacitor C2 is discharged, and the first junction capacitor C1 is charged. This process is very short, and the current i can be considered as... A Constant; Mode 6, time intervals t5 to t6: Due to the reverse current, the charge on the junction capacitance C2 of the second switch Q2 can be completely discharged. Therefore, at time t5, the second switch Q2 turns on with zero voltage, and the main inductor L... b and ZVS inductor L g The voltage across the terminals is the input voltage u. in The inductor current increases linearly, and the next switching cycle begins after this mode ends.

5. The control method for a totem-pole bridgeless PFC converter implementing ZVS using LC as described in claim 2, characterized in that, The specific steps of analog control are as follows: Step 1: The AC input differential sampling circuit acquires the input AC voltage source V. in live wire voltage and neutral line voltage The input AC voltage is then sent to the input voltage comparison module for comparison. and Perform differential calculations to obtain the input AC voltage. ; Step 2: The output voltage sampling circuit samples the output capacitor C. o The voltage at both ends is sampled to obtain the output voltage V. o It is then fed into the output voltage comparison module and compared with the reference voltage V. ref By comparison, the error voltage v is obtained. ea ; Step 3: Set the error voltage v ea Send to the PI controller, based on u in V o v ea Minimum current I for achieving ZVS zvs ZVS inductor L g The value of L gv and main inductor L b The value of L bv Calculate the turn-off time t of a switching transistor. off The other switch is complementary and conducts; Step 4: During the positive half-cycle of the power frequency, sample the current i obtained by the current sampling circuit. A The reference current I generated by the microcontroller c The current is fed into the current comparison module for comparison. The NCD signal generated by the current comparison module is used to turn off the second switch Q2. During the negative half-cycle of the power frequency, the current i sampled by the current sampling circuit is... A The reference current -I generated by the microcontroller c The signals are compared using a current comparison module. The NCD signal generated by the current comparison module is used to turn off the first switch Q1. During the positive and negative half-cycles, the conduction timing of the first switch Q1 and the second switch Q2 is opposite. During the positive half-cycle, the second switch Q2 acts as a boost switch and the first switch Q1 acts as a synchronous rectifier. During the negative half-cycle, the first switch Q1 acts as a boost switch and the second switch Q2 acts as a synchronous rectifier. Therefore, the selection of the PWM signals for the first switch Q1 and the second switch Q2 is achieved using a signal selection module. During the positive half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_B and the PWM signal for the first switch Q1 is PWM_SR. During the negative half-cycle of the power frequency, the PWM signal for the second switch Q2 is PWM_SR and the PWM signal for the first switch Q1 is PWM_B.

6. The control method for a totem-pole bridgeless PFC converter implementing ZVS by LC according to claim 5, characterized in that, Switch conduction time t on and shutdown time t off The calculation is as follows: On-time of the second switch Q2 The expression is: ， ， ， ， Turn-off time of the second switch Q2 The expression is: ， Among them, i in For the input current, I zvs To achieve the minimum current required for the switch to turn on in ZVS mode, V o V is the output voltage. m AC input voltage u in peak voltage, L bv Main inductor L b The magnitude of the sensitivity, L gv ZVS inductor L g The magnitude of the sensitivity value, i represents the phase of the AC input voltage at power frequency. pk For i A The peak current.

7. The control method for a totem-pole bridgeless PFC converter implementing ZVS by LC according to claim 5, characterized in that, Achieving the minimum current I of the ZVS of the switching transistor zvs Obtained under the following conditions: ， Among them, C oss V represents the value of the junction capacitance of the switching transistor. o For the output voltage, t dead Dead time; Peak current comparison signal I from the microcontroller DAC c and-I c It is determined by the following formula: ， ， in, For input current, For output power, This represents the peak value of the AC input voltage.

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