An enhanced GaN power device low-loss crosstalk suppression driving circuit

Abstract

The application relates to a low-loss crosstalk suppression driving circuit for an enhanced GaN power device. The driving circuit comprises a driving chip Driver, a negative voltage clamping unit, a dead zone positive voltage clamping and negative voltage generating unit and a power supply unit. The driving chip Driver receives a PWML control signal and generates a lower switch tube driving signal; when the lower switch tube driving signal drives the lower switch tube to be turned off, the dead zone positive voltage clamping and negative voltage generating unit clamps the gate-source voltage of the lower switch tube to a low positive voltage; when positive crosstalk occurs, the dead zone positive voltage clamping and negative voltage generating unit adjusts the gate-source voltage of the lower switch tube to a negative voltage to suppress the positive crosstalk; the negative voltage clamping unit generates a negative voltage clamping control signal; after the positive crosstalk ends and before negative crosstalk occurs, under the control of the negative voltage clamping control signal, the dead zone positive voltage clamping and negative voltage generating unit clamps the gate-source voltage of the lower switch tube to 0v to suppress the negative crosstalk in advance. The method can realize bridge arm crosstalk suppression and reduce the reverse conduction loss of the enhanced GaN power device under the condition of effectively reducing the cost.

Description

Technical Field

[0001] This application relates to the technical field of crosstalk suppression, and in particular to a low-loss crosstalk suppression drive circuit for enhanced GaN power devices. Background Technology

[0002] Against the backdrop of the ongoing global push for carbon neutrality and the accelerated shift of the energy structure towards cleaner energy sources, cutting-edge applications such as electric vehicles, AI data centers, and industrial robots are reshaping the technological landscape of power semiconductors at an unprecedented pace. Power electronic devices are being continuously pushed towards higher operating frequencies, better conversion efficiencies, and higher power densities. However, after more than half a century of development, traditional silicon-based power devices are approaching the limits of their material physical properties, and are increasingly struggling to perform in high-voltage, high-frequency, and high-temperature scenarios.

[0003] Wide-bandgap semiconductors, represented by silicon carbide (SiC) and gallium nitride (GaN), have opened up new performance possibilities thanks to their drastically different material properties. GaN's extremely low on-resistance and excellent high-frequency characteristics give it a unique advantage in MHz-level high-frequency switching applications. However, this performance advantage often comes with engineering challenges. The extremely high switching speed of GaN devices (dv / dt and di / dt can be several times that of traditional silicon devices) is both a source of efficiency improvement and a root cause of system design difficulties. Compared with Si and SiC devices, GaN HEMTs have a lower gate threshold voltage and a very limited safety margin for gate-source voltage. When the parasitic inductance that is difficult to eliminate in the power circuit resonates with the junction capacitance of the device, it can cause severe overshoot and oscillations in drain-source voltage and current. These high-frequency oscillations are coupled to the drive circuit through Miller capacitance and common-source parasitic inductance, which can easily generate considerable crosstalk voltage spikes at the gate. In half-bridge topologies widely used in electric vehicles and robotics, this crosstalk phenomenon is particularly troublesome: when one switch operates rapidly, the gate of the complementary switch may be pushed above the threshold by the induced positive voltage spike, causing false turn-on. Once the upper and lower switches conduct simultaneously, causing bridge arm shoot-through, it can lead to a sharp drop in system efficiency or even direct damage to power devices.

[0004] Negative voltage spikes generated by negative crosstalk are also significant. The gate structure of GaN devices is relatively fragile, and continuous negative overshoot can lead to gate breakdown or reliability degradation. One common engineering strategy is to use negative voltage turn-off to suppress positive crosstalk, but this introduces a new problem: the continuous negative bias voltage superimposed on the negative crosstalk spikes may create even greater negative voltage stress; and under long-term negative bias, the threshold voltage of GaN devices may drift, further weakening the long-term reliability of the gate. How to fully leverage the high-frequency advantages of GaN while effectively managing crosstalk risks has become one of the core challenges that urgently needs to be addressed in current power electronics design.

[0005] Existing technologies often employ multiple driver chips combined with positive and negative power supplies and negative voltage shutdown to suppress crosstalk in GaN devices. However, negative voltage shutdown requires an additional negative voltage power supply, increasing losses, and using multiple driver chips for control is costly and occupies a large board area. Summary of the Invention

[0006] Therefore, it is necessary to provide an enhanced GaN power device low-loss crosstalk suppression drive circuit that can suppress bridge arm crosstalk of GaN power devices while effectively reducing costs, in order to address the above-mentioned technical problems.

[0007] To achieve the above effects, the technical solution of the present invention is as follows: This invention provides a low-loss crosstalk suppression driving circuit for enhanced GaN power devices, including an upper switch and a lower switch. The source of the upper switch is connected to the drain of the lower switch. Negative crosstalk is generated when the upper switch is turned on to turn off and the lower switch is turned off. Positive crosstalk is generated when the lower switch is turned off and the upper switch is turned on. The circuit also includes a driver chip, a negative voltage clamping unit, a dead-zone positive voltage clamping and negative voltage generation unit, and a power supply unit. The input terminal of the driver chip receives the PWML control signal; the output terminal of the driver chip outputs the lower switch drive signal, and the output terminal of the driver chip is connected to the control signal input terminal of the negative voltage clamping unit, the control signal input terminal of the dead-zone positive voltage clamping and negative voltage generation unit, and the gate of the lower switch; the lower switch drive signal is used to control the switching state of the lower switch, and the switching state includes an on state and an off state; the negative voltage clamping unit is used to generate a negative voltage clamping control signal; The power supply unit is connected to the VCC pin of the driver chip, the first power input terminal of the dead zone positive pressure clamp and negative pressure generation unit, and the second power input terminal of the dead zone positive pressure clamp and negative pressure generation unit, respectively. The negative pressure clamping control signal output terminal of the negative pressure clamping unit is connected to the negative pressure clamping control signal input terminal of the dead zone positive pressure clamping and negative pressure generation unit. The voltage control output terminal of the dead zone positive pressure clamping and negative pressure generation unit is connected to the GND pin of the driver chip. The grounding terminals of the dead zone positive pressure clamping and negative pressure generating unit and the negative pressure clamping unit are all grounded; The dead-zone positive voltage clamping and negative voltage generation unit is used to clamp the gate-source voltage of the lower switch to a low positive voltage when the lower switch is turned off, and when positive crosstalk occurs, under the control of the lower switch drive signal, adjust the gate-source voltage of the lower switch from a low positive voltage to a negative voltage; or under the control of the negative voltage clamping control signal, clamp the gate-source voltage of the lower switch from a negative voltage to 0V; the low positive voltage is lower than the threshold voltage of the lower switch.

[0008] Preferably, the negative pressure clamping unit includes a resistor R3, a capacitor C2, a capacitor C3, a buffer U1, and a diode D1; The first end of the resistor R3 is connected to the output of the driver chip, the second input of the dead zone positive voltage clamping and negative voltage generation unit, and the gate of the lower switch transistor. The second end of the resistor R3 is connected to the first end of the capacitor C3 and the input of the buffer U1 through node P. The output of the buffer U1 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the first input of the dead zone positive voltage clamping and negative voltage generation unit and the anode of the diode D1 through node O. The cathode of the diode D1 and the second end of the capacitor C3 are both grounded.

[0009] Preferably, within the negative pressure clamping unit, the following conditions are met:

[0010]

[0011] in, VIH is the maximum voltage across capacitor C3, and VIH is the high-level input voltage of buffer U1. This is the minimum voltage across capacitor C3. For driving voltage, This is the Miller plateau voltage. The gate drive resistor for the lower switching transistor is... For conduction time, The off time is T, and the switching period is T. This represents the gate-drain charge of the switching transistor. This represents the gate-source voltage of the switching transistor.

[0012] Preferably, the voltage signal at node P is a triangular wave-like signal, and the frequency of the triangular wave-like signal is the same as the frequency of the lower switch drive signal.

[0013] Preferably, the dead zone positive pressure clamping and negative pressure generation unit includes transistor M1, transistor M2, transistor M3, and capacitor C1; The drain of transistor M1 is connected to the GND pin of the driver chip and the first terminal of capacitor C1. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1. The second terminal of capacitor C1 is connected to the power supply unit and the drain of transistor M3. The gate of transistor M3 is connected to the power supply unit and the drain of transistor M2 through node N. The gate of transistor M2 is connected to the output terminal of the driver chip, the first terminal of resistor R3, and the gate of the lower switch. The sources of transistors M1, M2, and M3 are all grounded. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1 through node O.

[0014] Preferably, the transistor M1 is a PMOS transistor.

[0015] Preferably, both transistor M2 and transistor M3 are NMOS transistors.

[0016] Preferably, the system further includes resistors R1 and R2. The first ends of resistors R1 and R2 are both connected to the power supply unit. The second end of resistor R1 is connected to the drain of transistor M2 and the gate of transistor M3, respectively. The second end of resistor R2 is connected to the drain of transistor M3 and the second end of capacitor C1, respectively.

[0017] Preferably, the voltage signal at node N is a square wave signal, and the frequency of the square wave signal is the same as the frequency of the lower switch drive signal.

[0018] Preferably, the step of clamping the gate-source voltage of the lower switching transistor to a low positive voltage when it is turned off, and adjusting the gate-source voltage of the lower switching transistor from a low positive voltage to a negative voltage under the control of the lower switching transistor drive signal when positive crosstalk occurs; or clamping the gate-source voltage of the lower switching transistor from a negative voltage to 0V under the control of the negative voltage clamping control signal, includes: When the lower switch drive signal drives the lower switch to turn off, the power supply unit charges the capacitor C1 through resistor R2. The voltage at the first end of the capacitor C1 is clamped to the low positive voltage by transistor M1. The low positive voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switch through the output terminal of the driver chip. The gate-source voltage of the lower switch is clamped to the low positive voltage. The power supply unit provides a high-level voltage at node N through resistor R1. The transistor M2 generates a square wave signal at node N according to the lower switch drive signal. The square wave signal and the high-level voltage are used to control the switching state of transistor M3. The switching state of transistor M3 includes an on state and an off state. After transistor M3 is turned on, the voltage at the second terminal of capacitor C1 is clamped to 0V. Since the voltage across capacitor C1 cannot change abruptly, the voltage at the first terminal of capacitor C1 changes from a low positive voltage to a negative voltage. The negative voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switching transistor through the output terminal of the driver chip. The gate-source voltage of the lower switching transistor is adjusted from a low positive voltage to a negative voltage. The resistor R3 and capacitor C3 generate a triangular wave signal based on the drive signal of the lower switch transistor. The buffer U1, capacitor C2 and diode D1 generate a negative voltage clamping control signal at node O according to the triangular wave signal. The negative voltage clamping control signal drives transistor M1 to clamp the gate-source voltage of the lower switching transistor from negative voltage to 0V.

[0019] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: This invention proposes a low-loss crosstalk suppression driving circuit for enhanced GaN power devices, including a driver chip, a negative voltage clamping unit, a dead-zone positive voltage clamping and negative voltage generation unit, and a power supply unit. The driver chip receives the PWML control signal and generates a lower switch drive signal based on the PWML control signal. When the lower switch drive signal turns off the lower switch, the dead-zone positive voltage clamping and negative voltage generation unit clamps the gate-source voltage of the lower switch to a low positive voltage to ensure normal turn-off of the lower switch and reduce its reverse conduction losses. When positive crosstalk occurs, the dead-zone positive voltage clamping and negative voltage generation unit adjusts the gate-source voltage of the lower switch from a low positive voltage to a negative voltage under the control of the lower switch drive signal to suppress positive crosstalk. The negative voltage clamping unit generates a negative voltage clamping control signal under the control of the lower switch drive signal. After the positive crosstalk ends and before the negative crosstalk arrives, under the control of the negative voltage clamping control signal, the dead-zone positive voltage clamping and negative voltage generation unit clamps the gate-source voltage of the lower switch from a negative voltage to 0V to suppress negative crosstalk in advance. This invention utilizes only a single driver chip and requires only a single power supply. It does not rely on complex logic control signals, nor does it require additional driver ICs, control signals, or negative power supplies. It can effectively reduce costs while suppressing bridge arm crosstalk and significantly reduce the reverse conduction loss of enhancement-mode GaN power devices. Attached Figure Description

[0020] Figure 1 This is a connection structure diagram of a low-loss crosstalk suppression drive circuit for an enhanced GaN power device proposed in one embodiment. Figure 2 Here is a schematic diagram of the bridge arm circuit structure of the synchronous rectification Buck circuit proposed in one embodiment; Figure 3This is a schematic diagram illustrating the level state changes of the PWMH control signal and the PWML control signal under the switching period T in one embodiment. Figure 4 This is a connection structure diagram of a low-loss crosstalk suppression drive circuit for an enhanced GaN power device proposed in one embodiment. Figure 5 The image shows a simulation waveform of the low-loss crosstalk suppression drive circuit for an enhanced GaN power device proposed in one embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] Example 1 This embodiment provides a low-loss crosstalk suppression driving circuit for enhanced GaN power devices, including an upper switch and a lower switch. The source of the upper switch is connected to the drain of the lower switch. When the upper switch turns on to off and the lower switch is off, negative crosstalk is generated; when the lower switch is off and the upper switch turns on, positive crosstalk is generated. Figure 1 As shown, the circuit also includes: a driver chip, a negative pressure clamping unit 3, a dead zone positive pressure clamping and negative pressure generation unit 4, and a power supply unit; The input terminal of the driver chip receives the PWML control signal; the output terminal of the driver chip outputs the lower switch drive signal, and the output terminal of the driver chip is connected to the control signal input terminal of the negative voltage clamping unit 3, the control signal input terminal of the dead-zone positive voltage clamping and negative voltage generation unit 4, and the gate of the lower switch; the lower switch drive signal is used to control the switching state of the lower switch, and the switching state includes an on state and an off state; the negative voltage clamping unit 3 is used to generate a negative voltage clamping control signal; The power supply unit is connected to the VCC pin of the driver chip, the first power input terminal 1 of the dead zone positive pressure clamping and negative pressure generation unit, and the second power input terminal 2 of the dead zone positive pressure clamping and negative pressure generation unit, respectively. The negative pressure clamping control signal output terminal of the negative pressure clamping unit 3 is connected to the negative pressure clamping control signal input terminal of the dead zone positive pressure clamping and negative pressure generating unit 4. The voltage control output terminal of the dead zone positive pressure clamping and negative pressure generation unit 4 is connected to the GND pin of the driver chip. The grounding terminals of the dead zone positive pressure clamping and negative pressure generating unit 4 and the negative pressure clamping unit 3 are all grounded; The dead zone positive voltage clamping and negative voltage generation unit 4 is used to clamp the gate-source voltage of the lower switch to a low positive voltage when the lower switch is turned off, and when positive crosstalk occurs, under the control of the lower switch drive signal, adjust the gate-source voltage of the lower switch from a low positive voltage to a negative voltage; or under the control of the negative voltage clamping control signal, clamp the gate-source voltage of the lower switch from a negative voltage to 0V; the low positive voltage is lower than the threshold voltage of the lower switch.

[0023] like Figure 2 As shown, this embodiment uses a synchronous rectification Buck circuit (48V to 12V, 2A; dead time 50ns) as an example. The synchronous rectification Buck circuit includes an upper switching transistor QH, a lower switching transistor QL, and an upper transistor gate drive resistor R. GH Gate drive resistor R of the lower transistor GL DC input bus V BUS 5. Upper switch PWMH drive signal source; 6. Lower switch PWMH drive signal source; 7. Load inductor L; 8. Output capacitor Cout; 9. Load resistor RL; The upper switch QH includes the upper switch gate-drain parasitic capacitance C. GDH The gate-source parasitic capacitance C of the upper switching transistor GSH Parasitic capacitance C of the drain source of the upper switching transistor DSH The lower switching transistor QL includes the gate-drain parasitic capacitance C of the lower switching transistor. GDL The gate-source parasitic capacitance C of the lower switching transistor GSL The drain-source parasitic capacitance C of the lower switching transistor DSL .

[0024] The DC input bus V BUS The upper switching transistor QH is connected to its drain. The source of the upper switching transistor QH is connected to the drain of the lower switching transistor QL, the negative terminal of the upper switching transistor PWMH drive signal source 5, and the first terminal of the load inductor L via the switching node SW. The gate of the upper switching transistor QH is connected to the gate drive resistor R of the upper transistor. GH The first terminal is connected, and the second terminal of the upper transistor gate drive resistor RGH is connected to the positive terminal of the upper switching transistor PWMH drive signal source 5. The gate of the lower switching transistor QL is connected to the lower transistor gate drive resistor RGH. GL The first terminal is connected to the gate drive resistor R of the lower transistor. GH The second terminal is connected to the positive terminal of the lower switching transistor PWML drive signal source 6. The second terminal of the load inductor L is connected to the first terminal of the output capacitor Cout and the first terminal of the load resistor RL, respectively. The negative terminal of the lower switching transistor PWML drive signal source 6, the source of the lower switching transistor QL, the second terminal of the output capacitor Cout, and the second terminal of the load resistor RL are all grounded to GND.

[0025] In the aforementioned synchronous rectification Buck circuit, the switching frequency is 1MHz. The drive signal after the control signal of the upper switching transistor QH is driven is a PWMH control signal: the voltage level switches between 0V and 5V; the delay time from the start to the rising edge of the pulse is 750 nanoseconds; the pulse high-level width is 250 nanoseconds, and the period is 1 microsecond. Preferably, the duty cycle of the PWM waveform is determined by the ratio of the pulse width to the period, i.e., 250 nanoseconds divided by 1 microsecond, yielding a 25% duty cycle, suitable for precise power output control. The waveform repeats periodically.

[0026] like Figure 3 As shown, the vertical axis represents the level state of the PWMH control signal and the PWML control signal, respectively, and the horizontal axis represents time. The PWMH control signal controls the switching state of the upper switch QH, and the PWML control signal controls the switching state of the lower switch QL. The time interval between the left dashed line and the right dashed line is the switching period T set in this embodiment.

[0027] In the aforementioned synchronous rectification Buck circuit, the causes of positive and negative crosstalk are as follows: C1: When the initial state is that the upper switch QH is on and the lower switch QL is off, the DC input bus V BUS The current loop is formed by the upper switching transistor QH, the load inductor L, the output capacitor Cout, and GND.

[0028] C2: To prevent shoot-through between the upper switch QH and the lower switch QL in the half-bridge, a dead time DT1, during which both switches are turned off, needs to be inserted between the turn-on to turn-off transition of the upper switch QH and the turn-on transition of the lower switch QL. During this period, since the inductor L current is continuous, the freewheeling path forms a loop through the reverse conduction branch of the lower switch QL. Let the reverse conduction voltage drop of the lower switch QL be V. rev1 Then the switching node voltage V SW From V BUS The jump to -Vrev1 generates a large dv / dt, which in turn forms a displacement current I through the Miller capacitance Crss of the lower switching transistor QL. GD I GD Flow through the gate drive resistor R of the lower transistor GL This induces a negative voltage spike at the gate, known as negative crosstalk. It's important to note that GaN HEMT devices have a unique structure, lacking an internal body diode, resulting in a reverse conduction voltage drop of approximately 2 V. Therefore, the reverse conduction loss is quite significant during this stage.

[0029] C3: After the dead time DT1 ends, the lower switch QL turns on. The freewheeling circuit still consists of inductor L, output capacitor Cout, and lower switch QL, but the channel is now open, and the reverse conduction voltage drop decreases to V. rev2 VSW = -V rev2 The reverse conduction loss is significantly reduced.

[0030] C4: When the current switch QL transitions from on to off while the previous switch QH remains off, the dead time DT2 begins. During DT2, the freewheeling state remains unchanged, and V... SW = -V rev1 The reverse conduction loss increases again.

[0031] C5: After the dead time DT2, the upper switching transistor QH turns on, and the load current loop returns to stage C1. Therefore, V SW The transition from -Vrev2 to V BUS The large dv / dt generates a displacement current on the Miller capacitance Crss of the downstream switching transistor QL. displacement current The current flows through the gate drive resistor R of the lower switch transistor GL This generates a positive voltage spike at the gate of the lower switching transistor QL, i.e., positive crosstalk.

[0032] For the reasons mentioned above, this embodiment designs an enhanced GaN power device low-loss crosstalk suppression drive circuit and applies it to a synchronous rectification buck circuit. For example... Figure 1 As shown, the lower switching transistor PWML drive signal source 6 is composed of the PWML control signal and the driver chip. The output terminal of the driver chip, the control signal input terminal of the negative voltage clamping unit 3, and the control signal input terminal of the dead-zone positive voltage clamping and negative voltage generation unit 4 are connected through the lower transistor gate drive resistor R. GL It is connected to the gate of the lower switching transistor.

[0033] In this embodiment, when the PWML control signal is low (i.e. when the lower switch drive signal controls the lower switch to turn off), the gate-source voltage of the lower switch is clamped to a low positive voltage using the dead-time positive voltage clamping and negative voltage generation unit 4, so that the gate-source voltage of the lower switch drops below the threshold, and at the same time the reverse conduction loss of the lower switch is reduced within the dead time DT1.

[0034] When positive crosstalk occurs, under the control of the lower switch drive signal, the dead zone positive voltage clamp and negative voltage generation unit 4 acts as a negative voltage source, adjusting the gate-source voltage of the lower switch from low positive voltage to negative voltage to suppress positive crosstalk.

[0035] After the positive crosstalk ends and before the negative crosstalk arrives, under the control of the lower switch drive signal, the negative voltage clamping unit 3 generates a negative voltage clamping control signal. Under the control of the negative voltage clamping control signal, the dead-zone positive voltage clamping and negative voltage generation unit 4 clamp the gate-source voltage of the lower switch from negative voltage to 0V to suppress the negative crosstalk in advance.

[0036] For the driver chip, the preferred option in this embodiment is 2EDB7259Y.

[0037] This solution utilizes only one driver chip and requires only a single power supply. It does not rely on complex logic control signals, nor does it require additional driver ICs, control signals, or negative power supplies. It can effectively reduce costs while suppressing bridge arm crosstalk and significantly reduce the reverse conduction loss of enhanced GaN power devices.

[0038] Example 2 like Figure 4 As shown, in this embodiment, the negative pressure clamping unit 3 includes a resistor R3, a capacitor C2, a capacitor C3, a buffer U1, and a diode D1; The first end of the resistor R3 is connected to the output terminal of the driver chip Driver, the second input terminal of the dead zone positive voltage clamping and negative voltage generation unit 4, and the gate of the lower switch transistor. The second end of the resistor R3 is connected to the first end of the capacitor C3 and the input terminal of the buffer U1 through node P. The output terminal of the buffer U1 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the first input terminal of the dead zone positive voltage clamping and negative voltage generation unit 4 and the anode of the diode D1 through node O. The cathode of the diode D1 and the second end of the capacitor C3 are both grounded.

[0039] To ensure that the negative pressure can completely suppress positive crosstalk and clamp in a timely manner, the following conditions are met inside the negative pressure clamping unit 3:

[0040]

[0041] in, VIH is the maximum voltage across capacitor C3, and VIH is the high-level input voltage of buffer U1. This is the minimum voltage across capacitor C3. For driving voltage, This is the Miller plateau voltage. The gate drive resistor for the lower switching transistor is... For conduction time, The off time is T, and the switching period is T. This represents the gate-drain charge of the switching transistor. This represents the gate-source voltage of the switching transistor.

[0042] The voltage signal at node P is a triangular wave-like signal, and the frequency of the triangular wave-like signal is the same as the frequency of the lower switch drive signal.

[0043] Specifically, the gate-driven lower switch drive signal is a square wave signal, which turns on and off too quickly. It needs to be converted into a triangular wave input buffer U1, and the square wave signal with a specific duty cycle output by buffer U1 is used as a clamping signal.

[0044] The dead zone positive pressure clamping and negative pressure generating unit 4 includes transistor M1, transistor M2, transistor M3, and capacitor C1; The drain of transistor M1 is connected to the GND pin of the driver chip and the first terminal of capacitor C1. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1. The second terminal of capacitor C1 is connected to the power supply unit and the drain of transistor M3. The gate of transistor M3 is connected to the power supply unit and the drain of transistor M2 through node N. The gate of transistor M2 is connected to the output terminal of the driver chip, the first terminal of resistor R3, and the gate of the lower switch. The sources of transistors M1, M2, and M3 are all grounded. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1 through node O.

[0045] The transistor M1 is a PMOS transistor.

[0046] Both transistor M2 and transistor M3 are NMOS transistors.

[0047] It also includes resistors R1 and R2. The first end of resistor R1 and the first end of resistor R2 are both connected to the power supply unit. The second end of resistor R1 is connected to the drain of transistor M2 and the gate of transistor M3, respectively. The second end of resistor R2 is connected to the drain of transistor M3 and the second end of capacitor C1, respectively.

[0048] The voltage signal at node N is a square wave signal, and the frequency of the square wave signal is the same as the frequency of the lower switch drive signal.

[0049] Example 3 In this embodiment, clamping the gate-source voltage of the lower switch to a low positive voltage when the lower switch is turned off, and adjusting the gate-source voltage of the lower switch from a low positive voltage to a negative voltage under the control of the lower switch drive signal when positive crosstalk occurs; or clamping the gate-source voltage of the lower switch from a negative voltage to 0V under the control of the negative voltage clamping control signal, includes: S1: When the lower switch drive signal drives the lower switch to turn off, the power supply unit charges the capacitor C1 through the resistor R2. The voltage at the first end of the capacitor C1 is clamped to the low positive voltage by the transistor M1. The low positive voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switch through the output terminal of the driver chip. The gate-source voltage of the lower switch is clamped to the low positive voltage. S2: The power supply unit provides a high-level voltage at node N through resistor R1. The transistor M2 generates a square wave signal at node N according to the lower switch drive signal. The square wave signal and the high-level voltage are used to control the switching state of transistor M3. The switching state of transistor M3 includes an on state and an off state. S3: After transistor M3 is turned on, the voltage at the second end of capacitor C1 is clamped to 0V. Since the voltage across capacitor C1 cannot change abruptly, the voltage at the first end of capacitor C1 changes from a low positive voltage to a negative voltage. The negative voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switching transistor through the output terminal of the driver chip. The gate-source voltage of the lower switching transistor is adjusted from a low positive voltage to a negative voltage. S4: The resistor R3 and capacitor C3 generate a triangular wave signal according to the drive signal of the lower switch transistor; S5: The buffer U1, capacitor C2 and diode D1 generate a negative voltage clamping control signal at node O according to the triangular wave signal. The negative voltage clamping control signal drives transistor M1 to clamp the gate-source voltage of the lower switching transistor from negative voltage to 0V.

[0050] like Figure 5 As shown, the horizontal axis represents time, the vertical axis of the first subplot represents the voltage level of node N, the vertical axis of the second subplot represents the voltage level of node O / node P (dashed line represents node P), and the vertical axis of the third subplot represents the gate-source voltage V of the switching transistor. GSH The voltage level state, the vertical axis of the fourth sub-graph represents the gate-source voltage V of the lower switch transistor. GSL The level state. Figure 4 The S1 time period in the example corresponds to the S1 proposed in this embodiment. The S3 time node corresponds to the adjustment of the gate-source voltage of the lower switching transistor from a low positive voltage to a negative voltage. The S5 time node corresponds to the negative voltage clamping control signal driving transistor M1 to clamp the gate-source voltage of the lower switching transistor from a negative voltage to 0V.

[0051] Furthermore, in S1, the voltage at the first terminal of capacitor C1 is clamped to a low positive voltage Vp by the body diode of transistor M1, where Vp is the forward conduction voltage drop of the body diode of transistor M1.

[0052] In S2, since transistor M2 is turned off, the power supply unit charges the gate-source capacitance CGS of transistor M3 through resistor R1. After the gate-source voltage VGS of transistor M3 exceeds its threshold voltage, transistor M3 turns on.

[0053] In S3, since the power supply voltage in S1 charges capacitor C1, the voltage across capacitor C1 satisfies the expression:

[0054] in, The supply voltage for the power supply unit. This is the forward voltage drop of the body diode of transistor M1. This is the conduction time of the lower switching transistor. Before the upper switching transistor turns on, after transistor M3 is turned on, the voltage at the second terminal of capacitor C1 is clamped to 0V. Since the voltage across the capacitor cannot change abruptly, the voltage at the first terminal of capacitor C1 becomes V. N V N It is a negative pressure, satisfying the expression:

[0055] in, The output charge of transistor M1, C1 is the output capacitor of transistor M1. At this time, capacitor C1 acts as a negative voltage source, adjusting the gate-source voltage of the lower switching transistor from a low positive voltage to a negative voltage to suppress positive crosstalk.

[0056] In S4, during the charging and discharging process of the gate-source voltage of the lower switching transistor (i.e., GaN HEMT), the low-pass filter composed of resistor R3 and capacitor C3 converts the square wave of the lower switching transistor drive signal into a triangular wave, which is then input to buffer U1. In S5, the output signal of buffer U1 is level-shifted through capacitor C2 and diode D1 to generate a negative voltage clamping control signal. The negative voltage clamping control signal drives transistor M1 to clamp the gate-source voltage of the lower switching transistor from negative voltage to 0V.

[0057] Specifically, the level conversion involves converting a positive level signal to a 0V signal and a 0V signal to a negative level signal. In this embodiment, capacitor C2 and diode D1 are used to convert the output signal (5V) of buffer U1 into a negative voltage clamping control signal (0V), and the output signal (0V) of buffer U1 is also converted into a negative voltage clamping control signal (-5V).

[0058] The same or similar labels correspond to the same or similar parts; The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A low-loss crosstalk suppression driving circuit for an enhanced GaN power device, comprising an upper switching transistor and a lower switching transistor, wherein the source of the upper switching transistor is connected to the drain of the lower switching transistor, negative crosstalk is generated when the upper switching transistor is turned on to off and the lower switching transistor is off; positive crosstalk is generated when the lower switching transistor is off and the upper switching transistor is turned on, characterized in that, Also includes: Driver chip, negative pressure clamping unit, dead zone positive pressure clamping and negative pressure generation unit, power supply unit; The input terminal of the driver chip receives the PWML control signal; the output terminal of the driver chip outputs the lower switch drive signal, and the output terminal of the driver chip is connected to the control signal input terminal of the negative voltage clamping unit, the control signal input terminal of the dead-zone positive voltage clamping and negative voltage generation unit, and the gate of the lower switch; the lower switch drive signal is used to control the switching state of the lower switch, and the switching state includes an on state and an off state; the negative voltage clamping unit is used to generate a negative voltage clamping control signal; The power supply unit is connected to the VCC pin of the driver chip, the first power input terminal of the dead zone positive pressure clamp and negative pressure generation unit, and the second power input terminal of the dead zone positive pressure clamp and negative pressure generation unit, respectively. The negative pressure clamping control signal output terminal of the negative pressure clamping unit is connected to the negative pressure clamping control signal input terminal of the dead zone positive pressure clamping and negative pressure generation unit. The voltage control output terminal of the dead zone positive pressure clamping and negative pressure generation unit is connected to the GND pin of the driver chip. The grounding terminals of the dead zone positive pressure clamping and negative pressure generating unit and the negative pressure clamping unit are all grounded; The dead-zone positive voltage clamping and negative voltage generation unit is used to clamp the gate-source voltage of the lower switch to a low positive voltage when the lower switch is turned off, and when positive crosstalk occurs, under the control of the lower switch drive signal, adjust the gate-source voltage of the lower switch from a low positive voltage to a negative voltage; or under the control of the negative voltage clamping control signal, clamp the gate-source voltage of the lower switch from a negative voltage to 0V; the low positive voltage is lower than the threshold voltage of the lower switch.

2. The low-loss crosstalk suppression driving circuit for enhanced GaN power devices according to claim 1, characterized in that, The negative pressure clamping unit includes a resistor R3, a capacitor C2, a capacitor C3, a buffer U1, and a diode D1; The first end of the resistor R3 is connected to the output of the driver chip, the second input of the dead zone positive voltage clamping and negative voltage generation unit, and the gate of the lower switch transistor. The second end of the resistor R3 is connected to the first end of the capacitor C3 and the input of the buffer U1 through node P. The output of the buffer U1 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the first input of the dead zone positive voltage clamping and negative voltage generation unit and the anode of the diode D1 through node O. The cathode of the diode D1 and the second end of the capacitor C3 are both grounded.

3. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 2, characterized in that, Inside the negative pressure clamping unit, the following conditions are met: in, The maximum voltage across capacitor C3 is V. IH The high-level input voltage of buffer U1, This is the minimum voltage across capacitor C3. For driving voltage, This is the Miller plateau voltage. The gate drive resistor for the lower switching transistor is... For conduction time, The off time is T, and the switching period is T. This represents the gate-drain charge of the switching transistor. This represents the gate-source voltage of the switching transistor.

4. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 2, characterized in that, The voltage signal at node P is a triangular wave-like signal, and the frequency of the triangular wave-like signal is the same as the frequency of the lower switch drive signal.

5. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 2, characterized in that, The dead zone positive pressure clamping and negative pressure generation unit includes transistor M1, transistor M2, transistor M3, and capacitor C1; The drain of transistor M1 is connected to the GND pin of the driver chip and the first terminal of capacitor C1. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1. The second terminal of capacitor C1 is connected to the power supply unit and the drain of transistor M3. The gate of transistor M3 is connected to the power supply unit and the drain of transistor M2 through node N. The gate of transistor M2 is connected to the output terminal of the driver chip, the first terminal of resistor R3, and the gate of the lower switch. The sources of transistors M1, M2, and M3 are all grounded. The gate of transistor M1 is connected to the second terminal of capacitor C2 and the anode of diode D1 through node O.

6. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 5, characterized in that, The transistor M1 is a PMOS transistor.

7. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 5, characterized in that, Both transistor M2 and transistor M3 are NMOS transistors.

8. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 5, characterized in that, It also includes resistors R1 and R2. The first end of resistor R1 and the first end of resistor R2 are both connected to the power supply unit. The second end of resistor R1 is connected to the drain of transistor M2 and the gate of transistor M3, respectively. The second end of resistor R2 is connected to the drain of transistor M3 and the second end of capacitor C1, respectively.

9. The low-loss crosstalk suppression drive circuit for enhanced GaN power devices according to claim 8, characterized in that, The voltage signal at node N is a square wave signal, and the frequency of the square wave signal is the same as the frequency of the lower switch drive signal.

10. The low-loss crosstalk suppression driving circuit for enhanced GaN power devices according to claim 9, characterized in that, The gate-source voltage of the lower switch is clamped to a low positive voltage when the lower switch is turned off, and when positive crosstalk occurs, the gate-source voltage of the lower switch is adjusted from a low positive voltage to a negative voltage under the control of the lower switch drive signal. Alternatively, under the control of the negative voltage clamping control signal, the gate-source voltage of the lower switching transistor may be clamped from negative voltage to 0V, including: When the lower switch drive signal drives the lower switch to turn off, the power supply unit charges the capacitor C1 through resistor R2. The voltage at the first end of the capacitor C1 is clamped to the low positive voltage by transistor M1. The low positive voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switch through the output terminal of the driver chip. The gate-source voltage of the lower switch is clamped to the low positive voltage. The power supply unit provides a high-level voltage at node N through resistor R1. The transistor M2 generates a square wave signal at node N according to the lower switch drive signal. The square wave signal and the high-level voltage are used to control the switching state of transistor M3. The switching state of transistor M3 includes an on state and an off state. After transistor M3 is turned on, the voltage at the second terminal of capacitor C1 is clamped to 0V. Since the voltage across capacitor C1 cannot change abruptly, the voltage at the first terminal of capacitor C1 changes from a low positive voltage to a negative voltage. The negative voltage is introduced by the GND pin of the driver chip and applied to the gate of the lower switching transistor through the output terminal of the driver chip. The gate-source voltage of the lower switching transistor is adjusted from a low positive voltage to a negative voltage. The resistor R3 and capacitor C3 generate a triangular wave signal based on the drive signal of the lower switch transistor. The buffer U1, capacitor C2 and diode D1 generate a negative voltage clamping control signal at node O according to the triangular wave signal. The negative voltage clamping control signal drives transistor M1 to clamp the gate-source voltage of the lower switching transistor from negative voltage to 0V.

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