A full conversion voltage ratio dual-path hybrid topology step-down converter applied to an AIoT chip

Abstract

The application discloses a full conversion voltage ratio dual-path hybrid topology step-down converter applied to an AIoT chip, which is composed of a power stage and a control stage, the power stage contains five power tubes, two PMOS tubes and three NMOS tubes, five drive circuits, two capacitors, one flying capacitor CF and one output capacitor Cout, one inductor, and a load Rload, the control stage contains feedback resistors R1 and R2, Rcom1, Rcom2, Ccom1, Ccom2 and Ccom3 in a compensation module, a band-gap reference voltage module, an error amplifier, a slope voltage generator, a pulse width modulation comparator, a dead time module, a clock signal module, a digital signal module and a level shifter. The full conversion voltage ratio of the hybrid topology step-down converter is realized by switching the dual modes to each other, and the dual current paths are realized by using a dual-input single-output mode.

Description

Technical Field

[0001] This invention relates to the field of converters, and more particularly to a dual-path hybrid topology buck converter with full conversion ratio for use in AIoT chips. Background Technology

[0002] The widespread application of AIoT chips has placed stringent performance requirements on their power supply systems. As the core power management module of AIoT chips, the buck converter directly determines the chip's efficiency, integration, battery life, and stability. With AIoT chips evolving towards higher density, higher energy efficiency, lower voltage, and higher current, the performance demands on buck converters are increasing in multiple dimensions: In terms of integration, embedded AIoT devices such as smart wearables and automotive sensors require miniaturization, necessitating highly integrated buck converter designs; in terms of energy efficiency, battery-powered AIoT devices require buck converters to maintain high energy efficiency in all operating modes to extend battery life; and in terms of electrical performance, the multi-core parallel computing and high-performance operation modes of AIoT chips require high current supply capabilities, and to adapt to the operating voltages of different functional modules, buck converters need to achieve full conversion ratio output.

[0003] Existing technologies using switched inductor architectures can achieve full transfer ratios, but under high current conditions, the DC conduction loss of the inductor is significant, affecting transmission efficiency. Switched capacitor architectures have fixed transfer ratios and cannot achieve full transfer ratios, limiting their application scenarios. Hybrid topology architectures can use dual current path technology to effectively reduce inductor DC conduction losses, but it is difficult to achieve full transfer ratios, with most being 0-0.5 or 0.5-1, resulting in narrower application scenarios and making them unsuitable for various AIoT chips. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a dual-path hybrid topology buck converter with full transfer ratio for use in AIoT chips.

[0005] The objective of this invention is achieved through the following technical solution: a dual-path hybrid topology buck converter with full conversion ratio for AIoT chips, comprising a power stage and a control stage; The power stage includes five drive circuits, which are respectively connected to the gates of two PMOS transistors and three NMOS transistors; The first PMOS transistor and the first NMOS transistor are connected to the first power supply and ground respectively and are connected in series. The midpoint input is the upper end of the flying capacitor and one end of the inductor. The second PMOS transistor and the second NMOS transistor are connected to the second power supply and ground respectively and are connected in series. The midpoint input is the lower end of the flying capacitor and the third NMOS transistor. The drain of the third NMOS transistor is connected to the other end of the inductor and the upper end of the output capacitor. The control stage includes: feedback resistors R1 and R2 for voltage divider sampling of the power stage output voltage; a bandgap reference voltage module; inputting the voltage divided and sampled voltage and the reference voltage to an error amplifier, outputting an error control voltage, which, together with a ramp voltage generator, is input to a pulse width modulation comparator, and the generated signal is input to a dead time module; the outputs of the dead time module, the clock signal module, and the mode selector are input to a digital signal module, and the output of the digital signal module is passed through a level shifter to generate five control signals to control the five drive circuits of the power stage.

[0006] Furthermore, the control stage also includes a compensation module, comprising a first compensation resistor, a second compensation resistor, a first compensation capacitor, a second compensation capacitor, and a third compensation capacitor; The connection method is as follows: the lower end of the first feedback resistor R1, the upper end of the second feedback resistor R2, the lower end of the first compensation capacitor, the right end of the third compensation capacitor, the right end of the second compensation resistor, and the negative terminal of the error amplifier are connected together; the lower end of the first compensation resistor is connected to the upper end of the first compensation capacitor; the output of the error amplifier is connected to the left end of the third compensation capacitor, the left end of the second compensation capacitor, and the negative terminal of the pulse width modulation comparator.

[0007] Furthermore, the mode selector includes two operating modes: a voltage ratio of 0-0.5 and a voltage ratio of 0.5-1.

[0008] Furthermore, the 0-0.5 voltage transfer ratio operating mode specifically refers to: The driving circuit of the first PMOS transistor is always at a high level, and the driving circuit of the second NMOS transistor is always at a low level, so that the first PMOS transistor is always off and the second NMOS transistor is always off. During the first inductor magnetization phase of a cycle: the driving circuit of the second PMOS transistor is at a low level, causing the second PMOS transistor to turn on and the other transistors to turn off; The second inductor demagnetization phase within one cycle is as follows: the driving circuit of the first NMOS transistor is at a high level, causing the first NMOS transistor to turn on; the driving circuit of the third NMOS transistor is at a high level, causing the third NMOS transistor to turn on; and the remaining transistors are turned off.

[0009] Furthermore, the operating mode with a voltage conversion ratio of 0.5-1 specifically refers to: The driving circuit of the first NMOS transistor is always at a low level, and the driving circuit of the second PMOS transistor is always at a high level, so that the first NMOS transistor is always off and the second PMOS transistor is always off. Phase of the first inductor magnetization stage within one cycle: the driving circuit of the first PMOS transistor is at a low level, causing the first PMOS transistor to turn on; the driving circuit of the third NMOS transistor is at a high level, causing the third NMOS transistor to turn on; and the other transistors are turned off. During the second inductor demagnetization phase within one cycle: the driving circuit of the second NMOS transistor is at a high level, causing the second NMOS transistor to turn on and the other transistors to turn off.

[0010] The beneficial effects of this invention are: achieving the full transfer ratio of a hybrid topology buck converter by switching between dual modes; and realizing dual current paths by using dual inputs and a single output. By using a hybrid topology converter and applying dual current path technology, the inductor current is reduced while achieving the full transfer ratio range, making it applicable to various scenarios in AIoT chips. Attached Figure Description

[0011] Figure 1 This is a block diagram of the converter proposed in this invention; Figure 2 This is a graph showing the result of converting 1.8V to 0.4V in converter mode 1 of the present invention; Figure 3 This is a diagram showing the result of converting 1.8V to 1V in converter mode 2 of the present invention. Detailed Implementation

[0012] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0013] like Figure 1 As shown, the present invention provides a dual-path dual-mode hybrid topology buck converter, which consists of two main parts: a power stage and a control stage.

[0014] The power stage contains 5 power transistors, including two PMOS (positive channel metal oxide semiconductor) transistors and three NMOS (negative channel metal oxide semiconductor) transistors; 5 drive circuits; 2 capacitors, one of which is a flying capacitor CF; one is an output capacitor Cout; 1 inductor; the load is Rload; and 2 feedback resistors R1 and R2.

[0015] The control stage includes an RC compensation module; a bandgap reference voltage module; an error amplifier; a ramp voltage generator; a pulse width modulation (PWM) comparator; a dead time module; a clock signal module; a digital signal module; a level shifter; and a mode selector.

[0016] The drain of the first PMOS transistor PM1 is connected to the power supply VIN1, the source is connected to the left end of the inductor L, the upper end of the flying capacitor CF, and the drain of the first NMOS transistor NM1, and the gate is connected to the output terminal of the driver D1. The source of the first NMOS transistor NM1 is grounded to GND1, and its gate is connected to the output terminal of the driver D2. The drain of the second PMOS transistor PM2 is connected to the power supply VIN2, and the source is connected to the lower end of the flying capacitor CF, the drain of the second NMOS transistor NM2, and the source of the third NMOS transistor NM3. The gate is connected to the output terminal of the driver D3. The source of the second NMOS transistor NM2 is grounded to GND2, and its gate is connected to the output terminal of the driver D4. The drain of the third NMOS transistor NM3 is connected to the right end of the inductor, the upper end of the output capacitor Cout, the upper end of the resistor Rload, the upper end of the first feedback resistor R1, and the upper end of the first compensation resistor Rcom1. The gate is connected to the output terminal of the driver D5. The lower ends of capacitor Cout, resistor Rload, and the second feedback resistor R2 are grounded; the lower ends of the first feedback resistor R1, the upper ends of the second feedback resistor R2, the right end of the RC compensation module, and the negative end of error amplifier EA are connected; the bandgap reference voltage module outputs reference voltage VREF, which is fed into the positive end of error amplifier EA; the output of the error amplifier is connected to the left end of the RC compensation module and the negative end of the pulse width modulation comparator; the output RAMP voltage of the ramp voltage generator is fed into the positive end of the pulse width modulation comparator; the output of the pulse width modulation comparator sends the compared signal to the dead time module; The clock signal module, dead time module, and mode selector output to the digital signal module. The output of the digital signal module is then passed through a level shifter to generate five control signals S1, S2, S3, S4, and S5. Control signal S1 is input to driver D1, which controls the first PMOS transistor PM1 to turn on or off. Control signal S2 is input to driver D2, which controls the first NMOS transistor NM1 to turn on or off. Control signal S3 is input to driver D3, which controls the second PMOS transistor PM2 to turn on or off. Control signal S4 is input to driver D4, which controls the second NMOS transistor NM2 to turn on or off. Control signal S5 is input to driver D5, which controls the third NMOS transistor NM3 to turn on or off.

[0017] Define the input voltage as VIN, the output voltage as VOUT, the voltage across the capacitor as VCF, one cycle as T, and the magnetization time of the inductor as D. T, the inductor demagnetization time is (1-D). T. Working principle: The two modes switch between each other to achieve full transfer rate.

[0018] Mode 1: Operating mode with a transfer ratio of 0-0.5. S1 is always high, and S4 is always low, keeping PM1 and NM2 always off. During the inductor magnetization phase (phase 1) of one cycle, S3 is low, turning on PM2 and turning off the other transistors. At this time, the voltage across the flying capacitor is VCF, and current flows from VIN2 through transistor PM2, capacitor CF, and inductor L into the output. During the inductor demagnetization phase (phase 2) of one cycle, S2 is high, turning on NM1, and S5 is high, turning on NM3 and turning off the other transistors. At this time, the upper plate of the flying capacitor is GND, and the lower plate is VOUT. The voltage across the capacitor is VOUT, so the voltage across VCF in phase 1 equals VOUT. Current flows from GND1 through NM1, one path through capacitor CF, through transistor NM3, and into the output; the other path flows through inductor L into the output, achieving a dual current path. According to the volt-second balance principle, during the magnetization phase of the inductor, the voltage on the left side of the inductor is VIN-VCF, i.e., VIN-VOUT, and the voltage on the right side of the inductor is VOUT; during the demagnetization phase of the inductor, the voltage on the left side of the inductor is 0, and the voltage on the right side of the inductor is VOUT. We can derive the formula: Therefore, the voltage conversion ratio (VCR) for mode 1 is: The relationship between inductor current IL and load current Iload is: The value of D ranges from 0 to 1, the voltage conversion ratio VCR is 0 to 0.5, and the inductor current IL is reduced to 1 / (1+D) of the load Iload. Compared with the switching inductor converter where IL=Iload, this effectively reduces the DC conduction loss on the inductor, which has a significant advantage.

[0019] Mode 2: Operating mode with a transfer ratio of 0.5-1. S2 is always low, and S3 is always high, keeping NM1 and PM2 always off. During the inductor magnetization phase (phase 1) of one cycle, S1 is low, turning on PM1; S5 is high, turning on NM3; and the remaining transistors are off. Since the voltage across the upper plate of the flying capacitor is VIN and the voltage across the lower plate is VOUT, the voltage across the flying capacitor is VCF = VIN - VOUT. Current flows from VIN1, through transistor PM1 and inductor L, into the output terminal, and through capacitor CF and transistor NM3, into the output terminal, achieving a dual current path. During the inductor demagnetization phase (phase 2) of one cycle, S4 is high, turning on NM2 and the remaining transistors are off. At this time, the voltage across the flying capacitor is still VCF, which is VIN - VOUT. Current flows from GND2 through NM2, capacitor CF, and inductor L into the output terminal. According to the volt-second balance principle, during the magnetization phase of the inductor, the voltage on the left side of the inductor is VIN, and the voltage on the right side is VOUT; during the demagnetization phase of the inductor, the voltage on the left side is VIN - VOUT, and the voltage on the right side is VOUT. We can derive the formula: Therefore, the voltage conversion ratio (VCR) for mode 2 is: The relationship between inductor current IL and load current Iload is: The value of D ranges from 0 to 1, the voltage conversion ratio VCR is 0.5 to 1, and the inductor current IL is reduced to 1 / (2-D) of the load Iload, which effectively reduces the DC conduction loss on the inductor and has a significant advantage.

[0020] When a voltage conversion ratio of 0-0.5 is required, the external input signal X1 is input to the mode selector, and the entire circuit operates in mode 1. When a voltage conversion ratio of 0.5-1 is required, the external input signal X2 is input to the mode selector, and the entire circuit operates in mode 2. Through a dual-path, dual-modal architecture, it can flexibly switch between different working scenarios to achieve full voltage conversion ratio functionality, making it suitable for various AIoT application scenarios.

[0021] like Figure 2 As shown, under normal operating conditions of 1.8V to 0.4V conversion, the hybrid topology of this application effectively reduces the inductor current to 0.5A when the load current is 1A. The inductor current is less than the load current. Compared with the traditional two-switch control architecture where the inductor current is equal to the load current, this application effectively reduces the DC conduction loss of the inductor, thereby improving the efficiency of voltage conversion.

[0022] like Figure 3 As shown, under normal operation of 1.8V to 1V conversion, the hybrid topology of this application effectively reduces the inductor current to 0.76A when the load current is 1A. The inductor current is less than the load current. Compared with the traditional two-switch control architecture where the inductor current is equal to the load current, this application effectively reduces the DC conduction loss of the inductor, thereby improving the efficiency of voltage conversion.

[0023] Combination Figure 2 and Figure 3 This application can work well in the range of voltage conversion ratios of 0-0.5 and 0.5-1, achieving full-range voltage conversion function and effectively reducing the energy loss of the inductor.

[0024] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. This application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A dual-path hybrid topology buck converter with full transfer ratio for AIoT chips, characterized in that, Includes power stage and control stage; The power stage includes five drive circuits, which are respectively connected to the gates of two PMOS transistors and three NMOS transistors; The first PMOS transistor and the first NMOS transistor are connected to the first power supply and ground respectively and are connected in series. The upper end of the flying capacitor and one end of the inductor are connected at the midpoint. The second PMOS transistor and the second NMOS transistor are connected to the second power supply and ground respectively and are connected in series. The lower end of the flying capacitor and the third NMOS transistor are connected at the midpoint. The drain of the third NMOS transistor is connected to the other end of the inductor and the upper end of the output capacitor. The control stage includes: feedback resistors R1 and R2 for voltage divider sampling of the power stage output voltage; a bandgap reference voltage module; inputting the voltage divided and sampled voltage and the reference voltage to an error amplifier, outputting an error control voltage, which, together with a ramp voltage generator, is input to a pulse width modulation comparator, and the generated signal is input to a dead time module; the outputs of the dead time module, the clock signal module, and the mode selector are input to a digital signal module, and the output of the digital signal module is passed through a level shifter to generate five control signals to control the five drive circuits of the power stage.

2. The dual-path hybrid topology buck converter with full transfer ratio applied to AIoT chips according to claim 1, characterized in that, The control level also includes a compensation module, comprising a first compensation resistor, a second compensation resistor, a first compensation capacitor, a second compensation capacitor, and a third compensation capacitor; The connection method is as follows: the lower end of the first feedback resistor R1, the upper end of the second feedback resistor R2, the lower end of the first compensation capacitor, the right end of the third compensation capacitor, the right end of the second compensation resistor, and the negative terminal of the error amplifier are connected together; the lower end of the first compensation resistor is connected to the upper end of the first compensation capacitor; the output of the error amplifier is connected to the left end of the third compensation capacitor, the left end of the second compensation capacitor, and the negative terminal of the pulse width modulation comparator.

3. The full-ratio dual-path hybrid topology buck converter for AIoT chips according to claim 1, characterized in that, The mode selector includes two operating modes: a voltage ratio of 0-0.5 and a voltage ratio of 0.5-1.

4. A dual-path hybrid topology buck converter with full transfer ratio applied to AIoT chips according to claim 3, characterized in that, The specific operating mode with a voltage transfer ratio of 0-0.5 is as follows: The driving circuit of the first PMOS transistor is always at a high level, and the driving circuit of the second NMOS transistor is always at a low level, so that the first PMOS transistor is always off and the second NMOS transistor is always off. During the first inductor magnetization phase of a cycle: the driving circuit of the second PMOS transistor is at a low level, causing the second PMOS transistor to turn on and the other transistors to turn off; The second inductor demagnetization phase within one cycle is as follows: the driving circuit of the first NMOS transistor is at a high level, causing the first NMOS transistor to turn on; the driving circuit of the third NMOS transistor is at a high level, causing the third NMOS transistor to turn on; and the remaining transistors are turned off.

5. A dual-path hybrid topology buck converter with full transfer ratio applied to AIoT chips according to claim 3, characterized in that, The operating mode with a voltage ratio of 0.5-1 is specifically as follows: The driving circuit of the first NMOS transistor is always at a low level, and the driving circuit of the second PMOS transistor is always at a high level, so that the first NMOS transistor is always off and the second PMOS transistor is always off. Phase of the first inductor magnetization stage within one cycle: the driving circuit of the first PMOS transistor is at a low level, causing the first PMOS transistor to turn on; the driving circuit of the third NMOS transistor is at a high level, causing the third NMOS transistor to turn on; and the other transistors are turned off. During the second inductor demagnetization phase within one cycle: the driving circuit of the second NMOS transistor is at a high level, causing the second NMOS transistor to turn on and the other transistors to turn off.

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