Single voltage loop driven three-phase llc hybrid modulation method, module, system and medium

Abstract

The application discloses a single-voltage-loop-driven three-phase LLC hybrid modulation method, module, system and medium, and belongs to the field of DC-DC conversion of power supply and distribution. A single voltage loop PI controller output value is used as a unified modulation control quantity of the three-phase LLC, and after comparison with a preset mode switching threshold value, a PFM or PWM modulation mode is selected. When the control quantity is greater than the threshold value, the PFM mode is entered, the switching frequency is adaptively changed with the load, the duty cycle is fixed at 50%, and the three phases share the same period. When the control quantity is not greater than the threshold value, the PWM mode is entered, the switching frequency is fixed at the highest frequency, and the duty cycle is determined by linear mapping of the control quantity. The three phases realize 120-degree accurate interleaving through independent PWM comparison registers, have phase cross detection and burst automatic shutdown functions in the PWM mode, and the secondary side synchronous rectification signal automatically follows the LLC drive signal and is provided with independent dead-time compensation and maximum conduction time saturation clamping. The application reduces the microcontroller resource requirement, optimizes the efficiency in the full load range, balances the three-phase currents, and realizes smooth mode switching.

Description

Technical Field

[0001] This invention belongs to the field of DC-DC conversion technology for power supply and distribution, specifically relating to a single-voltage-loop driven three-phase LLC hybrid modulation method, module, system, and medium. Background Technology

[0002] Multiphase interleaved parallel DC-DC converters are widely used in applications requiring high efficiency, high power density, and low output ripple, such as high-power server power supplies, electric vehicle on-board chargers, industrial power supplies, and communication power supplies. Among them, the LLC resonant converter (LLC) has become the mainstream topology for medium and high-power DC-DC converters because it can achieve zero-voltage turn-on (ZVS) of the primary-side switch and zero-current turn-off (ZCS) of the secondary-side rectifier across the entire load range. As the requirements for output power and power density in applications such as data centers and electric vehicles continue to increase, the three-phase staggered LLC resonant converter, by operating three LLC converter units in parallel with a 120° phase difference, can further reduce the output current ripple to one-third of the original, reduce the size of filter capacitors and magnetic components, and achieve higher power levels compared to the single-phase LLC.

[0003] Existing modulation and control schemes for three-phase or multi-phase LLC resonant converters mainly include: Scheme 1, independent control scheme for each phase, where each LLC phase is equipped with an independent voltage loop PI controller and PWM modulator, and phase current balancing is achieved through a current sharing loop; this scheme requires multiple independent control loops, resulting in a complex system structure, difficult debugging, and high microcontroller resource consumption. Scheme 2, centralized phase difference modulation scheme, where the microcontroller outputs the same frequency / duty cycle command to each phase, and each phase achieves a fixed phase shift through a hardware phase offset register; although this scheme shares the same main control quantity, it lacks mode switching capability and has low efficiency under light load. Scheme 3, pure PFM (pulse frequency modulation) method, which adjusts the output voltage by changing the switching frequency, has high efficiency under heavy load, but the excessively high frequency under light load leads to a sharp increase in switching losses.

[0004] As can be seen from the above, the existing technologies mainly have the following shortcomings: First, multi-phase independent control schemes require setting up independent PI controllers and current sharing loops for each phase, resulting in numerous control parameters, a large amount of debugging work, and microcontroller computing resource requirements that increase linearly with the number of phases, which is not conducive to large-scale deployment. Second, although existing centralized control schemes share the main control quantity, they lack the ability to perform hybrid scheduling in PFM / PWM modes, making it impossible to achieve optimal efficiency under heavy and light loads, with light load efficiency significantly lower than heavy load efficiency. Third, in three-phase interleaved operation, under the fixed frequency variable duty cycle mode of PWM, the phase offset value may exceed the PWM cycle range, causing the comparison register value to flip (CMP value overflow), resulting in phase-to-phase crossover timing disorder. Existing schemes lack effective detection and protection mechanisms for such anomalies. Fourth, under the hybrid modulation framework, the secondary-side synchronous rectification (SR) needs to adapt to the different dead-time compensation requirements and maximum conduction time limits of PFM and PWM modes. In existing schemes, SR control is often overly simplified or completely independent, lacking a consistent design with LLC main modulation. Summary of the Invention

[0005] This invention provides a single-voltage-loop driven three-phase LLC hybrid modulation method, module, system, and dielectric. The main objective is to simultaneously drive a three-phase LLC resonant converter with the output of a single voltage-loop PI controller, automatically switching between PFM and PWM modulation modes according to load conditions to achieve high-efficiency operation across the entire load range. This invention is achieved through the following technical solution:

[0006] The first aspect of the present invention provides a single-voltage-loop driven three-phase LLC hybrid modulation method, applied to a modulation system comprising three-phase LLC resonant converters Phase1, Phase2, and Phase3 connected in parallel with a 120° phase difference, three-phase secondary-side synchronous rectification units SR1, SR2, and SR3, and a single-voltage-loop PI controller; the modulation method includes the following steps:

[0007] S100: In each control cycle, the PI output value is calculated by the single voltage loop PI controller based on the output voltage error, and the PI output value is used as the unified modulation control quantity of the three-phase LLC resonant converter.

[0008] S200: Determine whether the unified modulation control quantity is greater than the preset mode switching threshold. If yes, execute step S300A; otherwise, execute S300B.

[0009] S300A: Entering PFM mode: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity and the maximum switching period, and is subject to minimum and maximum period limits; the duty cycle is fixed at half of the switching period; the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase;

[0010] S300B: Enter PWM mode: The switching period of the three-phase LLC resonant converter is fixed to the minimum switching period, and the duty cycle is determined by dividing the product of the unified modulation control quantity and the maximum switching period by 2 and is limited by the minimum / maximum duty cycle.

[0011] S400: Three-phase staggered phases are achieved through independent PWM comparison registers for each phase LLC resonant converter. Phase 1 is offset by 0° as the reference phase, Phase 2 is offset by 240°, and Phase 3 is offset by 120°.

[0012] S500: In PWM mode, detect whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value of the PWM compare register corresponding to the current switching cycle. If they exceed the limit, set the corresponding CMP toggle detection flag.

[0013] S600: In PWM mode, when the duty cycle is not greater than the preset Burst start threshold, the three-phase output enable is automatically turned off simultaneously. When the duty cycle recovers to a value greater than the preset Burst start threshold, the three-phase output is automatically enabled simultaneously.

[0014] S700: Generates a secondary-side synchronous rectification SR signal. The SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies a maximum on-time saturation clamp limit to the SR comparison value.

[0015] S800: Hysteresis control for enabling and disabling SR: Determine whether the unified modulation control quantity is greater than the preset first threshold. If so, enable the three-phase SR output after a delay count; otherwise, immediately disable the three-phase SR output.

[0016] As a preferred technical solution, in the PFM mode, the PWM comparator register of the three-phase LLC resonant converter is configured as follows: pwm_llc.period=period; pwm_llc.compa=dead_time; pwm_llc.compc=duty-dead_time; pwm_llc.compb=duty+dead_time; pwm_llc.compd=period-dead_time; duty cycle duty=period / 2, the half-bridge upper and lower transistor drive signals are automatically complementary and the duty cycle is fixed at 50%; in the PWM mode, the PWM comparator register of the three-phase LLC resonant converter is configured as follows: pwm_llc.period=period; pwm_llc.compa=dead_time; pwm_llc.compc=duty+dead_time; pwm_llc.compb=compc+dead_time×2; pwm_llc.compd=compb+duty; minimum duty cycle limit is 4. The maximum duty cycle is half a cycle minus twice the dead time.

[0017] As a preferred technical solution, the CMP flip detection in step S500 specifically involves: if the Phase3 offset value is greater than the upper limit compd of the current cycle comparison register and the corresponding hardware register CMPDR value is greater than the Phase3 offset value, then the Phase3 cross flag is set; if the Phase2 offset value is greater than the upper limit compd of the current cycle comparison register and the corresponding hardware register CMPDR value is greater than the Phase2 offset value, then the Phase2 cross flag is set; the flag is used for phase offset safety compensation processing in subsequent cycles.

[0018] As a preferred technical solution, in step S600, when the duty cycle is not greater than the preset Burst start-up threshold, the output enable bit of the half-bridge drive channel of the three-phase LLC resonant converter is controlled simultaneously by a single macro instruction; when the duty cycle recovers to a value greater than the preset Burst start-up threshold, the three-phase output is enabled simultaneously by the macro instruction; three-phase synchronous operation is adopted to avoid the phase current imbalance caused by single-phase disconnection and eliminate the ineffective switching loss under extremely light load.

[0019] As a preferred technical solution, the SR signal generation in step S700 adopts a unified calculation formula independent of the modulation mode: pwm_sr.period = period; pwm_sr.compa = dead_time + sr_on_dt; pwm_sr.compc = pwm_llc.compc - sr_off_dt; pwm_sr.compb = pwm_llc.compb + sr_on_dt; pwm_sr.compd = pwm_llc.compd - sr_off_dt; the saturation clamping of the SR comparison value is: upper limit of compc = sr_max + compa, upper limit of compd = sr_max + compb; sr_on_dt is the SR turn-on delay compensation, sr_off_dt is the SR turn-off advance compensation, and sr_max is the maximum safe conduction time of SR.

[0020] As a preferred technical solution, in step S800, the first threshold is set to 0.05. When the unified modulation control quantity is greater than 0.05, the SR enable direction introduces time hysteresis through the delay counter, and the SR disable direction is an instantaneous response. The delay counter increments automatically every control cycle after the system enters a stable state or a ramp-up state. The SR is only allowed to be enabled when the count value reaches the preset value, thus preventing false triggering during startup transients.

[0021] In a second aspect, the present invention provides a single-voltage-loop driven three-phase LLC hybrid modulation module, applied to a modulation system comprising three-phase LLC resonant converters Phase1, Phase2, and Phase3 connected in parallel with a 120° phase difference, three-phase secondary-side synchronous rectification units SR1, SR2, and SR3, and a single-voltage-loop PI controller; the modulation module includes:

[0022] Unified modulation control quantity calculation unit: used to calculate the PI output value by the single voltage loop PI controller based on the output voltage error in each control cycle, and use the PI output value as the unified modulation control quantity of the three-phase LLC resonant converter.

[0023] Mode selection unit: Determines whether the unified modulation control quantity is greater than the preset mode switching threshold. If yes, it enters PFM mode; otherwise, it enters PWM mode.

[0024] PFM mode processing unit: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity and the maximum switching period, and is subject to minimum and maximum period limits; the duty cycle is fixed at half of the switching period; the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase;

[0025] PWM mode processing unit: controls the switching period of the three-phase LLC resonant converter to be fixed at the minimum switching period, and the duty cycle is determined by dividing the product of the unified modulation control quantity and the maximum switching period by 2 and is limited by the minimum / maximum duty cycle.

[0026] Three-phase phase shift processing unit: used to achieve three-phase phase shifting through the independent PWM comparison register of each phase LLC resonant converter. Phase 1 is offset by 0° as the reference phase, Phase 2 is offset by 240°, and Phase 3 is offset by 120°.

[0027] CMP Flip Detection Unit: Used in PWM mode to detect whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value of the PWM compare register corresponding to the current control cycle. If they exceed the limit, the corresponding CMP flip detection flag is set.

[0028] Burst switch control unit: In PWM mode, when the duty cycle is not greater than the preset Burst start threshold, it automatically turns off the three-phase output enable at the same time, and when the duty cycle recovers to be greater than the preset Burst start threshold, it automatically enables the three-phase output at the same time.

[0029] SR signal generation and clamping unit: used to generate secondary-side synchronous rectified SR signal. The SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies maximum on-time saturation clamping limit to the SR comparison value.

[0030] SR Enable Hysteresis Control Unit: Used to determine whether the unified modulation control quantity is greater than a preset first threshold. If so, the three-phase SR output is enabled after a delay count; otherwise, the three-phase SR output is immediately turned off.

[0031] As a preferred technical solution, in PWM mode, the LLC comparator register is configured as compa = dead time, compc = duty cycle + dead time, compb = compc + 2 times dead time, and compd = compb + duty cycle. The minimum duty cycle limit is 4 times the dead time, and the maximum duty cycle limit is half a cycle minus 2 times the dead time. In PFM mode, the LLC comparator register is configured as compa = dead time, compc = duty cycle - dead time, compb = duty cycle + dead time, and compd = period - dead time. The duty cycle is duty = period / 2. The drive signals of the upper and lower transistors of the half-bridge are automatically complementary, and the duty cycle is fixed at 50%. The SR comparator register uses a unified formula: pwm_sr.compc = pwm_llc.compc - sr_off_dt, pwm_sr.compb = pwm_llc.compb + sr_on_dt.

[0032] In a third aspect, the present invention provides a single-voltage-loop driven three-phase LLC hybrid modulation system, comprising: a DC input bus, a microcontroller, three LLC resonant converters (Phase 1, Phase 2, Phase 3) connected in parallel with a 120° phase difference, and three-phase secondary-side synchronous rectification units (SR1, SR2, SR3); the microcontroller having a single-voltage-loop PI controller, an ADC module, a data processing module, and a PWM module; the single-voltage-loop driven three-phase LLC hybrid modulation system executes the hybrid modulation method described in the first aspect.

[0033] As a preferred technical solution, the microcontroller controls the full-bridge drive channels of the three-phase LLC resonant converter as follows: Phase 1 full-bridge is driven by the microcontroller's PWM4 channel, Phase 2 full-bridge is driven by the microcontroller's PWM6 channel, and Phase 3 full-bridge is driven by the microcontroller's PWM2 channel; the microcontroller controls the synchronous rectification of the three-phase SR secondary side as follows: SR1 is driven by the microcontroller's PWM3 channel, SR2 is driven by the microcontroller's PWM0 channel, and SR3 is driven by the microcontroller's PWM1 channel.

[0034] In a fourth aspect, the present invention provides a medium having a computer-readable program stored thereon, wherein the computer-readable program, when executed, implements the hybrid modulation method described in the first aspect above.

[0035] Compared with existing technologies, the beneficial effects of this invention are as follows: First, the single voltage loop drive architecture significantly reduces the microcontroller resource requirements. Traditional solutions require three independent voltage loop PI controllers and two current sharing loops, while this invention only requires one voltage loop PI controller. The workload for PI parameter tuning is reduced by approximately 67%, CPU computational resource usage is reduced by approximately 60%, and three-phase control can be achieved by calculating only one set of PWM comparator registers. Second, efficiency is optimized across the entire load range. The PFM mode maintains high efficiency under heavy load by utilizing ZVS characteristics (full load efficiency can reach over 96%), while the PWM mode avoids high-frequency switching losses under light load. The efficiency under light load PWM mode is improved by 5 to 8 percentage points compared to the pure PFM solution, and the Burst shutdown mechanism further reduces standby power consumption under extremely light load and no-load conditions. Third, the phase offset implementation based on the comparator register fundamentally solves the limitation of insufficient number of hardware phase offset registers (usually only supporting 1-2 slave channels). Theoretically, it can be expanded to any number of phases, and the phase offset is calculated by software, not constrained by the fixed offset step size of the hardware. The phase accuracy is determined by the PWM time base resolution (up to 150ps at high-resolution PWM 32x; approximately 300ps at 16x in actual engineering). Fourth, the cross-detection mechanism (CMP flip detection) in PWM mode effectively prevents timing errors caused by phase offset crossing the cycle boundary. Fifth, the unified SR signal generation framework uses consistent calculation logic in both PFM and PWM modes, differing only in input parameters, simplifying software implementation and ensuring consistency of SR timing in both modes. The SR maximum on-time saturation clamp provides additional safety margin for the system. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart of a single-voltage loop driven three-phase LLC hybrid modulation method provided for a specific embodiment of the present invention.

[0038] Figure 2 The block diagram of a single-voltage-loop driven three-phase LLC hybrid modulation module provided for a specific embodiment of the present invention is shown.

[0039] Figure 3 The schematic diagram of the overall architecture of the single-voltage loop driven three-phase LLC hybrid modulation method, module and system provided for specific embodiments of the present invention.

[0040] Figure 4A schematic diagram of PFM / PWM modulation mode switching for a single-voltage-loop driven three-phase LLC hybrid modulation method, module, and system provided for a specific embodiment of the present invention.

[0041] Figure 5 A schematic diagram of the timing and phase offset mechanism of the three-phase interleaved PWM drive waveform of the single-voltage loop driven three-phase LLC hybrid modulation method, module and system provided for specific embodiments of the present invention.

[0042] Figure 6 The diagram shows the timing and saturation clamping of the secondary-side synchronous rectification (SR) of a single-voltage-loop driven three-phase LLC hybrid modulation method, module, and system provided for specific embodiments of the present invention. Detailed Implementation

[0043] To make the technical solution of the present invention clearer and its technical advantages more apparent, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of the present invention.

[0044] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0045] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0048] Combination Figure 1 and Figure 3 As shown, the single-voltage-loop driven three-phase LLC hybrid modulation system provided in this embodiment includes: a DC input bus, a single-voltage-loop PI controller, three LLC resonant converters Phase1, Phase2, and Phase3 connected in parallel with a 120° phase difference, and three-phase secondary-side synchronous rectification units SR1, SR2, and SR3.

[0049] Specifically, the DC input bus can be a 400V DC input bus. Phase 1 includes a full-bridge (upper transistor Q1A, lower transistor Q1B), a Phase 1 resonant cavity (Lr1 and Cr1), with a resonant frequency of approximately 130kHz. The transformer for Phase 1 is T1 (turns ratio n:1), and the corresponding secondary-side synchronous rectification unit for Phase 1 is SR1. Phase 2 includes a full-bridge (upper transistor Q2A, lower transistor Q2B), a Phase 2 resonant cavity (Lr2 and Cr2), a Phase 2 transformer T2 (turns ratio n:1), and the corresponding secondary-side synchronous rectification unit for Phase 2 is SR2. Phase 3 includes a full-bridge (upper transistor Q3A, lower transistor Q3B), a Phase 3 resonant cavity (Lr3 and Cr3), a Phase 3 transformer T3 (turns ratio n:1), and the corresponding secondary-side synchronous rectification unit for Phase 3 is SR3. The output filter capacitor Co and the load (rated output 53.5V / maximum power 3kW) are also included. In the above text, Q1A, Q1B...T3, etc. are only device names or abbreviations, not part of the attached diagram.

[0050] The microcontroller's main frequency can be 200MHz, and it has a built-in high-resolution PWM (HRPWM) module with a PWM clock resolution of approximately 300ps (HRPWM 16 times in actual engineering). The detailed mapping relationship of the microcontroller's PWM channels is as follows: The Phase 1 full-bridge drive signal is generated by the PWM hardware configuration constant channel (llc_1_pwm_num=4), that is, the Phase 1 full bridge is driven by the microcontroller's PWM4 channel, corresponding to the start bit BIT(21), and the control bits are LLC1_PWM4_CTRL_A_BIT (BIT(8)) and LLC1_PWM4_CTRL_B_BIT (BIT(9)); The Phase 2 full-bridge drive signal is generated by the PWM hardware configuration constant channel (llc_2_pwm_num=6), that is, the Phase 2 full bridge is driven by the microcontroller's PWM4 channel. The 6-channel drive corresponds to the start bit BIT(23), and the control bits are LLC2_PWM6_CTRL_A_BIT (BIT(12)) and LLC2_PWM6_CTRL_B_BIT (BIT(13)). The Phase3 full-bridge drive signal is generated by the constant channel of the PWM hardware configuration (llc_3_pwm_num=2), that is, the Phase3 full-bridge is driven by the PWM2 channel of the microcontroller, corresponding to the start bit BIT(19), and the control bits are LLC3_PWM2_CTRL_A_BIT (BIT(4)) and LLC3_PWM2_CTRL_B_BIT (BIT(5)). The SR1 drive signal is generated by the constant channel configured by the PWM hardware (sr_1_pwm_num=3), meaning that SR1 is driven by the microcontroller's PWM3 channel; the SR2 drive signal is generated by the constant channel configured by the PWM hardware (sr_2_pwm_num=0), meaning that SR2 is driven by the microcontroller's PWM0 channel; and the SR3 drive signal is generated by the constant channel configured by the PWM hardware (sr_3_pwm_num=1), meaning that SR3 is driven by the microcontroller's PWM1 channel.

[0051] The microcontroller's ADC sampling is triggered by a constant PWM hardware configuration channel at a fixed frequency of 100kHz (corresponding to ADC_TRIGGER_PWM5), which is the microcontroller's PWM channel. The control interrupt service routine executes with a fixed 10μs cycle. The ADC channel includes output voltage sampling (Vout), output current sampling (Iout), and temperature sampling. The sampling results of each channel are read by the ADC data acquisition function adc_data_get() and stored in the global structure llc. All PWM compare register update operations are uniformly broadcast in the PWM6 channel interrupt corresponding to Phase 2 through a hardware broadcast mechanism to ensure that the three-phase PWM compare registers are updated synchronously within the same PWM cycle, preventing time deviations caused by independent updates of each phase. During the update operation, the PWM6 interrupt is first disabled (__LL_PWM hardware configuration constant lv_Period_INT_Dis), and then re-enabled after each PWM compare register is written (__LL_PWM hardware configuration constant lv_Period_INT_En).

[0052] The single-voltage-loop driven three-phase LLC hybrid modulation system described above performs the single-voltage-loop driven three-phase LLC hybrid modulation method described below, which includes the following steps:

[0053] S100: In each control cycle, the single voltage loop PI controller calculates the PI output value (llc.vloop_result) based on the output voltage error, and uses the PI output value as the unified modulation control quantity (llc.llc_result) of the three-phase LLC resonant converter.

[0054] S200: Determine whether the unified modulation control quantity (llc.llc_result) is greater than the preset mode switching threshold (MODE_SWITCH). If yes, execute step S300A; otherwise, execute S300B.

[0055] S300A: Entering PFM mode: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity (llc.llc_result) and the maximum switching period (LLC_SW_PERIOD_MAX), and is limited by the minimum and maximum periods; the duty cycle is fixed at half of the switching period (i.e., 50% duty cycle); the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase.

[0056] S300B: Entering PWM mode: The switching period of the three-phase LLC resonant converter is fixed at the minimum switching period (LLC_SW_PERIOD_MIN), corresponding to the highest switching frequency. The duty cycle is determined by dividing the product of the unified modulation control quantity (llc.llc_result) and the maximum switching period (LLC_SW_PERIOD_MAX) by 2 and is limited by the minimum / maximum duty cycle.

[0057] S400: Three-phase phase interleaving is achieved through independent PWM comparator registers for each phase LLC resonant converter. Phase 1 is used as the reference phase with an offset of 0°, Phase 2 offset (Phase_2_value) is 4×period / 6 (corresponding to 240°), and Phase 3 offset (Phase_3_value) is 2×period / 6 (corresponding to 120°).

[0058] S500: In PWM mode, the system detects in real time whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value (compd) of the PWM comparator register corresponding to the current switching cycle. If they exceed the limit, the PWM comparator register value of that phase may cross the cycle boundary. The corresponding CMP toggle detection flag is set for subsequent cycles to read for phase offset safety processing.

[0059] S600: In PWM mode, automatic Burst shutdown and recovery operations are required. When the duty cycle is not greater than the preset Burst start threshold (LLC_BURST_MODE_START_CNT), the three-phase output enable is automatically shut down simultaneously. When the duty cycle recovers to a value greater than the preset Burst start threshold (LLC_BURST_MODE_START_CNT), the three-phase output is automatically enabled simultaneously. This mechanism avoids power loss caused by ineffective switching actions under extremely light load conditions.

[0060] S700: Generates a secondary-side synchronous rectification SR signal. In both PFM and PWM modes, the SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies a maximum on-time saturation clamping limit to the SR comparison value.

[0061] S800: Hysteresis control for enabling and disabling SR: Determine whether the unified modulation control quantity is greater than the preset first threshold. If so, enable the three-phase SR output after a delay count; otherwise, immediately disable the three-phase SR output.

[0062] The following details the algorithm flow and three-phase phase-shifting implementation mechanism under PWM modulation mode, combined with... Figure 5 As shown.

[0063] Specifically, the switching period in PFM mode is calculated as follows: period = (llc.llc_result × LLC_SW_PERIOD_MAX). The period is clamped: if the calculated result is greater than LLC_SW_PERIOD_MAX, it is clamped to LLC_SW_PERIOD_MAX; if it is less than LLC_SW_PERIOD_MIN, it is clamped to LLC_SW_PERIOD_MIN. LLC_SW_PERIOD_MAX corresponds to the system's lowest switching frequency (approximately 60kHz), and LLC_SW_PERIOD_MIN corresponds to the system's highest switching frequency (approximately 200kHz). As llc.llc_result increases from MODE_SWITCH to 1.0, period increases from LLC_SW_PERIOD_MIN to LLC_SW_PERIOD_MAX, and the switching frequency correspondingly decreases from 200kHz to 60kHz. Duty = period / 2 (i.e., right-shifted by 1 bit), and the duty cycle is fixed at 50%.

[0064] Specifically, in PWM mode, the switching period is fixed at period = LLC_SW_PERIOD_MIN (corresponding to a maximum switching frequency of 200kHz) and does not change with llc.llc_result. The duty cycle is calculated as: duty = ((llc.llc_result × LLC_SW_PERIOD_MAX) / 2). Duty is subject to dual limiting: the lower limit is dead time (dead) × 4, and the upper limit is half_period - dead × 2 (where half_period = period / 2, dead_x2 = dead × 2, dead_x4 = dead × 4). When llc.llc_result = 0, duty = dead × 4, which is a very small minimum turn-on pulse; when llc.llc_result = MODE_SWITCH, duty = half_period - dead_time × 2, corresponding to the maximum turn-on time from the PWM mode boundary to the PFM mode.

[0065] To make this embodiment clearer, the relevant parameters of the PWM compare register are explained below, as shown in Table 1:

[0066] Table 1

[0067] compa CMPA Cycle start dead zone, upper pipe opening point The beginning of the cycle, the start of the dead zone SR activation delay reference point compc CMPC Upper pipe shutdown timestamp Upper pipe shutdown timestamp SR First Bridge Arm Closure Time compb CMPB Pipeline opening timestamp Pipeline opening timestamp SR Second Bridge Arm Opening Time compd CMPD End of cycle dead zone, pipe shut-off Downpipe shut-off timestamp SR Second Bridge Arm Closure Time

[0068] Combined with Table 1 and Figure 4As shown, in the PFM mode, the PWM comparator register of the three-phase LLC resonant converter is configured as follows (based on pwm_llc): pwm_llc.period = period; pwm_llc.compa = dead_time (dead time, abbreviated as dead); pwm_llc.compc = duty - dead_time; pwm_llc.compb = duty + dead_time; pwm_llc.compd = period - dead_time. Under this configuration, the drive signals for the upper and lower transistors of the LLC half-bridge decrease at CMPC (turning off the upper transistor), increase at CMPB (turning on the lower transistor), decrease at CMPD (turning off the lower transistor), and increase at CMPA (turning on the upper transistor), forming a symmetrical 50% duty cycle complementary drive waveform. The dead time dead_time is automatically inserted between the upper and lower transistors. In PFM mode, the system outputs a high level to GPIOC_PIN_3 (GPIOC->BSR = general purpose I / O pin) via GPIO to indicate that it is currently operating in PFM mode, and at the same time clears the updclr_cnt counter (llc.updclr_cnt = 0).

[0069] Combined with Table 1 and Figure 4 As shown, in the PWM mode, the PWM comparator register of the three-phase LLC resonant converter is configured (based on pwm_llc): pwm_llc.period = period; pwm_llc.compa = dead_time; pwm_llc.compc = duty + dead_time; pwm_llc.compb = compc + dead_time × 2; pwm_llc.compd = compb + duty. This configuration generates a variable duty cycle drive signal under asymmetric PWM: CMPA determines the dead time start point, CMPC determines the upper transistor conduction end point, CMPB determines the lower transistor conduction start point (interval with CMPC by 2 times the dead time), and CMPD determines the lower transistor conduction end point. The conduction time duty cycle is directly controlled by the duty value. In PWM mode, the system outputs a low level to GPIOC_PIN_3 (GPIO->BSR = general purpose I / O pin << 16) via GPIO to indicate that it is currently operating in PWM mode.

[0070] Phase shifting is achieved through independent PWM compare registers (CMPA / CMPB / CMPC / CMPD) rather than a global phase offset register. Each phase LLC has an independent TW_PWM hardware configuration constant ypeDef structure, storing period and four compare values. Phase shifts in Phase 2 and Phase 3 are achieved by adding a fixed offset to each phase's own compare value, resulting in a uniform 120° distribution within the complete PWM cycle. Phase 2 offset = 4 × period / 6 (240° electrical angle), Phase 3 offset = 2 × period / 6 (120° electrical angle), and Phase 1 uses zero offset as the reference.

[0071] In Phase 2, the values ​​of all four comparison registers are added to the base value with an offset of phase_2_value, and in Phase 3, the same applies with an offset of phase_3_value. Since the comparison values ​​for each phase are within the same period, when phase_2_value or phase_3_value, after adding the corresponding compd, exceeds the period, the excess portion is automatically wrapped around to the beginning of the next cycle by the PWM hardware, naturally achieving phase allocation within a 360° cycle. This scheme eliminates the need for hardware phase offset registers (which typically only support 1-2 slave channels) for the three PWM channels. Instead, it achieves arbitrary angle offsets by calculating independent complete comparison register sets for each phase in software, providing excellent scalability.

[0072] In PFM mode, the phase offset value changes dynamically with the period: phase_2_value = 4 × period / 6, phase_3_value = 2 × period / 6. When the period changes due to frequency modulation, the offset value automatically adjusts accordingly to ensure that the three phases always maintain a precise 120° phase difference across the entire frequency range from 60kHz to 200kHz.

[0073] The following explains the Burst automatic shutdown recovery mechanism and the phase crossover CMP flip detection mechanism in PWM mode.

[0074] The Burst automatic shutdown and recovery logic is as follows: In PWM mode, after the duty cycle (duty) is calculated, the system determines whether the duty is greater than the preset Burst start threshold (LLC_BURST_MODE_START_CNT). When duty > LLC_BURST_MODE_START_CNT (load conditions allow effective power transfer), the system executes the LLC_ALL_PHASES_OEN macro, and simultaneously enables the PWM outputs of Phase 1, Phase 2, and Phase 3 (corresponding to LLC1_PWM4_CTRL_A_BIT and LLC1_PWM4_CTRL_B_BIT, LLC2_PWM6_CTRL_A_BIT and LLC2_PWM6_CTRL_B_BIT, LLC3_PWM2_CTRL_A_BIT and LLC3_PWM2_CTRL_B_BIT, respectively), and the three phases output drive pulses normally. When duty ≤ LLC_BURST_MODE_START_CNT, the system executes the LLC_ALL_PHASES_ODIS macro, simultaneously shutting down the three-phase PWM output, and the power stage enters a high-impedance state. This Burst shutdown is a complete three-phase simultaneous operation, avoiding the phase-to-phase current imbalance problem caused by single-phase shutdown. When duty recovers to a level greater than the threshold in the next control cycle, the three-phase output automatically re-enables, and the recovery process is smooth and shock-free.

[0075] Combination Figure 5 As shown, the phase crossover (CMP flip) detection mechanism is a preventative detection mechanism for the comparator register value to flip due to the phase offset value exceeding the current cycle range in PWM mode. The detection logic is as follows: In PWM mode, the system checks the conditions of Phase 3 and Phase 2 respectively. For Phase 3, if phase_3_value > pwm_llc.compd and the current PWM comparator register value (CMPDR) in the hardware register is greater than phase_3_value (i.e., the offset of the previous cycle has exceeded the limit and the hardware has not yet wrapped back), then a preset flag bit (llc.llc3_cmp_over) for Phase 3 is set to 1; otherwise, it is cleared to zero. For Phase 2, if phase_2_value > pwm_llc.compd and the current PWM comparator register value (CMPDR) in the hardware register is greater than phase_2_value, then a preset flag bit (llc.llc2_cmp_over) for Phase 3 is set to 1; otherwise, it is cleared to zero. Figure 5In this context, phase_3_value and phase_2_value are referred to as phase_value, pwm_llc.compd is abbreviated as pwm.compd, and llc.llc3_cmp_over and llc.llc2_cmp_over are referred to as cmp_over.

[0076] The function of the CMP toggle detection flag is as follows: When the corresponding flag is detected to be valid, the PWM comparison value of the corresponding phase will be compensated in the next update cycle (such as delaying the update by one cycle or updating in segments) to avoid PWM output timing errors (such as simultaneous conduction of upper and lower transistors, phase sequence reversal, etc.) caused by the comparison register value crossing the cycle boundary. Since the duty cycle is fixed at 50% in PFM mode and compd = period - dead, the phase offset values ​​2×period / 6 and 4×period / 6 will theoretically not exceed the range of compd. Therefore, CMP toggle detection is only performed in PWM mode, reducing unnecessary CPU detection overhead.

[0077] This document details the unified generation method for the secondary-side synchronous rectifier (SR) signal in both PFM and PWM modes, including independent dead-time compensation, maximum on-time saturation clamping, and SR enable / disable hysteresis control. Figure 6 As shown.

[0078] A unified framework for SR comparator register calculation: After both PFM and PWM modes are completed, the same SR comparator register calculation code block is executed, eliminating mode branches. The comparison value calculation method for the SR template structure pwm_sr is as follows: pwm_sr.period = period (same as the LLC switching period); pwm_sr.compa = dead_time + sr_on_dt ( Figure 6 The abbreviation for sr_on_dead_time refers to the SR turn-on delay compensation. sr_on_dt means that the SR turn-on lags behind the LLC to avoid premature SR turn-on caused by transformer leakage inductance; pwm_sr.compc = pwm_llc.compc - sr_off_dt ( Figure 6 The abbreviation for sr_off_dead_time refers to the SR turn-off advance compensation. sr_off_dt is a positive time when the SR turns off before the LLC to avoid reverse recovery losses of the SR body diode. pwm_sr.compb = pwm_llc.compb + sr_on_dt; pwm_sr.compd = pwm_llc.compd - sr_off_dt.

[0079] Because the comparison values ​​of pwm_llc are defined differently in PFM and PWM modes (compc = duty - dead in PFM, compc = duty + dead in PWM), the above SR calculation logic automatically adapts to the timing requirements of the two modes. In PFM mode, pwm_sr.compc = duty - dead - sr_off_dt, reflecting the SR turn-off point under PFM symmetrical drive. In PWM mode, pwm_sr.compc = duty + dead - sr_off_dt, reflecting the SR turn-off point under PWM asymmetric drive. That is, regardless of whether it is PFM or PWM mode, the compc of SR is limited by the upper limit sr_max + compa, and the compd is limited by the upper limit sr_max + compb, preventing the SR conduction time from exceeding the safe range under abnormal operating conditions. This unified framework ensures the simplicity of the code and the consistency of SR behavior in the two modes.

[0080] SR Maximum On-Time Saturation Clamping: After the SR compare register is calculated, a uniform saturation clamping process is performed. The saturation upper limit is defined as: sr_limit_c = sr_max + pwm_sr.compa, sr_limit_d = sr_max + pwm_sr.compb. If pwm_sr.compc > sr_limit_c, then pwm_sr.compc is clamped to sr_limit_c, meaning the C channel compare value of the SR does not exceed the time range of sr_max after compa. If pwm_sr.compd > sr_limit_d, then pwm_sr.compd is clamped to sr_limit_d, meaning the D channel compare value of the SR does not exceed the time range of sr_max after compb. sr_max is the maximum safe on-time of the SR (…). Figure 6 The abbreviation for sr_max_on_time (with a value such as 5500ns) is used to prevent overrunning caused by excessive SR conduction time under transformer saturation or abnormal resonance conditions.

[0081] Hysteresis control for enabling and disabling SR uses `llc.llc_result > 0.05` as the load condition threshold for enabling SR, i.e., the first threshold is 0.05. The specific logic is as follows: when `llc.llc_result > 0.05`, if the current SR state is off (`llc.sr_pwm == sr_pwm_off`), then a delay confirmation is first performed using the `sr_delay_cnt` counter. The `sr_delay_cnt` value increments by 1 each control cycle. When `sr_delay_cnt` ≥ 1 and the SR is still off, the system performs an SR enable operation: A high-level output is sent to GPIOA (GPIOA->BSR = general-purpose I / O pin) to indicate that the SR is enabled. Then, the macros `SR_PHASE1_OUT_EN`, `SR_PHASE2_OUT_EN`, and `SR_PHASE3_OUT_EN` are executed sequentially to enable the three-phase SR outputs (corresponding to `SR1_PWM3_CTRL_A_BIT / SR1_PWM3_CTRL_B_BIT`, `SR2_PWM0_CTRL_A_BIT / SR2_PWM0_CTRL_B_BIT`, and `SR3_PWM1_CTRL_A_BIT / SR3_PWM1_CTRL_B_BIT`, respectively). `llc.sr_pwm` is set to `sr_pwm_on`, and `sr_delay_cnt` is cleared. If the SR is already on, the value remains unchanged. When llc.llc_result ≤ 0.05, if the current SR state is on (llc.sr_pwm == sr_pwm_on), the SR shutdown operation is immediately executed: the three-phase SR output is shut down by outputting a low level through GPIOA (GPIOA->BSR = general IO pin << 16), the macros SR_PHASE1_OUT_DIS, SR_PHASE2_OUT_DIS, and SR_PHASE3_OUT_DIS are executed in sequence to shut down the three-phase SR output, llc.sr_pwm = sr_pwm_off is set, and sr_delay_cnt is cleared.

[0082] The design principle of SR hysteresis control is as follows: both the turn-on threshold and the turn-off threshold are set to `llc_result = 0.05` (zero hysteresis width), but a time hysteresis is introduced in the turn-on direction through the `sr_delay_cnt` delay counter to prevent SR from being falsely turned on due to transient startup or brief load fluctuations. This delay mechanism ensures that SR is only enabled after `llc_result` has been continuously greater than 0.05 for a period of time, while the turn-off action is instantaneous, guaranteeing that SR can quickly turn off to protect the device under light load or fault conditions. The SR body diode naturally assumes the rectification function during SR turn-off; although the forward voltage drop is relatively large, the impact on losses is minimal under light load conditions.

[0083] Combination Figure 2 As shown, this embodiment of the invention also provides a single-voltage-loop driven three-phase LLC hybrid modulation module, comprising:

[0084] Unified modulation control quantity calculation unit: used to calculate the PI output value based on the output voltage error by the single voltage loop PI controller in each control cycle, and use the PI output value as the unified modulation control quantity of the three-phase LLC resonant converter.

[0085] Mode selection unit: Determines whether the unified modulation control quantity is greater than the preset mode switching threshold. If yes, it enters PFM mode; otherwise, it enters PWM mode.

[0086] PFM mode processing unit: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity and the maximum switching period, and is subject to minimum and maximum period limits; the duty cycle is fixed at half of the switching period; the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase;

[0087] PWM mode processing unit: controls the switching period of the three-phase LLC resonant converter to be fixed at the minimum switching period, and the duty cycle is determined by dividing the product of the unified modulation control quantity and the maximum switching period by 2 and is limited by the minimum / maximum duty cycle.

[0088] Three-phase phase shift processing unit: used to achieve three-phase phase shifting through the independent PWM comparison register of each phase LLC resonant converter. Phase 1 is offset by 0° as the reference phase, Phase 2 is offset by 240°, and Phase 3 is offset by 120°.

[0089] CMP Flip Detection Unit: Used in PWM mode to detect whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value of the PWM compare register corresponding to the current control cycle. If they exceed the limit, the corresponding CMP flip detection flag is set.

[0090] Burst switch control unit: In PWM mode, when the duty cycle is not greater than the preset Burst start threshold, it automatically turns off the three-phase output enable at the same time, and when the duty cycle recovers to be greater than the preset Burst start threshold, it automatically enables the three-phase output at the same time.

[0091] SR signal generation and clamping unit: used to generate secondary-side synchronous rectified SR signal. The SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies maximum on-time saturation clamping limit to the SR comparison value.

[0092] SR Enable Hysteresis Control Unit: Used to determine whether the unified modulation control quantity is greater than a preset first threshold. If so, the three-phase SR output is enabled after a delay count; otherwise, the three-phase SR output is immediately turned off.

[0093] In PWM mode, the LLC comparator register is configured as compa = dead time, compc = duty cycle + dead time, compb = compc + 2 times dead time, and compd = compb + duty cycle. The minimum duty cycle limit is 4 times the dead time, and the maximum duty cycle limit is half a cycle minus 2 times the dead time. In PFM mode, the LLC comparator register is configured as compa = dead time, compc = duty cycle - dead time, compb = duty cycle + dead time, and compd = period - dead time. The duty cycle is duty = period / 2. The drive signals of the upper and lower transistors of the half-bridge are automatically complementary, and the duty cycle is fixed at 50%. The SR comparator register uses a unified formula: pwm_sr.compc = pwm_llc.compc - sr_off_dt, pwm_sr.compb = pwm_llc.compb + sr_on_dt.

[0094] The present invention also provides a computer-readable storage medium storing a computer-readable program, wherein the processor executes the computer-readable program to implement the above-described hybrid modulation method.

[0095] The single-voltage-loop driven three-phase LLC hybrid modulation method, module, system, and medium provided in the above embodiments have beneficial effects including but not limited to the following aspects:

[0096] Reduced microcontroller resource consumption and simplified debugging: The traditional multi-phase multi-PI + current sharing loop architecture is abandoned, and only a single voltage loop PI controller is used to drive the three-phase LLC. The workload of PI parameter debugging is reduced by about 67%, CPU computing resource consumption is reduced by about 60%, and three-phase control can be completed by calculating only one set of PWM comparator registers, which facilitates large-scale engineering deployment.

[0097] Full load range efficiency optimization: The heavy load PFM mode maintains the original side ZVS characteristics, and the full load efficiency can reach more than 96%; the light load switches to PWM fixed frequency mode to avoid high frequency switching losses, and the light load efficiency is improved by 5-8 percentage points compared with the pure PFM solution; the Burst synchronous shutdown mechanism further reduces the standby power consumption under no-load and extremely light load conditions.

[0098] Three-phase interleaving offers strong scalability and high phase accuracy: Phase offset is achieved by relying on independent PWM comparator registers for each phase, eliminating the limitation on the number of hardware phase offset register channels, and theoretically expandable to any number of phases; Phase offset is calculated in real time by software, and phase accuracy is determined by the PWM time base resolution, reaching 150ps level under high-resolution PWM conditions (32 times frequency; approximately 300ps under actual 16 times frequency); The offset during PFM frequency modulation is adaptive with the period, maintaining a precise 120° phase shift across the entire frequency range.

[0099] Enhanced fault protection capabilities: The PWM mode introduces a CMP flip detection mechanism to identify the risk of phase offset crossing the cycle boundary, and sets a flag in advance for subsequent compensation to avoid faults such as timing errors and shoot-through between upper and lower transistors.

[0100] The secondary-side synchronous rectification timing is unified and highly secure: the PFM and PWM modulation modes reuse the same SR timing calculation logic, resulting in concise code and good consistency in timing behavior; configuration of turn-on delay and turn-off advance compensation suppresses reverse recovery loss; the maximum conduction time saturation clamp of SR is added to limit the SR conduction window under abnormal transformer and resonance conditions, thereby improving hardware safety margin; SR turn-on has time hysteresis and turn-off has instantaneous response, avoiding frequent SR switching caused by load fluctuations and startup transients.

[0101] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A single-voltage-loop driven three-phase LLC hybrid modulation method, applied to a modulation system comprising three-phase LLC resonant converters Phase1, Phase2, and Phase3 connected in parallel with a 120° phase difference, three-phase secondary-side synchronous rectification units SR1, SR2, and SR3, and a single-voltage-loop PI controller; characterized in that, The modulation method includes the following steps: S100: In each control cycle, the PI output value is calculated by the single voltage loop PI controller based on the output voltage error, and the PI output value is used as the unified modulation control quantity of the three-phase LLC resonant converter. S200: Determine whether the unified modulation control quantity is greater than the preset mode switching threshold. If yes, execute step S300A; otherwise, execute S300B. S300A: Entering PFM mode: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity and the maximum switching period, and is subject to minimum and maximum period limits; the duty cycle is fixed at half of the switching period; the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase; S300B: Enter PWM mode: The switching period of the three-phase LLC resonant converter is fixed to the minimum switching period, and the duty cycle is determined by dividing the product of the unified modulation control quantity and the maximum switching period by 2 and is limited by the minimum / maximum duty cycle. S400: Three-phase staggered phases are achieved through independent PWM comparison registers for each phase LLC resonant converter. Phase 1 is offset by 0° as the reference phase, Phase 2 is offset by 240°, and Phase 3 is offset by 120°. S500: In PWM mode, detect whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value of the PWM compare register corresponding to the current switching cycle. If they exceed the limit, set the corresponding CMP toggle detection flag. S600: In PWM mode, when the duty cycle is not greater than the preset Burst start threshold, the three-phase output enable is automatically turned off simultaneously. When the duty cycle recovers to a value greater than the preset Burst start threshold, the three-phase output is automatically enabled simultaneously. S700: Generates a secondary-side synchronous rectification SR signal. The SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies a maximum on-time saturation clamp limit to the SR comparison value. S800: Hysteresis control for enabling and disabling SR: Determine whether the unified modulation control quantity is greater than the preset first threshold. If so, enable the three-phase SR output after a delay count; otherwise, immediately disable the three-phase SR output.

2. The single-voltage loop driven three-phase LLC hybrid modulation method according to claim 1, characterized in that, In the PFM mode, the PWM comparator register of the three-phase LLC resonant converter is configured as follows: pwm_llc.period = period; pwm_llc.compa = dead_time; pwm_llc.compc = duty - dead_time; pwm_llc.compb = duty + dead_time; pwm_llc.compd = period - dead_time; duty cycle duty = period / 2, the drive signals of the upper and lower half-bridge transistors are automatically complementary and the duty cycle is fixed at 50%; in the PWM mode, the PWM comparator register of the three-phase LLC resonant converter is configured as follows: pwm_llc.period = period; pwm_llc.compa = dead_time; pwm_llc.compc = duty + dead_time; pwm_llc.compb = compc + dead_time × 2; pwm_llc.compd = compb + duty; The minimum duty cycle limit is 4 times the dead time, and the maximum duty cycle limit is half a cycle minus 2 times the dead time.

3. The single-voltage loop driven three-phase LLC hybrid modulation method according to claim 1, characterized in that, The CMP flip detection in step S500 is specifically as follows: if the Phase3 offset value is greater than the current cycle comparison register upper limit compd and the corresponding hardware register CMPDR value is greater than the Phase3 offset value, then the Phase3 cross flag is set. If the Phase2 offset value is greater than the current cycle's upper limit compd of the compare register and the corresponding hardware register CMPDR value is greater than the Phase2 offset value, then the Phase2 cross flag is set; the flag is used for phase offset safety compensation in subsequent cycles.

4. The single-voltage loop driven three-phase LLC hybrid modulation method according to claim 1, characterized in that, In step S600, when the duty cycle is not greater than the preset Burst start threshold, the output enable bit of the half-bridge drive channel of the three-phase LLC resonant converter is controlled simultaneously by a single macro instruction. When the duty cycle recovers to a value greater than the preset Burst start threshold, the three-phase output is enabled simultaneously via macro instructions; three-phase synchronous operation is adopted to avoid the phase current imbalance caused by single-phase disconnection and to eliminate the ineffective switching loss under extremely light load.

5. The single-voltage loop driven three-phase LLC hybrid modulation method according to claim 2, characterized in that, In step S700, the SR signal generation adopts a unified calculation formula independent of the modulation mode: pwm_sr.period = period; pwm_sr.compa = dead_time + sr_on_dt; pwm_sr.compc = pwm_llc.compc - sr_off_dt; pwm_sr.compb = pwm_llc.compb + sr_on_dt; pwm_sr.compd = pwm_llc.compd - sr_off_dt; the saturation clamping of the SR comparison value is: upper limit of compc = sr_max + compa, upper limit of compd = sr_max + compb; sr_on_dt is the SR turn-on delay compensation, sr_off_dt is the SR turn-off advance compensation, and sr_max is the maximum safe conduction time of SR.

6. The single-voltage loop driven three-phase LLC hybrid modulation method according to claim 1, characterized in that, In step S800, the first threshold is set to 0.

05. When the unified modulation control quantity is greater than 0.05, the SR enable direction introduces time hysteresis through the delay counter, and the SR disable direction is an instantaneous response. The delay counter increments automatically every control cycle after the system enters a stable state or a ramp-up state. The SR is only allowed to be enabled when the count value reaches the preset value to prevent false triggering during startup transients.

7. A single-voltage-loop driven three-phase LLC hybrid modulation module, applied to a modulation system comprising three-phase LLC resonant converters Phase1, Phase2, and Phase3 connected in parallel with a 120° phase difference, three-phase secondary-side synchronous rectification units SR1, SR2, and SR3, and a single-voltage-loop PI controller; characterized in that, The modulation module includes: Unified modulation control quantity calculation unit: used to calculate the PI output value by the single voltage loop PI controller based on the output voltage error in each control cycle, and use the PI output value as the unified modulation control quantity of the three-phase LLC resonant converter. Mode selection unit: Determines whether the unified modulation control quantity is greater than the preset mode switching threshold. If yes, it enters PFM mode; otherwise, it enters PWM mode. PFM mode processing unit: The switching period of the three-phase LLC resonant converter is determined by the product of the unified modulation control quantity and the maximum switching period, and is subject to minimum and maximum period limits; the duty cycle is fixed at half of the switching period; the three phases share the same switching period, and phase misalignment is achieved through independent PWM comparison registers for each phase; PWM mode processing unit: controls the switching period of the three-phase LLC resonant converter to be fixed at the minimum switching period, and the duty cycle is determined by dividing the product of the unified modulation control quantity and the maximum switching period by 2 and is limited by the minimum / maximum duty cycle. Three-phase phase shift processing unit: used to achieve three-phase phase shifting through the independent PWM comparison register of each phase LLC resonant converter. Phase 1 is offset by 0° as the reference phase, Phase 2 is offset by 240°, and Phase 3 is offset by 120°. CMP Flip Detection Unit: Used in PWM mode to detect whether the phase offset values ​​of Phase2 and Phase3 exceed the upper limit value of the PWM compare register corresponding to the current control cycle. If they exceed the limit, the corresponding CMP flip detection flag is set. Burst switch control unit: In PWM mode, when the duty cycle is not greater than the preset Burst start threshold, it automatically turns off the three-phase output enable at the same time, and when the duty cycle recovers to be greater than the preset Burst start threshold, it automatically enables the three-phase output at the same time. SR signal generation and clamping unit: used to generate secondary-side synchronous rectified SR signal. The SR signal automatically follows the half-bridge PWM comparison value of the corresponding LLC resonant converter, applies independent turn-on delay and turn-off advance compensation, and applies maximum on-time saturation clamping limit to the SR comparison value. SR Enable Hysteresis Control Unit: Used to determine whether the unified modulation control quantity is greater than a preset first threshold. If so, the three-phase SR output is enabled after a delay count; otherwise, the three-phase SR output is immediately turned off.

8. A three-phase LLC hybrid modulation system driven by a single voltage loop, characterized in that, include: The system comprises a DC input bus, a microcontroller, three LLC resonant converters (Phase 1, Phase 2, Phase 3) connected in parallel with a 120° phase difference, and three-phase secondary synchronous rectification units (SR1, SR2, SR3); the microcontroller includes a single-voltage-loop PI controller, an ADC module, a data processing module, and a PWM module; the single-voltage-loop driven three-phase LLC hybrid modulation system executes the single-voltage-loop driven three-phase LLC hybrid modulation method according to any one of claims 1-6.

9. The single-voltage-loop driven three-phase LLC hybrid modulation system according to claim 8, characterized in that, The microcontroller controls the full-bridge drive channels of the three-phase LLC resonant converter as follows: Phase 1 full-bridge is driven by the microcontroller's PWM4 channel, Phase 2 full-bridge is driven by the microcontroller's PWM6 channel, and Phase 3 full-bridge is driven by the microcontroller's PWM2 channel; the microcontroller controls the synchronous rectification of the three-phase SR secondary side as follows: SR1 is driven by the microcontroller's PWM3 channel, SR2 is driven by the microcontroller's PWM0 channel, and SR3 is driven by the microcontroller's PWM1 channel.

10. A medium having a computer-readable program stored thereon, characterized in that, When the computer-readable program is executed, it implements the single-voltage loop driven three-phase LLC hybrid modulation method according to any one of claims 1-6.

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