Three-level dc transformer power module of series half-bridge and control method

Abstract

The application relates to a series half-bridge three-level DC transformer power module and a control method, which comprises the following steps: collecting the transient voltage between the first high-voltage side support capacitor and the transient voltage between the second high-voltage side support capacitor; constructing a charge equalization model, and solving the first half-bridge unit timing conduction Boolean function and the second half-bridge unit timing conduction Boolean function; regulating the conduction timing of the power device in the first half-bridge unit and the conduction timing of the power device in the second half-bridge unit; the conduction timing of the power device in the first half-bridge unit and the conduction timing of the power device in the second half-bridge unit satisfy the single-switch-period charge integral equalization constraint. The application can match the voltage fluctuation state of the high-voltage side support capacitor in real time, solve the half-bridge unit conduction timing suitable for the topology working condition, realize the charge equalization regulation and control of the two groups of support capacitors in the single-switch-period, inhibit the capacitor voltage and charge deviation problems, and guarantee the basic stability of the series half-bridge three-level topology power conversion.

Description

Technical Field

[0001] This application relates to the field of DC transformer technology, specifically to a series half-bridge three-level DC transformer power module and its control method. Background Technology

[0002] With the rapid development of medium- and high-voltage DC power grids, bidirectional energy storage converter systems, and grid-connected power generation technologies for new energy sources, DC transformers must simultaneously meet stringent requirements for high voltage withstand capability, efficient energy conversion, flexible bidirectional power flow, high power quality, and high fault tolerance. Traditional diode-clamped and flying capacitor-type three-level half-bridge topologies are essentially unidirectional optimized architectures with many inherent defects: under bidirectional power feedback conditions, the neutral point potential and flying capacitor voltage balance conditions change drastically, rendering conventional voltage equalization control strategies completely ineffective. Complex logic such as operating mode recognition, parameter switching, and active compensation must be added, resulting in high control coupling and significant development difficulty. In high-frequency operating scenarios, asymmetrical timing drive of multiple switches easily leads to severe hard switching losses and electromagnetic interference. Furthermore, the operating frequency and conduction duration of internal and external switches differ greatly, resulting in extremely uneven module thermal distribution. Local hot spots accelerate device aging, significantly shortening the system's mean time between failures (MTBF).

[0003] However, existing technologies have obvious drawbacks: existing improvement solutions often optimize performance by adding clamping devices, auxiliary compensation circuits, and complex algorithms, but this leads to a bulky drive structure, reduced overall power density, and decreased operational reliability.

[0004] Therefore, this invention proposes a series half-bridge three-level DC transformer power module and its control method. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this application provides a series half-bridge three-level DC transformer power module and control method, specifically adopting the following technical solution.

[0006] A series half-bridge three-level DC transformer power module includes: a high-voltage compartment, a transformer compartment, and a low-voltage compartment. The high-voltage compartment, the transformer compartment, and the low-voltage compartment are isolated from each other.

[0007] The high-voltage compartment is equipped with a fuse, a high-voltage side support capacitor, a high-voltage side control board, high-voltage side power devices, a high-voltage side water-cooled plate, and a DC blocking capacitor.

[0008] The high-voltage side power devices consist of four identical power semiconductor devices. Each pair of high-voltage side power devices is connected in series in the forward direction to form a standard half-bridge unit. Each half-bridge unit has a high-voltage side support capacitor connected independently in parallel at both ends, forming two symmetrical high-voltage power units. These two high-voltage power units are cascaded end-to-end to form the high-voltage side three-level main converter bridge arm. Each high-voltage power unit has an independent fuse connected in series at its input end; a current sampling transformer is installed through the output power line of one set of fuses. The negative terminal of the upper unit and the positive terminal of the lower unit of the two high-voltage power units are cascaded in series via a laminated busbar to form the high-voltage side three-level main converter bridge arm. The fuses and their corresponding high-voltage side support capacitors, as well as the high-voltage side support capacitors and their corresponding half-bridge unit input lines, are all connected via the laminated busbar.

[0009] The high-voltage side power devices are independently controlled by the high-voltage side control board.

[0010] A transformer is fixedly installed in the transformer compartment. The other end of the DC blocking capacitor is reliably electrically connected to one end of the transformer primary side, and the other end of the transformer primary side is connected to the negative output terminal of the main converter arm on the high-voltage side, forming a complete transformer primary side power conversion circuit. The transformer output terminal is connected to the input line of the low-voltage side power device.

[0011] The low-voltage compartment is equipped with low-voltage side power devices, low-voltage side water-cooled plates, low-voltage side support capacitors, low-voltage side control boards, and mechanical bypass switches.

[0012] The low-voltage side power devices consist of four identical power semiconductor devices. Each pair of low-voltage side power devices is connected in forward series to form a rectifier unit, resulting in two sets of rectifier units with completely identical structure and parameters. These two sets of series-connected low-voltage rectifier units are then connected in parallel to form a low-voltage side synchronous rectifier array. Low-voltage side support capacitors are connected in parallel across the output bus of the low-voltage side synchronous rectifier array. The low-voltage side power devices are fixed to the low-voltage side water-cooled plate. The low-voltage side power devices are independently controlled via a low-voltage side control board.

[0013] The low-voltage side power device outputs are connected to the low-voltage side support capacitors via a laminated busbar.

[0014] This invention provides a control method for a series half-bridge three-level DC transformer power module, comprising the following steps.

[0015] Real-time acquisition of the instantaneous voltage across the first high-voltage side support capacitor and the instantaneous voltage across the second high-voltage side support capacitor.

[0016] A charge balancing model is constructed, which takes the instantaneous voltages across the first high-voltage side supporting capacitor and the second high-voltage side supporting capacitor as inputs, and combines the timing mutual exclusion constraint conditions to obtain the timing conduction Boolean functions of the first half-bridge unit and the second half-bridge unit.

[0017] The conduction timing of the power devices in the first half-bridge unit is controlled according to the timing Boolean function of the first half-bridge unit, and the conduction timing of the power devices in the second half-bridge unit is controlled according to the timing Boolean function of the second half-bridge unit. The conduction timing of the power devices in the first half-bridge unit and the conduction timing of the power devices in the second half-bridge unit satisfy the single-switch cycle charge integral balance constraint.

[0018] The above technical solution involves real-time acquisition of the instantaneous voltages across the first and second high-voltage side supporting capacitors. Using these two sets of instantaneous capacitor voltages as input, a charge balance model is constructed. Combined with timing mutual exclusion constraints, the timing Boolean functions for the first and second half-bridge units are obtained. Based on these two types of timing Boolean functions, the conduction timing of the power devices within the corresponding half-bridge units is adjusted, ensuring that the conduction timing of the power devices in both sets of half-bridge units satisfies the single-switching cycle charge integral balance constraint. This approach can match the voltage fluctuation state of the high-voltage side supporting capacitors in real time, solve for the half-bridge unit conduction timing adapted to the topology, effectively achieve charge balance control of the two sets of supporting capacitors within a single switching cycle, suppress capacitor voltage and charge offset issues, and ensure the fundamental stability of the series half-bridge three-level topology power conversion.

[0019] As an optional embodiment of the present invention, the instantaneous charge fluctuation of the first high-voltage side supporting capacitor is calculated based on the instantaneous voltage across the first high-voltage side supporting capacitor; the instantaneous charge fluctuation of the second high-voltage side supporting capacitor is calculated based on the instantaneous voltage across the second high-voltage side supporting capacitor; and the timing conduction Boolean function of the first half-bridge unit and the timing conduction Boolean function of the second half-bridge unit are solved based on the instantaneous charge fluctuation of the first high-voltage side supporting capacitor and the instantaneous charge fluctuation of the second high-voltage side supporting capacitor.

[0020] The above technical solution utilizes the instantaneous charge fluctuations of the two sets of capacitors to obtain the Boolean functions for the timing conduction of the first and second half-bridge units. By using capacitor charge fluctuations as the basis for calculation, compared to directly relying on voltage regulation, this approach reflects the real-time charge shift of the capacitors, making the obtained Boolean functions for the timing conduction of the half-bridge units more closely reflect actual operating condition fluctuations, thus improving the accuracy of timing regulation and the targeted nature of charge balance control.

[0021] As an optional embodiment of the present invention, the single-switch cycle charge integral balance constraint is as follows: within the same complete switching cycle of the first half-bridge unit power device and the second half-bridge unit power device, the charge fluctuation integral of the first high-voltage side support capacitor is equal to the charge fluctuation integral of the second high-voltage side support capacitor.

[0022] By using the above technical solution, the total integral of charge fluctuations in the two sets of supporting capacitors within a single switching cycle can achieve cycle-level charge balance, avoid charge accumulation deviations within a single switching cycle, avoid capacitor voltage imbalance and uneven stress in power devices during long-term operation, and improve the long-term stability of the power module.

[0023] As an optional solution of the present invention, the instantaneous voltage and current of the transformer primary side are collected in real time, and the instantaneous active power of the transformer primary side is calculated based on the instantaneous voltage and current of the transformer primary side; based on the instantaneous active power of the transformer primary side, the forward operating condition and the reverse operating condition are distinguished.

[0024] The positive operating condition is the condition in which energy is transferred from the primary side of the transformer to the secondary side, and the negative operating condition is the condition in which energy is fed back from the secondary side to the primary side.

[0025] The above technical solution, by real-time acquisition of the instantaneous voltage and current of the transformer primary side, calculates the instantaneous active power of the transformer primary side. Based on the instantaneous active power, it distinguishes between forward and reverse operating conditions, clarifying that the forward operating condition is the transfer of energy from the transformer primary side to the transformer secondary side, and the reverse operating condition is the feedback of energy from the transformer secondary side to the transformer primary side. It can identify the bidirectional energy transfer conditions of the power module, providing a basis for determining the operating conditions for differentiated charge balancing and timing constraint control under different operating conditions, realizing targeted control of bidirectional operating conditions, and avoiding the problem that a single control logic cannot adapt to bidirectional energy transfer.

[0026] As an optional embodiment of the present invention, the charge balance model is as follows.

[0027] .

[0028] .

[0029] In the formula: For a single switching cycle; This refers to the instantaneous charge fluctuation of the first high-voltage side supporting capacitor; This refers to the instantaneous charge fluctuation of the second high-voltage side supporting capacitor; , Here are the Boolean functions for the timing of the first half-bridge unit and the second half-bridge unit. This refers to the instantaneous voltage across the first high-voltage side support capacitor. This is the instantaneous voltage across the second high-voltage side support capacitor; The rated capacity of the first high-voltage side supporting capacitor. The rated capacity of the second high-voltage side support capacitor; This is the steady-state reference value of the voltage of the first high-voltage side supporting capacitor. This is the steady-state voltage reference value for the second high-voltage side support capacitor.

[0030] The above technical solution utilizes the instantaneous charge fluctuations of the two sets of high-voltage side support capacitors within a single switching cycle, along with the Boolean functions of the first and second half-bridge units, to construct an integral balance constraint relationship. This quantifies the coupling relationship between capacitor charge fluctuations and the timing conduction state. It enables the quantification of the matching relationship between capacitor charge offset and timing conduction under different operating conditions, achieving quantification and precision in charge balance control. This provides model support for solving the timing Boolean functions of the half-bridge units, significantly improving the accuracy and reliability of charge balance control.

[0031] As an optional solution of the present invention, the timing mutual exclusion constraint condition is: the first half-bridge unit and the second half-bridge unit are not simultaneously turned on at any time, and the logical product of the timing turn-on states of the first half-bridge unit and the second half-bridge unit is always zero.

[0032] Through the above technical solutions, and by strictly constraining timing mutual exclusion, the bridge arm shoot-through and bus short-circuit faults caused by the simultaneous conduction of two sets of half-bridge units are avoided. From the perspective of timing mechanism, the operational safety of the series half-bridge three-level topology is guaranteed, and a safe constraint basis is provided for the stable implementation of charge balance and timing control.

[0033] As an optional solution of the present invention, under forward operating conditions, the instantaneous voltage difference between the two ends of the support capacitor under forward operating conditions is calculated based on the instantaneous voltage across the first high-voltage side support capacitor and the instantaneous voltage across the second high-voltage side support capacitor.

[0034] In reverse operation, the instantaneous voltage difference across the supporting capacitors under reverse operation is calculated based on the instantaneous voltage across the first high-voltage side supporting capacitor and the instantaneous voltage across the second high-voltage side supporting capacitor.

[0035] Based on the instantaneous voltage difference across the supporting capacitor under the forward operating condition and the instantaneous voltage difference across the supporting capacitor under the reverse operating condition, constraints are applied to the timing conduction Boolean function of the first half-bridge unit and the timing conduction Boolean function of the second half-bridge unit.

[0036] By applying the above technical solution to constrain the timing conduction Boolean function of the two sets of half-bridge units based on the voltage difference between the two types of operating conditions, it is possible to achieve operating condition-adaptive timing constraint control for the differentiated voltage fluctuation characteristics of bidirectional energy transmission operating conditions. This solves the problem that a single constraint logic cannot adapt to the voltage offset difference between forward and reverse operating conditions, and improves the adaptability of charge balance under bidirectional operating conditions.

[0037] As an optional solution of the present invention, a time-symmetric equivalent adaptation model is established, and cross-condition equilibrium constraints are applied to the time-series conduction Boolean function of the first half-bridge unit and the time-series conduction Boolean function of the second half-bridge unit through the time-symmetric equivalent adaptation model and then solved.

[0038] The above technical solution establishes a time-symmetric equivalent adaptation model. Based on this model, cross-condition equalization constraints are applied to the time-series conduction Boolean functions of the first and second half-bridge units, and the results are solved. This overcomes the limitations of single-condition time-series control, enabling cross-condition collaborative adaptation of time-series control under both forward and reverse conditions. It eliminates time-series control deviations during bidirectional condition switching and ensures the continuity and stability of charge balance control during condition switching.

[0039] As an optional embodiment of the present invention, the time-symmetric equivalent adaptation model is as follows.

[0040] .

[0041] =C[ ]; =C[ ].

[0042] In the formula: These are the instantaneous charge offset under forward operating conditions and the instantaneous charge offset under reverse operating conditions, respectively. For time-series coupling derived variables under positive operating conditions, For the time-coupling derived variable under reverse operating conditions, C is the rated capacity of the supporting capacitor; To support the instantaneous voltage difference across the capacitor under positive operating conditions; This is to support the instantaneous voltage difference across the capacitor under reverse operating conditions.

[0043] By employing the aforementioned technical solution, and matching the equivalent periodic integral of capacitor charge offset and timing-coupled derived variables under forward and reverse operating conditions, symmetrical adaptation of timing control under bidirectional operating conditions is achieved. This enables quantifiable, symmetrical, equivalent timing control under bidirectional operating conditions, balancing the charge offset and timing coupling characteristics of forward and reverse operating conditions, effectively reducing control oscillations caused by operating condition switching, ensuring consistent charge balance across operating conditions, and enhancing the adaptability of the power module for bidirectional operation.

[0044] As an optional embodiment of the present invention, a ripple suppression step is also included.

[0045] Dynamic monitoring of inductor current ripple is performed. The inductor is a high-frequency resonant filter inductor integrated inside the transformer to identify abnormal ripple conditions. Based on the abnormal ripple conditions, dynamic correction of the volt-second product deviation is performed to obtain the dynamic correction result. Combined with the dynamic correction result, hardware and software collaborative filtering is performed.

[0046] The above technical solution involves dynamically monitoring the inductor current ripple of the integrated high-frequency resonant filter inductor within the transformer to identify abnormal ripple conditions. Based on these abnormal conditions, dynamic correction of the volt-second product deviation is performed, and the results are then combined with hardware-software collaborative filtering. This approach allows for real-time monitoring of current ripple anomalies during high-frequency conversion. By using volt-second product deviation correction combined with hardware-software collaborative filtering, inductor current ripple is effectively suppressed, optimizing the waveform quality of the power module's high-frequency conversion, reducing device losses and electromagnetic interference caused by ripple, and further improving the operational stability of the power module.

[0047] The technical solution of this application has achieved the following beneficial effects.

[0048] By real-time acquisition of the instantaneous voltages across the first and second high-voltage side supporting capacitors, a charge balance model is constructed using these two sets of capacitor instantaneous voltages as input. Combined with timing mutual exclusion constraints, the timing Boolean functions for the first and second half-bridge units are obtained. Based on these two types of timing Boolean functions, the conduction timing of the power devices within the corresponding half-bridge units is adjusted to ensure that the conduction timing of the power devices in both sets of half-bridge units satisfies the single-switching cycle charge integral balance constraint. This approach can match the voltage fluctuation state of the high-voltage side supporting capacitors in real-time, solve for the half-bridge unit conduction timing adapted to the topology operating conditions, effectively achieve charge balance control of the two sets of supporting capacitors within a single switching cycle, suppress capacitor voltage and charge offset issues, and ensure the basic stability of the series half-bridge three-level topology power conversion. Attached Figure Description

[0049] Figure 1 This is a flowchart illustrating the control method for the three-level DC transformer power module of the series half-bridge in this embodiment of the application.

[0050] Figure 2 This is a topology diagram of the three-level DC transformer power module with a series half-bridge in the embodiments of this application.

[0051] Figure 3 This is a layout diagram of the high-voltage compartment, transformer compartment, and low-voltage compartment of the three-level DC transformer power module with a series half-bridge in this embodiment of the application.

[0052] Figure 4 This is a schematic diagram of the internal structure of the three-level DC transformer power module with series half-bridge in an embodiment of this application.

[0053] Reference numerals: 1. High-voltage compartment; 2. Transformer compartment; 3. Low-voltage compartment; 4. Fuse; 5. High-voltage side support capacitor; 6. High-voltage side control board; 7. High-voltage side power device; 8. High-voltage side water-cooled plate; 9. DC blocking capacitor; 10. Transformer; 11. Low-voltage side power device; 12. Low-voltage side water-cooled plate; 13. Low-voltage side support capacitor; 14. Low-voltage side control board; 15. Mechanical bypass switch; 16. Current sampling transformer; 17. High-frequency resonant filter inductor; 18. Electronic main bypass switch; 19. Electronic auxiliary bypass switch. Detailed Implementation

[0054] The present application will now be further described with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application and should not be construed as limiting the scope of protection of the present application. It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of the present application.

[0055] like Figure 2 , Figure 3 and Figure 4 As shown, this invention discloses a series half-bridge three-level DC transformer power module, which adopts a multi-compartment independent layout structure, including: a high-voltage compartment 1, a transformer compartment 2, and a low-voltage compartment 3. The high-voltage compartment 1, transformer compartment 2, and low-voltage compartment 3 are isolated from each other and arranged in separate zones, which can effectively achieve high and low voltage electrical isolation, avoid the risk of high and low voltage crosstalk, and facilitate modular assembly, independent maintenance, and zoned control of heat dissipation air ducts and water channels. The overall structure is well-organized and highly integrated, and is suitable for the modular stacking installation requirements of high-voltage high-power DC conversion equipment.

[0056] The high-voltage compartment 1 is equipped with a fuse 4, a high-voltage side support capacitor 5, a high-voltage side control board 6, a high-voltage side power device 7, a high-voltage side water-cooled plate 8, and a DC blocking capacitor 9. All core electrical components on the high-voltage side are centrally located inside the high-voltage compartment 1, forming an independent high-voltage functional unit, effectively improving the overall safety and operational stability of the high-voltage circuit. Among them, the fuse 4, as a front-end protection device on the high-voltage side, can quickly melt and disconnect the high-voltage input circuit when abnormal faults such as overcurrent and short circuit occur in the power module, preventing the core components such as the downstream high-voltage side power device 7 and transformer 10 from burning out and being damaged, thus achieving overall fault protection.

[0057] The DC blocking capacitor 9 adopts a multi-branch parallel configuration to achieve equal voltage and current. The high-voltage compartment 1 is equipped with a sampling circuit for real-time acquisition of the voltage and operating temperature across the DC blocking capacitor 9, continuously monitoring capacitor aging and capacitance drift. When the monitored parameters exceed the preset threshold, an early warning protection is triggered.

[0058] The high-voltage side power device 7 consists of four identical power semiconductor devices. Two high-voltage side power devices 7 are connected in series in the forward direction to form a standard half-bridge unit, resulting in two sets of independent half-bridge units with completely identical structure and parameters. Each half-bridge unit has a high-voltage side support capacitor 5 connected in parallel at both ends, forming two symmetrical high-voltage power units. These two sets of high-voltage power units are cascaded end-to-end to form the high-voltage side three-level main converter bridge arm. Each high-voltage power unit has an independent fuse 4 connected in series at its input front end to provide independent overcurrent and short-circuit protection for each branch. A current sampling transformer 16 is installed through the output power line of any set of fuses 4 to collect the instantaneous and average current of the transformer primary input circuit. Two sets of high-voltage power units are cascaded and connected in series, with the upper unit's negative terminal and the lower unit's positive terminal connected via a laminated busbar, forming a three-level main converter arm on the high-voltage side. The fuse 4 and the corresponding high-voltage side supporting capacitor 5, and the high-voltage side supporting capacitor 5 and the corresponding half-bridge unit's input line are all connected via the laminated busbar. The high-voltage side power device 7 is integrally bonded and fixed to the surface of the high-voltage side water-cooled plate 8; this is a physical heat dissipation bonding installation with no electrical connection. RC buffer absorption circuits are connected in parallel across the two ends of the power device, the two ends of the high-voltage side supporting capacitor, and the primary side connection port of the transformer. Typical RC parameters are: R = 10–100Ω, C = 100–1000pF, optimized based on switching frequency and stray inductance simulations to suppress voltage oscillations caused by high-frequency switching. The laminated busbar's conductor width, interlayer spacing, and current return path are optimized based on three-dimensional electromagnetic field simulation results to reduce local stray inductance in the circuit. The RC buffer absorption circuit is a mature existing technology and is only used in this application.

[0059] The power module has two high-voltage side support capacitors 5. One high-voltage side support capacitor 5 is connected in parallel across the two ends of the upper first half-bridge unit, defined as the first high-voltage side support capacitor; the other high-voltage side support capacitor is connected in parallel across the two ends of the lower second half-bridge unit, defined as the second high-voltage side support capacitor; the structural parameters of the two are identical. The two upper high-voltage side power devices 7 form a half-bridge structure, arranged above the high-voltage input bus, with the first high-voltage side support capacitor connected in parallel at both ends, forming the first half-bridge unit; the two lower high-voltage side power devices 7 form a half-bridge structure, arranged below the high-voltage input bus, with the second high-voltage side support capacitor connected in parallel at both ends, forming the second half-bridge unit. The first half-bridge unit and the second half-bridge unit are connected in series along the high-voltage bus, and their connection node forms the transformation midpoint.

[0060] Replacing traditional cable connections with laminated busbars significantly reduces wiring space in high-voltage power circuits, effectively lowers stray inductance, suppresses voltage spikes during device switching, reduces electromagnetic interference, and improves the stability of high-frequency operation. Simultaneously, the integrated connection structure of the laminated busbars results in low contact resistance and high current carrying capacity, effectively reducing conduction losses and adapting to high-power, high-frequency power conversion conditions. The high-voltage side power devices have a large contact area and high heat exchange efficiency, effectively dissipating heat generated during high-frequency operation and preventing localized heat buildup and overheating aging.

[0061] The high-voltage side support capacitor 5 and DC blocking capacitor 9 are arranged close to the water-cooled heat-conducting pad made of high thermal conductivity silicone material and are included in the water-cooled heat dissipation control range; the high-voltage compartment inner wall is covered with a galvanized steel plate electromagnetic shielding layer to block the internal high-frequency electromagnetic radiation outward.

[0062] The high-voltage side power device 7 is independently controlled by the high-voltage side control board 6. The high-voltage side control board 6 integrates drive signal output, fault sampling, logic protection, and timing control functions. It can output drive signals and independently manage the on / off timing of the high-voltage side power devices 7 within the two sets of half-bridge units, ensuring the high-voltage side circuit operates stably according to the preset three-level timing logic. The intermediate common midpoint node formed by the cascaded series connection of the two sets of high-voltage power units is reliably electrically connected to one end of the DC blocking capacitor 9 via a stacked busbar, resulting in neat wiring and a simple circuit, further optimizing the high-voltage side power circuit layout. The high-voltage side control board 6 is equipped with a topology midpoint potential sampling channel to collect the cascaded midpoint voltage in real time, used to construct an active midpoint potential compensation closed loop to suppress potential drift under long-term operating conditions. The high-voltage side control board 6 is a standardized integrated control unit adapted to the three-level timing control of this invention, integrating power device driving, electrical parameter sampling, timing logic operation, fault diagnosis, and closed-loop control functions. Those skilled in the art can conventionally select and reproduce it according to functional requirements.

[0063] Transformer 10 is fixedly installed inside transformer compartment 2. Transformer compartment 2 serves as an independent isolation chamber, housing the isolation transformer 10 separately. This physically isolates the transformer's alternating electromagnetic radiation, vibration noise, and high and low voltage power devices and control board components, effectively reducing the impact of electromagnetic interference on control signals. Simultaneously, it prevents the transformer's heat from affecting the precision components on the high and low voltage sides, improving the overall electromagnetic compatibility performance and operational reliability. The inner wall of transformer compartment 2 is lined with a heat-insulating damping lining, and a vibration-damping mounting base is installed at the bottom to block heat conduction and vibration transmission. Metal shielding partitions are installed around the chamber to weaken the coupling interference of the alternating magnetic field. The other end of the DC blocking capacitor 9 is reliably electrically connected to one end of the primary side of transformer 10, and the other end of the primary side of transformer 10 is connected to the negative output terminal of the high-voltage side main converter bridge arm, forming a complete power conversion circuit on the primary side of the transformer. This effectively blocks DC bias voltage, eliminates DC flux accumulation at the transformer input, and avoids problems such as DC bias and core saturation of the transformer core, as well as increased excitation losses, ensuring the high-frequency, high-efficiency, and stable operation of transformer 10. The transformer 10 internally integrates a high-frequency resonant filter inductor 17, which is equivalent to the parasitic leakage inductance on the primary side. This eliminates the need for external independent resonant devices. The built-in resonant structure broadens the soft-switching range across all operating conditions, enabling low-loss soft-switching operation under both light and heavy loads. This results in a simpler structure and significantly improved integration and power density. The high-voltage side control board incorporates a light-load frequency adaptive strategy, setting the light-load threshold to 10%–30% of the rated load. The upper limit of frequency adjustment does not exceed twice the rated switching frequency, compensating for insufficient resonant energy and maintaining the light-load soft-switching operating range. The output of the transformer 10 is connected to the input of the low-voltage side power device 11, achieving isolated transformation and energy transfer from the high-voltage side to the low-voltage side. Electrical isolation is achieved through a high-frequency isolation transformer, effectively improving the insulation safety and electrical compatibility of the high- and low-voltage systems.

[0064] The low-voltage compartment 3 is equipped with low-voltage side power devices 11, low-voltage side water-cooled plates 12, low-voltage side supporting capacitors 13, low-voltage side control boards 14, and mechanical bypass switches 15. All power devices, control devices, and protection devices on the low-voltage side are integrated and arranged in separate zones to form independent low-voltage conversion and fault bypass units. The structure is clearly layered and the functional zones are well-defined, which facilitates the commissioning, maintenance, and fault diagnosis of the low-voltage circuit.

[0065] The low-voltage side power devices 11 consist of four identical power semiconductor devices. Each pair of low-voltage side power devices 11 is connected in forward series to form a rectifier unit, resulting in two sets of rectifier units with identical structure and parameters. These two sets of series-connected low-voltage rectifier units are then connected in parallel to form a low-voltage side synchronous rectifier array. Low-voltage side support capacitors 13 are connected in parallel across the output bus of the low-voltage side synchronous rectifier array to achieve passive filtering and voltage regulation of the low-voltage side output voltage and absorb current ripple. The low-voltage side power devices 11 are fixed to the low-voltage side water-cooled plate 12 using a close-fitting installation method, which allows for rapid heat dissipation, adapting to high-current operating conditions on the low-voltage side and avoiding excessive temperature rise caused by high-current conduction.

[0066] The low-voltage side power device 11 is independently controlled by the low-voltage side control board 14, and works in conjunction with the high-voltage side control board 6 to achieve dual-side synchronous timing control, ensuring bidirectional power conversion, voltage balance, and ripple suppression effects for the entire unit. The output lines of the low-voltage side power device 11 are connected to the low-voltage side support capacitor 13 via a stacked busbar, forming a high- and low-voltage dual-side hardware and software collaborative filtering system with the high-voltage side support capacitor 5 and DC blocking capacitor 9. This effectively smooths output voltage fluctuations and current ripple, suppresses waveform distortion and harmonic disturbances, and ensures continuous and stable low-voltage side output power quality, fully adapting to the ripple suppression strategy of the control method. The low-voltage side control board 14 is a standardized integrated control unit adapted to the three-level timing control of this invention, integrating power device driving, electrical parameter sampling, timing logic operation, fault diagnosis, and closed-loop control functions. Those skilled in the art can conventionally select and reproduce it according to functional requirements.

[0067] This power module is equipped with a three-level timing-based bypass fault-tolerant architecture, including a mechanical bypass switch 15, an electronic main bypass switch 18, and an electronic auxiliary bypass switch 19. These three types of switching devices work together and are indispensable. The mechanical bypass switch 15 uses a permanent magnet holding contactor with a mechanical latch. After closing, it maintains the conducting state through a mechanical locking structure, requiring no continuous power supply, thus ensuring reliable bypass conduction even after the module loses control power. The electronic main bypass switch 18 and the electronic auxiliary bypass switch 19 are identical high-speed electronic switching devices with completely consistent parameters, structure, and electrical characteristics. They are connected in parallel to form an electronic high-speed bypass branch; this electronic bypass branch is connected in parallel with the mechanical bypass switch 15. The electronic bypass branch, connected in parallel with the mechanical bypass switch, bridges the high-voltage input and high-voltage output ports of this power module, covering only the primary-side main conversion circuit of the transformer. Under normal operating conditions, the electronic main bypass switch 18 remains on, and the electronic auxiliary bypass switch 19 remains off, ensuring the power module can normally engage in power conversion operations. In a cascaded DC transformer system, when a power module detects an internal fault, it actively reports a bypass request. The overall control system then determines whether to issue a bypass fault-tolerant command. If bypass is prohibited, the entire system is shut down; if bypass is permitted, a standardized fault-tolerant switching procedure is executed. The electronic main bypass switch 18, electronic auxiliary bypass switch 19, and mechanical bypass switch 15 are all located in the low-voltage compartment 3.

[0068] The fault diagnosis hierarchy is divided into sensor abnormal faults, single power device open circuit partial faults, unit-level faults, and module major faults. Power device short circuit faults directly prohibit degraded operation and prioritize shutdown protection. Vector reconstruction degraded operation is only attempted for non-short circuit partial faults such as single device open circuits and sampling drift. The bypass process is only initiated when degraded operation fails or a major fault occurs.

[0069] Upon receiving the bypass command, the power module blocks all pulse width modulation (PWM) drive signals, shuts down the high-voltage side power device 7 and the low-voltage side power device 11, and cuts off the main power conversion path. Subsequently, it shuts off the electronic main bypass switch 18 and turns on the electronic auxiliary bypass switch 19, completing a microsecond-level electrical transition under fault conditions. Finally, it closes the mechanical bypass switch 15 and checks whether it closes successfully. If it closes successfully, the module bypass process is complete. After the mechanical bypass switch reliably engages, the electronic auxiliary bypass switch 19 is turned off, relying solely on the mechanical bypass branch for long-term conduction to reduce steady-state bypass losses and ensure uninterrupted operation of the cascaded system. If the mechanical bypass switch 15 fails to close, the bypass fault tolerance is deemed to have failed, triggering the overall system shutdown protection to prevent fault propagation.

[0070] The electronic main bypass switch 18 and the electronic auxiliary bypass switch 19 have an ultra-fast switching response speed of 1.0μs, which can achieve rapid switching of operating conditions and interference-free disconnection when the module fails, ensuring that the external characteristics of the cascaded system are stable and distortion-free. The mechanical bypass switch 15 undertakes the long-term steady-state locking function under fault conditions, and can maintain reliable bypass conduction after the module loses control power. It builds a bypass architecture with microsecond-level electronic transient transition and mechanical long-term steady-state fault tolerance, which is fully matched with the hierarchical fault-tolerant timing of the module control method.

[0071] Furthermore, this module is configured with a multi-parameter synchronous high-precision acquisition architecture to meet the requirements of closed-loop control and status monitoring under all operating conditions of the entire machine: it adopts a current sampling transformer 16 to synchronously acquire the instantaneous current and average current at the transformer input terminal, eliminating single-device sampling errors and improving the sampling accuracy of the primary current; it is equipped with high and low voltage sampling units, which are standardized voltage sampling and conditioning circuits configured on the high voltage bus side and the low voltage bus side respectively, including a high voltage divider sampling module and a low voltage precision sampling module, used to acquire high voltage bus voltage, low voltage bus output voltage, topology midpoint potential, and voltage parameters across the DC blocking capacitor in real time, providing complete synchronous voltage and current sampling data for voltage and current phase difference discrimination, power flow direction identification, and accurate bidirectional operating condition determination; at the same time, the system synchronously acquires power device temperature, drive status, communication link, and water cooling system parameters, realizing comprehensive and accurate perception of the module's operating status, providing comprehensive and high-precision sampling data support for accurate bidirectional operating condition determination, closed-loop control, and fault protection of the entire machine. The built-in sampling loop fault diagnosis logic can identify sampling disconnection, sampling drift, and sampling saturation anomalies in real time. When sampling fails, a redundant observation model is activated to estimate the state. The maximum allowable working time of the redundant model is preset. If there is still no effective sampling signal after the time limit, the shutdown protection is triggered to avoid blindly running based on the estimated value for a long time, which may cause control disorder or false protection.

[0072] The power devices of this invention adopt a fixed hardware grouping configuration. The topology grouping structure of the two sets of half-bridge units on the high-voltage side is fixed at the factory and uniquely corresponds. During the operation of the whole machine, the grouping architecture is not dynamically reorganized or randomly changed, ensuring that the preset timing drive logic, voltage equalization integral constraints, and mutual exclusion conduction rules always accurately match the hardware grouping relationship. Each half-bridge unit is a standardized power conversion unit. The two power devices inside the unit are matched with synchronous timing drive logic. The midpoint of the series connection of the two sets of half-bridge units is electrically connected to the primary input terminal of the transformer 10 through the DC blocking capacitor 9, forming a complete three-level conversion topology loop. The four low-voltage side power devices 11 are used as a synchronous conversion array, which works in sequence and collaboratively with the two sets of half-bridge units on the high-voltage side.

[0073] This invention relies on a symmetrical device configuration on the high and low voltage sides and a fixed-group hardware architecture with series half-bridges, combined with a synchronous time-division timing control mechanism for power devices on the high and low voltage sides, to achieve stable output. / 2, 0, + / 2 Symmetrical three-level voltage waveform; Compared with the traditional independent multi-transistor three-level topology, it can effectively distribute the high voltage bus pressure, reduce the voltage stress on a single half-bridge power device, eliminate the need to select power devices with ultra-high withstand voltage ratings, and can be adapted to high-frequency, low-loss high-performance devices; At the same time, this topology simplifies redundant power devices, reduces the overall number of power devices, simplifies the drive and protection peripheral circuits, effectively reduces the overall size of the module, and improves the overall power density of the machine.

[0074] The transformer 10 of the series half-bridge three-level DC transformer power module adopts a high-frequency isolation transformer. Compared with traditional power frequency transformers, the high-frequency design can significantly reduce the transformer core volume and the number of winding turns, significantly reduce the transformer's own losses and the overall space occupied by the unit, effectively improve power conversion efficiency, and reduce the overall size of the equipment, operating energy consumption, and long-term operating costs. The power module adopts a water-cooled heat dissipation structure. The high-voltage side water-cooling plate 8 and the low-voltage side water-cooling plate 12 respectively provide targeted heat dissipation for the core heat-generating components on the high and low voltage sides. Compared with the traditional air-cooling method, the heat exchange efficiency is higher and the heat dissipation effect is more uniform. It can effectively control the operating temperature rise of the components and avoid the accumulation of local hot spots. While ensuring heat dissipation performance, it further reduces the overall size of the module and improves the module integration and long-term operating stability.

[0075] Stable output - / 2, 0, + The / 2 symmetrical three-level waveform provides intuitive waveform evidence for the timing-coupled self-voltage equalization control mechanism of this invention. This power module supports multi-module input series output parallel cascade operation mode, with reserved communication interfaces between modules, and is equipped with inter-module voltage equalization, current equalization, and circulating current suppression control logic, adapting to the networking requirements of large-capacity high-voltage DC-DC converter systems.

[0076] Reference Figure 1 This invention provides a control method for a series half-bridge three-level DC transformer power module, the specific steps of which are as follows.

[0077] Step S1, Module Parameter Sampling and Operating Condition Determination: Through synchronous acquisition of multi-dimensional high-precision parameters, operating condition identification and load classification are achieved, providing a benchmark for subsequent closed-loop control and avoiding the problems of single sampling, lagging operating condition determination, and critical oscillation in traditional solutions.

[0078] Step S2, High-voltage side synchronous timing control: Construct a dedicated timing control logic for the high-voltage side. Through the mutual exclusion time-sharing conduction of two sets of half-bridge units and the timing-coupled charge balance constraint, the high-voltage side capacitor self-equalization and midpoint potential stability are achieved, providing core mechanism support for the stable operation of the whole machine under all working conditions.

[0079] Step S3, Dual Closed-Loop Adjustment of Frequency and Duty Cycle: To address the shortcomings of traditional fixed-parameter modulation, such as poor adaptability, inability to balance ripple and loss, and lag in dynamic response, a multi-dimensional adaptive control strategy is adopted. Relying on the resonant characteristics of the built-in high-frequency resonant filter inductor, and in conjunction with the timing constraints on the high-voltage side, the switching frequency and modulation duty cycle are dynamically corrected to achieve optimal performance under all operating conditions.

[0080] Step S4, Bidirectional Power Smooth Commutation Control: Based on the symmetrical device configuration architecture on the high and low voltage sides, it realizes seamless adaptation, shock-free switching, and failure-free smooth commutation under forward and reverse power conversion conditions, thereby improving the stability of bidirectional energy transmission.

[0081] Step S5, Power Device Thermal Equilibrium Low-Loss Collaborative Control: This step addresses the issues of local hot spots and inconsistent device aging caused by uneven power device operation frequency and loss distribution in traditional topologies. By relying on a symmetrical four-tube configuration architecture on both high and low voltage sides, it achieves even loss distribution, temperature balance, and low-loss operation across all operating conditions for all devices.

[0082] Step S6, Output Current Ripple Suppression: Through coordinated hardware and software control, combined with the module's high and low voltage dual-sided capacitor filtering structure and built-in resonant inductor characteristics, the problem of excessive current ripple and waveform distortion under bidirectional, light and heavy load conditions is improved, and the output power quality is stabilized.

[0083] Step S7, Timing-based hierarchical mechanical bypass fault-tolerant control: To address the problems of easy shutdown due to module failure, large impact of bypass switching, significant potential oscillation, and low reliability of long-term fault-tolerant operation, this invention adopts a three-level timing-based hierarchical bypass fault-tolerant architecture with ultra-fast electronic timing transition and long-term steady-state locking of mechanical switches; the electronic main bypass switch and the electronic auxiliary bypass switch are connected in parallel to form an electronic ultra-fast transition branch, which is connected in parallel with the mechanical bypass switch to bridge the main circuit of the whole machine. Relying on the hierarchical bypass hardware structure, instantaneous microsecond-level disturbance-free isolation of faults and uninterrupted continuous operation of the system are achieved, which greatly improves the fault tolerance capability and long-term operational stability of the module.

[0084] Example 1.

[0085] This embodiment 1 discloses a series half-bridge three-level DC transformer power module, wherein S1 includes the following steps.

[0086] S11. Multi-parameter synchronous acquisition: The current sampling transformer 16 is used to synchronously acquire the instantaneous current and average current at the transformer input terminal, eliminating the sampling error of a single device and improving the sampling accuracy of the primary current. The high-voltage bus voltage, low-voltage bus output voltage, topology midpoint potential, and voltage across the DC blocking capacitor are acquired in real time, providing complete voltage and current synchronous sampling data for voltage and current phase difference discrimination, power flow identification, and accurate bidirectional operating condition determination, matching the module's full-condition closed-loop control and status monitoring requirements.

[0087] S12. Bidirectional operating condition determination: Based on the real-time phase difference of voltage and current and the power flow logic, it can distinguish between two operating conditions: forward buck power supply and reverse boost feedback. It does not require an independent identification algorithm and preset threshold, thus avoiding the problems of misjudgment of operating conditions and switching lag.

[0088] S13, Graded load hysteresis anti-oscillation control: Based on the output current, instantaneous power and device temperature parameters, four levels of operating conditions are divided: light load, medium load, heavy load and full load; to address the critical load fluctuation problem, an independent hysteresis threshold constraint is set to avoid frequent changes in switching frequency and duty cycle, and to ensure the stability of steady-state operation.

[0089] S14. Power-on initial self-test calibration: During the module's power-on initialization phase, the sampling circuit calibration, switch driver self-test, bypass status reset, and timing reference synchronization calibration are automatically completed to ensure the optimal initial operating state of the system.

[0090] In this technical solution, a current sampling transformer 16 is used to synchronously collect the instantaneous and average current at the transformer input, eliminating single-device sampling errors and improving the primary-side current sampling accuracy. By real-time acquisition of high-voltage bus voltage, low-voltage bus output voltage, topology midpoint potential, and voltage across the DC blocking capacitor, complete synchronous voltage and current sampling data is provided for voltage and current phase difference discrimination, power flow identification, and accurate bidirectional operating condition determination, matching the module's full-condition closed-loop control and status monitoring requirements. Based on the real-time voltage and current phase difference and power flow logic, forward buck power supply and reverse boost feedback are identified step-by-step, eliminating the need for independent identification algorithms and preset thresholds, thus avoiding operating condition misjudgments and switching lag issues. Combining output current, instantaneous power, and device temperature parameters, four operating conditions—light load, medium load, heavy load, and full load—are defined, and an independent hysteresis threshold constraint is set for critical load fluctuations, preventing frequent changes in switching frequency and duty cycle and ensuring stable steady-state operation. By automatically completing sampling circuit calibration, switch driver self-test, bypass status reset and timing reference synchronization calibration during the module power-on initialization phase, the system can ensure optimal initial operating state and lay the initial foundation for stable operation of the whole machine.

[0091] Example 2.

[0092] This embodiment 2 discloses a series half-bridge three-level DC transformer power module, wherein S2 includes the following steps.

[0093] S21. Fixed Grouping Configuration of Power Devices: This invention uses a fixed array division based on the module hardware topology. There are four high-voltage side power devices (7), with two connected in series to form a half-bridge unit. Two sets of half-bridge units with identical structure and parameters are defined as the first power array. There are four low-voltage side power devices (11), with two connected in series to form a rectifier unit. These two sets of rectifier units are connected in parallel to form a synchronous rectifier array, defined as the second power array. The device parameters and drive timing parameters of the first and second power arrays are completely matched. The entire system adopts a factory-fixed grouping architecture, prohibiting dynamic grouping and reassembly throughout the process. Real-time grouping discrimination logic is unnecessary, significantly simplifying the dual-side timing coupling control logic and eliminating timing offset and phase deviation problems caused by dynamic grouping switching. This ensures stable three-level voltage generation timing and high synchronization of bidirectional power conversion.

[0094] S22. Synchronous conduction within the group: Establish a unified high-frequency timing reference, and control the turn-on and turn-off timing deviation of all power devices within the group to within 50ns, thereby eliminating voltage spikes, harmonic interference and local loss accumulation caused by timing misalignment.

[0095] S23. Inter-group time-division alternating level output: Two power device arrays are arranged in series along the DC bus. The two power device arrays are strictly mutually exclusive and conduct in a time-division manner, with no overlapping conduction and no synchronous turn-off blind zone. The mutual exclusion constraint of the two sets of switching signals is achieved by the software mutual exclusion logic of the high-voltage side control board and the hardware interlock circuit of the driver chip, which avoids the risk of bus shoot-through short circuit caused by the simultaneous conduction of the two sets of half-bridge units. When the upper first array is turned on, the midpoint of the converter is connected to the high-voltage level. When the second array below is turned on, the midpoint of the transformation is connected to zero level; relying on the alternating connection of the upper and lower arrays to the midpoint potential to form an alternating voltage, the traditional complex multi-level modulation strategy is replaced by dual-state sequential logic, reducing computational overhead and driving complexity.

[0096] S24. DC blocking capacitor voltage timing coupling shaping: Construct a voltage timing coupling generation model adapted to three-level conversion. Based on the differentiated timing logic of two sets of half-bridge units and the voltage coupling shaping characteristics of DC blocking capacitor, the voltage timing coupling generation model is as follows.

[0097] .

[0098] Formula constraint boundaries: Timing mutual exclusion constraints satisfy: the logical product of the Boolean functions of the first half-bridge unit and the second half-bridge unit is always zero, and simultaneous conduction is prohibited at any time; simultaneous turn-off is only allowed during the device switching dead time, and simultaneous turn-off is not allowed under steady-state operation; only applicable to the series symmetrical three-level topology of this invention, satisfying strict mutual exclusion timing constraints. This avoids direct short circuits in the busbars and ensures the effective establishment of the mechanism.

[0099] In the formula: The instantaneous voltage change of the transformer primary side is obtained by real-time sampling of the voltage on the primary side of the topology; The rated voltage of the high-voltage busbar is a fixed preset constant in the system. The first and second half-bridge units are Boolean functions for timing the on / off states. These are standard Boolean switching functions in the field of power electronics, generated by the control board's preset synchronous mutually exclusive timing logic. The values ​​are either 0 or 1, and the two sets of functions are strictly mutually exclusive. Due to the strict mutual exclusion of the two sets of switching functions, the timing difference has positive and negative values, corresponding to a three-level output potential: when... hour, ;when hour, ;when hour, This negative voltage is the negative level component required for the topology to function properly, and it is the generator... / 2, 0, + The core requirement for a symmetrical three-level waveform is to adapt the voltage shifting characteristics of the DC blocking capacitor to the alternating positive and negative voltage output, thereby achieving a standard symmetrical three-level transformation. Through a voltage timing coupling generation model, a stable symmetrical three-level voltage waveform can be output without the need for a flying capacitor or midpoint closed-loop compensation.

[0100] Considering nonlinear factors such as the on-state voltage drop and dead-time effect of power devices, the primary-side transformation voltage in practical engineering must meet certain requirements.

[0101] .

[0102] In the formula: This is the instantaneous voltage on the primary side of the actual transformer; The compensation amount for the on-state voltage drop of the power device is obtained by looking up a table in real time based on the on-state voltage drop characteristic curve of the power device. This is the dead-time effect voltage correction, derived from the dead time. It is calculated and generated together with the loop current. This is the rated voltage of the high-voltage busbar; , These are the timing conduction Boolean functions for the first half-bridge unit and the second half-bridge unit, respectively. and After being processed in real time by the control program, it is superimposed onto the modulation output command.

[0103] S25, Time-coupled midpoint charge balance control: Construct a charge balance model to adapt to the hardware architecture of two sets of half-bridge units on the high-voltage side, each connected in parallel with an independent high-voltage side support capacitor, to achieve self-equalization under all operating conditions. The charge balance model is as follows.

[0104] .

[0105] . .

[0106] In the formula: It is a single-switching cycle, defined by a fixed configuration of the system frequency parameters; This refers to the instantaneous charge fluctuation of the first high-voltage side supporting capacitor; This refers to the instantaneous charge fluctuation of the second high-voltage side supporting capacitor; both are obtained by real-time sampling of the voltage across the corresponding capacitor and calculation using electrical formulas in conjunction with the capacitor's rated capacity parameters. , The first and second half-bridge unit timing conduction Boolean functions are defined, each taking a value of 0 or 1, to characterize the conduction state of the corresponding half-bridge unit. These functions satisfy a mutual exclusion constraint and are dynamically generated based on the charge balance model solution, serving as a quantitative representation of the driving timing of the high-voltage side power devices. By adjusting the conduction timing of the two sets of half-bridge units, the charging and discharging processes of the first and second high-voltage side supporting capacitors are altered, achieving capacitor charge balance. This application employs integral coupling constraints, forcing the charge fluctuation difference between the two sets of high-voltage side supporting capacitors to completely cancel each other out within a single switching cycle through symmetrical timing. This eliminates the need for midpoint potential sampling and software active compensation, fundamentally solving the technical problems of midpoint potential drift and voltage equalization failure in traditional topologies under bidirectional operation. This is to collect the instantaneous voltage across the first high-voltage side support capacitor in real time. This is to collect the instantaneous voltage across the second high-voltage side support capacitor in real time; The rated capacity of the first high-voltage side supporting capacitor. The rated capacity of the second high-voltage side support capacitor; This is the steady-state reference value of the voltage of the first high-voltage side supporting capacitor. This is the steady-state voltage reference value for the second high-voltage side support capacitor.

[0107] This application employs integral coupling constraints, which force the charge fluctuation difference of the high-voltage dual-sided capacitor bank to be completely canceled within a single switching cycle through symmetrical timing. This eliminates the need for midpoint potential sampling and software active compensation, thus solving the technical problems of midpoint potential drift and voltage equalization failure in the bidirectional operation of traditional topologies from a physical mechanism perspective.

[0108] Formula constraint boundary: Applicable to all operating conditions including forward, reverse, and steady state. Small deviations are allowed in the instantaneous charge fluctuations within a single switching cycle. The time-series integral of the cycle is always zero, and there is no steady-state midpoint potential shift.

[0109] In this application, the charge balance model provides the core constraints, which are then used in conjunction with the basic modulation timing framework of the converter for optimization. Among the multiple feasible solutions that satisfy the integral equalization constraints, the timing set that takes into account the conditions of output voltage regulation, low ripple, and soft switching is selected as the optimal operating timing set.

[0110] S26. Adaptive Dead-Time Timing Quantization Optimization: To address the shoot-through and short-circuit risks and output waveform distortion issues during the alternating switching of power devices, a topology-adaptive dead-time constraint formula is constructed.

[0111] In the formula, The optimal dead time is preset for the system. This refers to the voltage rise time of the high-voltage side power device. It is the voltage drop time of the high-voltage side upper-side power device; It is the voltage rise time of the high-voltage side power device. This refers to the voltage drop time of the high-voltage side power device. By quantitatively constraining and precisely matching the switching characteristics of the devices, the dead time is compressed to the maximum extent while avoiding the risk of bridge arm shoot-through, thus balancing operational safety and waveform quality and effectively suppressing harmonic distortion induced by the dead time.

[0112] In this technical solution, the high-voltage and low-voltage power devices are configured with fixed hardware groups. Four high-voltage power devices are connected in series in pairs to form two half-bridge units, and four low-voltage power devices are connected in series and parallel in pairs to form a synchronous rectifier array, forming the first and second power arrays with matched parameters. The factory-fixed grouping architecture prohibits dynamic grouping and recombination throughout the process, eliminating the need for real-time grouping discrimination logic. This significantly simplifies the timing coupling control logic on both sides, eliminating timing offsets and phase deviations caused by dynamic grouping switching, ensuring stable three-level voltage generation timing and high synchronization of bidirectional power conversion. By establishing a unified high-frequency timing reference, the turn-on and turn-off timing deviations of all power devices are controlled within 50ns, eliminating voltage spikes, harmonic interference, and local loss accumulation caused by timing misalignments. Through the strictly mutually exclusive time-division alternating level output of the two power device arrays, coupled with strict timing constraints implemented by software mutual exclusion logic and hardware interlocking circuits, the risk of bus short circuits is avoided. The dual-state timing logic replaces the traditional complex multi-level modulation strategy, reducing computational overhead and drive complexity. By constructing a voltage timing coupling generation model and superimposing real-time corrections for device on-state voltage drop and dead-time effect, a stable symmetrical three-level voltage waveform can be output, achieving standard symmetrical three-level conversion without the need for flying capacitors and midpoint closed-loop compensation. By constructing a single-switch-cycle integral charge balancing model, the charge fluctuation difference between the two sets of high-voltage-side supporting capacitors is forced to completely cancel out within a single switching cycle, eliminating the need for midpoint potential sampling and software active compensation. This physically solves the technical problems of midpoint potential drift and voltage equalization failure in bidirectional operation under traditional topologies. By constructing a dead-time constraint formula for the switching characteristics of adapter devices, the dead-time duration is compressed to the maximum extent while avoiding bridge arm shoot-through risks, balancing operational safety and waveform quality, and effectively suppressing dead-time-induced harmonic distortion.

[0113] Example 3.

[0114] This embodiment 3 discloses a series half-bridge three-level DC transformer power module, wherein S3 includes the following steps.

[0115] S31. Load Adaptive Frequency Matching: Under light load conditions, the switching frequency is increased to suppress light load current ripple and waveform distortion; under heavy load and full load conditions, the optimal operating frequency of the resonant inductor is matched to widen the soft switching range, reduce hard switching losses, and achieve a dynamic balance between losses and ripple. This frequency adaptive matching strategy is implemented by adapting the standard frequency conversion control logic in this field to the timing topology characteristics of this invention. Those skilled in the art can reproduce it based on the overall power and voltage parameters.

[0116] S32. Dual-Loop Duty Cycle Correction for Voltage and Current: A dual-loop architecture with an outer high-voltage loop and an inner primary-side current loop is constructed to correct the modulation duty cycle in real time, compensating for volt-second product imbalance errors caused by bus voltage fluctuations, device voltage drops, and line impedance, thereby improving voltage regulation accuracy and dynamic response speed. The dual-loop architecture introduces a load feedforward component, shortening the dynamic adjustment time under sudden load changes and suppressing voltage and current overshoot. This dual-loop feedback correction architecture is a standard control architecture commonly used in power electronics, and can be fully reproduced by combining the adaptive iteration of timing constraint parameters of this invention.

[0117] S33. Three-Level Redundancy Vector Optimization Allocation: Based on the redundancy characteristics of three-level vectors, the duration of the zero vector and the effective vector is dynamically adjusted to optimize the sinusoidal nature of the voltage waveform, suppress higher harmonics, and reduce device harmonic losses and stress impacts. This dynamic vector allocation logic is a general optimization approach for three-level modulation, achieving optimal adaptation based on the symmetrical timing mechanism of this invention.

[0118] S34. Load Sudden Change Smoothing Control: Duty cycle gradual change constraint logic is set to avoid voltage and current spikes caused by load switching and power sudden changes, achieving a smooth transition without oscillations under dynamic operating conditions. This smoothing limiting constraint is a common anti-impact strategy in the converter control field, and is adaptively configured according to the overall dynamic response parameters of the unit.

[0119] S35, Low-voltage side power device timing coordination matching: The driving phase of the four low-voltage side power devices 11 is synchronously adjusted according to the power transmission direction and the operating frequency of the transformer primary side; the conduction timing of the low-voltage side power devices is coordinated with the conduction timing of the first half-bridge unit and the second half-bridge unit on the high-voltage side to ensure that the charge balance integral constraint condition is continuously met throughout the bidirectional energy transmission process, and to achieve volt-second balance between the primary and secondary sides.

[0120] In this technical solution, a load-adaptive frequency matching strategy is employed. Under light load conditions, the switching frequency is increased to suppress light load current ripple and waveform distortion. Under heavy load and full load conditions, the optimal operating frequency of the resonant inductor is matched to widen the soft-switching range and reduce hard-switching losses, achieving a dynamic balance between losses and ripple. By constructing a dual closed-loop architecture with a high-voltage outer loop and a primary-side current inner loop and introducing a load feedforward component, the modulation duty cycle is corrected in real time. This compensates for the volt-second product imbalance error caused by bus voltage fluctuations, device voltage drops, and line impedance, improving voltage regulation accuracy and dynamic response speed, shortening the dynamic adjustment time under sudden load changes, and suppressing voltage and current overshoot. Through three-level redundant vector optimization allocation, the duration of the zero vector and effective vector is dynamically adjusted, optimizing the sinusoidal nature of the voltage waveform, suppressing higher harmonics, and reducing device harmonic losses and stress impacts. By setting duty cycle gradual constraint logic, voltage and current spikes caused by load switching and power surges are avoided, achieving a smooth transition without oscillation under dynamic conditions. By synchronously adjusting the driving phase of the low-voltage side power devices according to the power transmission direction and the operating frequency of the transformer primary side, the conduction timing of the low-voltage side is coordinated with the conduction timing of the two sets of half-bridge units on the high-voltage side, ensuring that the charge integral balance constraint condition is continuously met throughout the bidirectional energy transmission process, and stably achieving the volt-second balance between the primary and secondary sides.

[0121] Example 4.

[0122] This embodiment 4 discloses a series half-bridge three-level DC transformer power module, wherein S4 includes the following steps.

[0123] S41. Construction of a unified timing reference across the entire domain: A synchronous clock reference is built for the high and low voltage sides. The forward and reverse power conversions share a set of timing logic, modulation vectors and drive parameters. There is no need for operating condition prediction, parameter switching and strategy reconstruction, which eliminates the problems of lag and control failure in bidirectional operating condition switching from the root.

[0124] S42. Dynamic Optimization of Bidirectional Commutation Path: The system determines the forward and reverse transformation modes based on the real-time power flow direction. Combining the instantaneous current amplitude of the primary side and the on-state voltage drop characteristics of the devices, it adaptively optimizes the commutation path with the minimum loss. By dynamically fine-tuning the timing intervals of complementary power devices, the system compresses the overlapping conduction time of device voltage and current, adaptively matching the differences in commutation characteristics under light and heavy loads and bidirectional operating conditions. This effectively reduces the instantaneous conduction loss and high-frequency electromagnetic interference during bidirectional switching, achieving low-loss operation of bidirectional commutation under all operating conditions. This adaptive optimization logic is a dynamic matching strategy implemented based on the fixed-group timing architecture of this invention, which can be adaptively reproduced by those skilled in the art based on operating parameters.

[0125] S43. Bidirectional time-series symmetric charge balance adaptation: In response to the problems of inconsistent forward and reverse charge constraints and reverse voltage equalization collapse in traditional topologies, a time-series symmetric equivalent adaptation model is established by combining the high and low voltage symmetric topology and the dual-sided capacitor energy storage structure of this invention.

[0126] .

[0127] The charge offset satisfies: =C[ ]; =C[ ].

[0128] The model constraint boundary is applicable to the fully steady-state bidirectional switching condition; the core constraint is that the integral mean of the product of charge offset and time-coupled derived variables over one switching cycle is equivalently symmetrical under both forward and reverse operating conditions; the model allows for reasonable deviations in instantaneous charge fluctuations, requiring only that the steady-state periodic integral satisfies the symmetry relationship. This integral symmetry constraint is realized based on the symmetrical series half-bridge topology dual-sided energy storage structure of this invention. Conventional asymmetrical three-level topologies are limited by the inherent circuit architecture and find it difficult to meet this equilibrium condition.

[0129] The current operating condition is identified based on the instantaneous active power of the transformer primary side; if it is identified as a positive operating condition, then select... , Participate in the calculation; if identified as a reverse working condition, then select... , The time-symmetric equivalent adaptation model uses the equal mean of the period integral under both forward and reverse operating conditions as a constraint to solve the time-series conduction Boolean functions of the two sets of half-bridge units.

[0130] In the formula: These are the instantaneous charge offsets under forward and reverse operating conditions, respectively, which are independently sampled and calculated under the corresponding power flow direction conditions. The charge offset is derived from the capacitor voltage fluctuation and is calculated based on the real-time sampled capacitor voltage difference and the rated capacitor capacity through electrical relationships. The time-coupled derived variable under the positive operating condition is generated in real time by the timing conduction Boolean function of two sets of half-bridge units combined with the constraints of the positive operating condition. It is solved iteratively by relying on the mutual exclusion timing logic of the two sets of switches and can be completely reproduced through the system timing parameters. The time-coupled derived variable under reverse operating conditions is generated in real time by combining the timing conduction Boolean functions of two sets of half-bridge units with the constraints of reverse operating conditions. It is solved iteratively by relying on the mutual exclusion timing logic of the two sets of switches and can be completely reproduced through the system timing parameters. C is the rated capacity of the supporting capacitor; the rated capacity of the first high-voltage side supporting capacitor and the second high-voltage side supporting capacitor are the same, and the rated capacity is denoted as C. To support the instantaneous voltage difference across the capacitor under positive operating conditions; This is to support the instantaneous voltage difference across the capacitor under reverse operating conditions.

[0131] For asymmetrical load conditions such as forward heavy load and reverse light load, a forward fine-tuning coefficient is configured for the forward integral operation term, and a reverse fine-tuning coefficient is configured for the reverse integral operation term to compensate for the integral imbalance caused by load asymmetry. The forward and reverse fine-tuning coefficients are obtained through a two-dimensional lookup table based on the real-time load rate difference and the current operating switching frequency. The load rate difference and the switching frequency are used as the lookup table input dimensions, and the lookup table pre-stores the reference fine-tuning coefficients obtained through simulation and prototype calibration. After obtaining the reference coefficients from the lookup table, a secondary correction is performed in combination with the correction gain corresponding to the input voltage and the power device temperature to obtain the final forward and reverse fine-tuning coefficients used in the operation.

[0132] This time-symmetric equivalent adaptation model establishes a unified bidirectional equilibrium constraint criterion, eliminating the need to set two independent voltage equalization control modes for forward and reverse operating conditions. It suppresses potential drift, voltage equalization failure, and output waveform distortion in the reverse operating condition of traditional topologies from a mechanistic perspective, achieving bidirectional adaptive equilibrium control without mode switching.

[0133] Forward and reverse operating conditions are identified based on the direction of instantaneous active power on the primary side of the transformer: real-time acquisition of the instantaneous voltage on the primary side of the transformer. With the instantaneous current of the primary side Calculate the instantaneous active power of the primary side. Preset forward and reverse shared power determination thresholds When instantaneous active power > When the instantaneous active power is determined to be in a positive operating condition; <- When | is determined to be a reverse working condition; when | |≤ When the system is deemed to be in a zero-power operating condition, bidirectional integral imbalance compensation will not be activated. Threshold Based on the pre-calibrated sampling noise level of the prototype, the frequent switching oscillations caused by sampling noise are suppressed. The integral symmetric constraint is not forcibly enabled in the transient range of power commutation, but is only used in continuous steady-state conditions to avoid control oscillations induced by transient shocks.

[0134] S44. Low-voltage side active full-bridge coordinated control: The driving timing of the four low-voltage side power devices 11 is generated based on the phase of the transformer secondary induced voltage and the power flow direction of the system; active synchronous rectification control is performed on the low-voltage side power devices under forward power transmission conditions, and the four low-voltage side power devices form an inverter bridge under reverse energy feedback conditions; the conduction timing of the low-voltage side power devices 11 is matched with the mutually exclusive timing of the first half-bridge unit and the second half-bridge unit on the high-voltage side, in conjunction with the timing-coupled midpoint charge balance control strategy; the driving phase of the low-voltage side power devices is synchronously adjusted during frequency regulation and duty cycle correction to maintain the volt-second balance of the original secondary side and broaden the soft-switching operating range under all operating conditions.

[0135] S45. Bidirectional Harmonic Synergistic Suppression: Targeting the differentiated harmonic characteristics under forward and reverse operating conditions, the vector ratio is dynamically fine-tuned to suppress characteristic subharmonics and ensure stable power quality across all operating conditions.

[0136] This technical solution establishes a unified timing reference across the high and low voltage sides, allowing forward and reverse power conversions to share a single set of timing logic, modulation vectors, and drive parameters. This eliminates the need for condition prediction, parameter switching, and strategy reconfiguration, fundamentally resolving the issues of lag and control failure during bidirectional switching. By determining the conversion mode in real-time power flow, the solution adaptively selects the least-loss commutation path, dynamically fine-tunes the timing intervals of complementary power devices, and compresses the overlapping conduction time of device voltages and currents. This allows for adaptive matching of commutation characteristics under light and heavy loads and bidirectional operating conditions, reducing instantaneous conduction losses and high-frequency electromagnetic interference during bidirectional switching, and achieving low-loss operation of bidirectional commutation under all operating conditions. By establishing a time-symmetric equivalent adaptation model, the periodic integral mean of the charge offset and time-coupled derived variables under forward and reverse operating conditions is made equivalent and symmetrical. Combined with the load rate and switching frequency lookup table fine-tuning coefficients for secondary correction and compensation of load asymmetry deviation, a unified bidirectional equilibrium constraint criterion is constructed. This eliminates the need for two independent voltage equalization control modes for forward and reverse operating conditions, fundamentally suppressing the potential drift, voltage equalization failure, and output waveform distortion problems of traditional topologies under reverse operating conditions, thus achieving mode-free bidirectional adaptive equilibrium control. By accurately identifying forward, reverse, and zero-power operating conditions based on the instantaneous active power of the primary side, setting a shared judgment threshold, and suppressing sampling noise oscillations, integral symmetric constraints are applied only under steady-state conditions, avoiding control oscillations induced by transient impacts and improving the stability of operating condition identification and equilibrium control. By employing active full-bridge coordinated control on the low-voltage side, the rectification and inverting operating modes are switched according to the power flow direction. This synchronously matches the mutual exclusion timing and charge balance control strategies on the high-voltage side, and simultaneously corrects the low-voltage side drive phase during frequency and duty cycle adjustments, continuously maintaining the volt-second balance between the primary and secondary sides, effectively widening the soft-switching operating range across all operating conditions. Furthermore, by dynamically fine-tuning the vector ratio to adapt to the differentiated harmonic characteristics in both forward and reverse directions, characteristic subharmonics are effectively suppressed, ensuring stable power quality across all operating conditions.

[0137] Example 5.

[0138] This embodiment discloses a series half-bridge three-level DC transformer power module, wherein S5 includes the following steps.

[0139] S51. Time-Equal Loss Distribution: By using fixed-group synchronous timing logic, the operating frequency, duty cycle, and switching stress of all power devices on both the high-voltage and low-voltage sides (7 and 11) are completely consistent, eliminating the problem of asymmetrical operating states between internal and external devices in traditional topologies. Inconsistent timing and operating frequencies in traditional topologies directly lead to differential accumulation of switching and conduction losses, resulting in uneven heating of individual devices and concentrated local hotspots. This further causes imbalances in device aging rates and parameter drift, making it prone to single-point device failure under long-term operation. This, in turn, leads to increased harmonics, significantly increased losses, decreased operational stability, and a substantial shortening of equipment lifespan. This time-equal distribution strategy avoids the drawbacks of differential losses at the source, achieving a uniform distribution of temperature and stress fields across all power devices on both the high-voltage and low-voltage sides.

[0140] S52. Loss Quantization and Equalization Control: Constructing a Criterion for Equal Distribution of Losses Across the Entire Device Domain. In the formula The average loss of any two sets of power devices over a period of time is calculated by integrating the on-state voltage drop and the real-time current. The loss of all devices is made to be consistent through timing fine-tuning.

[0141] S53. Widening of the soft-switching range under all operating conditions: Relying on the resonant characteristics of the high-frequency resonant filter inductor 17 integrated inside the transformer 10, and with timing fine-tuning, the range of zero-voltage turn-on and zero-current turn-off under all operating conditions under light and heavy loads is widened, which greatly reduces hard switching losses and electromagnetic radiation, and realizes low-loss soft-switching operation under all operating conditions.

[0142] S54. Temperature control and control synergy optimization: Real-time acquisition of device temperature, optimization of loss distribution by fine-tuning the switching frequency, and independent water cooling structure to achieve uniform temperature distribution of the module, delay device aging, and improve system lifespan.

[0143] In this technical solution, by using fixed-group synchronous timing logic, the operating frequency, duty cycle, and switching stress of all power devices on both the high-voltage and low-voltage sides are made completely consistent. This eliminates the problems of differential loss accumulation and local hot spot concentration caused by the asymmetry of the operating states of devices in traditional topologies, and avoids the drawbacks of unbalanced device aging rates, parameter drift and discretization, and premature failure of single-point devices. It effectively suppresses the problems of overall harmonic rise and sharp increase in losses, extending the service life of the equipment. By constructing a loss equalization criterion for all devices, the average loss is calculated based on the device's on-state voltage drop and real-time current timing integration. Through timing fine-tuning, the average loss of any power device is made to be consistent over a period of time, achieving uniform distribution of overall device losses. Relying on the resonant characteristics of the high-frequency resonant filter inductor integrated inside the transformer, combined with timing fine-tuning, the zero-voltage turn-on and zero-current turn-off range under all operating conditions under light and heavy loads is effectively widened, reducing hard switching losses and electromagnetic radiation, and achieving low-loss soft-switching operation under all operating conditions. By real-time acquisition of device temperature and fine-tuning of switching frequency to optimize loss distribution, combined with an independent water-cooling structure, a uniform temperature field distribution of the module is achieved, further delaying device aging and improving the overall operational stability and service life of the system.

[0144] Example 6.

[0145] This embodiment discloses a series half-bridge three-level DC transformer power module, wherein S6 includes the following steps.

[0146] S61. Ripple Dynamic Monitoring: Real-time extraction of peak, valley and fluctuation amplitude of inductor current during a single switching cycle to identify abnormal ripple conditions.

[0147] S62. Dynamic Correction of Volt-Second Product Deviation: Bidirectional switching of the converter, timing deviations of complementary switches, differences in on-state voltage drops of devices, and dynamic fluctuations in the bus can easily cause asymmetry in the positive and negative volt-second products of the inductor within a single switching cycle, leading to volt-second product imbalance, DC bias of the inductor, and increased current ripple. This invention relies on the high-frequency resonant filter inductor 17 integrated within the transformer 10 to dynamically correct the cyclic volt-second product deviation by real-time fine-tuning the modulation duty cycle and the duration of the redundant vector action. This maintains the inductor volt-second product balance constraint, significantly suppressing DC current deviation and dynamic ripple, thus eliminating the source of abnormal ripple generation from the control end. This correction strategy is a topology-adaptive dynamic correction logic, which can be adaptively reproduced by those skilled in the art based on operating parameters.

[0148] S63. Hardware and software coordinated filtering: On the high-voltage side, two sets of high-voltage side support capacitors 5 form a voltage divider capacitor group to achieve high-voltage bus voltage stabilization and passive filtering. Together with DC blocking capacitor 9, it ensures adaptive shift of topology voltage and isolation of DC bias components. On the low-voltage side, the low-voltage side support capacitor 13 quickly absorbs the large current ripple caused by operating condition fluctuations, constructing a hardware passive filtering basic system on both high and low voltage sides. At the software level, it deeply integrates the core control logic of volt-second product deviation dynamic compensation, three-level redundant vector optimization allocation, and load change smoothing regulation. It specifically corrects the DC offset of inductor current and optimizes the output voltage and current waveform quality, forming a dual-layer closed-loop ripple suppression system of hardware passive ripple suppression and software dynamic correction optimization. It suppresses waveform distortion and harmonic disturbances in multiple dimensions and under all operating conditions, ensuring the continuous stability of steady-state output power quality.

[0149] S64. Steady-State Ripple Closed-Loop Calibration: During long-term operation of the module, aging of power devices, temperature drift of capacitor values, and deviation of line parameters gradually introduce fixed deviation ripple increments, causing a slow degradation of steady-state waveform quality. This invention employs ripple amplitude closed-loop adaptive calibration logic, which collects the peak-to-valley difference of inductor current and the harmonic distortion rate of output voltage under steady-state conditions in real time. It performs iterative calculations on the difference between the real-time ripple index and the system reference threshold. Relying on voltage and current dual closed-loop, volt-second product deviation correction, and adjustable vector ratio mechanisms, it adaptively corrects the modulation duty cycle and vector allocation coefficients with small increments, offsetting the cumulative ripple increments caused by parameter drift and aging cycle by cycle. This achieves zero cumulative waveform error during long-term operation, ensuring continuous and stable power quality throughout the entire lifecycle of the entire device. This adaptive calibration is an iterative optimization strategy based on the existing dual closed-loop architecture, which can be fully reproduced by those skilled in the art based on the system reference parameters.

[0150] In this technical solution, abnormal ripple conditions are identified by extracting the peak, valley, and fluctuation amplitude of the inductor current during a single switching cycle in real time, accurately capturing dynamic ripple disturbances during high-frequency conversion. Addressing the volt-second product asymmetry caused by bidirectional switching, timing deviations, device voltage drops, and bus fluctuations, the solution relies on the high-frequency resonant filter inductor integrated within the transformer. Real-time fine-tuning of the modulation duty cycle and redundant vector duration dynamically corrects the volt-second product deviation, effectively maintaining the inductor volt-second product balance constraint and eliminating the root causes of inductor DC bias and current ripple rise. By constructing a hardware passive filter system consisting of high-voltage side dual-sided support capacitors, DC blocking capacitors, and low-voltage side support capacitors, combined with software correction logic for volt-second product deviation compensation, redundant vector optimization, and load smoothing control, a hardware-software dual-layer closed-loop ripple suppression system is formed, suppressing waveform distortion and harmonic disturbances from multiple dimensions. By collecting steady-state ripple indicators and harmonic distortion rates in real time, and relying on dual closed-loop control, volt-second product correction and adjustable vector ratio mechanism for cycle-by-cycle adaptive calibration, the cumulative increase in ripple caused by device aging, capacitor temperature drift and line parameter deviation is offset, achieving no bottoming out of waveform error during long-term operation, and ensuring the stability of steady-state power quality throughout the module's entire life cycle.

[0151] Example 7.

[0152] This embodiment discloses a series half-bridge three-level DC transformer power module, wherein step S7 includes the following steps.

[0153] S71. Multi-dimensional fault identification and normal state initialization: Under normal operating conditions, the electronic main bypass switch 18 remains on and the electronic auxiliary bypass switch 19 remains off, ensuring the normal operation of the power module; it monitors various fault signals such as overcurrent, overtemperature, overvoltage, drive failure, and communication abnormalities in the module in real time around the clock, and combines short-term fluctuation hysteresis discrimination logic to accurately distinguish between instantaneous interference jitter and permanent hardware faults, filter invalid trigger signals, avoid false triggering and malfunction of fault tolerance protection from the source, and ensure accurate and reliable fault monitoring.

[0154] S72. Fault Classification and Reporting: Valid fault signals are uploaded to the overall control system. The system intelligently classifies faults into minor, moderate, and severe levels based on real-time module operating conditions and fault severity. Minor faults prioritize parameter correction and continued alarm operation; moderate faults attempt vector reconstruction and degraded operation; bypass fault-tolerant execution commands are issued only as needed for severe fault scenarios; if a short-circuit fault is detected in a power device, it is directly classified as the highest-level fault, degraded operation is prohibited, and emergency shutdown logic is immediately executed to quickly cut off power transmission and prevent fault propagation, device breakdown, and other derivative risks. Moderate faults are limited to non-short-circuit faults.

[0155] S73, Power Circuit Drive Signal Blocking: The main power circuit is a three-level high-frequency conversion main circuit consisting of two sets of cascaded half-bridge units of high-voltage side power device 7 and two sets of parallel rectifier units of low-voltage side power device 11. It is the core power path that undertakes bidirectional power conversion and three-level waveform output under normal operating conditions of the module. After receiving the bypass fault-tolerant command, the PWM drive signals of all power devices on the high-voltage and low-voltage sides are immediately blocked, the main power circuit is reliably shut down, and the high-frequency power transmission is cut off. This completely avoids the risks of voltage oscillation, device breakdown, and waveform jump during the switching process, providing a safe operating condition basis for the smooth switching of the bypass.

[0156] S74, Fault Potential Unobstructed Clamping Transition: The main circuit prioritizes blocking all PWM drive signals of power devices and shuts down the main power conversion. After the high-frequency power transmission is completely terminated, relying on the hardware symmetry characteristics of the series symmetrical half-bridge topology of this invention, and in conjunction with the voltage clamping characteristics of two sets of high-voltage side support capacitors 5 and DC blocking capacitors 9, the potential of the conversion port is autonomously balanced and smoothly clamped, effectively eliminating problems such as port floating, residual potential oscillation, and voltage spikes after the main circuit is turned off. No additional electronic bypass transition branch is required to complete the smooth switching of fault conditions, providing unobstructed operating conditions for long-term switching of mechanical bypass.

[0157] S75, Three-level switch timing coordination and long-term steady-state locking of mechanical switches: After the fault potential transition is completed and the system operating conditions are completely stable, microsecond-level bypass timing switching logic is executed. The electronic main bypass switch 18 and electronic auxiliary bypass switch 19 have an ultra-fast switching response speed of 1.0μs, which can realize rapid disconnection from the grid and disturbance-free transition under fault conditions. The specific timing is as follows: after blocking the drive and turning off the main power device, the electronic main bypass switch 18 is turned off first, then the electronic auxiliary bypass switch 19 is turned on to complete the instantaneous electrical transition, and finally the mechanical bypass switch 15 is closed after a delay. The bypass loss formula distinguishes between two operating conditions: in the case of successful mechanical bypass closing, the electronic auxiliary bypass is subsequently turned off, and only the mechanical bypass undertakes steady-state conduction; in the case of failed closing, the electronic auxiliary bypass continues to conduct. An optimal loss model adapted to the fault-tolerant timing of the entire process is constructed.

[0158] .

[0159] In the formula: The real-time total loss of the bypass circuit is obtained through calculation of the system's real-time electrical parameters. This refers to the equivalent loss of the circuit during the transient transition phase of a fault. Both the steady-state conduction loss of the mechanical switch and the overall operating parameters can be obtained through calibration of the device's intrinsic parameters and the overall operating parameters. The system's real-time running time is collected in real time by the control board's clock counter; The fault bypass transient transition time constant is a preset fixed timing calibration constant of the system, used to characterize the rate at which losses decay over time during the fault transition phase. It is a unit step function, which belongs to the standard general basic mathematical function in the field of automatic control. It is used to accurately characterize the step change characteristics of the system operating condition from transient transition state to steady-state locked state during the mechanical switch delay switching process. It is a well-known standard definition and does not require additional time domain modeling and deduction. The moment the mechanical bypass switch successfully closes; if the mechanical switch fails to close, Taking infinity, only the electronic bypass loss term is retained. The loss-optimal model accurately depicts the dynamic changes in loss throughout the fault-switching process: initially relying on the exponential decay term. Characterizing the rapid decay of losses during the transient transition phase of a fault, the subsequent phase relies on a step function. It characterizes the steady-state low-loss operation characteristics after the mechanical switch is put into operation, fully covers the fault-tolerant timing advantages of transient-free potential transition and long-term low-loss locking of mechanical bypass, and achieves precise control with minimal loss throughout the fault-tolerant process.

[0160] S76. Bypass Status Self-Check Protection and Fault Interlocking Judgment: After the bypass is switched on, the system performs real-time closed-loop detection of the conduction status and closing reliability of the electronic bypass switch and mechanical bypass switch 15, identifying abnormal operating conditions such as switch misconnection, failure to close, and poor contact. If the mechanical bypass switch 15 is detected to be temporarily not closed, the electronic auxiliary bypass conduction status is maintained and the mechanical switch closing is periodically retried. The closing retry is set with a maximum number of retry attempts. If the closing fails after reaching the maximum number of retry attempts or the preset duration, the module bypass fault tolerance is determined to be in failure, and the whole machine shutdown protection is immediately triggered to avoid abnormal operation of the module with defects. This avoids secondary breakdown, voltage oscillation, waveform distortion and other derivative faults from the root, ensuring the safety and stability of the system's fault-tolerant operation.

[0161] S77. Reversible Fault Reset and Recovery: After the external fault is completely eliminated and the system operating conditions return to normal, the mechanical bypass branch is smoothly disconnected and the main power circuit gradually resumes high-frequency conversion operation through step-by-step timing reset logic. The entire switching process is shock-free, the operating conditions are reversible, and the operation is stable, which greatly improves the convenience of equipment operation and maintenance and the adaptability of operating conditions.

[0162] This technical solution utilizes all-weather, multi-dimensional fault monitoring combined with short-term fluctuation hysteresis discrimination logic to distinguish between transient interference jitter and permanent hardware faults, filtering invalid trigger signals and avoiding false triggering and malfunction of fault-tolerant protection from the source, ensuring accurate and reliable fault monitoring. By intelligently classifying and judging valid fault signals, it distinguishes between mild, moderate, and severe faults and matches corresponding control, degradation, and shutdown strategies. For short-circuit faults in power devices, it directly executes emergency shutdown logic, enabling tiered protection as needed and accurately avoiding fault propagation and device breakdown risks. Upon receiving a fault-tolerant command, it immediately blocks the PWM drive signals of all power devices on both high and low voltage sides, reliably shutting down the main power circuit and completely avoiding the risks of voltage oscillation, device breakdown, and waveform jumps during switching, providing a safe operating condition foundation for smooth bypass switching. By relying on the hardware symmetry characteristics of the series symmetrical half-bridge topology and the capacitor voltage clamping characteristics, it achieves autonomous balancing and smooth clamping transition of the switching port potential after the main circuit is turned off, completing a seamless fault switching without the need for an additional electronic bypass transition branch. By executing microsecond-level three-level switching timing coordination logic, coupled with an optimal loss model adapted to the entire fault-tolerant process, transient attenuation and steady-state low-loss operating conditions are accurately characterized, achieving minimized loss control throughout the fault switching process. Through bypass status closed-loop self-checking and multi-level retry and failure shutdown protection, anomalies such as switch malfunctions and closing failures can be effectively identified, avoiding secondary breakdowns, waveform distortion, and other derivative faults, ensuring fault-tolerant operational safety. Through fault reversible reset recovery logic, bypass branches can smoothly exit and main power circuits can gradually resume operation, with a shock-free switching process and reversible operating conditions, improving equipment maintenance convenience and operational condition adaptability stability.

[0163] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A control method for a three-level DC transformer power module with a series half-bridge, characterized in that, Includes the following steps: Real-time acquisition of the instantaneous voltage across the first high-voltage side support capacitor and the instantaneous voltage across the second high-voltage side support capacitor; A charge balancing model is constructed, which takes the instantaneous voltages across the first high-voltage side supporting capacitor and the second high-voltage side supporting capacitor as inputs, and combines the timing mutual exclusion constraint conditions to solve for the timing conduction Boolean function of the first half-bridge unit and the timing conduction Boolean function of the second half-bridge unit. The conduction timing of the power devices in the first half-bridge unit is controlled according to the timing Boolean function of the first half-bridge unit, and the conduction timing of the power devices in the second half-bridge unit is controlled according to the timing Boolean function of the second half-bridge unit. The conduction timing of the power devices in the first half-bridge unit and the conduction timing of the power devices in the second half-bridge unit satisfy the single-switch cycle charge integral balance constraint.

2. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 1, characterized in that... The instantaneous charge fluctuation of the first high-voltage side supporting capacitor is calculated based on the instantaneous voltage across the first high-voltage side supporting capacitor; the instantaneous charge fluctuation of the second high-voltage side supporting capacitor is calculated based on the instantaneous voltage across the second high-voltage side supporting capacitor. Based on the instantaneous charge fluctuation of the first high-voltage side supporting capacitor and the instantaneous charge fluctuation of the second high-voltage side supporting capacitor, the timing conduction Boolean function of the first half-bridge unit and the timing conduction Boolean function of the second half-bridge unit are obtained.

3. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 1, characterized in that... The single-switch cycle charge integral balance constraint is as follows: within the same complete switching cycle of the first half-bridge unit power device and the second half-bridge unit power device, the charge fluctuation integral of the first high-voltage side support capacitor is equal to the charge fluctuation integral of the second high-voltage side support capacitor.

4. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 3, characterized in that... Real-time acquisition of instantaneous voltage and current on the primary side of the transformer; calculation of instantaneous active power on the primary side of the transformer based on the instantaneous voltage and current; and differentiation between forward and reverse operating conditions based on the instantaneous active power on the primary side of the transformer. The positive operating condition is the condition in which energy is transferred from the primary side of the transformer to the secondary side, and the negative operating condition is the condition in which energy is fed back from the secondary side to the primary side.

5. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 2, characterized in that... The charge balance model is as follows: ； ； In the formula: For a single switching cycle; This refers to the instantaneous charge fluctuation of the first high-voltage side supporting capacitor; This refers to the instantaneous charge fluctuation of the second high-voltage side supporting capacitor; , The Boolean functions for the timing of the first half-bridge unit and the second half-bridge unit are provided. This refers to the instantaneous voltage across the first high-voltage side support capacitor. This is the instantaneous voltage across the second high-voltage side support capacitor; The rated capacity of the first high-voltage side supporting capacitor. The rated capacity of the second high-voltage side support capacitor; This is the steady-state reference value of the voltage of the first high-voltage side supporting capacitor. This is the steady-state voltage reference value for the second high-voltage side support capacitor.

6. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 5, characterized in that... The timing mutual exclusion constraint is as follows: the first half-bridge unit and the second half-bridge unit are not simultaneously turned on at any time, and the logical product of the timing turn-on states of the first half-bridge unit and the second half-bridge unit is always zero.

7. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 4, characterized in that... : Under forward operating conditions, the instantaneous voltage difference across the supporting capacitors under forward operating conditions is calculated based on the instantaneous voltage across the first high-voltage side supporting capacitor and the instantaneous voltage across the second high-voltage side supporting capacitor. In reverse operation, the instantaneous voltage difference across the supporting capacitors under reverse operation is calculated based on the instantaneous voltage across the first high-voltage side supporting capacitor and the instantaneous voltage across the second high-voltage side supporting capacitor. Based on the instantaneous voltage difference across the supporting capacitor under the forward operating condition and the instantaneous voltage difference across the supporting capacitor under the reverse operating condition, constraints are applied to the timing conduction Boolean function of the first half-bridge unit and the timing conduction Boolean function of the second half-bridge unit.

8. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 7, characterized in that... Establish a time-symmetric equivalent adaptation model, and apply cross-condition equilibrium constraints to the time-series conduction Boolean function of the first half-bridge unit and the time-series conduction Boolean function of the second half-bridge unit through the time-series symmetric equivalent adaptation model and solve them.

9. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 8, characterized in that... The temporal symmetric equivalent adaptation model is as follows: ； =C[ ]; =C[ ]; In the formula: These are the instantaneous charge offset under forward operating conditions and the instantaneous charge offset under reverse operating conditions, respectively. For time-series coupling derived variables under positive operating conditions, For the time-coupling derived variable under reverse operating conditions, C is the rated capacity of the supporting capacitor; To support the instantaneous voltage difference across the capacitor under positive operating conditions; This is to support the instantaneous voltage difference across the capacitor under reverse operating conditions.

10. The control method for a three-level DC transformer power module with a series half-bridge as described in claim 5, characterized in that... It also includes a ripple suppression step: Dynamic monitoring of inductor current ripple is performed, wherein the inductor is a high-frequency resonant filter inductor integrated inside the transformer, to identify abnormal ripple conditions. Based on the aforementioned abnormal ripple conditions, dynamic correction of the volt-second product deviation is performed to obtain the dynamic correction result. Based on the dynamic correction results, a combined hardware and software filtering process is performed.

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