Dual Active Bridge DC-DC Converter and its Control Method

Abstract

This invention discloses a dual active bridge DC-DC converter and its control method. The converter includes a first active bridge, a second active bridge, a transformer, and a transmission impedance. At least one active bridge uses a normally-on first-type power semiconductor switch and a normally-off second-type power semiconductor switch to form a heterogeneous active bridge. The controller employs triple phase-shift modulation to coordinate the phase-shift parameters within the two bridges and the external phase-shift parameters between the bridges. When the target transmission power constraint is met, the target turn-off current of the second-type power semiconductor switch is zero, ensuring that the absolute value of its turn-off current does not exceed a preset turn-off current threshold. The first-type switch uses a normally-on wide-bandgap field-effect power device, and the second-type switch uses a silicon-based insulated-gate bipolar transistor, a normally-off silicon-based metal-oxide-semiconductor field-effect transistor, or a common-source common-gate power semiconductor switch with overall normally-off characteristics.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, specifically to a dual active bridge DC-DC converter and its control method that uses normally-on power semiconductor switches and normally-off power semiconductor switches to form a heterogeneous active bridge. Background Technology

[0002] A dual active bridge DC-DC converter (DAB) achieves isolated bidirectional DC power transmission through two active bridges, a high-frequency transformer, and a transmission impedance. The transmission impedance can be composed of a series inductor or include a series resonant branch consisting of a series resonant capacitor and a series resonant inductor. Silicon carbide power semiconductor devices possess characteristics such as high voltage tolerance, suitability for high switching frequencies and high-temperature operation, and reduced losses, which are well-suited to the high efficiency and high power density requirements of dual active bridge DC-DC converters.

[0003] With the development of artificial intelligence computing, the power supply capacity and power density of data centers continue to increase, creating a greater demand for solid-state transformers capable of medium-voltage access, high-frequency isolation, and modular DC power supply. This also places higher demands on long-term continuous operational reliability. Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) have been used in various high-frequency power conversion applications, but their gate oxide layer and the interface between silicon carbide and the gate oxide layer can be affected by interface traps, gate bias, and temperature stress, causing threshold voltage drift, gate oxide layer degradation, or changes in related parameters. Therefore, the long-term reliability of the gate oxide layer remains a key factor that needs to be evaluated in high-reliability solid-state transformers. Solid-state transformers typically contain multiple power conversion modules and numerous power semiconductor switches; the reliability risk of individual devices can also affect system availability, maintenance costs, and redundancy design. Summary of the Invention

[0004] Silicon carbide junction field-effect transistors (SCFETs) utilize a junction gate to control the conductive channel. Unlike silicon carbide metal-oxide-semiconductor (SiO2) SCFETs, they do not employ the metal-oxide-semiconductor gate structure used in silicon carbide metal-oxide-semiconductor (SiO2) SCFETs, thus avoiding the reliability issues associated with the same type of gate oxide layer. Therefore, they have potential applications in solid-state transformers. However, high-voltage SiO2 SCFETs typically exhibit normally-on characteristics. If directly used as the entire power switch of an H-bridge, additional handling is required to address the risks of simultaneous conduction of upper and lower power switches in the same bridge arm and DC bus shoot-through when drive failure or control failure occurs. This makes it difficult to directly apply the drive and fail-safe logic of normally-off H-bridge devices.

[0005] In a solid-state transformer, the DC voltage across a dual active bridge DC-DC converter unit is typically constrained by the preceding stage, following stage, or system bus, allowing for relatively limited voltage ratio variations within the design operating range. This relatively limited voltage variation range allows the controller to retain phase-shift adjustment freedom while meeting the target power transmission requirements. Furthermore, the upper and lower power switches of the dual active bridge do not necessarily bear the same shutdown current and shutdown losses in every operation.

[0006] One objective of this invention is to provide a dual active bridge DC-DC converter utilizing a normally-on power semiconductor switch, which, while meeting the requirements of high-frequency isolation and bidirectional power transfer, leverages the device reliability advantages of normally-on power semiconductor switches. The first type of power semiconductor switch in this invention can employ a single normally-on silicon carbide junction field-effect transistor (JFET), a single normally-on gallium nitride (GaN) JFET, a single normally-on gallium oxide (GaO) JFET, or a single depletion-type GaN high electron mobility transistor (HEMT). In some embodiments of this invention, the aforementioned normally-on power semiconductor switch employs a device structure without a gate oxide layer; wherein, the JFET can control the conductive channel through a gate formed by the semiconductor junction, and the HEMT can employ a gate structure without a gate oxide layer. Compared to power semiconductor switches that rely on a gate oxide layer for gate insulation and channel control, this type of normally-on power semiconductor switch without a gate oxide layer avoids or mitigates long-term reliability risks such as gate oxide layer interface defects, threshold voltage drift, gate oxide layer degradation, and dielectric breakdown, thus making it suitable for solid-state transformers and data center power supply applications with high requirements for long-term continuous operation reliability. To address the risk of undriven conduction when normally-on power semiconductor switches are directly used to form an active bridge, this invention forms a heterogeneous configuration of normally-on first-type power semiconductor switches and normally-off second-type power semiconductor switches in at least one active bridge, and coordinates the phase shift parameters. While utilizing the reliability advantages of normally-on devices, it blocks the DC bus direct path in the undriven state and reduces the turn-off current of normally-off second-type power semiconductor switches during normal power transmission.

[0007] This invention further combines the fixed physical configuration of two types of power semiconductor switches in a heterogeneous active bridge with triple phase-shift modulation. Triple phase-shift modulation provides multiple degrees of freedom for adjustment, including internal phase shift of the first active bridge, internal phase shift of the second active bridge, and external phase shift between the two active bridges. By selecting the physical positions of the first type of power semiconductor switch and the second type of power semiconductor switch, and coordinating the intra-bridge and inter-bridge phase shifts, different types of power semiconductor switches can undertake different turn-off processes. During power transmission in the first and second power transmission directions, the normally-off second type of power semiconductor switch is turned off at a smaller current or its turn-off current approaches zero, while the first type of power semiconductor switch bears the corresponding non-zero current commutation stress, while maintaining the required power transmission.

[0008] More importantly, the second type of power semiconductor switch uses a normally-off power semiconductor switch, which remains in the off state when no effective drive signal is applied. Since each arm of the heterogeneous active bridge includes a second type normally-off power semiconductor switch connected in series with the first type normally-on power semiconductor switch, even if the first type of power semiconductor switch remains on during power-on initialization, before the controller is established, in case of abnormal drive power supply, or loss of drive signal, the series conduction path from the positive to the negative terminal of the DC bus is still blocked by the second type of power semiconductor switch, preventing the DC bus from being in a continuous shoot-through state. This avoids the power-on shoot-through path formed by using only normally-on power semiconductor switches and reduces the risk of bus short-circuit overcurrent, power device damage, and even explosion. The aforementioned no-drive turn-off state is based on the premise that the control terminal of the second type of power semiconductor switch has reliable turn-off holding conditions, and does not replace turn-off control with a floating control terminal. A charge discharge resistor, a driver pull-down branch, or an active clamping branch can be installed between the gate and emitter or source to keep the control terminal at the off potential during drive undervoltage, reset, signal loss, or protection activation. During startup, first confirm that the second type of power semiconductor switch is off, then establish the effective off bias required for the first type of normally-on power semiconductor switch. After confirming that the DC ports on both sides and the drive state meet the conditions, modulation begins. The on / off levels and negative voltage off requirements of the first type of device should be determined based on the selected device. The drive circuit can be equipped with gate clamping, undervoltage lockout, and interlocking protection.

[0009] In the two arms of a heterogeneous active bridge, if both Type I power semiconductor switches are positioned in the upper switch position or both in the lower switch position (i.e., both on the same DC bus side), and the system drive power suddenly fails or all effective drive signals disappear simultaneously, the Type II power semiconductor switches, due to their normally off characteristics, switch to or remain off, blocking the direct path from the positive to the negative terminal of the DC bus. Simultaneously, the Type I power semiconductor switches, due to their normally on characteristics, remain on, clamping the two AC terminals of the heterogeneous active bridge to the same DC bus potential, thus bringing the output voltage of the active bridge close to zero. The current in the series inductance, transformer leakage inductance, or series resonant inductance in the transmission impedance obtains a low-resistance closed freewheeling path formed by the Type I power semiconductor switches and the transformer windings. The inductor ends are effectively short-circuited or clamped at a low voltage in a circuit sense, preventing the inductor current from being suddenly cut off and generating a high induced voltage, thus reducing the risk of overvoltage breakdown of the power semiconductor switches, transformer windings, and insulation structures.

[0010] In one aspect, the present invention provides a dual active bridge DC-DC converter, comprising a first DC port, a second DC port, a first active bridge, a second active bridge, a transformer, a transmission impedance, and a controller. The first active bridge is connected between the first DC port and a first winding of the transformer, and the second active bridge is connected between the second DC port and a second winding of the transformer. The transmission impedance is configured in a power transmission loop formed by the first active bridge, the transformer, and the second active bridge.

[0011] At least one side of the first active bridge and the second active bridge is a heterogeneous device active bridge. The heterogeneous device active bridge includes a first bridge arm and a second bridge arm, each bridge arm including an upper power switch and a lower power switch connected in series; the upper power switch and the lower power switch are different types of power semiconductor switches, one of which is a normally-on type first type power semiconductor switch, and the other is a normally-off type second type power semiconductor switch.

[0012] The controller can be configured to control the first and second active bridges using triple phase shift modulation (TPS). TPS includes a first internal phase shift parameter characterizing the phase shift within the first active bridge, a second internal phase shift parameter characterizing the phase shift within the second active bridge, and an external phase shift parameter characterizing the relative phase shift between the two active bridges. The phase shift parameters can be represented by angle, normalized phase shift, time difference, or equivalent control quantities. The first power transmission direction refers to power transmission from the first DC port to the second DC port, and the second power transmission direction refers to power transmission from the second DC port to the first DC port.

[0013] The controller sets zero as the target turn-off current of the second type of power semiconductor switch and adjusts at least one of the first inner phase shift parameter, the second inner phase shift parameter, and the outer phase shift parameter in the direction of reducing the absolute value of the turn-off current of the second type of power semiconductor switch, so that the absolute value of the turn-off current of the second type of power semiconductor switch in the heterogeneous device active bridge is not greater than a preset turn-off current threshold.

[0014] It should be noted that targeting zero turn-off current indicates that the control tends to minimize the absolute value of the turn-off current, without requiring the actual turn-off current to be strictly equal to zero in all operating states. The preset turn-off current threshold is an engineering boundary that allows deviations from zero, and is determined based on at least one of the allowable turn-off losses, switching characteristics, and reliability requirements of the second type of power semiconductor switch. The preset turn-off current threshold can be zero or an engineering allowable value greater than zero. This avoids replacing the optimization objective with a fixed non-zero current, while reserving implementation margins for device variations, sampling errors, and operational constraints.

[0015] In one embodiment, the allowable turn-off loss can be determined based on one or more of the following: the datasheet of the second type of power semiconductor switch, upper junction temperature limit, thermal conditions, switching frequency, bus voltage, turn-off energy curve, or test calibration results. The controller can determine a preset turn-off current threshold based on the correspondence between allowable turn-off loss and turn-off current. This threshold can be a fixed value or can be updated according to bus voltage, switching frequency, device temperature, or operating mode.

[0016] In one embodiment, during power transmission in both the first and second power transmission directions, the absolute value of the turn-off current of all second-type power semiconductor switches in the heterogeneous active bridge does not exceed a preset turn-off current threshold. All second-type power semiconductor switches can be evaluated using a common threshold, or each can use a threshold determined based on its own allowable turn-off loss.

[0017] In one embodiment, the transmission impedance is constituted by a fixed series inductor, meaning that the nominal inductance value of the series inductor cannot be adjusted by the controller. Adjustment of the turn-off current is achieved through phase-shift parameters, without relying on online changes to the nominal inductance value of the series inductor.

[0018] The first type of power semiconductor switch can be a single normally-on silicon carbide junction field-effect transistor, a single normally-on gallium nitride junction field-effect transistor, a single normally-on gallium oxide junction field-effect transistor, or a single depletion-mode gallium nitride high electron mobility transistor. These devices belong to the category of normally-on wide-bandgap field-effect power devices, with the normally-on silicon carbide junction field-effect transistor being preferred.

[0019] The second type of power semiconductor switch can be a silicon-based insulated-gate bipolar transistor, a normally off silicon-based metal-oxide-semiconductor field-effect transistor, a cascode silicon carbide junction field-effect transistor power semiconductor switch with normally off characteristics, a cascode gallium nitride junction field-effect transistor power semiconductor switch with normally off characteristics, a cascode gallium oxide junction field-effect transistor power semiconductor switch with normally off characteristics, or a cascode gallium nitride high electron mobility transistor power semiconductor switch with normally off characteristics.

[0020] A cascode power semiconductor switch, also known as a common-source, common-gate power semiconductor switch, participates in bridge arm connection and driving as a single unit. It can include a high-voltage normally-on power semiconductor device and a low-voltage normally-off silicon-oxide-semiconductor field-effect transistor (MOSFET). The source of the high-voltage normally-on power semiconductor device is connected to the drain of the low-voltage normally-off MOSFET, and the gate of the high-voltage normally-on power semiconductor device is connected to the source of the low-voltage normally-off MOSFET, making the entire combination normally-off. The high-voltage normally-on power semiconductor device can be a normally-on silicon carbide junction field-effect transistor, a normally-on gallium nitride junction field-effect transistor, a normally-on gallium oxide junction field-effect transistor, a depletion-mode gallium nitride high electron mobility transistor, or other high-voltage normally-on power semiconductor devices that can achieve overall normally-off operation through the cascode connection.

[0021] In one embodiment, both the first active bridge and the second active bridge are heterogeneous device active bridges. The two heterogeneous device active bridges can be configured in the same direction, that is, the first type of power semiconductor switch is either set in the upper switch position or both are set in the lower switch position in both heterogeneous device active bridges.

[0022] Alternatively, the two heterogeneous active bridges can be configured in a mirror image, with the first type of power semiconductor switch positioned as the upper switch in one heterogeneous active bridge and as the lower switch in the other. Correspondingly, the second type of power semiconductor switch is located in a physical position complementary to the first type of power semiconductor switch in each bridge arm.

[0023] In one embodiment, the transmission impedance is formed by a series inductor, which can be an external inductor, the leakage inductance of a transformer, or a combination of both. In another embodiment, the transmission impedance includes a series resonant branch composed of a series resonant capacitor and a series resonant inductor to form a dual active bridge series resonant DC-DC converter; the series resonant inductor can be an external inductor, the leakage inductance of a transformer, or a combination of both.

[0024] In another aspect, the present invention provides a control method for a dual active bridge DC-DC converter. This method employs triple phase-shift modulation, setting an external phase-shift parameter based on the target transmission power, and jointly adjusting a first internal phase-shift parameter and a second internal phase-shift parameter; under the constraint of satisfying the target transmission power, the absolute value of the turn-off current of the second type of power semiconductor switch in the heterogeneous active bridge is ensured not to exceed a preset turn-off current threshold.

[0025] During power transmission in both the first and second power transmission directions, phase-shifting parameters corresponding to the current power direction can be determined separately. By jointly adjusting the two inner phase-shifting parameters, all second-type power semiconductor switches can meet the turn-off current constraint. The outer phase-shifting parameter can change with the target transmitted power, port voltage, or power direction, while the two inner phase-shifting parameters provide the adjustment freedom to reduce the turn-off current of a specified switch.

[0026] Compared to active bridges that use only the same type of power semiconductor switches, this invention allows power semiconductor switches with different conduction and switching characteristics to be placed in the same bridge arm. By coordinating device position with phase shift control, the turn-off current of normally open power semiconductor switches can be made close to zero, thereby helping to reduce their turn-off losses.

[0027] Furthermore, the turn-off current control of the present invention does not require a variable inductor as a necessary condition, and is compatible with a single normally-off device and a common-source common-gate power semiconductor switch composed of multiple devices but exhibiting normal-off characteristics as a whole; through same-direction configuration or mirror configuration, it can also adapt to dual-sided heterogeneous bridges and bidirectional power transmission. Attached Figure Description

[0028] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments are briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0029] Figure 1 This is a schematic diagram of the overall topology of a dual active bridge DC-DC converter according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of the waveforms of the output voltage and series inductor current of an active bridge under an ideal turn-off current condition.

[0031] Figure 3 This is a schematic diagram of the waveforms of the active bridge output voltage and series inductor current under the first non-ideal turn-off current state.

[0032] Figure 4 This is a schematic diagram of the waveforms of the active bridge output voltage and series inductor current under the second non-ideal turn-off current state.

[0033] Figure 5This is a schematic diagram of the waveforms of the active bridge output voltage and series inductor current under the third non-ideal turn-off current state.

[0034] Figure 6 This is a schematic diagram of the bridge arm and waveform of the first type of device position combination in the first power transmission direction.

[0035] Figure 7 This is a schematic diagram of the bridge arm and waveforms for the first type of device position combination in the second power transmission direction.

[0036] Figure 8 This is a schematic diagram of the bridge arm and waveform for the second type of device position combination in the first power transmission direction.

[0037] Figure 9 This is a schematic diagram of the bridge arm and waveform for the second type of device position combination in the second power transmission direction.

[0038] Figure 10 This is a schematic diagram of a common-source, common-gate power semiconductor switch according to an embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram of the overall topology of a dual active bridge series resonant DC-DC converter according to an embodiment of the present invention.

[0040] Figure 12 This is a schematic diagram of an active bridge for a heterogeneous device that uses a silicon-based insulated-gate bipolar transistor and a normally-through silicon carbide junction field-effect transistor.

[0041] Figure 13 This is a schematic diagram of an active bridge device that uses a cascode silicon carbide junction field-effect transistor power semiconductor switch and a single normally-on silicon carbide junction field-effect transistor. Detailed Implementation

[0042] The embodiments of the present invention are described below with reference to the accompanying drawings. The described embodiments are only a portion of, and not all, of the embodiments of the present invention. Other implementations obtained by those skilled in the art based on these embodiments without inventive effort may also fall within the protection scope of the present invention.

[0043] In this invention, the terms "first" and "second" are used to distinguish identical or similar objects and do not necessarily indicate that the objects have a temporal, spatial, or hierarchical order. The term "connection" includes direct electrical connections as well as indirect electrical connections made through elements or branches capable of achieving the corresponding electrical functions.

[0044] A "power semiconductor switch" is a switching unit that can be integrated into a power circuit as a whole and switch between an on and off state according to a control signal. This switching unit can be composed of a single power semiconductor device or multiple power semiconductor devices forming a combined structure. Therefore, a cascode power semiconductor switch, as a whole, belongs to the category of power semiconductor switches, without requiring each device within it to occupy a separate power switching position in a bridge arm.

[0045] "Normal on" indicates that the power semiconductor switch is in the on state when no effective control action is applied to turn it off; "Normal off" indicates that the power semiconductor switch is in the off state when no effective control action is applied to turn it on. For cascode power semiconductor switches, the normally off characteristic is determined based on the overall port state of the combined system. In embodiments of the first type of power semiconductor switch of this invention, which employ the listed wide bandgap field-effect devices, it is also referred to as a normally on wide bandgap field-effect power device; this designation does not change the scope of the first type of power semiconductor switch as defined in the claims. Depletion-type gallium nitride high electron mobility transistors themselves have normally on characteristics, but cascode power semiconductor switches using them as internal high-voltage devices should be judged by the port characteristics of the combined system to determine their normally off attribute. The physical location of the first type of power semiconductor switch is also called the normally on switch position, and the physical location of the second type of power semiconductor switch is also called the normally off switch position; "normally off switch position" does not mean that this position is always off during normal operation. The high-voltage normally-on devices inside the first type of power semiconductor switch and the second type of power semiconductor switch of common source and common gate are different circuit objects and are not considered as the same bridge arm switch because the device types are the same.

[0046] "Upper switch position" and "lower switch position" indicate the physical connection locations determined by the circuit design. Once the devices are set up, their positions do not change due to changes in the power transmission direction. Changes in the power transmission direction are achieved by controlling the driving timing and phase shift relationship of each power semiconductor switch.

[0047] "Shutdown current" refers to the current flowing through a power semiconductor switch when it transitions from a conducting state to a shut-off state. The sign of the shutdown current can be determined based on a preset reference direction, and its absolute value is used for control constraints, thus remaining unaffected by changes in the reference direction or power transmission direction. Hard shutdown, as referred to in this invention, means the shutdown process where a power semiconductor switch transitions from a conducting state to a shut-off state and interrupts the flow of a non-zero power transmission current. Making the shutdown current of the second type of power semiconductor switch zero or close to zero does not exclude conduction losses, turn-on losses, junction capacitance charging and discharging losses, and other parasitic losses.

[0048] "Heterogeneous device active bridge" refers to an active bridge in which the upper and lower power switches of each of the first and second bridge arms are of different types, with one being a normally-on power semiconductor switch and the other a normally-off power semiconductor switch. Both bridge arms can use the same upper and lower device configuration so that the switches at corresponding positions can employ the same drive and thermal design.

[0049] See Figure 1 The dual active bridge DC-DC converter includes a first DC port 10, a first active bridge 20, a transmission impedance 30, a transformer 40, a second active bridge 50, a second DC port 60, and a controller 70. The DC side of the first active bridge 20 is connected to the first DC port 10, and the AC side is connected to the first winding of the transformer 40; the DC side of the second active bridge 50 is connected to the second DC port 60, and the AC side is connected to the second winding of the transformer 40; the two active bridges are coupled through the transmission impedance 30 and the transformer 40.

[0050] exist Figure 1 In one embodiment shown, the transmission impedance 30 is composed of a series inductor. The series inductor may be a separate external inductor or may be provided wholly or partially by the leakage inductance of the transformer 40. It can serve as an inductive component of the transmission impedance 30 as long as its equivalent inductance contributes to limiting and shaping the current in the power transmission loop. In other embodiments, the transmission impedance 30 may also include a series resonant capacitor and a series resonant inductor.

[0051] The first active bridge 20 includes power semiconductor switches p1, p2, p3, and p4, and the second active bridge 50 includes power semiconductor switches s1, s2, s3, and s4. The midpoints of the arms of the first active bridge 20 can be denoted as a and b, respectively, and the midpoints of the arms of the second active bridge 50 can be denoted as c and d, respectively. The voltages formed between the midpoints of the arms are denoted as Uab and Ucd, respectively, and the power transmission loop current is denoted as Ia.

[0052] exist Figure 1 In the illustrated embodiment, both active bridges are heterogeneous device active bridges and can be configured in a mirror image. For example, in the first active bridge 20, the first type of power semiconductor switch is located in the upper switch position, and the second type of power semiconductor switch is located in the lower switch position; in the second active bridge 50, the first type of power semiconductor switch is located in the lower switch position, and the second type of power semiconductor switch is located in the upper switch position. This example is not limited to this specific mirror image orientation, and the aforementioned positions can be interchanged entirely.

[0053] Alternatively, the first active bridge 20 and the second active bridge 50 may be configured in the same direction. For example, the first type of power semiconductor switches in both active bridges may be set to the upper switch position, and the second type of power semiconductor switches may be set to the lower switch position; or the first type of power semiconductor switches may be set to the lower switch position, and the second type of power semiconductor switches may be set to the upper switch position.

[0054] Taking a heterogeneous active bridge with both Type I power semiconductor switches positioned at the upper switch position as an example, when the drive power suddenly fails, both Type I power semiconductor switches remain on, clamping the midpoints of the two bridge arms of the active bridge to the positive terminal of the DC bus, thus bringing the voltage between the midpoints of the two bridge arms close to zero. When both Type I power semiconductor switches are positioned at the lower switch position, the midpoints of the two bridge arms are clamped to the negative terminal of the DC bus, similarly bringing the voltage between the midpoints of the two bridge arms close to zero. For both sides of the heterogeneous active bridge in a co-directional or mirror configuration, each heterogeneous active bridge can form the above clamping state according to the position of its own Type I power semiconductor switch.

[0055] In the aforementioned undriven state, the original currents in the series inductance, series resonant inductance, and transformer leakage inductance within the transmission impedance 30 can form a freewheeling loop through the normally open first-type power semiconductor switch, transformer windings, and corresponding connecting conductors, and gradually attenuate, thereby limiting the voltage change across the corresponding inductor. The equivalent short circuit across the inductor, as referred to here, means that the bridge output is clamped and the inductor obtains a low-resistance freewheeling path, not that the positive and negative terminals of the DC bus are directly short-circuited; the normally open characteristic of the second-type power semiconductor switch is precisely used to cut off the latter type of DC bus direct-through path. The actual clamping voltage and current attenuation process can be affected by the on-state voltage drop of the power semiconductor switch, line parasitic parameters, transformer leakage inductance, series resonant capacitance, and absorption or clamping circuits, but it does not change the function of using a normally open switch to provide a low-resistance release path for inductor energy storage and suppress overvoltage caused by sudden power failure. The above description of forming a complete freewheeling path by clamping the outputs of both bridges applies to embodiments where both sides are heterogeneous active bridges, the first-type devices within each bridge are located on the same DC bus side, and the required current path is complete. When only one side is an active bridge with heterogeneous devices, that side can form the aforementioned local clamping. However, whether the entire power transmission loop can be closed depends on the switching or diode state of the other side of the bridge, the transformer connection, and additional branches. It cannot be assumed that all stored energy can be safely released solely from the clamping on that side. During abnormal drive transitions, the time difference between the first type of device resuming conduction and the second type of device entering turn-off should also be checked. If necessary, transient overvoltages should be limited through absorption or clamping branches. When a series resonant capacitor exists, the freewheeling current may also exchange with the capacitor's stored energy; the bridge output approaching zero does not mean that the voltage across each inductor is zero, nor does the current need to monotonically decay at every instant.

[0056] In another embodiment, only the first active bridge 20 or only the second active bridge 50 is a heterogeneous device active bridge, and the other active bridge may employ the same type of power semiconductor switch. The controller 70 performs shutdown current control for the second type of power semiconductor switch in the heterogeneous device active bridge.

[0057] The controller 70 may include a processor, memory, a sampling interface, and a drive signal output interface. The controller 70 receives one or more of the following: a first DC port voltage, a second DC port voltage, a power transfer loop current, an output voltage, an output current, a device temperature, or a power command, and generates drive signals for each power semiconductor switch. The controller 70 may be implemented using a digital signal processor, a microcontroller, a field-programmable gate array, an application-specific integrated circuit, or a combination thereof.

[0058] See Figure 2 Ideally, controller 70 sets phase-shifting parameters so that the turn-off action of the second type of power semiconductor switch corresponds to the position where the power transmission circuit current Ia crosses zero or is close to zero. Therefore, the absolute value of the turn-off current of the second type of power semiconductor switch is zero or close to zero. The voltage waveforms Uab and Ucd and the current waveform Ia in the figure are used to illustrate the relationship between the phase-shifting parameters and the turn-off current, without specifying a particular voltage, current, or time ratio.

[0059] See Figures 3 to 5 When the phase shift parameters, port voltage ratio, or load condition deviate from the above relationships, the second type of power semiconductor switch may enter the turn-off process when Ia is non-zero. Different internal phase shift relationships can cause the turn-off point to be located in different segments of the current waveform, thus generating turn-off currents of different signs and amplitudes. The controller 70 can change the corresponding phase shift parameters according to the direction of the turn-off current deviating from zero, so as to move the turn-off point toward the current zero-crossing position.

[0060] Figures 2 to 5 The terms "ideal" and "non-ideal" are used to describe the state of the turn-off current relative to a zero target, rather than to make an absolute judgment on other soft-switching conditions in the circuit. The fact that the turn-off current of a Type II power semiconductor switch meets a threshold does not necessarily mean that every power semiconductor switch achieves zero-voltage turn-on, zero-current turn-on, or other soft-switching states in all operations.

[0061] Figures 2 to 5 In the diagram, the horizontal axis θ represents the electrical angle within the switching cycle, Uab represents the output voltage between the midpoints of the two arms of the first active bridge 20, Ucd represents the output voltage between the midpoints of the two arms of the second active bridge 50, and Ia represents the voltage according to... Figure 2 The arrows define the power transfer loop current. Each vertical dashed line indicates the state transition position of the corresponding bridge or power semiconductor switch, and the hollow circles on the current curves represent the current sampling points used to evaluate the corresponding switch operation.

[0062] In the embodiment where the transmission impedance 30 is composed of a series inductor, ignoring parasitic parameters during the commutation transient, the equivalent voltage across the series inductor can be determined by the difference between Uab and Ucd referred to the same side. Therefore, within each switching state interval, the slope of Ia is determined by the equivalent voltage and the inductance value of the series inductor. Triple phase-shift modulation changes the start and end positions and overlap of each level interval of Uab and Ucd, thereby simultaneously changing the slope duration, zero-crossing position, and current value corresponding to each turn-off position of Ia.

[0063] For the power semiconductor switches installed in the first active bridge 20, their turn-off current can be determined by Ia at the time of the turn-off drive edge; for the power semiconductor switches installed in the second active bridge 50, their turn-off current can be determined by Ia calculated according to the transformer 40 turns ratio. The current reference direction only affects the sign; whether the constraint is satisfied is determined by the absolute value of the turn-off current. When calculating the device turn-off current based on the power transmission loop current, the actual current path should be determined in conjunction with the bridge arm state, and the corrections required for transformer turns ratio, excitation current, parallel branch current shunting, and commutation transients should be considered; the loop current at any switching moment should not be unconditionally equated to the turn-off current of each device.

[0064] Figure 2 The ideal state shown refers to the expected distribution of hard-turn-off current among different types of power semiconductor switches, and does not mean that all power semiconductor switches in the figure are turned off at zero current. By coordinating device location and phase shift timing, the non-zero current hard-turn-off events marked in the figure can be assigned to the first type of power semiconductor switch, while the turn-off drive edge of the second type of power semiconductor switch is located at or near the zero-crossing point of Ia.

[0065] When the turn-off drive edge of the second type of power semiconductor switch coincides with the zero-crossing position of Ia, its target turn-off current is zero. When it cannot coincide completely due to the influence of target transmission power, minimum pulse width, dead time, peak current or other operating constraints, the controller 70 makes the drive edge as close to the zero-crossing position as possible, and takes the absolute value of the turn-off current not greater than the preset turn-off current threshold as an acceptable condition.

[0066] Figures 3 to 5 Three possible states of a dual active bridge DC-DC converter during operation are shown. In these three states, the turn-off drive of at least one type-II power semiconductor switch deviates from the zero-crossing position of the power transfer loop current Ia, causing the type-II power semiconductor switch to turn off under non-zero current. These states can be caused by changes in the input-side DC port voltage, changes in the output-side DC port voltage, changes or improper settings of the first inner phase-shift parameter, the second inner phase-shift parameter, or the outer phase-shift parameter in triple phase-shift modulation, or a combination of the above factors.

[0067] The controller 70 can acquire or estimate the turn-off current of each of the second type of power semiconductor switches, and dynamically adjust the phase shift parameters according to the direction and magnitude of the turn-off current deviation from zero, so that the corresponding turn-off drive moves along the zero-crossing position towards Ia. The controller 70 preferentially uses the first inner phase shift parameter and the second inner phase shift parameter as interrelated adjustment quantities for joint adjustment; the outer phase shift parameter can be set or modified accordingly according to the target transmission power to maintain the required power transmission during the turn-off current adjustment process.

[0068] The ideal goal of the dynamic adjustment is to make the converter... Figures 3 to 5 The status shown has been adjusted to Figure 2 The state shown causes the turn-off drive edge of the second type of power semiconductor switch to coincide with the zero-crossing position of Ia, thereby making its turn-off current zero. This is possible when the target transmission power, port voltage, minimum pulse width, dead time, peak current, or other operational constraints prevent complete achievement of this state. Figure 2 In the indicated state, the controller 70 minimizes the absolute value of the turn-off current of one or more second-type power semiconductor switches to the minimum possible within the feasible range of satisfying the operating constraints, with a condition that it is not greater than a preset turn-off current threshold.

[0069] For the second type of power semiconductor switch, the controller 70 aims to adjust its turn-off current to approach zero. The preset turn-off current threshold is determined based on at least one of the allowable turn-off losses, switching characteristics, and reliability requirements of the second type of power semiconductor switch. It is used to determine whether the turn-off current control result meets engineering constraints, rather than serving as a non-zero optimization target. The preset turn-off current threshold can be zero or a greater-than-zero engineering allowable value. When multiple second-type power semiconductor switches exist, the absolute value of the turn-off current of each switch can be ensured to be no greater than its corresponding preset turn-off current threshold, with priority given to reducing the turn-off current of switches with larger absolute values.

[0070] See Figure 6 and Figure 7 The first device position combination can be configured with a first type of power semiconductor switch and a second type of power semiconductor switch respectively at the upper and lower positions of the same bridge arm. Figure 6 Indicates the first power transmission direction. Figure 7 This indicates the second power transmission direction. After the power direction changes, the physical position of the device remains unchanged. The controller 70 changes the phase relationship of the drive signal to ensure that the second type of power semiconductor switch of interest satisfies the turn-off current constraint in both power directions.

[0071] See Figure 8 and Figure 9 The second device position combination swaps the top and bottom positions of the first and second type power semiconductor switches. Figure 8 and Figure 9These represent opposite power transmission directions. By comparison... Figures 6 to 9 It is known that different combinations of physical locations correspond to different current directions and turn-off events. Therefore, the triple phase-shifting parameters and the switching logic of each power semiconductor switch in the H-bridge can be determined for the selected combination, including the turn-on and turn-off sequence of each power semiconductor switch and their correspondence with the power transmission direction.

[0072] exist Figure 6 and Figure 7 In the first device position combination shown, the first type of power semiconductor switches s1 and s3 are located in the upper switch position, and the second type of power semiconductor switches s2 and s4 are located in the lower switch position. Ix represents the AC side current of the active bridge of this heterogeneous device as defined by the arrow direction in the figure; after conversion by the transformer turns ratio, Ix corresponds to the power transmission circuit current Ia. The hard turn-off positions of s1 and s3 marked in the figure correspond to the first type of power semiconductor switch undertaking non-zero current turn-off, while the turn-off drive edges of the second type of power semiconductor switches s2 and s4 are arranged in the section where Ix is zero or close to zero.

[0073] Figure 6 and Figure 7 These correspond to opposite power transmission directions. After the power transmission direction changes, the physical connection positions of the first type power semiconductor switches s1 and s3 and the second type power semiconductor switches s2 and s4 remain unchanged, but the reference direction of Ix and the relative order of the bridge output voltage and the gate drive signal change. The controller 70 sets phase shift parameters for the two directions respectively, so that the first type power semiconductor switch handles the non-zero current hard turn-off event shown in the figure in both directions.

[0074] exist Figure 8 and Figure 9 In the second device position combination shown, the second type of power semiconductor switches s1 and s3 are located in the upper switch position, and the first type of power semiconductor switches s2 and s4 are located in the lower switch position. The hard turn-off positions of s2 and s4 marked in the figure correspond to the first type of power semiconductor switches undertaking non-zero current turn-off, while the turn-off drive edges of the second type of power semiconductor switches s1 and s3 are arranged in the segment where Ix is zero or close to zero.

[0075] Therefore, the first type of power semiconductor switch, whether set in the upper or lower switch position, can handle non-zero turn-off current through a driving sequence that matches its physical position; the second type of power semiconductor switch is located in a complementary position and obtains near-zero turn-off current through phase shifting. Figures 6 to 9 The device position and power direction can be used for both active bridges in a co-directional or mirror configuration.

[0076] When both the first active bridge 20 and the second active bridge 50 are heterogeneous device active bridges, the controller 70 can acquire or estimate the turn-off current of all second-type power semiconductor switches in the two bridges. The turn-off current can be directly sampled or calculated based on the power transmission loop current Ia flowing through the transmission impedance 30, the transformer turns ratio, the bridge arm state, and the switching timing. For symmetrically arranged power semiconductor switches, the symmetry of half a switching cycle can be used to reduce the amount of sampling or calculation, but this symmetry is not necessary.

[0077] The controller 70 can determine the phase-shifting parameters using closed-loop search, lookup tables, analytical models, numerical optimization, or a combination thereof. It can also obtain initial values ​​for the phase-shifting parameters based on the first DC port voltage, the second DC port voltage, the target transmitted power, and the power transmission direction, and then correct them using turn-off current feedback. All of the above methods are optional and do not limit the control method of this invention.

[0078] Triple phase-shift modulation can generate three-level bridge output voltages for the first active bridge 20 and the second active bridge 50 respectively within one switching cycle. The first inner phase-shift parameter determines the relative phase between the driving waveforms of the two bridge arms in the first active bridge 20, the second inner phase-shift parameter determines the relative phase between the driving waveforms of the two bridge arms in the second active bridge 50, and the outer phase-shift parameter determines the relative phase between the reference driving waveforms of the two active bridges.

[0079] In a preferred control method, the external phase-shifting parameter is set according to the target transmission power, and the first and second internal phase-shifting parameters are used as joint adjustment variables. Under the constraint of satisfying the target transmission power, the controller 70 adjusts the two internal phase-shifting parameters to make the turn-off current of one or more second-type power semiconductor switches approach zero, and to ensure that the absolute value of their turn-off current does not exceed a preset turn-off current threshold. Here, "joint adjustment" includes synchronous adjustment, sequential iterative adjustment, or jointly solving for the two internal phase-shifting parameters; when the actual transmission power deviates from the target transmission power, the external phase-shifting parameters can be adjusted accordingly.

[0080] The first internal phase-shifting parameter primarily changes the commutation position within the first active bridge 20, and the second internal phase-shifting parameter primarily changes the commutation position within the second active bridge 50. Both internal phase-shifting parameters can influence the turn-off current in the other active bridge by altering the segmented waveform of the power transmission loop current Ia. Therefore, the controller 70 can adjust the two internal phase-shifting parameters in a correlated manner based on the sampled, estimated, or model-predicted values ​​of the turn-off current, without requiring the two internal phase-shifting parameters to change in the same direction or with the same amplitude.

[0081] The first power transmission direction is defined as power being transmitted from the first DC port 10 to the second DC port 60, and the second power transmission direction is defined as power being transmitted from the second DC port 60 to the first DC port 10. When the power transmission direction changes, the physical position of the power semiconductor switch remains unchanged. The controller 70 changes the power command symbol, the inter-bridge phase relationship, and the two inner phase-shifting parameters corresponding to the new direction, and continues to adjust the turn-off current of the second type of power semiconductor switch. The controller 70 can save the initial values ​​of the phase-shifting parameters for each of the two power transmission directions. During the transition process of switching the power transmission direction, the target transmission power can be reduced first or the transmission current can be reduced to a preset transition condition. Then, the two inner phase-shifting parameters and the outer phase-shifting parameters can be gradually adjusted according to the new direction, in conjunction with parameter limiting, slope limiting, interlocking, and overcurrent detection. During the transition, the actual turn-off current of the second type of power semiconductor switch should still be evaluated to avoid turning it off at a current exceeding the allowable threshold simply because of the switching command; if necessary, the power should be reduced, transmission should be suspended, or a protection state should be entered. The transition is achieved through coordination of triple phase shift parameters, without requiring switching between small duty cycle and large duty cycle regions using three-phase asymmetric duty cycle control.

[0082] The controller 70 can set operating constraints such as phase shift parameter range, minimum pulse width, dead time, transformer flux balance, peak current, or circulating current. When the operating constraints prevent the turn-off current of the second type of power semiconductor switch from strictly reaching zero, the controller 70 minimizes the absolute value of the turn-off current within the feasible range of satisfying the target transmission power and operating constraints, and uses whether it is not greater than a preset turn-off current threshold as the criterion for judging whether the engineering constraints are satisfied. The preset turn-off current threshold is greater than zero and determined according to the allowable turn-off loss, but zero is still the target turn-off current of the second type of power semiconductor switch. The actual gate drive signal is formed by the controller adding an interlocked dead time to the ideal triple phase-shifting switch sequence. During commutation of the same bridge arm, the drive signal of the currently conducting switch is first made to enter the turn-off level, and the complementary switch is allowed to enter the conduction level only after passing through the preset dead time. The turn-off current should be evaluated according to the actual time when the controlled device enters the turn-off process, and the influence of sampling time, drive propagation delay, and dead time on the actual commutation time should be considered; the edge of the ideal switching function of the complementary device does not directly replace the actual turn-off edge of the device. The above driving implementation does not change the definitions of the two inner phase shift parameters and the outer phase shift parameter.

[0083] See Figure 10 The common-source, common-gate power semiconductor switch 93 includes a high-voltage normally-on power semiconductor device 94 and a low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor 95. The source of the high-voltage normally-on power semiconductor device 94 is connected to the drain of the low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor 95, and the gate of the high-voltage normally-on power semiconductor device 94 is connected to the source of the low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor 95.

[0084] The common-source common-gate power semiconductor switch 93 has a power terminal P, a power terminal N, and a control terminal G. The control terminal G controls a low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor 95; the state of this low-voltage device changes the gate-source voltage of a high-voltage normally-on power semiconductor device 94, causing the combined switch 93 to switch between an on state and an off state, and to be in a normally-off state when there is no effective on signal.

[0085] When the high-voltage normally-on power semiconductor device 94 is a silicon carbide junction field-effect transistor (SFET), a common-source cas-gate SFET power semiconductor switch is formed; when it is a gallium nitride (GaN) junction field-effect transistor (GaN) FET, a common-source cas-gate GaN FET power semiconductor switch is formed; when it is a depletion-mode gallium nitride high electron mobility transistor (GaNH transistor), a common-source cas-gate GaNH transistor power semiconductor switch is formed. When the internal high-voltage device uses a normally-on gallium oxide (GaO) junction field-effect transistor, its source is connected to the drain of a low-voltage normally-off silicon metal-oxide-semiconductor (SiMDS) field-effect transistor, and its gate is connected to the source of the low-voltage device; the gate of the low-voltage device is used as the combined control terminal. When the low-voltage device is turned off and a blocking voltage is established across the combined terminals, a bias is established between the gate and source of the high-voltage device through the above connection to turn it off, thereby making the entire combination normally-off. The cutoff voltage of the selected high-voltage device, the withstand voltage of the low-voltage device, and the gate clamping parameters should be matched; the replacement of other high-voltage normally-on devices should also be based on the condition of achieving the above-mentioned overall normally-off function. The independent normally-continuous devices of the bridge arm and the high-voltage devices inside the assembly can be selected separately, and it is not required that they use the same material or device type.

[0086] The common-source, common-gate power semiconductor switch 93 functions as a second type of power semiconductor switch in a heterogeneous active bridge. The controller 70 determines its turn-off current based on the overall power terminal current of the combined switch 93, rather than treating the internal high-voltage device 94 and low-voltage device 95 as separate bridge arm power switch positions. The normally-on power semiconductor device 94 can also be other types of normally-on wide-bandgap power semiconductors.

[0087] When the second type of power semiconductor switch is a silicon-based insulated-gate bipolar transistor or a normally-off silicon-based metal-oxide-semiconductor field-effect transistor, its turn-off current is the current flowing through that single power semiconductor switch. When the second type of power semiconductor switch is a cascode power semiconductor switch 93, its turn-off current is the overall switching current flowing between power terminal P and power terminal N. The controller 70 evaluates the cascode structure as a whole as a bridge arm power switch, rather than evaluating the turn-off currents of its two internal devices separately.

[0088] For the cascode power semiconductor switch 93, after the drive signal of the low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor 95 is removed, the combined switch enters the turn-off process through its connection with the high-voltage normally-on power semiconductor device 94. Limiting the overall turn-off current can reduce the energy stress during the turn-off process of the combined switch, rather than interpreting the two internal devices as two independent physical switch positions in an active bridge. Bidirectional power transfer and undriven freewheeling also require verification of the forward and reverse current paths of each switch position in the on, off, and dead-time states. Independent normally-on field-effect devices are evaluated based on the channel current-carrying characteristics of the selected devices; silicon IGBTs can provide a reverse current path with anti-parallel diodes or a combined structure that meets the reverse current requirements; silicon MOSFETs should distinguish between channel conduction and body diode conduction; cascode power semiconductor switches are evaluated based on the complete path formed by the internal high- and low-voltage devices and related diodes. The required freewheeling path, reverse voltage drop, reverse recovery, and allowable gate bias should be determined according to the specific device. The reverse conduction mechanism of normally-on SiCJFETs should not be directly extended to all alternative devices to have the same characteristics.

[0089] See Figure 11 The transmission impedance 30 may include a series resonant branch consisting of a series resonant capacitor and a series resonant inductor. The series resonant inductor may be an independent external inductor, or it may be provided wholly or partially by the leakage inductance of the transformer 40. The series resonant branch may be located on the first winding side, the second winding side, or equivalently distributed on both sides of the transformer 40. The controller 70 may still employ triple phase-shift modulation and perform turn-off current control for the second type of power semiconductor switch.

[0090] In embodiments where the transmission impedance 30 includes a series resonant branch, the controller 70 may incorporate the effects of the series resonant capacitor and series resonant inductor on the current waveform into the phase shift parameter calculation model. The preset turn-off current threshold is still determined based on the allowable turn-off loss of the second type of power semiconductor switch and is not automatically changed to zero due to the use of a series resonant branch.

[0091] See Figure 12 In a specific device combination, the upper switching position of the heterogeneous active bridge can use a silicon-based insulated-gate bipolar transistor as a second type of power semiconductor switch; the lower switching position can use a single normally-on silicon carbide junction field-effect transistor as a first type of power semiconductor switch. The positions of the upper and lower devices can also be interchanged.

[0092] exist Figure 12In the illustrated combination, controller 70 prioritizes bringing the absolute value of the turn-off current of the silicon-based insulated-gate bipolar transistor (SMT) close to zero and within a preset turn-off current threshold. A normally-on silicon carbide junction field-effect transistor (SFET) performs the switching process corresponding to its physical location. This combination utilizes the different characteristics of the two types of devices but does not require them to have the same rated current, chip area, or drive voltage.

[0093] Alternatively, Figure 12 The second type of power semiconductor switch can be a normally off silicon-based metal-oxide-semiconductor field-effect transistor; the first type of power semiconductor switch can be a single normally on gallium nitride junction field-effect transistor, a single normally on gallium oxide junction field-effect transistor, or a single depletion-mode gallium nitride high electron mobility transistor. The control target remains the turn-off current of the second type of power semiconductor switch.

[0094] exist Figure 12 In the illustrated embodiment, the ratio of the absolute value of the turn-off current of the second type of power semiconductor switch to the absolute value of the reference turn-off current of the first type of power semiconductor switch can be used as a relative turn-off current index. The reference turn-off current can be the maximum value among the absolute values ​​of the turn-off currents of one or more first type power semiconductor switches that undertake a non-zero current turn-off process within the same operating state, the same power transmission direction, and the same switching cycle or multiple consecutive switching cycles; the turn-off current of the second type of power semiconductor switch can be the maximum value among the absolute values ​​of the turn-off currents of one or more controlled second type power semiconductor switches.

[0095] when Figure 12 When the second type of power semiconductor switch is a silicon-based insulated-gate bipolar transistor or a normally-off silicon-based metal-oxide-semiconductor field-effect transistor, the controller 70 can adjust the phase-shifting parameters to ensure that the absolute value of the turn-off current of the second type of power semiconductor switch is not greater than 10% of the absolute value of the reference turn-off current, preferably not greater than 5%, while simultaneously meeting a preset turn-off current threshold. Zero remains the target turn-off current for the second type of power semiconductor switch; the 10% and 5% are used to represent the permissible relative turn-off current boundaries, not as non-zero optimization targets. This further reduces the turn-off energy, switching losses, and temperature rise of this type of second type of power semiconductor switch.

[0096] exist Figure 12In the embodiments shown, where the first type of power semiconductor switch uses a single normally-on silicon carbide junction field-effect transistor (SCT) and the second type uses a silicon-based insulated-gate bipolar transistor (SBBT), the short-circuit saturation current and short-circuit withstand time can be designed differently for the two types of switches. Short-circuit saturation current refers to the saturated or confined current exhibited by the power semiconductor switch after entering the short-circuit operating state under specified DC bus voltage, gate drive conditions, junction temperature, and test time. Short-circuit withstand time (SCWT) refers to the time the power semiconductor switch can withstand short-circuit stress before protection operation under specified short-circuit conditions. These parameters can be selected or combined through device chip structure, rated current, chip area, number of parallel chips, gate drive voltage, gate resistance, packaging, and heat dissipation conditions. To distinguish the actual current in a series fault path from the device's own saturation characteristics, this paper defines the drain current of the normally-on silicon carbide junction field-effect transistor as the drain-source voltage increases into the current saturation region under specified conditions as the short-circuit saturation current; it is compared with the short-circuit saturation current of the SBBT under specified drive conditions, junction temperature, DC bus voltage, and short-circuit duration. The aforementioned device characteristic parameters are not equivalent to the actual short-circuit current flowing through the fault path after the two types of switches are connected in series; the actual short-circuit current is affected by the output characteristics of the two types of devices and the fault loop parameters.

[0097] In a configuration where a bridge arm shoot-through short circuit or other fault causes two types of switches to be connected in series into the same fault current path, and the above parameter comparison conditions are met, the short-circuit saturation current of the silicon-based insulated gate bipolar transistor (SGBBT) is less than that of the normally-on silicon carbide junction field-effect transistor (SFCFET), and the short-circuit withstand time (SCWT) of the former is greater than that of the latter. This allows the short-circuit current to be preferentially limited by the lower short-circuit saturation current of the SGBBT, reducing the short-circuit voltage drop of the normally-on SFCFET under short-circuit conditions and reducing short-circuit thermal stress. Another alternative is that, in configurations where a bridge arm shoot-through short circuit or other fault causes the two types of switches to be connected in series into the same fault current path, and the above parameter comparison conditions are met, the above parameter relationships can be reversed. That is, the short-circuit saturation current of the silicon-based insulated-gate bipolar transistor (SMT) is greater than the short-circuit saturation current of the normally-on silicon carbide junction field-effect transistor (SFCFET), and the short-circuit withstand time (SCWT) of the former is less than that of the latter, so that the short-circuit current is preferentially limited by the normally-on SFCFET. The controller or independent protection circuit can set the fault detection and turn-off times according to the shorter actual allowable short-circuit withstand time of the two types of power semiconductor switches. Therefore, this invention does not limit the short-circuit saturation current and short-circuit withstand time of the two types of switches to adopt one of the fixed magnitudes. The total protection delay is calculated from the occurrence of the fault until the fault current path is cut off, including detection or blanking, logic judgment, signal transmission, drive response, and current turn-off, and should have a design margin relative to the shorter actual allowable withstand time of the two types of devices. The actual allowable withstand time should be determined in conjunction with the voltage, current, junction temperature and energy distribution in the fault circuit. It cannot be replaced by the above verification simply by the short-circuit withstand time ranking in the datasheet under different comparison conditions.

[0098] See Figure 13 In another specific device combination, the upper switching position of the heterogeneous active bridge can be a common-source, common-gate silicon carbide junction field-effect transistor power semiconductor switch with normally-off characteristics, serving as a second type of power semiconductor switch; the lower switching position can be a single normally-on silicon carbide junction field-effect transistor, serving as a first type of power semiconductor switch. The positions of the upper and lower devices can also be interchanged.

[0099] and Figure 13 Similarly, the first type of power semiconductor switch can be replaced with a single depletion-mode gallium nitride high electron mobility transistor (GaN HEM), and the second type of power semiconductor switch can be replaced with a cascode GaN HEM power semiconductor switch exhibiting normally-on characteristics. High-voltage depletion-mode GaN HEMs and low-voltage normally-on silicon-based metal-oxide-semiconductor field-effect transistors are compared according to... Figure 10 The relationships shown are connected.

[0100] The first type of power semiconductor switch can be replaced with a single normally-on gallium nitride junction field-effect transistor (GaN junction field-effect transistor), and the second type of power semiconductor switch can be replaced with a cascode GaN junction field-effect transistor power semiconductor switch that exhibits normally-off characteristics. High-voltage normally-on GaN junction field-effect transistors and low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistors are configured according to... Figure 10 The relationships shown are connected.

[0101] exist Figure 13 In the cascode power semiconductor switch of type II shown, the high-voltage normally-on device and the low-voltage normally-off device interact during the turn-off transient. When multiple cascode power semiconductor switches are connected in parallel, device parameter dispersion, drive delay, inconsistencies in parasitic parameters of the power circuit and drive circuit, temperature differences, and parameter drift during service may cause uneven dynamic current distribution, parasitic oscillations, or local overstress. Even without using multiple cascode power semiconductor switches in parallel, the above-mentioned parameter changes may alter the transient coordination between the internal devices of the cascode power semiconductor switch and its switching characteristics.

[0102] for Figure 13 and with Figure 13 In a similar cascode embodiment, the controller 70 ensures that the absolute value of the turn-off current of the cascode type II power semiconductor switch does not exceed 20% of the absolute value of the reference turn-off current, while simultaneously meeting a preset turn-off current threshold. Limiting the turn-off current within this range reduces the magnitude of current variations in the cascode power semiconductor switch during the turn-off transient and its sensitivity to differences in device parameters and inconsistencies in parasitic parameters, thereby reducing the probability or severity of parallel dynamic current imbalance, parasitic oscillations, and local overstress. This turn-off current control does not necessarily mean that the static current sharing problem in the conduction interval is eliminated.

[0103] The above-described combination of the first and second type power semiconductor switches can be configured in one or two active bridges and can be arbitrarily combined with in-phase or mirror configurations. Device materials, package types, number of parallel chips, and rated parameters can be selected based on port voltage, target power, switching frequency, and thermal design requirements. In an optional embodiment, a physical switch location for the second type power semiconductor switch can be constructed by paralleling a silicon-based IGBT with a normally-off silicon-based MOSFET or a cascode power semiconductor switch exhibiting overall normally-off characteristics. The main current paths of each branch are connected to the same two power nodes, and the overall combination maintains normally-off characteristics. Utilizing the low-current resistive conduction characteristics of the MOSFET or cascode combination, based on the selected device's on-state voltage drop, junction temperature, and loss comparison, the branch can be preferentially activated under light load, while the IGBT or both branches can be activated simultaneously under increased load; simultaneous turn-on and turn-off control can also be used. Hysteresis can be set for the activation and deactivation thresholds, and the specific efficiency gains depend on the device and operating conditions. When using this parallel structure, the triple phase-shift modulation is still constrained by the zero target turn-off current and preset threshold of the second type of power semiconductor switch. Simultaneously, the turn-off current, drive time difference, and inter-branch current transfer of each actual operating branch should be checked to avoid assuming that each branch meets the turn-off condition simply because the combined port current is small. If the condition is not met, the branch switching timing can be restricted, the phase-shift parameters adjusted, or the operating range limited. This embodiment does not imply that each parallel branch will automatically meet the dynamic current sharing requirements.

[0104] When the transmission impedance 30 is composed of a fixed series inductor, the controller 70 does not provide the series inductor with a control quantity to change its nominal inductance value. A fixed inductance does not preclude the inherent variation of the inductance value with current, frequency, or temperature, nor does it preclude the selection of a different nominal value by replacing the inductor during the manufacturing or maintenance phase.

[0105] In one control cycle, the controller 70 can acquire the target transmission power and operating status, set the external phase shift parameter according to the target transmission power, set the first internal phase shift parameter and the second internal phase shift parameter according to the device configuration and power transmission direction, generate drive signals for each power semiconductor switch, acquire or estimate the turn-off current of the second type of power semiconductor switch, and jointly adjust the two internal phase shift parameters under the condition of satisfying the target transmission power and operating constraints; if necessary, the external phase shift parameter is corrected. When the absolute value of the turn-off current is not greater than the preset turn-off current threshold, the current phase shift parameter can be maintained or tracked; when the absolute value of the turn-off current exceeds the threshold, the phase shift parameter is readjusted.

[0106] Although the examples numbered below are not limiting of the invention, they illustrate some aspects of the invention.

[0107] Example 1. A dual active bridge DC-DC converter includes a first DC port, a second DC port, a first active bridge, a second active bridge, a transformer, a transmission impedance, and a controller, wherein at least one active bridge is a heterogeneous active bridge composed of normally-on type I power semiconductor switches and normally-off type II power semiconductor switches.

[0108] Example 2. According to the dual active bridge DC-DC converter of Example 1, the controller employs triple phase-shift modulation including two inner phase-shift parameters and one outer phase-shift parameter, with zero as the target turn-off current of the second type of power semiconductor switch, and adjusts at least one phase-shift parameter so that the absolute value of its turn-off current is not greater than a preset turn-off current threshold.

[0109] Example 3. The dual active bridge DC-DC converter according to Example 2, wherein the preset turn-off current threshold is determined based on at least one of the allowable turn-off loss, switching characteristics, and reliability requirements of the second type of power semiconductor switch; the preset turn-off current threshold may be zero or an engineering allowable value greater than zero.

[0110] Example 4. A dual active bridge DC-DC converter according to Example 2 or 3, wherein all second-type power semiconductor switches meet the turn-off current threshold during power transmission in the first power transmission direction and the second power transmission direction.

[0111] Example 5. A dual active bridge DC-DC converter according to any one of Examples 1 to 4, wherein the transmission impedance is constituted by a fixed series inductor whose nominal inductance value cannot be adjusted by the controller.

[0112] Example 6. A dual active bridge DC-DC converter according to any one of Examples 1 to 5, wherein the first type of power semiconductor switch is selected from normally-on silicon carbide junction field-effect transistors, normally-on gallium nitride junction field-effect transistors, normally-on gallium oxide junction field-effect transistors, and depletion-mode gallium nitride high electron mobility transistors, and the second type of power semiconductor switch is selected from silicon-based insulated-gate bipolar transistors, normally-off silicon-based metal-oxide-semiconductor field-effect transistors, and cascode power semiconductor switches with generally normally-off characteristics.

[0113] Example 7. The dual active bridge DC-DC converter according to Example 6, wherein both the first active bridge and the second active bridge are heterogeneous device active bridges.

[0114] Example 8. According to the dual active bridge DC-DC converter described in Example 7, the first type of power semiconductor switch is a single normally-on silicon carbide junction field-effect transistor, and the second type of power semiconductor switch is a cascode silicon carbide junction field-effect transistor power semiconductor switch with normally-off characteristics.

[0115] Example 9. According to the dual active bridge DC-DC converter of Example 8, the common-source cascode silicon carbide junction field-effect transistor power semiconductor switch includes a high-voltage normally-on silicon carbide junction field-effect transistor and a low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor, and is configured in accordance with... Figure 10 The relationships shown are connected.

[0116] Example 10. According to the dual active bridge DC-DC converter described in Example 7, the first type of power semiconductor switch is a single depletion-mode gallium nitride high electron mobility transistor, and the second type of power semiconductor switch is a cascode gallium nitride high electron mobility transistor power semiconductor switch with normally off characteristics.

[0117] Example 11. According to the dual active bridge DC-DC converter of Example 10, the common-source cascode gallium nitride high electron mobility transistor power semiconductor switch comprises a high-voltage depletion-mode gallium nitride high electron mobility transistor and a low-voltage normally-on silicon metal-oxide-semiconductor field-effect transistor, and is configured in accordance with... Figure 10 The relationships shown are connected.

[0118] Example 12. According to the dual active bridge DC-DC converter described in Example 7, the first type of power semiconductor switch is a single normally-on gallium nitride junction field-effect transistor, and the second type of power semiconductor switch is a cascode gallium nitride junction field-effect transistor power semiconductor switch with normally-off characteristics.

[0119] Example 13. According to the dual active bridge DC-DC converter of Example 12, the common-source cascode gallium nitride junction field-effect transistor power semiconductor switch includes a high-voltage normally-on gallium nitride junction field-effect transistor and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor, and is configured in accordance with... Figure 10 The relationships shown are connected.

[0120] Example 14. The dual active bridge DC-DC converter according to Example 7, wherein the first type of power semiconductor switch is either the single normally-on or depletion-type power semiconductor switch, and the second type of power semiconductor switch is a silicon-based insulated-gate bipolar transistor or a normally-off silicon-based metal-oxide-semiconductor field-effect transistor.

[0121] Example 15. A dual active bridge DC-DC converter according to any one of Examples 8 to 14, wherein the two heterogeneous active bridges are configured in the same direction.

[0122] Example 16. A dual active bridge DC-DC converter according to any one of Examples 8 to 14, wherein the two heterogeneous active bridges are configured in a mirror image.

[0123] Example 17. According to the dual active bridge DC-DC converter of Example 7, the transmission impedance includes a series resonant branch consisting of a series resonant capacitor and a series resonant inductor, wherein the series resonant inductor is composed of an external inductor, the leakage inductance of a transformer, or both.

[0124] Example 18. A control method for a dual active bridge DC-DC converter, comprising implementing triple phase-shift modulation on a dual active bridge DC-DC converter with at least one side employing a heterogeneous device active bridge; under the condition of satisfying the target transmission power constraint, setting or modifying the external phase-shift parameter according to the target transmission power, setting zero as the target turn-off current of the second type of power semiconductor switch, and jointly adjusting the two internal phase-shift parameters in the direction of reducing the absolute value of the turn-off current of the second type of power semiconductor switch, so that the absolute value of the turn-off current of the second type of power semiconductor switch is not greater than a preset turn-off current threshold; generating drive signals for each power semiconductor switch in the first and second active bridges according to the two internal phase-shift parameters and the external phase-shift parameter.

[0125] Example 19. According to the control method described in Example 18, during power transmission in the first power transmission direction and the second power transmission direction, two internal phase shift parameters are jointly adjusted so that all second-type power semiconductor switches meet the turn-off current threshold.

[0126] Example 20. The control method according to Example 19, wherein both active bridges are heterogeneous device active bridges, employing any corresponding combination of the first and second types of power semiconductor switches described above, and in a unidirectional or mirror configuration.

[0127] Although the invention has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms and details set forth herein. The scope of protection of the invention is defined by the claims and their equivalents. Technical features in different embodiments may be combined with each other where there is no contradiction, and the order of the claims does not imply that the corresponding steps must be performed in a specific order.

Claims

1. A dual active bridge (DAB) DC-DC converter, characterized in that, include: The system comprises a first DC port, a second DC port, a first active bridge, a second active bridge, a transformer, a transmission impedance, and a controller. The first active bridge is connected between the first DC port and the first winding of the transformer, and the second active bridge is connected between the second DC port and the second winding of the transformer. The transmission impedance is configured in a power transmission loop formed by the first active bridge, the transformer, and the second active bridge. At least one of the first and second active bridges is a heterogeneous device active bridge, which includes a first bridge arm and a second bridge arm. The first bridge arm and the second bridge arm respectively include an upper power switch and a lower power switch connected in series, and the upper power switch and the lower power switch are different types of power semiconductors. The controller is configured to employ triple phase-shift modulation, including phase shift within the first active bridge, phase shift within the second active bridge, and phase shift relative to the two active bridges, with zero as the target turn-off current of the second type of power semiconductor switch. Under the condition of satisfying the target transmission power constraint, the phase-shift parameters are adjusted so that the absolute value of the turn-off current of the second type of power semiconductor switch is not greater than a preset turn-off current threshold. In each of the first and second bridge arms, one of the upper power switch and the other of the lower power switch are a first type of power semiconductor switch, and the other is a second type of power semiconductor switch, wherein the first type of power semiconductor switch is a normally-on power semiconductor switch, and the second type of power semiconductor switch is a normally-off power semiconductor switch.

2. The dual active bridge DC-DC converter according to claim 1, characterized in that, The controller is configured to control the first active bridge and the second active bridge using triple phase-shift modulation. The triple phase-shift modulation includes a first inner phase-shift parameter characterizing the internal phase shift of the first active bridge, a second inner phase-shift parameter characterizing the internal phase shift of the second active bridge, and an outer phase-shift parameter characterizing the relative phase shift between the first active bridge and the second active bridge. The controller sets zero as the target turn-off current of the second type of power semiconductor switch and adjusts at least one of the first inner phase-shift parameter, the second inner phase-shift parameter, and the outer phase-shift parameter in a direction that reduces the absolute value of the turn-off current of the second type of power semiconductor switch, so that the absolute value of the turn-off current of the second type of power semiconductor switch in the heterogeneous device active bridge is not greater than a preset turn-off current threshold.

3. The dual active bridge DC-DC converter according to claim 2, characterized in that, The preset turn-off current threshold is determined based on at least one of the allowable turn-off loss, switching characteristics, and reliability requirements of the second type of power semiconductor switch.

4. The dual active bridge DC-DC converter according to claim 3, characterized in that, During power transmission in the first power transmission direction and the second power transmission direction, the absolute value of the turn-off current of all second-type power semiconductor switches in the heterogeneous device active bridge is not greater than the preset turn-off current threshold.

5. The dual active bridge DC-DC converter according to claim 4, characterized in that, The transmission impedance is composed of a fixed series inductor, and the nominal inductance value of the fixed series inductor cannot be adjusted by the controller.

6. The dual active bridge DC-DC converter according to claim 5, characterized in that, The first type of power semiconductor switch is any one of a normally-on silicon carbide junction field-effect transistor, a normally-on gallium nitride junction field-effect transistor, a normally-on gallium oxide junction field-effect transistor, or a depletion-mode gallium nitride high electron mobility transistor; the second type of power semiconductor switch is any one of the following power semiconductor switches: silicon-based insulated-gate bipolar transistor; normally-off silicon-based metal-oxide-semiconductor field-effect transistor; a common-source cascode power semiconductor switch with normally-off characteristics; the common-source cascode power semiconductor switch includes high-voltage normally-on power semiconductor devices and low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistors.

7. The dual active bridge DC-DC converter according to claim 6, characterized in that, Both the first active bridge and the second active bridge are active bridges for the heterogeneous device.

8. The dual active bridge DC-DC converter according to claim 7, characterized in that, The first type of power semiconductor switch is composed of any one of a normally-on silicon carbide junction field-effect transistor, a normally-on gallium nitride junction field-effect transistor, a normally-on gallium oxide junction field-effect transistor, or a depletion-type gallium nitride high electron mobility transistor; the second type of power semiconductor switch is the common-source common-gate power semiconductor switch.

9. The dual active bridge DC-DC converter according to claim 8, characterized in that, The source of the high-voltage normally-on power semiconductor device is connected to the drain of the low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor, and the gate of the high-voltage normally-on power semiconductor device is connected to the source of the low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor.

10. The dual active bridge DC-DC converter according to claim 9, characterized in that, The first type of power semiconductor switch is a normally-on silicon carbide junction field-effect transistor, and the high-voltage normally-on power semiconductor device in the common-source common-gate power semiconductor switch is a normally-on silicon carbide junction field-effect transistor.

11. The dual active bridge DC-DC converter according to claim 7, characterized in that, The first type of power semiconductor switch is composed of any one of a single normally-on silicon carbide junction field-effect transistor, a single normally-on gallium nitride junction field-effect transistor, a single normally-on gallium oxide junction field-effect transistor, or a single depletion-mode gallium nitride high electron mobility transistor; the second type of power semiconductor switch is a silicon-based insulated-gate bipolar transistor or a normally-off silicon-based metal-oxide-semiconductor field-effect transistor.

12. The dual active bridge DC-DC converter according to any one of claims 8 to 11, characterized in that, In both the first and second active bridges, the first type of power semiconductor switches are located in the upper switch position, and the second type of power semiconductor switches are located in the lower switch position; or, in both the first and second active bridges, the first type of power semiconductor switches are located in the lower switch position, and the second type of power semiconductor switches are located in the upper switch position.

13. The dual active bridge DC-DC converter according to any one of claims 8 to 11, characterized in that, In the first active bridge, a first type of power semiconductor switch is positioned at the upper switch position, and a second type of power semiconductor switch is positioned at the lower switch position; in the second active bridge, a first type of power semiconductor switch is positioned at the lower switch position, and a second type of power semiconductor switch is positioned at the upper switch position; or, in the first active bridge, a first type of power semiconductor switch is positioned at the lower switch position, and a second type of power semiconductor switch is positioned at the upper switch position; in the second active bridge, a first type of power semiconductor switch is positioned at the upper switch position, and a second type of power semiconductor switch is positioned at the lower switch position.

14. The dual active bridge DC-DC converter according to claim 4, characterized in that, The transmission impedance includes a series resonant capacitor and a series resonant inductor. The series resonant capacitor and the series resonant inductor are connected in series in the power transmission circuit and form a series resonant branch.

15. A control method for a dual active bridge DC-DC converter, characterized in that, The dual active bridge DC-DC converter includes a first active bridge, a second active bridge, a transformer, and a transmission impedance. Power transmission between the first and second active bridges is achieved through the transformer and the transmission impedance. At least one of the first and second active bridges is a heterogeneous device active bridge. Each arm of the heterogeneous device active bridge includes an upper power switch and a lower power switch connected in series. One of the upper and lower power switches is a first type of power semiconductor switch, and the other is a second type of power semiconductor switch. The first type of power semiconductor switch is a normally-on power semiconductor switch, and the second type of power semiconductor switch is a normally-off power semiconductor switch. The control method includes: acquiring the target transmission power; and using triple phase-shift modulation to control the first and second active bridges. The triple phase-shift modulation includes characterizing the first... The active bridge has a first internal phase-shift parameter, a second internal phase-shift parameter characterizing the internal phase shift of the second active bridge, and an external phase-shift parameter characterizing the relative phase shift between the first and second active bridges. Under the condition of satisfying the target transmission power constraint, the external phase-shift parameter is set or modified according to the target transmission power, with zero as the target turn-off current of the second type of power semiconductor switch. The first internal phase-shift parameter and the second internal phase-shift parameter are jointly adjusted in the direction of reducing the absolute value of the turn-off current of the second type of power semiconductor switch, so that the absolute value of the turn-off current of the second type of power semiconductor switch in the heterogeneous device active bridge is not greater than a preset turn-off current threshold. The drive signal of each power semiconductor switch in the first and second active bridges is generated according to the first internal phase-shift parameter, the second internal phase-shift parameter, and the external phase-shift parameter.

16. The control method according to claim 15, characterized in that, During power transmission in the first power transmission direction and the second power transmission direction, by jointly adjusting the first internal phase shift parameter and the second internal phase shift parameter, the absolute value of the turn-off current of all second type power semiconductor switches in the heterogeneous device active bridge is not greater than the preset turn-off current threshold.

17. The control method according to claim 16, characterized in that, Both the first active bridge and the second active bridge are active bridges of the heterogeneous devices; the first type of power semiconductor switch is composed of any one of a single normally-on silicon carbide junction field-effect transistor, a single normally-on gallium nitride junction field-effect transistor, a single normally-on gallium oxide junction field-effect transistor, or a single depletion-mode gallium nitride high electron mobility transistor; the second type of power semiconductor switch is any one of a silicon-based insulated-gate bipolar transistor, a normally-off silicon-based metal-oxide-semiconductor field-effect transistor, or a common-source common-gate power semiconductor switch with overall normally-off characteristics; the common-source... The common-gate power semiconductor switch includes a high-voltage normally-on power semiconductor device and a low-voltage normally-off silicon-based metal-oxide-semiconductor field-effect transistor; the two heterogeneous device active bridges are configured in the same direction or in a mirror configuration, wherein the same-direction configuration means that the first type of power semiconductor switch is set in the upper switch position or the lower switch position in both heterogeneous device active bridges; the mirror configuration means that the first type of power semiconductor switch is set in the upper switch position in one heterogeneous device active bridge and in the lower switch position in the other heterogeneous device active bridge.

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