An active phased radar power supply

Abstract

The application discloses an active phased radar power supply, comprising: an input filter unit connected with a satellite high-voltage primary bus; a front-stage synchronous rectification Buck conversion unit connected with the input filter unit, comprising a PWM controller, a gate drive module and a half-bridge power MOS tube, and used for converting the primary bus voltage into an intermediate bus voltage; an intermediate bus used for transmitting the voltage; a DC-DC conversion unit connected with the intermediate bus and used for converting the intermediate bus into multiple different voltage outputs, at least comprising a four-phase interleaved parallel Buck conversion module, four power phases of which are staggered and actively current-sharing, and used for providing instantaneous large-current output for a radar pulse load; and a timing control unit composed of pure hardware, which samples the intermediate bus voltage as a timing decision basis, and whose multiple outputs are respectively connected with the enable ends of the converters in the DC-DC conversion unit to control the converters to start in a preset order. The scheme realizes efficient and high-density power supply and guarantees high reliability of the satellite.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to an active phased array radar power supply. Background Technology

[0002] Active phased array payloads such as spaceborne synthetic aperture radar are core equipment for satellite-based Earth observation and reconnaissance. They integrate numerous subsystems, including digital beamforming, high-speed signal processing, radio frequency transceiver channels, and beam control units. These subsystems place extremely stringent requirements on the power supply: they need to provide multiple precise voltages simultaneously, including 3.3V, 5V, 5.5V, and -5V, and the 5V digital processing power supply must withstand transient peak currents of up to 80A during radar pulse transmission.

[0003] Satellite primary power buses typically provide DC voltages from 70V to 110V. Traditional spaceborne power supplies often employ a centralized architecture of "high-voltage bus direct-to-low-voltage" or use multi-channel isolation converters. However, as spaceborne radars evolve towards higher resolution and more multifunctionality, the physical space allocated to the power system within the payload bay is drastically reduced, making the size, efficiency, and heat dissipation issues of traditional architectures irreconcilable. Specifically: during high-voltage direct-to-low-voltage conversion, the extremely large duty cycle difference leads to extremely high switching losses, and the required large-size heat dissipation structure severely encroaches on the effective payload space; multi-channel isolation schemes rely on bulky transformers with poor cross-regulation, making it difficult to achieve stable high-current output within a confined space. Summary of the Invention

[0004] An embodiment of this application provides a power supply for an active phased array radar.

[0005] To achieve the above objectives, embodiments of this application provide an active phased array radar power supply, comprising: The input filter unit is connected to the satellite's high-voltage primary bus. The front-stage synchronous rectification Buck converter unit has its input terminal connected to the output terminal of the input filter unit. The front-stage synchronous rectification Buck converter unit includes a PWM controller, a gate drive module, and a half-bridge power MOSFET. The PWM controller outputs a PWM drive signal to the gate drive module, which drives the half-bridge power MOSFET to convert the satellite high-voltage primary bus voltage into an intermediate bus voltage. The intermediate busbar, whose input end is connected to the output end of the preceding synchronous rectifier Buck converter unit, is used to transmit the intermediate busbar voltage. The DC-DC converter unit has its input terminal connected to the output terminal of the intermediate bus, and is used to convert the intermediate bus voltage into multiple DC outputs with different voltage values. The DC-DC converter unit includes at least one four-phase interleaved parallel Buck converter module. The four power phases of the four-phase interleaved parallel Buck converter module are staggered and configured with active current sharing control to provide radar pulse loads with outputs that can withstand instantaneous large current steps. The timing control unit is composed of pure hardware devices. It is connected to the intermediate bus and is used to sample the voltage signal of the intermediate bus as the basis for timing decision. The multiple output terminals of the timing control unit are respectively connected to the enable terminals of each DC-DC converter in the DC-DC conversion unit, and are used to control each DC-DC converter to start up in a preset order.

[0006] In one embodiment, the input filtering unit includes multiple parallel ceramic capacitors, Y capacitors, and two cascaded common-mode inductors; Multiple ceramic capacitors connected in parallel are connected between the positive terminal of the satellite's high-voltage primary bus and the power ground to bypass differential-mode noise current; Two cascaded common-mode inductors are connected in series in the positive and negative paths of the satellite high-voltage primary bus. The input side of the two cascaded common-mode inductors is connected to the positive and negative terminals of the satellite high-voltage primary bus, and the output side of the two cascaded common-mode inductors is connected to the voltage input terminal of the preceding synchronous rectification Buck converter unit. The Y capacitor is connected between the power bus on the output side of the two cascaded common-mode inductors and the chassis ground to provide a common-mode noise discharge circuit.

[0007] In one embodiment, the PWM controller in the front-end synchronous rectification Buck converter unit is a synchronous rectification buck controller, the gate drive module includes a first external independent gate drive submodule and a second external independent gate drive submodule, and the half-bridge power MOSFET includes an upper power MOSFET and a lower power MOSFET. The synchronous rectification buck controller outputs two complementary PWM drive signals, which are respectively input to the input terminals of the first external independent gate drive submodule and the second external independent gate drive submodule; the output terminals of the first external independent gate drive submodule and the second external independent gate drive submodule respectively drive the upper power MOSFET and the lower power MOSFET. The drain of the upper power MOSFET is connected to the output of the input filter unit. The source of the upper power MOSFET is connected to the drain of the lower power MOSFET to form a switching node. The switching node is connected to the input of the power inductor. The source of the lower power MOSFET is connected to power ground. The output of the power inductor is connected to the input of the intermediate bus.

[0008] In one embodiment, the front-end synchronous rectification Buck converter unit further includes a voltage divider input over / under voltage protection circuit and a spread spectrum frequency modulation module. The voltage divider input over / under voltage protection circuit is composed of a resistor voltage divider network. The resistor voltage divider network samples the satellite high voltage primary bus voltage and outputs an enable control signal to the PWM controller. Hardware lockout protection is implemented when the satellite high voltage primary bus voltage is lower than the undervoltage threshold or higher than the overvoltage threshold. The spread spectrum frequency modulation module is located in the PWM controller and is used to periodically modulate the switching frequency, broaden the switching harmonic energy, and reduce the peak electromagnetic interference.

[0009] In one embodiment, the DC-DC converter unit further includes a -5V output converter module, a 5.5V output converter module, and a 3.3V output converter module; The -5V output conversion module uses an inverting synchronous buck-boost converter topology to convert the intermediate bus voltage to a -5V output voltage. The 5.5V output conversion module adopts a synchronous buck topology to step down the intermediate bus voltage to a 5.5V output voltage. The output link of the 5.5V output conversion module is configured with a multi-stage LC filter structure, which includes a first-stage power LC low-pass network and a second-stage high-frequency noise attenuation network. The second-stage high-frequency noise attenuation network is composed of ferrite beads and ceramic capacitors. The 3.3V output conversion module adopts a voltage-mode synchronous rectification buck topology to step down the intermediate bus voltage to a 3.3V output voltage.

[0010] In one embodiment, the four power phases of the four-phase interleaved parallel Buck converter module correspond to four PWM drive signals, and the phases of the four PWM drive signals are staggered by 90°.

[0011] In one embodiment, the timing control unit includes a comparator, an optocoupler, and a resistor-capacitor network; The power supply terminal of the timing control unit is connected to the output terminal of the high-voltage linear regulator, and the input terminal of the high-voltage linear regulator is connected to the satellite high-voltage primary bus to convert the satellite high-voltage primary bus voltage to 12V to power the comparator and optocoupler.

[0012] In one embodiment, the timing control unit samples the intermediate bus voltage as a timing decision basis, and the preset order is as follows: Once the intermediate bus voltage is established and reaches the undervoltage lockout threshold, the timing control unit outputs the first enable signal to turn on the -5V output conversion module. Once the -5V output conversion module establishes its output voltage, the timing control unit outputs a second enable signal via an optocoupler to turn on the 5.5V output conversion module. When an external enable command is received, the timing control unit outputs an external enable signal to activate the four-phase interleaved parallel Buck converter module and the 3.3V output converter module, respectively.

[0013] In one embodiment, the input filter unit, intermediate bus, DC-DC converter unit, and timing control unit are soldered to the main power board; the half-bridge power MOSFETs of the front-end synchronous rectification Buck converter unit are soldered to an independent copper substrate; the independent copper substrates are stacked below the main power board and are electrically connected to the main power board through terminals; the bottom surface of the copper substrates is bonded to the device housing through a thermally conductive medium.

[0014] In one embodiment, the inner layer of the main power board is covered with a continuously laid solid copper foil; a dense array of vias is arranged on the main power board. The main power board has an exposed copper cladding edge, which is pressed tightly against the equipment housing by a high thermal conductivity insulating pad. The device housing is provided with protrusions at the positions of each heating element. The height of each protrusion is adapted to the height of the corresponding heating element. A thermally conductive pad is filled between each protrusion and the top surface of the corresponding heating element. Localized thermally conductive potting is applied to the gap between the heating element and the equipment housing.

[0015] This application has the following advantages over the prior art: This application utilizes a front-stage synchronous rectification Buck converter to first convert the satellite's high-voltage primary bus voltage to an intermediate bus voltage, and then a subsequent DC-DC converter to convert it into multiple low-voltage outputs, forming a two-stage architecture of high-voltage pre-regulation + intermediate-voltage bus + low-voltage secondary conversion. Based on this architecture, the front-stage only needs to handle the single-stage conversion from high voltage to intermediate voltage, achieving a high efficiency of over 98% within the optimal duty cycle range, significantly reducing heat dissipation from the source. The subsequent modules use a fixed intermediate bus as input and can employ low-voltage, high-current, high-performance devices, thus replacing the single, massive heat source of traditional centralized converters with a distributed heat source approach, making it possible to convert hundreds of watts of power without additional heat sinks. Meanwhile, the four-phase interleaved parallel Buck converter module in the DC-DC converter unit achieves a significant increase in the equivalent switching frequency and a substantial reduction in the amplitude of the output current ripple frequency through the staggered conduction of multiple phase power stages. This results in a significant reduction in the number and size of the output energy storage capacitors while maintaining the same dynamic response requirements. The four-phase active current sharing control evenly distributes the pulse current to each phase, requiring each phase power stage to be designed based on average power. This avoids the overcurrent and overheating risks caused by a single phase bearing all peak currents, further reducing the space occupied by filtering and heat dissipation components. Furthermore, the timing control unit, composed entirely of hardware devices, directly samples the intermediate bus voltage as the decision criterion, eliminating the need for additional digital programmable devices and software. This fundamentally eliminates the possibility of timing errors caused by software malfunctions or single-event upsets under spaceborne irradiation conditions, ensuring that each DC-DC converter starts safely in a system with complex multi-voltage interconnections, strictly following the preset sequence. This effectively avoids the risk of latch-up or damage to load devices caused by abnormal power supply sequence. In summary, the technical features of this application form a progressive and synergistic cooperation in three aspects: high voltage conversion, pulse power supply, and timing control. Together, they realize a power supply solution with high power density, high efficiency, and high radiation resistance reliability in the extremely confined space of spacecraft, solving the technical problem that traditional architectures cannot balance size, heat dissipation, and timing security. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the power supply structure for the active phased array radar in an embodiment of this application; Figure 2 This is a circuit diagram of the input filter unit in the power supply of the active phased array radar in an embodiment of this application; Figure 3 The circuit schematic diagram of the front-stage synchronous rectification Buck converter unit in the power supply of the active phased array radar in this embodiment of the application is shown. Figure 4 This is a schematic diagram of the upper and lower half-bridge power MOSFETs in the power supply for an active phased array radar according to an embodiment of this application. Figure 5 This is a schematic diagram of the -5V and 5.5V output control principle in the power supply for the active phased array radar in this embodiment of the application.

[0018] In the diagram, 1 is the input filter unit; 2 is the front-end synchronous rectification Buck converter unit; 3 is the intermediate bus; 4 is the DC-DC converter unit; and 5 is the timing control unit. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation", "connection" and "joining" should be interpreted broadly, for example, they can refer to fixed connection, detachable connection, or integral connection; for those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] This application aims to solve the following technical problems in spaceborne radar power supplies, which face a series of contradictions, such as achieving a transition from a 70V-110V high-voltage bus to multiple low-voltage high-current outputs while simultaneously meeting the 80A peak pulse load requirements, all within extremely limited physical space, harsh operating environments, and complex electromagnetic environments: To achieve power conversion of hundreds of watts within a small volume, losses must be extremely low; otherwise, heat buildup will lead to device failure. Traditional solutions are inefficient and require large heat sinks. If a large number of parallel output capacitors are used to ensure dynamic performance for an 80A peak current, it will seriously encroach on the volume. Therefore, the number of energy storage components must be reduced through architectural innovation. Without software and digital controllers, highly reliable multi-channel power-on / power-off timing control is achieved solely through pure analog hardware to protect load devices and prevent latch-up. If multiple independent power supplies operate independently, they will repeatedly occupy board space and filter components, making it difficult to achieve a compact structure.

[0024] Reference Figure 1 The embodiments of this application provide an active phased array radar power supply, including an input filtering unit 1, a front-stage synchronous rectification Buck converter unit 2, an intermediate bus 3, a DC-DC (Direct Current to Direct Current) converter unit 4, and a timing control unit 5.

[0025] The input of input filter unit 1 is connected to the satellite's high-voltage primary bus. Input filter unit 1 is used for input voltage input and pre-noise filtering. The satellite's high-voltage primary bus typically provides a DC voltage of 70V to 110V.

[0026] The input of the front-stage synchronous rectification Buck converter unit 2 is connected to the output of the input filter unit 1. The front-stage synchronous rectification Buck converter unit 2 includes a PWM (Pulse Width Modulation) controller, a gate drive module, and half-bridge power MOSFETs. The PWM controller continuously outputs PWM drive signals to the gate drive module, which drives the half-bridge power MOSFETs to turn on and off in an orderly manner, transforming the fluctuating satellite high-voltage primary bus voltage into a stable intermediate bus voltage. Specifically, the front-stage synchronous rectification Buck converter unit 2 efficiently converts a wide-range DC bus voltage of 70V-110V into a stable 50V intermediate bus voltage.

[0027] The input terminal of intermediate bus 3 is connected to the output terminal of the preceding synchronous rectification Buck converter unit 2, and is used to transmit the intermediate bus voltage. The intermediate bus voltage is set to 50V, serving as the unified input source for the subsequent DC-DC converter unit 4, and providing a unified power supply input for all subsequent power-consuming modules. The selection of the 50V intermediate bus is a key factor in system-level space optimization. Directly reducing the voltage from 70V-110V to 3.3V or 5V results in a very small duty cycle, a significant increase in switching losses, and the subsequent MOSFETs need to withstand high voltage, with the product of on-resistance and gate charge being much greater than that of low-voltage devices. This application selects 50V as the intermediate bus voltage, ensuring that the preceding synchronous rectification Buck converter unit 2 operates in a high-efficiency range with a suitable duty cycle, and allowing the subsequent DC-DC converter unit 4 to use high-performance MOSFETs with a 100V withstand voltage rating, whose advantages are significantly superior to high-voltage devices. This careful selection of voltage level enables both the preceding and following stages to achieve optimal efficiency within a minimal volume, achieving a comprehensive balance between space and performance at the system architecture level.

[0028] The input terminal of the DC-DC converter unit 4 is connected to the output terminal of the intermediate bus 3, which is used to convert the single intermediate bus voltage into multiple DC outputs with different voltage values ​​to meet the power supply requirements of radar multi-load. The DC-DC converter unit 4 includes at least one four-phase interleaved parallel Buck converter module. The four power phases of the four-phase interleaved parallel Buck converter module are staggered and configured with active current sharing control to provide radar pulse load with an output that can withstand instantaneous large current step.

[0029] The timing control unit 5 is composed of pure hardware devices, without any digital programmable devices (such as MCU (Microcontroller Unit), FPGA (Field-Programmable Gate Array), DSP (Digital Signal Processor), etc.) and without software programs. The timing control unit 5 is connected to the intermediate bus 3 and is used to sample the voltage signal of the intermediate bus 3 as the basis for timing decision. The multiple output terminals of the timing control unit 5 are respectively connected to the enable terminals of each DC-DC converter in the DC-DC conversion unit 4, which are used to control each DC-DC converter to start up in a preset order to avoid the inrush current generated by multiple modules being powered on at the same time.

[0030] The power supply adopts an architecture of pre-filtering, high-voltage step-down in the front stage, voltage regulation on the intermediate bus, multi-channel precise conversion in the rear stage, and hardware timing power-on. It is adapted to the core working conditions of high-voltage input on the spaceborne platform and dynamic operation of radar pulse load. From the system architecture level, it takes into account electromagnetic compatibility, voltage conversion stability, load adaptability and power-on safety.

[0031] In this embodiment, a dedicated power supply system architecture adapted to spaceborne active phased array radar is constructed. Through graded voltage transformation, multi-channel differentiated output, and pure hardware timing control, the problems of traditional power supply architecture being single, unable to adapt to radar pulse load, and having uncontrollable power-on timing are solved. The system has high integration and strong adaptability to operating conditions, providing a stable system foundation for the subsequent optimization design of each unit.

[0032] In one embodiment, such as Figure 2 As shown, the input filter unit 1 includes multiple parallel ceramic capacitors, Y capacitors, and two cascaded common-mode inductors; the three work together to form a composite filter topology to achieve layered suppression of differential-mode and common-mode noise.

[0033] Multiple ceramic capacitors connected in parallel are positioned between the positive terminal of the satellite's high-voltage primary bus and power ground to bypass differential-mode noise current. Within a limited space, these parallel capacitors provide an extremely low ESR (Equivalent Series Resistance) high-frequency decoupling path, effectively bypassing the differential-mode noise current generated by the high-speed switching of the Buck switch and suppressing high-frequency differential-mode interference. Multiple ceramic capacitors, such as... Figure 2 C1-C44 in the middle.

[0034] Two cascaded common-mode inductors are connected in series in the positive and negative paths of the satellite's high-voltage primary bus. The input sides of the two cascaded common-mode inductors are connected to the positive and negative terminals of the satellite's high-voltage primary bus, and the output sides are connected to the voltage input of the preceding synchronous rectifier Buck converter unit 2. The cascaded common-mode inductors achieve high insertion loss over a wide frequency band from 150kHz to 30MHz, suppressing common-mode conducted emissions of the fundamental frequency and its higher harmonics. The common-mode inductors are as follows... Figure 2 L1 and L2 in the example.

[0035] The Y capacitor is connected between the power bus on the output side of the two cascaded common-mode inductors and the chassis ground to provide a controlled, low-impedance discharge path for common-mode noise. The Y capacitor, as shown... Figure 2 CY1-C Y8 in the middle.

[0036] This composite filtering topology can meet the CE102 conducted emission and RE102 radiated emission requirements specified in GJB151B-2013 within the confined space of spaceborne equipment installation. Through three-dimensional noise reduction logic of differential mode bypass, common mode suppression, and noise discharge, it thoroughly purifies the input voltage of the satellite's high-voltage primary bus, avoiding interference of power switch noise to radar radio frequency signals from the source.

[0037] In this embodiment, the design goal is to achieve a wide bandwidth and high rejection ratio in a small space. Multiple ceramic capacitors are connected in parallel to bypass the differential mode noise of the switch under extremely low ESR. Two common-mode inductors cover the fundamental and higher harmonic frequency bands respectively. Y capacitors provide a controlled common-mode circuit. The three work together to achieve full-band conducted emission suppression in a small space with the fewest components, ensuring that the whole machine meets the requirements of spaceborne electromagnetic compatibility.

[0038] In one embodiment, such as Figure 3 , Figure 4 As shown, the PWM controller in the front-end synchronous rectification Buck converter unit 2 is a synchronous rectification buck controller. The gate drive module includes a first external independent gate drive submodule and a second external independent gate drive submodule. The half-bridge power MOSFET includes an upper power MOSFET and a lower power MOSFET. The synchronous rectification buck controller outputs two complementary PWM drive signals, which are respectively input to the input terminals of the first external independent gate drive submodule and the second external independent gate drive submodule. The output terminals of the first external independent gate drive submodule and the second external independent gate drive submodule respectively drive the upper power MOSFET and the lower power MOSFET, thereby realizing complementary switching control of the upper and lower MOSFETs and avoiding shoot-through risk. The drain of the upper power MOSFET is connected to the output of the input filter unit 1. The source of the upper power MOSFET is connected to the drain of the lower power MOSFET to form a switching node. The switching node is connected to the input of the power inductor. The source of the lower power MOSFET is connected to power ground. The output of the power inductor is connected to the input of the intermediate bus 3.

[0039] Specifically, the front-stage synchronous rectification Buck converter unit 2 is the first power conversion stage of the satellite-borne active phased array radar power supply, responsible for the core task of efficiently converting the 70V-110V wide-range satellite high-voltage primary bus voltage into a stable 50V intermediate bus voltage. This unit is based on a synchronous rectification buck topology, and the synchronous rectification buck controller is as follows: Figure 3 The U1 uses the CSV36117, and the gate drive module is as follows: Figure 3 U2 and U3 use two EG3012 high-speed gate driver chips, and the half-bridge power MOSFETs are as follows: Figure 4 In the middle, Q1 and Q2 use two NCEP02T10D power MOSFETs, and EG3012 provides a peak drive current of 9A to ensure that the MOSFET completes the switching transition in nanosecond time, which greatly reduces switching losses.

[0040] Since the gate driver built into the synchronous rectification buck controller CSV36117 has limited output current capability, directly driving a high-current MOSFET will result in slow switching speed and high switching losses. Therefore, this embodiment adopts a solution of inserting an independent high-speed gate driver chip EG3012 between the synchronous rectification buck controller and the upper and lower power MOSFETs to form a two-stage driving architecture and improve the gate driving capability.

[0041] The EG3012 features a peak drive current of up to 9A, extremely low propagation delay and rise / fall time, and its inputs are compatible with TTL (Transistor-Transistor Logic) / CMOS (Complementary Metal-Oxide-Semiconductor) logic levels, directly matching the 12V gate drive output level of the CSV36117. The EG3012 is supplied at 12V, provided by the DRVCC and NDRV pins of the CSV36117.

[0042] The TG (upper gate drive) output pin of the synchronous rectification buck controller is connected to the input of the first EG3012, and the output of the first EG3012 is connected to the gate of the upper half-bridge power MOSFET NCEP02T10D. The BG (lower gate drive) output pin of the synchronous rectification buck controller is connected to the input of the second EG3012, and the output of the second EG3012 is connected to the gate of the lower half-bridge power MOSFET NCEP02T10D. The DRVCC pin mainly supplies power to the gate drive output stage (the final push-pull circuit of TG and BG) inside the CSV36117. The NDRV pin is the dedicated power supply for the lower gate drive output stage (BG) of the CSV36117. The NDRV pin is directly connected to the DRVCC pin to ensure that the upper and lower gate drive stages share the same supply voltage, and also to provide a certain load capacity externally.

[0043] Under normal operating conditions, the PWM comparator inside the synchronous rectifier buck controller generates a square wave signal with a controlled duty cycle based on the error amplifier output and the current detection signal. After internal logic and level conversion, it outputs a complementary pulse with an amplitude of approximately 12V and dead-time control from the TG and BG pins.

[0044] Taking the TG channel as an example: When the TG output is high (approximately 12V), the first EG3012 receives the signal at its input. After passing through its internal high-speed comparator and push-pull output stage, it generates a drive pulse with an amplitude of 12V and an extremely steep rise edge (typical rise time less than 25ns) at the output. This pulse is directly applied between the gate and source of the upper MOSFET of the half-bridge power MOSFET, causing the upper MOSFET to turn on quickly. When the TG output is low, the output of the EG3012 is quickly pulled to 0V. The gate charge of the upper MOSFET is rapidly discharged through the N-channel pull-down diode inside the EG3012. The gate voltage drops to below the turn-off threshold at an extremely fast speed, and the upper MOSFET turns off.

[0045] Similarly, the BG signal of the synchronous rectification buck controller is converted into a high-speed gate drive waveform with an amplitude of 12V by the second EG3012, which controls the conduction and turn-off of the lower half-bridge power MOSFET.

[0046] A fixed dead time is set between the two drive waveforms (controlled internally by the synchronous rectifier buck controller, typically about 30~50ns). During the dead time, both TG and BG are low, and the outputs of both EG3012 chips are also low, simultaneously turning off the upper and lower half-bridge power MOSFETs. This mechanism strictly prevents catastrophic failures caused by shoot-through of the upper and lower half-bridge power MOSFETs leading to a short circuit to ground. The specific schematic diagram is shown below. Figure 4 As shown (where TG and BG are the drive pulses for the first and second channels, respectively).

[0047] The NCEP02T10D is a 200V N-channel power MOSFET with extremely low on-resistance (approximately 12mΩ typically) and moderate gate charge, making it ideal as the power switch for this front-end synchronous rectification Buck converter unit 2.

[0048] The two NCEP02T10D transistors adopt a standard half-bridge configuration of "source-drain series connection": the drain of the upper power MOSFET (hereinafter referred to as the upper transistor) is connected to the 70V-110V input bus; the source of the upper transistor is connected to the drain of the lower power MOSFET (hereinafter referred to as the lower transistor), and this common node is the switching node (SW) of the front-end synchronous rectification Buck converter unit 2, which is connected to the input terminal of the power inductor; the source of the lower transistor is connected to the input power ground.

[0049] The detailed working process within one switching cycle is as follows: Phase 1: Upper transistor conducts, inductor charges. The EG3012 outputs a high level (12V) to the gate of the upper transistor, turning it on. Input current flows from the drain to the source of the upper transistor, through the inductor to the output, simultaneously charging the output capacitor. The inductor experiences a forward voltage (Vin-Vout), causing the inductor current to rise linearly. During this phase, the gate of the lower transistor remains low, turning it off.

[0050] Phase Two: Dead Time 1 When TG goes low, EG3012 quickly pulls the gate of the upper transistor low. The upper transistor turns off, the inductor current cannot change abruptly, and the switching node voltage begins to drop. During the dead time, both the upper and lower transistors are turned off, and the inductor current freewheels through the body diode of the lower transistor. This process is extremely short, and then immediately proceeds to the next stage.

[0051] Phase 3: Lower transistor conducts, inductor freewheeling current. When BG goes high, the second EG3012 outputs a 12V drive pulse to the gate of the lower transistor. The lower transistor turns on, and the inductor current flows from the source to the drain (synchronous rectification mode). Due to the extremely low on-resistance of the lower transistor, its on-state voltage drop is much smaller than the forward voltage drop of the body diode, significantly reducing freewheeling losses. The inductor is subjected to a negative voltage (-Vout), and the inductor current decreases linearly. This phase continues until the controller decides to switch again.

[0052] Phase Four: Dead Zone 2 When BG goes low, the lower transistor turns off. Inductor current briefly freewheels through the lower transistor's body diode again, and the switching node voltage begins to rise. The upper transistor turns on again after a very short dead time, entering the next cycle.

[0053] Throughout the switching process, the strong, steep gate drive waveform provided by the EG3012 ensures that the MOSFET completes the switching transition within nanoseconds, minimizing switching overlap losses. Simultaneously, the 12V gate drive voltage ensures that the NCEP02T10D is fully enhanced to conduct, achieving its lowest nominal channel resistance and effectively controlling conduction losses.

[0054] In this embodiment, the front-end synchronous rectification Buck converter 2 achieves a measured conversion efficiency of up to 98% under rated operating conditions of 100V input and 50V output by employing a synchronous rectification buck controller, low on-resistance MOSFETs, and external enhanced drive to shorten the switching transition time. At a full load of 800W, the loss is only about 16W, which is distributed across three physical locations: the upper and lower MOSFETs, and the inductor.

[0055] At power levels of several hundred watts, every percentage point of efficiency loss translates to several watts of heat. If this heat cannot be dissipated quickly enough in a small, vacuum-like space, designers will be forced to add heat sinks or increase the board area. In this embodiment, a CSV36117 synchronous rectification buck controller, low on-resistance MOSFETs, and an external EG3012 strong drive are used to shorten the switching transition time, pushing the peak efficiency to 98%. This effectively controls heat and lays the foundation for a heatsink-free design. Simultaneously, dead-time control strictly prevents shoot-through between the upper and lower transistors, ensuring system reliability.

[0056] In one embodiment, the front-end synchronous rectification Buck converter unit 2 further includes a voltage divider input over / under voltage protection circuit and a spread spectrum frequency modulation module; both modules are hardware-based and require no software control.

[0057] The voltage divider input over / under voltage protection circuit is composed of a resistor voltage divider network. The resistor voltage divider network samples the satellite high voltage primary bus voltage and outputs an enable control signal to the PWM controller. When the satellite high voltage primary bus voltage is lower than the undervoltage threshold or higher than the overvoltage threshold, hardware lockout protection is implemented. That is, the resistor voltage divider network outputs a lockout enable signal, which directly shuts down the PWM controller output, realizing fully automatic hardware lockout protection and avoiding circuit damage caused by high voltage breakdown or abnormal low voltage operation.

[0058] Specifically, the RUN pin of the synchronous rectification buck controller (CSV36117, hereinafter referred to as the controller) has a precise enable threshold, with an internal reference of approximately 1.2V. The start-up and shutdown voltage thresholds of the preceding synchronous rectification Buck converter unit 2 can be precisely set via an external voltage divider resistor network. A voltage divider network composed of high-precision resistors is set at the input, dividing the satellite high-voltage primary bus voltage via upper voltage divider resistor R3 and lower voltage divider resistor R4 before connecting it to the RUN pin. When the RUN pin voltage is higher than its enable rise threshold (typically approximately 1.22V), the controller's internal reference is established, soft start begins, and the preceding synchronous rectification Buck converter unit 2 starts operating. When the RUN pin voltage is lower than its shutdown fall threshold (typically approximately 1.16V), the controller shuts down all switching actions.

[0059] By selecting appropriate R3 and R4 resistance ratios, the input undervoltage protection lockout point is set at approximately 65V, and the input overvoltage protection lockout point is set at approximately 115V. The specific operating process is as follows: When the input voltage is below 65V, the RUN pin voltage is below 1.16V, the controller shuts down, implementing undervoltage protection to prevent malfunction of the front-end synchronous rectification Buck converter unit 2 when the satellite high-voltage primary bus voltage is insufficient; when the input voltage is above 115V, an additional overvoltage detection voltage divider network, in conjunction with an external comparator or utilizing the OVLO function pin of the CSV36117, forces the RUN pin low, achieving overvoltage shutdown protection to prevent downstream devices from experiencing excessive voltage stress; when the input voltage recovers to the normal operating range of 70V~110V, the RUN pin voltage rises above 1.22V again, and the controller restarts smoothly through a soft-start process.

[0060] This pure hardware resistor voltage divider protection mechanism requires no additional microcontroller and features fast response speed and high radiation resistance reliability.

[0061] The spread spectrum frequency modulation module is located inside the PWM controller and is used to periodically modulate the switching frequency, spreading the concentrated switching harmonic energy to adjacent frequency bands, reducing the electromagnetic interference peak value at a single frequency point, and achieving dual-layer EMI suppression in conjunction with the front-stage input filter unit 1.

[0062] For details, please refer to... Figure 3 The nominal switching frequency is set to 250kHz by connecting an external resistor to the FREQ pin of the CSV36117. Simultaneously, the spread spectrum frequency modulation function is enabled using the MODE pin to periodically modulate the switching frequency, broadening the switching harmonic energy and reducing electromagnetic interference peaks. The switching frequency changes periodically around the nominal value with a certain modulation amplitude and rate, dispersing and broadening the switching harmonic energy, effectively reducing electromagnetic interference peaks and meeting the stringent electromagnetic compatibility requirements of spaceborne equipment.

[0063] The CSV36117 senses the output voltage via the feedback pin VFB. The output voltage is divided by a voltage divider network and sent to the VFB pin. The controller's internal error amplifier compares this voltage with an internal high-precision 0.8V reference voltage, using a closed-loop adjustment of the upper transistor's duty cycle. By setting the ratio of the voltage divider resistors, the feedback voltage after voltage division at a 50V output is precisely equal to 0.8V, thus stabilizing the output voltage at 50V.

[0064] In this embodiment, a purely hardware-based voltage divider input over / under voltage protection and spread spectrum frequency modulation module are used to achieve fast-response, high-radiation-resistant, and reliable input-side abnormal protection with a very simple pure hardware circuit. At the same time, the peak value of electromagnetic interference is effectively reduced, laying a solid front-end protection foundation for the whole machine to achieve high power density and high reliability power supply in the confined space of spacecraft.

[0065] In one embodiment, the DC-DC converter unit 4 further includes a -5V output converter module, a 5.5V output converter module, and a 3.3V output converter module; the -5V output converter module, the 5.5V output converter module, the 3.3V output converter module, and the four-phase interleaved parallel Buck converter module all use a stable 50V intermediate bus voltage as their input source. Because the input voltage is fixed and moderate, the power switching devices in each module can be selected from 100V rated MOSFETs, whose on-resistance and gate charge figures are significantly better than those of high-voltage solutions, laying the foundation for high efficiency.

[0066] Specifically, the -5V output conversion module adopts an inverting synchronous buck-boost converter topology to convert the intermediate bus voltage to a -5V output voltage; this module is used in circuits that require negative voltage, such as the gate bias of the RF front-end amplifier.

[0067] In this topology, the positive 50V input is connected between the common node of the inductor and power switch in the front-stage synchronous rectifier Buck converter unit 2 and the system reference ground, while the output capacitor and load are connected between the system reference ground and the generated negative voltage output terminal. When the main switch is turned on, the voltage across the inductor is the input voltage, the current rises linearly, and energy is stored in the inductor; when the main switch is turned off and the synchronous freewheeling diode is turned on, the inductor current freewheels through the output capacitor and load, and energy is released to the output terminal, thereby establishing a negative voltage at the output terminal relative to the system ground.

[0068] In the power stage design, a P-channel MOSFET is selected as the main switch, with its source connected to the positive input and its drain connected to the inductor input terminal to simplify the gate drive circuit design; an N-channel MOSFET is selected as the synchronous freewheeling transistor; and the inductor value is 22μH, which must be able to withstand the magnetizing ampere-turns of the superposition of the input peak current and the negative voltage output current.

[0069] In terms of feedback and control, the feedback circuit needs to perform level inversion, amplifying the negative output voltage in reverse and comparing it with the positive reference voltage. A dedicated inverting converter controller is used, integrating the reference voltage and inverting error amplifier internally, and adjusting the switch duty cycle in a closed loop to stabilize the -5V output within ±1.5% accuracy. The output voltage ripple can be reduced to below 30mV through a low ESR capacitor and an LC post-filter.

[0070] In terms of special protection, since a negative voltage output failure may cause the load device to be subjected to reverse bias overvoltage, the module is equipped with an absolute value overvoltage protection for the output voltage. Once the -5V value is detected to be higher than -5.75V, it will immediately shut down to protect the RF components.

[0071] The 5.5V output conversion module adopts a synchronous buck topology to step down the intermediate bus voltage to a 5.5V output voltage. This module mainly supplies power to the radar RF receiving channel and analog front end, and has extremely stringent requirements for ripple noise.

[0072] Specifically, regarding topology and device selection: a synchronous buck topology is also used. To minimize high-frequency noise, both the upper and lower transistors are shielded MOSFETs with low gate charge and low reverse recovery charge. The on-resistance of the upper transistor is approximately 25mΩ, and that of the lower transistor is approximately 10mΩ.

[0073] Low-noise design measures: The power inductor uses a core made of low magnetostriction material to avoid generating audible or ultrasonic noise. The copper foil area of ​​the switching node is strictly controlled, and an RC snubber circuit is added between the drain and source of the MOSFET to suppress ringing.

[0074] The output link of the 5.5V output converter module is configured with a multi-stage LC filter structure. This multi-stage LC filter structure includes a first-stage power LC low-pass network and a second-stage high-frequency noise attenuation network. The first-stage power LC low-pass network is a low-pass network composed of a power inductor and a ceramic capacitor, while the second-stage high-frequency noise attenuation network is a high-frequency noise attenuation network composed of ferrite beads and ceramic capacitors, ensuring that the high-frequency spike noise superimposed on the output voltage is below 5mV.

[0075] Switching frequency synchronization: The controller provides an external clock synchronization pin to lock its switching frequency with a central clock of the system, thus avoiding frequency interference between different modules.

[0076] Protection features: The module has built-in cycle-by-cycle current limiting and high-precision overvoltage protection. Once the output voltage is detected to exceed the rated value by 6% for several microseconds, it will be locked and shut down to protect the expensive RF load.

[0077] The 3.3V output conversion module employs a voltage-mode synchronous rectification buck topology to step down the intermediate bus voltage to a 3.3V output. The module is designed to provide a continuous output current of 15A.

[0078] Specifically, the circuit adopts a synchronous rectification buck topology, with a single-phase voltage mode synchronous buck controller that integrates MOSFET drivers and control loops as its core.

[0079] Power stage design: Both the upper and lower MOSFETs are N-channel MOSFETs with a withstand voltage of 100V and typical on-resistances of 18mΩ and 8mΩ, respectively. The upper MOSFET transfers input energy to the inductor during conduction, while the lower MOSFET conducts during freewheeling to reduce conduction losses. The power inductor is a shielded inductor wound with a ferrite core, measuring 15μH, with a DC resistance of less than 6mΩ and a saturation current rating greater than 25A, ensuring no magnetic saturation occurs across the entire load range.

[0080] Switching frequency and efficiency optimization: The switching frequency is set at 300kHz to achieve a balance between inductor size and switching losses. An adaptive dead-time control circuit ensures that the upper and lower transistors do not conduct simultaneously, while minimizing the conduction time of the body diode to reduce reverse recovery losses.

[0081] Output filtering: Several multilayer ceramic capacitors and one or two large-capacity polymer tantalum capacitors are connected in parallel at the output terminal to provide low equivalent series resistance and sufficient capacitance value to control the output voltage ripple within 20mV peak-to-peak value.

[0082] Control loop: Voltage-mode control with a three-type compensation network is adopted, the crossover frequency is set at 1 / 5 of the switching frequency, and the phase margin is greater than 60 degrees to ensure unconditional stability of the system across the full load range.

[0083] In this embodiment, each module uses a 50V intermediate bus voltage as input, which is fixed and moderate. High-performance MOSFETs with a 100V withstand voltage rating are selected as the power switching devices, whose on-resistance and gate charge figures are significantly superior to high-voltage devices, laying the foundation for high efficiency. Each output voltage is independently closed-loop regulated, resulting in low ripple and fast dynamic response. The -5V output converter module meets the negative voltage bias requirements of the RF front-end; the 5.5V output converter module uses multi-stage LC filtering to ensure high-frequency spike noise is below 5mV, meeting the stringent ripple requirements of the RF receiving channel; and the 3.3V output converter module provides a stable, low-ripple 15A power supply to the digital circuits.

[0084] In one embodiment, the four power phases of the four-phase interleaved parallel Buck converter module correspond to four PWM drive signals, and the phases of the four PWM drive signals are staggered by 90°.

[0085] Specifically, the four-phase interleaved parallel Buck converter module is used to power the radar's digital beamforming and high-speed processing board, requiring an instantaneous current of up to 80A during radar pulse transmission.

[0086] This four-phase interleaved parallel Buck converter module uses four-phase Buck converters operating in parallel. Each phase is a complete synchronous buck power stage, consisting of an independent inductor, upper transistor, and lower transistor. The four-phase outputs are combined to the same output filter capacitor bank and the load terminal. The four phases are uniformly managed by a multi-phase controller, outputting four PWM signals with phases staggered by 90 degrees. Interleaved operation results in: partial cancellation of the four-phase components of the input current ripple at the input terminal, significantly reducing the ripple impact on the 50V intermediate bus 3 and lowering the requirements for the input filter capacitor; the output current ripple frequency is equivalent to four times the single-phase switching frequency, which can significantly reduce the value of the output filter inductor and capacitor under the same output voltage ripple requirements, improving the loop response speed; the increase in the equivalent switching frequency pushes up the resonant frequency of the LC output filter, allowing the control loop to be designed with a higher crossover frequency, thereby obtaining an extremely fast transient response.

[0087] Single-phase power stage design: Each phase is designed to carry a continuous current of 25A and a rated peak current of 35A, with a total four-phase current capacity of 100A continuous and 140A peak, fully meeting the 80A peak requirement with a margin. Each phase MOSFET uses low-resistance devices with an upper MOSFET of 10mΩ and a lower MOSFET of 3mΩ. The conduction loss is distributed across all four phases at a total current of 80A, with each phase experiencing only about 20A, resulting in very low single-phase conduction loss. Each phase inductor is a 0.68μH low-loss ferrite inductor with a DC resistance of approximately 1.5mΩ and a saturation current greater than 45A. The switching frequency of each phase is set to 400kHz, with an equivalent output ripple frequency of 1.6MHz, allowing the output to require only a small ceramic capacitor array to control the steady-state ripple to within 10mV.

[0088] Active current sharing control: The multi-phase controller integrates a current sharing loop. The current of each phase inductor is sampled by a precision current-sensing resistor or an inductor DC resistance detection method and fed back to the current sharing error amplifier. The current sharing amplifier compares the current signal of each phase with the average current reference and fine-tunes the PWM duty cycle of each phase, ensuring that the current of each phase evenly shares the total load current under any load condition. The static current sharing error is less than 5%, and the dynamic current sharing error is less than 10%. This ensures that no single-phase current is too large, triggering current limiting or overheating, and that the temperature rise of each phase power device is uniform, thus improving system reliability.

[0089] Pulse load energy storage and dynamic response: To cope with the instantaneous current jump from extremely light load to 80A peak, the output end is constructed with an energy storage array consisting of dozens of large-capacity, ultra-low ESR conductive polymer tantalum capacitors and hundreds of multilayer ceramic capacitors, with a total equivalent capacitance of up to tens of millifarads and an equivalent series resistance of less than 0.2mΩ.

[0090] When an 80A step load is suddenly applied, these energy storage capacitors can release a huge instantaneous current within microseconds, maintaining the output voltage within the specified range (e.g., 5V ± 3%). The multiphase controller, with its optimized bandwidth of up to 100kHz, can rapidly adjust the duty cycle within tens of microseconds supported by the capacitors, increasing the output current from light load to full load and achieving rapid voltage recovery.

[0091] In this embodiment, the 50V intermediate bus capacitor 3 and the 5V output energy storage capacitor constitute a two-stage hierarchical buffering mechanism: the 50V intermediate bus capacitor 3 absorbs the average power fluctuations within the pulse repetition cycle, maintaining the long-term stability of the bus voltage; the small-capacity, low-ESR capacitor at the 5V output only handles the transient charge supply for tens of microseconds at the pulse leading edge, coping with microsecond-level current step impacts. This two-stage synergy decomposes the buffering pressure of the pulse load into different time scales. Each stage only needs to be specifically optimized according to the amount of charge it handles, avoiding the contradiction of a single-stage energy storage needing to simultaneously consider large capacity and low ESR. This further compresses the overall volume of the output capacitor and improves the power density of the entire device.

[0092] In this embodiment, a doubling of frequency is used to reduce size. A single-phase Buck converter requires a large number of output capacitors in parallel to suppress pulse drops, and the total capacitor volume is unacceptable within the limited space onboard environment. This embodiment uses four-phase Buck converters in interleaved parallel configurations, achieving a significant reduction in the number of output capacitors with a limited increase in the number of switching transistors. The four phases are driven at 90 degrees, increasing the equivalent output ripple frequency to four times that of a single phase, while simultaneously reducing the single-cycle charge throughput. The total capacitor capacity and volume are significantly reduced, representing a volume substitution of passive components with active components. The four phases generate an equivalent ripple frequency of 1.6MHz at a single-phase frequency of 400kHz, and the LC cutoff frequency can be set in the tens of kilohertz range, with a loop bandwidth sufficient to respond to microsecond-level pulse leading edges. Active current sharing evenly distributes the 80A peak current across the four phases, with each phase receiving only 20A. Conduction losses are evenly distributed, and the four power stages are dispersed on the PCB, forming four spatially separated weak heat sources, complementing the overall heatsink-free design. The 5V / 80A pulse output module of the power stage adopts a four-phase interleaved parallel architecture, which achieves a fast and stable response to step pulses from 0 to 80A within a very small output filter capacitor volume. The output voltage drop is strictly controlled, and the heat source is evenly distributed, which is seamlessly integrated with the whole machine's heat sink-free design concept.

[0093] In one embodiment, the timing control unit 5 includes a comparator, an optocoupler, and a resistor-capacitor network, but does not contain any digital programmable devices.

[0094] The power supply terminal of the timing control unit 5 is connected to the output terminal of the high-voltage linear regulator, and the input terminal of the high-voltage linear regulator is connected to the satellite high-voltage primary bus to convert the satellite high-voltage primary bus voltage to 12V to power the comparator and optocoupler.

[0095] Specifically, the timing control unit 5 is powered by a high-voltage low-dropout linear regulator (HV LDO). This HV LDO draws power directly from the 70V-110V input bus, generating a stable 12V voltage to power all operational amplifiers and comparators. This HV LDO is implemented using either a 150V linear regulator or a simple constant current source circuit with a Zener diode built from a high-voltage depletion-mode MOSFET, resulting in extremely low power consumption, meeting spaceborne requirements.

[0096] The high-voltage LDO directly generates 12V from the satellite's high-voltage primary bus to power the control circuit, eliminating the need for an additional isolation transformer or complex multi-stage step-down circuitry. The circuit is simple, small in size, and highly reliable.

[0097] In this embodiment, the simplified auxiliary power supply design utilizes a high-voltage LDO to directly generate 12V from the satellite's high-voltage primary bus to power the control circuit. This eliminates the need for an additional isolation transformer or complex multi-stage step-down circuitry, resulting in a simple, small, and highly reliable circuit. The pure hardware timing control circuit exhibits strong resistance to total dose radiation and single-event effects, fundamentally avoiding the risk of timing errors caused by software malfunctions or logic flips.

[0098] In one embodiment, the timing control unit 5 samples the intermediate bus voltage as the basis for timing decision, and its preset order is as follows: Once the intermediate bus voltage is established and reaches the undervoltage lockout threshold, the timing control unit 5 outputs the first enable signal to turn on the -5V output conversion module. Specifically, once the 50V intermediate bus voltage is established and reaches the undervoltage lockout threshold, the comparator determines and outputs the first enable signal to turn on the -5V output conversion module.

[0099] Once the -5V output conversion module establishes its output voltage, timing control unit 5 outputs a second enable signal via optocoupler activation, turning on the 5.5V output conversion module. Specifically: after the -5V output is established, optocoupler U5 conducts, the voltage at pin 3 of comparator is greater than the 3.2V voltage drop across pin 2, therefore comparator pin 1 outputs a high level, U8 conducts, the 5.5V output conversion module is activated, and the 5.5V output is established. The detailed circuit is as follows... Figure 5 As shown.

[0100] Upon receiving an external enable command, the timing control unit 5 outputs an external enable signal, activating both the four-phase interleaved parallel Buck converter module and the 3.3V output converter module. Specifically, the 5V and 3.3V output control is performed through the enable terminal of the optocoupler control module. Upon receiving an external EN-5V power-on signal, the corresponding optocoupler conducts, enabling both 5V and 3.3V outputs.

[0101] The timing control unit 5 is embedded with 50V bus voltage monitoring, which can automatically shut down relevant modules when the input is undervoltage or a certain output is abnormal, thus achieving full protection of the load.

[0102] In this embodiment, the highly reliable pure hardware timing control is based entirely on the power-on and power-off timing implemented using comparators and optocouplers. It contains no digital programmable devices, exhibiting strong resistance to total dose radiation and single-event effects, fundamentally avoiding the risk of timing errors caused by software crashes or logic flips. The timing control circuit incorporates 50V bus voltage monitoring, automatically shutting down relevant modules in case of input undervoltage or an abnormal output, thus providing ample protection for the load.

[0103] In one embodiment, the input filter unit 1, intermediate bus 3, DC-DC converter unit 4, and timing control unit 5 are soldered to the main power board; the half-bridge power MOSFETs of the front-end synchronous rectification Buck converter unit 2 are soldered to an independent copper substrate; the independent copper substrates are stacked below the main power board and are electrically connected to the main power board through terminals; the bottom surface of the copper substrates is bonded to the device housing through a thermally conductive medium.

[0104] Specifically, the two half-bridge power MOSFETs of the front-end synchronous rectification Buck converter unit 2 are independently soldered onto a copper-based PCB. This copper substrate is positioned directly below the main power board and is electrically connected to the main power board via terminals, forming a three-dimensional stacked structure. The bottom surface of the copper substrate is directly attached to the housing with thermal grease. This three-dimensional stacked structure physically separates the power circuit and signal circuit in the vertical direction, saving valuable board space on the motherboard and evenly conducting the concentrated losses of the switching transistors to the housing through the low thermal resistance path of the copper substrate, achieving a simultaneous improvement in space utilization and heat dissipation efficiency.

[0105] The upper and lower half-bridge power MOSFETs of the front-end synchronous rectification Buck converter unit 2 are independently soldered onto a copper-based PCB. This copper-based PCB is placed directly below the main power board and electrically connected via terminals. The bottom surface of the copper-based PCB is directly attached to the housing with thermally conductive silicone grease. This structure allows the bottom surface of the copper-based PCB of the front-end synchronous rectification Buck converter unit 2 to be directly attached to the housing with thermally conductive silicone grease, forming the shortest heat dissipation path from the main power circuit to the housing.

[0106] The front-end synchronous rectification Buck converter unit 2 is not an isolated conventional synchronous rectification buck circuit. Instead, it is a comprehensive, end-to-end design addressing the core challenge of high-voltage, high-power, low-loss conversion in extremely confined spaces (small size and light weight) and complex electromagnetic environments. This design encompasses everything from component selection and drive architecture to control strategies. Through this design, the front-end synchronous rectification Buck converter unit 2 not only achieves a high efficiency of 98% itself, but also lays a decisive foundation for the entire power system to achieve high power density and reliable operation without additional heat sinks within extremely confined spaces.

[0107] In this embodiment, the three-dimensional stacked structure physically separates the power circuit and the signal circuit in the vertical direction, saving valuable board space on the motherboard and uniformly conducting the concentrated losses of the switching transistors to the casing through the low thermal resistance path of the copper substrate, achieving a simultaneous improvement in space utilization and heat dissipation efficiency. The high efficiency of the front-stage synchronous rectification Buck converter unit 2 effectively controls heat, laying the foundation for a design without an additional heat sink for the entire machine.

[0108] In one embodiment, the inner layer of the main power board is covered with a continuously laid solid copper foil; a dense via array is arranged on the main power board. Specifically, the inner layer of the PCB power main board uses a large area of ​​solid copper foil, and the heat from the components is conducted to the inner layer heat-spreading copper foil for planar diffusion through the dense via array. The pads of the power devices are connected to the large area of ​​solid copper foil in the inner layer through the via array, which is used to conduct the heat generated by the power devices to the inner layer solid copper foil for planar diffusion.

[0109] The drain pads of all power MOSFETs are directly soldered to the large copper foil on the top layer, and heat is conducted to the inner heat spreader copper foil through a dense array of vias for planar diffusion, utilizing the entire circuit board itself as a built-in heat spreader. The bottom of the power inductor is in close contact with the board surface, and excess heat is dissipated through the PCB copper foil.

[0110] The main power board has an exposed copper cladding edge, which is pressed tightly against the equipment housing by a high thermal conductivity insulating pad.

[0111] Specifically, the PCB edge design exposes a copper cladding as a heat collection busbar. A high thermal conductivity insulating pad is sandwiched between the copper cladding and the housing, and then tightened with screws. While meeting the insulation requirements of the satellite high-voltage primary busbar for the housing, heat is directly transferred to the housing from the board edge via a low thermal resistance path, eliminating the need for additional heat dissipation components. This solution, while meeting the insulation requirements of the satellite high-voltage primary busbar for the housing, utilizes the PCB itself as a built-in heat sink. Heat is transferred to the outer shell via the copper cladding and insulating pad via a low thermal resistance path, eliminating the need for additional heat dissipation components and achieving safe, uniform, and efficient conductive heat dissipation within a small volume.

[0112] The device housing is provided with protrusions at the positions of each heating element. The height of each protrusion is adapted to the height of the corresponding heating element. A thermally conductive pad is filled between each protrusion and the top surface of the corresponding heating element.

[0113] Specifically, raised protrusions of varying heights are placed on the bottom of the housing corresponding to the locations of each heat-generating component. Thermal pads fill the gaps between the top surfaces of the components and the protrusions, ensuring complete heat dissipation for major power devices and other heat-generating components, thus increasing structural strength and heat sink capacity. This design solves the problem of non-uniformly sized components not being able to contact the housing simultaneously. It constructs a low-thermal-resistance conduction path directly from each heat-generating point to the housing with a minimal structure, eliminating localized heat dissipation blind spots and ensuring uniform and efficient heat dissipation within a very small space.

[0114] Localized thermally conductive potting is applied to the gap between the heating element and the equipment housing.

[0115] Specifically, a localized low-density thermally conductive potting process is used at the bottom of the housing and the root area of ​​the heat-generating device. The potting height only covers the gap between the bottom surface of the device and the housing, rather than using full-board potting. The rationale is that while full potting provides an additional heat conduction path, it incurs an unacceptable weight penalty. Under the stringent weight constraints of spaceborne payloads, the hundreds of grams of weight gain from full-board potting would directly reduce the effective payload. Furthermore, the thermal expansion stress of the large-volume potting compound under vacuum temperature cycling could crack the solder joints, posing a reliability risk. This application employs a localized potting strategy, incurring only a few grams of weight gain, utilizing the high volumetric heat capacity of the potting compound to absorb the heat from pulsed power spikes, thus mitigating transient temperature rises and achieving an optimal balance between heat dissipation gain, weight control, and structural reliability.

[0116] For component selection, power devices with lower on-resistance MOSFETs are preferred under the same voltage rating to reduce conduction losses from the source. Inductor selection should focus on low DCR design, using flat magnetic cores to increase the bottom contact area. Thermal grease can then be used to directly transfer heat from the magnetic core to the PCB copper foil plane for diffusion, avoiding localized hot spots. This selection strategy, combined with thermal design, enables high efficiency and uniform heat dissipation of the entire system without a dedicated heatsink, through minimal component-level optimization.

[0117] The two-stage architecture physically separates the main heat generation from the front-end synchronous rectification Buck converter unit and the pulse loss from the 5V multiphase module, preventing localized overheating. In the satellite vacuum environment, this design ensures that all device junction temperatures remain within the rated range without the need for any additional heat sinks.

[0118] In this embodiment, a three-path synergistic thermal management scheme—PCB heat dissipation, shell conduction, and local potting—achieves highly efficient heat dissipation without the need for additional heat sinks. A large area of ​​copper foil on the inner layer of the PCB, combined with a via array, enables planar heat diffusion; the copper edging, through highly thermally conductive insulating pads, transfers heat from the board edge to the shell, achieving efficient conduction while meeting insulation requirements; differentiated height bosses solve the problem of non-uniform height components not being able to contact the shell simultaneously; local potting, at the cost of a few grams of added weight, utilizes the high volumetric heat capacity of the potting compound to absorb pulsed power spikes, smoothing transient temperature rises, achieving an optimal balance between heat dissipation gain, weight control, and structural reliability. The overall power density, efficiency, and reliability of the device comprehensively surpass existing solutions.

[0119] The active phased array radar power supply provided in this application can be widely used in the power supply systems of active phased array payloads such as spaceborne synthetic aperture radar, and can also be used in other spacecraft power supply applications with stringent requirements for size, efficiency, and heat dissipation. This application features a compact structure, high reliability, and good industrial applicability.

[0120] The active phased array radar power supply provided in this application has the following characteristics: Extremely high power density: By dispersing losses through a two-stage architecture, reducing the size of passive components through high-frequency operation, and reducing output filtering requirements through multi-phase interleaving, the whole machine can achieve pulse power output of more than 800W in a very small space, with a power density that is significantly better than traditional solutions.

[0121] Extremely high system efficiency: The efficiency of the front-end synchronous rectification Buck converter unit 2 is up to 98%, and the efficiency of the back-end can also reach more than 95% under 50V input. The full-load efficiency of the whole machine exceeds 93%, and the heat generation is significantly reduced compared with the direct high-voltage conversion scheme, making it suitable for the satellite vacuum heat dissipation environment.

[0122] Superior pulse load capacity: The 5V output adopts multi-phase interleaved parallel connection, combined with energy storage capacitor, which can easily cope with 0~80A transient jumps and ensure the stability of radar transmission waveform envelope.

[0123] High-reliability pure hardware timing control: The power-on and power-off timing is implemented entirely based on comparators and optocouplers, without any digital programmable devices. It has strong resistance to total dose radiation and single-event effects, fundamentally avoiding the risk of timing errors caused by software failures or logic flips.

[0124] Simplified auxiliary power supply design: The high-voltage LDO directly generates 12V from the satellite's high-voltage primary bus to power the control circuit, eliminating the need for an additional isolation transformer or complex multi-stage step-down circuit. The circuit is simple, small in size, and highly reliable.

[0125] Independent output with excellent quality: Each output voltage is independently closed-loop regulated, resulting in low ripple and fast dynamic response. Furthermore, the multi-phase interleaving technology effectively improves the ripple frequency and reduces the filtering burden.

[0126] Natural undervoltage protection and sequential interlocking: The timing control circuit is embedded with 50V intermediate bus voltage monitoring, which can automatically shut down the relevant modules when the input is undervoltage or a certain output is abnormal, so as to achieve full protection of the load.

[0127] Example The entire active phased array radar power supply uses a multi-layer thick copper printed circuit board as the main power board. The front side mainly houses power devices and inductors, while the back and inner layers contain signal traces and a large area of ​​grounding / heat dissipation copper foil. The two half-bridge power MOSFETs of the front-end synchronous rectification Buck converter unit 2 are independently soldered onto a copper substrate PCB. This copper substrate is placed directly below the main power board and is electrically connected to the main power board through terminals, forming a three-dimensional stacked structure.

[0128] 1. Input Protection, Filtering, and Pre-Stage Synchronous Rectification Buck Converter Unit: The input terminal is sequentially equipped with a miniaturized surface-mount fuse, surge protection circuit, and a wideband cascaded common-mode-differential-mode composite noise suppression unit (i.e., input filter unit 1). This noise suppression unit consists of multiple ceramic capacitors in parallel, a Y capacitor, and two stages of cascaded common-mode inductors: the multiple ceramic capacitors in parallel provide a high-frequency decoupling channel with extremely low ESR within a limited space, effectively bypassing the differential-mode noise current generated by the high-speed switching of the switching transistor in the pre-stage synchronous rectification Buck converter unit 2; the Y capacitor is connected between the power bus and the chassis ground, providing a controlled low-impedance discharge circuit for common-mode noise; the two stages of cascaded common-mode inductors achieve high insertion loss in a wide frequency band from 150kHz to 30MHz, respectively suppressing the common-mode conducted emission of the fundamental frequency and its higher harmonics of the switching frequency. The three components work together to achieve full-band conducted emission suppression in a confined space with minimal components, ensuring that the entire device passes the CE102 conducted emission and RE102 radiated emission tests specified in GJB151B-2013.

[0129] Following the input filter unit 1 is the front-end synchronous rectification Buck converter unit 2, consisting of a CSV36117, two EG3012 MOSFETs, and two NCEP02T10D MOSFETs. The RUN pin of the CSV36117 is connected to the input resistor divider network, setting the 65V undervoltage shutdown and 115V overvoltage shutdown points. The DRVCC and NDRV pins are directly connected to the VDD terminals of the two EG3012 MOSFETs, providing a 12V drive voltage. The input terminal of the upper MOSFET EG3012 is connected to the TG terminal of the CSV36117, and its output drives the gate of the upper MOSFET NCEP02T10D; the input terminal of the lower MOSFET EG3012 is connected to the BG terminal, and its output drives the gate of the lower MOSFET. The two MOSFETs are arranged in a half-bridge configuration, and the copper foil area of ​​the switching node is strictly minimized to reduce radiated noise. The power inductor is a flat-core, thin, high-current shielded inductor, placed close to the main power board surface, with thermal grease used to conduct the heat from the core into the PCB copper foil plane for diffusion.

[0130] Two half-bridge power MOSFETs are soldered to an independent copper-based PCB, which is positioned directly below the main power board and connected to the upper board via terminals. The bottom surface of the copper-based PCB is directly attached to the housing using thermal grease. This three-dimensional stacked structure physically separates the power circuit and signal circuit in the vertical direction, saving valuable board space on the motherboard and evenly conducting the concentrated losses of the switching transistors to the housing through the low thermal resistance path of the copper-based PCB, achieving a simultaneous improvement in space utilization and heat dissipation efficiency.

[0131] The output capacitors utilize multiple large-capacity ceramic capacitors connected in parallel with low-ESR tantalum capacitors, providing sufficient capacitance and extremely low impedance within a very small footprint. This stage efficiently converts the 70V-110V input to the 50V intermediate bus 3, achieving a peak efficiency of 98%.

[0132] 2. Secondary Power Conversion (i.e., DC-DC Conversion Unit 4) Layout: The 50V intermediate bus 3 distributes power to four independent conversion modules via an inner thick copper plane. Each module is arranged adjacent to its corresponding output port. The 3.3V and 5.5V output conversion modules use compact integrated synchronous buck regulators, requiring only a small external inductor and a few capacitors. The -5V output conversion module consists of an inverting converter controller, inductors, and capacitors, also in a compact form. The 5V / 80A pulse output conversion module uses a four-phase interleaved parallel controller. The four power stages are evenly distributed around the output connectors. Each phase consists of a pair of small MOSFETs and a small inductor. Active current sharing evenly distributes the 80A peak current to the four phases, with each phase handling only about 20A. Conduction losses are evenly distributed. The four power stages are distributed on the PCB, forming four spatially separated weak heat sources. After the four-phase output current is combined, it passes through an energy storage array composed of several large-capacity conductive polymer tantalum capacitors and ceramic capacitors, directly supplying power to the load. Interleaved operation increases the ripple frequency to 1.6MHz, making the total capacitance required for output filtering only a fraction of that required for a single-phase solution, thus significantly reducing the total volume of the energy storage components.

[0133] 3. Overall heat dissipation design The overall heat dissipation adopts a three-path synergistic thermal management solution: PCB heat dissipation, shell conduction, and local potting.

[0134] The inner layer of the PCB main power board uses a large area of ​​solid copper foil. The drain pads of all power MOSFETs are directly soldered to the top layer of large copper foil, and heat is conducted to the inner layer heat-spreading copper foil through a dense array of vias for planar diffusion, utilizing the entire circuit board itself as a built-in heat sink. The bottom of the power inductor is in close contact with the board surface, and excess heat is dissipated through the PCB copper foil. The PCB edge is designed with exposed copper cladding as a heat collection busbar. A high thermal conductivity insulating pad is sandwiched between the copper cladding and the housing and pressed tightly with screws. While meeting the insulation requirements of the primary busbar to the housing, heat is directly transferred to the housing from the board edge through a low thermal resistance path, eliminating the need for additional heat dissipation components.

[0135] Differentiated height bosses are set at the bottom of the housing corresponding to the positions of each heat-generating component. The gap between the top surface of the component and the boss is filled by a thermal pad, which enables complete heat dissipation of multiple components against the housing and solves the problem that components of different heights cannot make contact with the housing at the same time. The bottom surface of the copper substrate PCB of the front-end synchronous rectification Buck converter unit 2 is directly attached to the housing with thermal grease, forming the shortest heat dissipation path from the main power circuit to the housing.

[0136] Localized low-density thermally conductive potting is used at the bottom of the housing and the root area of ​​the heat-generating device. The potting height only covers the gap between the bottom surface of the device and the housing, rather than completely potting the entire board. While complete potting provides an additional heat conduction path, it comes at an unacceptable weight cost. Under the stringent weight limits of spaceborne loads, the hundreds of grams of weight gain from full-board potting would directly reduce the effective payload. Furthermore, the thermal expansion stress of the large-volume potting compound under vacuum temperature cycling could crack the solder joints. Localized potting, at the cost of a few grams of weight gain, utilizes the high volumetric specific heat capacity of the potting compound to absorb the heat from pulsed power spikes, smoothing out transient temperature rises and converting the transient thermal shock of the pulsed load into a slowly varying heat flow. This achieves an optimal balance between heat dissipation gain, weight control, and structural reliability.

[0137] The two-stage architecture physically separates the main heat generation from the pre-regulator stage of the front-end synchronous rectification Buck converter unit 2 and the pulse loss of the 5V multiphase module, preventing localized overheating. In the satellite vacuum environment, this design ensures that all device junction temperatures remain within the rated range without the need for any additional heat sinks.

[0138] 4. Control and Protection: The system can be optionally equipped with a pure hardware timing control unit 5, consisting of comparators and operational amplifiers. Its 12V power supply is obtained directly from the 90V satellite high-voltage primary bus by a small-power high-voltage LDO, which controls the power-on and power-off sequence of each output. Its size is almost negligible. The input terminals are also equipped with undervoltage lockout and overcurrent protection, and all output terminals are equipped with output overvoltage and output short-circuit protection to ensure automatic protection in case of fluctuations in the satellite high-voltage primary bus or abnormal load.

[0139] Through the above compact and efficient design, this power supply system perfectly achieves the multi-channel stable power supply and 80A peak pulse power output required by the spaceborne radar within a strictly limited volume. The overall power density, efficiency and reliability of the system all surpass the existing solutions.

[0140] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power supply for an active phased array radar, characterized in that, include: Input filtering unit (1), the input end of which is connected to the satellite high-voltage primary bus; The front-stage synchronous rectification Buck converter unit (2) is connected to the output of the input filter unit (1). The front-stage synchronous rectification Buck converter unit (2) includes a PWM controller, a gate drive module and a half-bridge power MOSFET. The PWM controller outputs a PWM drive signal to the gate drive module, and the gate drive module drives the half-bridge power MOSFET to convert the satellite high-voltage primary bus voltage into an intermediate bus voltage. Intermediate bus (3), the input end of the intermediate bus (3) is connected to the output end of the front-stage synchronous rectifier Buck converter unit (2) for transmitting the intermediate bus voltage; DC-DC converter unit (4), the input terminal of the DC-DC converter unit (4) is connected to the output terminal of the intermediate bus (3), and is used to convert the intermediate bus voltage into multiple DC outputs with different voltage values; the DC-DC converter unit (4) includes at least one four-phase interleaved parallel Buck converter module, the four power phases of the four-phase interleaved parallel Buck converter module are staggered, and active current sharing control is configured to provide radar pulse load with an output that can withstand instantaneous large current step; The timing control unit (5) is composed of pure hardware devices. The timing control unit (5) is connected to the intermediate bus (3) and is used to sample the voltage signal of the intermediate bus (3) as the basis for timing decision. The multiple output terminals of the timing control unit (5) are respectively connected to the enable terminals of each DC-DC converter in the DC-DC conversion unit (4) and are used to control each DC-DC converter to start up in a preset order.

2. The active phased array radar power supply according to claim 1, characterized in that, The input filtering unit (1) includes multiple parallel ceramic capacitors, Y capacitors and two cascaded common-mode inductors; The multiple parallel ceramic capacitors are connected between the positive terminal of the satellite's high-voltage primary bus and the power ground to bypass differential-mode noise current. The two-stage cascaded common-mode inductors are connected in series in the positive and negative paths of the satellite high-voltage primary bus. The input side of the two-stage cascaded common-mode inductors is connected to the positive and negative terminals of the satellite high-voltage primary bus. The output side of the two-stage cascaded common-mode inductors is connected to the voltage input terminal of the front-stage synchronous rectification Buck converter unit (2). The Y capacitor is connected between the power bus on the output side of the two cascaded common-mode inductors and the chassis ground, and is used to provide a common-mode noise discharge circuit.

3. The active phased array radar power supply according to claim 2, characterized in that, The PWM controller in the front-end synchronous rectification Buck converter unit (2) is a synchronous rectification buck controller. The gate drive module includes a first external independent gate drive submodule and a second external independent gate drive submodule. The half-bridge power MOSFET includes an upper power MOSFET and a lower power MOSFET. The synchronous rectification buck controller outputs two complementary PWM drive signals, which are respectively input to the input terminals of the first external independent gate drive submodule and the second external independent gate drive submodule; the output terminals of the first external independent gate drive submodule and the second external independent gate drive submodule respectively drive the upper power MOSFET and the lower power MOSFET. The drain of the upper power MOSFET is connected to the output terminal of the input filter unit (1). The source of the upper power MOSFET is connected to the drain of the lower power MOSFET to form a switching node. The switching node is connected to the input terminal of the power inductor. The source of the lower power MOSFET is connected to power ground. The output terminal of the power inductor is connected to the input terminal of the intermediate bus (3).

4. The active phased array radar power supply according to claim 1, characterized in that, The front-end synchronous rectifier Buck converter unit (2) also includes a voltage divider input over / under voltage protection circuit and a spread spectrum frequency modulation module; The voltage divider input over / under voltage protection circuit is composed of a resistor voltage divider network. The resistor voltage divider network samples the satellite high voltage primary bus voltage and outputs an enable control signal to the PWM controller. Hardware lockout protection is implemented when the satellite high voltage primary bus voltage is lower than the undervoltage threshold or higher than the overvoltage threshold. The spread spectrum frequency modulation module is located in the PWM controller and is used to periodically modulate the switching frequency, broaden the switching harmonic energy, and reduce the peak value of electromagnetic interference.

5. The active phased array radar power supply according to claim 1, characterized in that, The DC-DC converter unit (4) further includes a -5V output converter module, a 5.5V output converter module, and a 3.3V output converter module; The -5V output conversion module adopts an inverting synchronous buck-boost converter topology to convert the intermediate bus voltage into a -5V voltage output. The 5.5V output conversion module adopts a synchronous buck topology to step down the intermediate bus voltage to a 5.5V output voltage. The output link of the 5.5V output conversion module is configured with a multi-stage LC filter structure, which includes a first-stage power LC low-pass network and a second-stage high-frequency noise attenuation network. The second-stage high-frequency noise attenuation network is composed of ferrite beads and ceramic capacitors. The 3.3V output conversion module adopts a voltage-mode synchronous rectification buck topology to step down the intermediate bus voltage to a 3.3V output voltage.

6. The active phased array radar power supply according to claim 1, characterized in that, The four power phases of the four-phase interleaved parallel Buck converter module correspond to four PWM drive signals, and the phases of the four PWM drive signals are staggered by 90°.

7. The active phased array radar power supply according to claim 5, characterized in that, The timing control unit (5) includes a comparator, an optocoupler, and a resistor-capacitor network; The power supply terminal of the timing control unit (5) is connected to the output terminal of the high voltage linear regulator, and the input terminal of the high voltage linear regulator is connected to the satellite high voltage primary bus, which is used to convert the satellite high voltage primary bus voltage to 12V to power the comparator and the optocoupler.

8. The active phased array radar power supply according to claim 7, characterized in that, The timing control unit (5) samples the intermediate bus voltage as the basis for timing decision, and its preset order is as follows: When the intermediate bus voltage is established and reaches the undervoltage lockout threshold, the timing control unit (5) outputs a first enable signal to turn on the -5V output conversion module; After the -5V output conversion module establishes an output voltage, the timing control unit (5) outputs a second enable signal through the optocoupler to turn on the 5.5V output conversion module; When an external enable command is received, the timing control unit (5) outputs an external enable signal to turn on the four-phase interleaved parallel Buck converter module and the 3.3V output converter module respectively.

9. The active phased array radar power supply according to any one of claims 1-8, characterized in that, The input filter unit (1), the intermediate bus (3), the DC-DC converter unit (4), and the timing control unit (5) are soldered to the main power board; the half-bridge power MOSFET of the front-end synchronous rectification Buck converter unit (2) is soldered to an independent copper substrate; the independent copper substrate is stacked and arranged below the main power board, and the independent copper substrate is electrically connected to the main power board through terminals; the bottom surface of the copper substrate is bonded to the device housing through a thermally conductive medium.

10. The active phased array radar power supply according to claim 9, characterized in that, The inner layer of the main power board is covered with a continuous solid copper foil; the main power board is arranged with a dense array of vias. The main power board has an exposed copper cladding edge, which is pressed tightly against the equipment housing by a high thermal conductivity insulating pad. The device housing is provided with protrusions at the positions of each heating element. The height of each protrusion is adapted to the height of the heating element at the corresponding position. A thermally conductive pad is filled between each protrusion and the top surface of the heating element at the corresponding position. The gap between the heating element and the device housing is locally filled with thermally conductive potting.

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