Submodule capacitor voltage equalization method suitable for offshore wind power dc energy consumption device

Abstract

This invention relates to a method for equalizing the capacitor voltage of submodules in an offshore wind power DC power dissipation device, belonging to the field of power electronics technology. It solves the problem that existing technologies struggle to achieve effective equalization control of the capacitor voltage of HBSM-DCC submodules during fault ride-through. The method includes: performing two-stage submodule capacitor voltage equalization within each HBSM-DCC power dissipation control cycle; wherein: the first stage of submodule capacitor voltage equalization is coarse equalization, including input equalization and output equalization; the second stage of submodule capacitor voltage equalization is fine equalization, initiated after the output equalization phase is completed, including: acquiring the capacitor voltage of each submodule and sorting it from high to low; selecting the capacitor with the highest voltage based on the sorting result. x Each submodule is designated as a submodule to be bypassed; the submodule to be bypassed is periodically switched between bypass and insertion states, so that the remaining submodules remain in the insertion state and continue charging until the termination condition of fine-tuning equalization is met.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method for equalizing the voltage of submodule capacitors in offshore wind power DC energy consumption devices. Background Technology

[0002] As offshore wind power expands to large-scale, deep-sea applications, flexible high-voltage direct current (HVDC) transmission based on modular multilevel converters (MMCs) is a key technology for its reliable grid connection. Surplus power can easily trigger DC overvoltages, jeopardizing system stability; therefore, the transmitting system must possess fault ride-through (FRT) capability. Among existing methods for handling surplus power, adding DC power dissipation devices (DCCs) to discharge power is highly practical. DCC topologies vary; early centralized structures suffer from voltage imbalance and electrical surge problems, while modular topologies present challenges in submodule energy control. Half-Bridge Submodule (HBSM) DC power dissipation devices (HBSM-DCCs) are a reliable solution for fault ride-through of offshore wind power via flexible DC transmission systems and have already been applied in engineering projects.

[0003] However, the unidirectional nature of the energy-consuming current during HBSM-DCC operation makes it difficult to balance the capacitor voltages between submodules. Without effective control, some submodules may experience overvoltage, posing a potential damage risk. Under trapezoidal wave modulation, traditional submodule voltage balancing methods typically employ a strategy of "high voltage priority bypass and low voltage priority connection." While this strategy can alleviate voltage differences between submodules, its balancing capability is limited.

[0004] Specifically, HBSM-DCC often uses trapezoidal wave modulation. Because the switching actions of the switching SMs within the DCC arm are asynchronous and the energy-consuming current is unidirectional, the energy absorbed by each SM is uneven. To achieve voltage balance among SMs, a sorting-based switching strategy similar to MMC nearest-level modulation can be introduced. During the ramp section of the trapezoidal wave, the DCC submodule capacitors undergo a charging process regardless of whether they are in the energy-consuming phase or out. Since the energy-consuming current is large at the beginning of the out-of-energy-consuming phase, the charging energy gained by the submodule capacitors during this phase is significant. If reasonable submodule capacitor voltage balancing control is not implemented, some SMs may be at risk of overvoltage, endangering the safe and stable operation of the DCC. In existing research, HBSM-DCC generally adopts a "high-voltage priority bypass, low-voltage priority activation" strategy. This traditional method, based on the SM capacitor voltage sorting results, prioritizes bypassing SMs with higher capacitor voltages in the bridge arm when the DCC is gradually activated; and prioritizes activating SMs with lower capacitor voltages in the bridge arm when the DCC is gradually deactivated. However, due to the nonlinear variation of the energy-consuming current, the equal-interval switching operation between SMs is difficult to achieve a voltage equalization effect comparable to carrier phase-shift modulation. Especially during DCC deactivation, the SM capacitors continue to charge during the current decay period even when they are already charged, which may lead to some SMs facing a serious overvoltage risk.

[0005] Therefore, how to achieve effective balanced control of the capacitor voltage of the HBSM-DCC submodule during fault ride-through is a technical challenge that urgently needs to be overcome. Summary of the Invention

[0006] Based on the above analysis, the present invention aims to provide a method for equalizing the voltage of submodule capacitors in offshore wind power DC energy consumption devices, in order to solve the problem that existing technologies are unable to achieve effective equalization control of the voltage of HBSM-DCC submodule capacitors during fault ride-through.

[0007] This invention provides a method for equalizing the voltage of submodule capacitors in offshore wind power DC energy consumption devices, the method comprising: Two-stage submodule capacitor voltage balancing is performed within each HBSM-DCC power consumption control cycle; wherein: The first-level submodule capacitor voltage equalization is a coarse equalization, which includes equalization input and equalization output. The second-level submodule capacitor voltage balancing is a fine-tuning balancing process, which starts after the power consumption phase is completed, and includes: Obtain the capacitor voltage of each submodule and sort them from high to low; Based on the sorting results, select the capacitor with the highest voltage. x Each submodule is designated as a submodule to be bypassed, among which... x are positive integers and x ≤0.5 , This represents the total number of submodules. The bypass submodule is periodically switched between bypass and insertion states, while the remaining submodules remain in the insertion state and continue charging until the fine-tuning and equalization termination conditions are met.

[0008] Based on the above solution, the present invention also makes the following improvements: Furthermore, the step of periodically switching the bypass state and insertion state of the submodule to be bypassed includes: Generate a control signal for each submodule to be bypassed; Each of the control signals is logically ANDed with a square wave signal of fixed frequency and duty cycle of 0.5 to generate the corresponding lower switch drive signal of the submodule to be bypassed. Set the drive signal of the upper switch transistor of the corresponding bypass submodule to zero.

[0009] Furthermore, the activation condition for the fine-tuning equalization is that the following conditions are met simultaneously: The difference between the highest and lowest capacitor voltages in all submodules exceeds a preset threshold. The energy consumption current is greater than zero; The fine-tuning duration did not reach the preset time limit.

[0010] Furthermore, the fine-tuning equalization process terminates when one of the following conditions is met: The difference between the highest and lowest capacitor voltages in all submodules is reduced to within the allowable range; The fine-tuning equalization duration reaches the preset time limit; The energy-consuming current decays to zero.

[0011] Furthermore, the preset time upper limit is the same as the step time of the trapezoidal wave.

[0012] Furthermore, the input equilibrium includes: During the energy consumption phase, based on the sorting results of the capacitor voltages of all sub-modules in the bridge arm, the sub-modules are switched from the insertion state to the bypass state in order of capacitor voltage from high to low at equal time intervals.

[0013] Furthermore, the exit from equilibrium includes: During the exit energy consumption phase, based on the sorting results of the capacitor voltages of all sub-modules in the bridge arm, the sub-modules are switched from the bypass state to the insertion state in equal time intervals, according to the order of capacitor voltage from low to high.

[0014] Furthermore, the termination condition for the input equilibrium is exceeding the ramp time of the trapezoidal wave.

[0015] Furthermore, the termination condition for exiting equilibrium is exceeding the ramp time of the trapezoidal wave.

[0016] further, x = 2.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: This invention proposes a method for equalizing the voltage of submodule capacitors in offshore wind power DC power consumption devices. This method employs a two-stage submodule capacitor voltage equalization strategy, applicable to fault ride-through in offshore wind power flexible DC power transmission and grid connection systems, effectively improving the equalization effect of submodule capacitor voltages. Based on the traditional coarse-adjustment voltage equalization control (first stage), this two-stage strategy introduces fine-adjustment voltage equalization control (second stage). By fine-tuning the voltage of some submodule capacitors after the HBSM-DCC is completely decommissioned, a better equalization effect is achieved. This strategy effectively extends the equalization time window of the HBSM-DCC submodule capacitor voltage from the traditional trapezoidal slope range to the current decay period and even the hot standby stage, thereby improving the safety and reliability of HBSM-DCC operation.

[0018] This method, based on traditional strategies, introduces dynamic submodule capacitor voltage regulation during current decay. Based on the sorting results, it periodically bypasses submodules with higher capacitor voltages, temporarily raising the voltages of the remaining modules to achieve better balancing. Compared to traditional methods, this proposed method can further reduce submodule capacitor voltage deviations while having minimal impact on DC bus voltage and energy consumption current, ensuring the safe and reliable operation of the DC energy-consuming device.

[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Figure 1 A flowchart of a submodule capacitor voltage equalization method for offshore wind power DC energy consumption devices provided in an embodiment of the present invention; Figure 2 A flowchart illustrating another method for equalizing the voltage of submodule capacitors in an offshore wind power DC energy-consuming device, provided by an embodiment of the present invention; Figure 3This is a schematic diagram of a typical offshore wind power transmission system with DCC (Dynamic Control Center) connected to MMC-HVDC (Multi-Mechanical Control Center) at both ends. Figure 4 This is a topology diagram of HBSM-DCC; Figure 5 These are the key electrical waveforms of the DCC during the energy consumption process; Figure 6 These are the key electrical waveforms of DCC during the energy dissipation process; Figure 7 This is a traditional submodule capacitor voltage balancing strategy; Figure 8 This is the control logic for DCC two-stage SM capacitor voltage balancing described in this invention; Figure 9 This is the DCC fine-tuning voltage equalization control startup logic described in this invention; Figure 10 This is the control signal generation logic for the switching transistor under the DCC submodule described in this invention; Figure 11 The waveform of the capacitor in the DCC submodule under the traditional voltage balancing strategy; Figure 12 The DC voltage waveform under the traditional voltage equalization strategy; Figure 13 The waveform of DCC energy consumption current under the traditional voltage balancing strategy; Figure 14 The capacitor voltage waveform of the DCC submodule under a two-stage voltage balancing strategy; Figure 15 The DC voltage waveform under a two-stage voltage balancing strategy; Figure 16 The waveform of DCC energy consumption current under a two-stage voltage balancing strategy. Detailed Implementation

[0021] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0022] A specific embodiment of the present invention discloses a method for equalizing the capacitor voltage of submodules in an offshore wind power DC energy dissipation device. In this embodiment, each HBSM-DCC energy dissipation control cycle includes two levels of submodule capacitor voltage equalization. The first level of submodule capacitor voltage equalization is coarse equalization, which can be further divided into input equalization and output equalization, with each submodule performing stepwise actions at equal time intervals according to its voltage ranking. The second level of submodule capacitor voltage equalization is fine equalization, focusing on actively bypassing submodules with higher voltage to promote charging of submodules with lower voltage. The flowchart of this method is as follows: Figure 1 As shown.

[0023] Two-stage submodule capacitor voltage balancing is performed within each HBSM-DCC power consumption control cycle; wherein: The first-level submodule capacitor voltage equalization is a coarse equalization, which includes equalization input and equalization output. The second-level submodule capacitor voltage balancing is a fine-tuning balancing process, which starts after the power consumption phase is completed, and includes: Obtain the capacitor voltage of each submodule and sort them from high to low; Based on the sorting results, select the capacitor with the highest voltage. x Each submodule is designated as a submodule to be bypassed, among which... x are positive integers and x ≤0.5 , This represents the total number of submodules. The bypass submodule is periodically switched between bypass and insertion states, while the remaining submodules remain in the insertion state and continue charging until the fine-tuning and equalization termination conditions are met.

[0024] To better understand the complete execution process, the flowchart of this method can also be shown as follows: Figure 2 As shown.

[0025] Step S1: When the HBSM-DCC starts connecting the lumped resistor, the HBSM-DCC performs the first-stage submodule capacitor voltage balancing – connection balancing: based on the sorting result of the capacitor voltages of all submodules within the bridge arm, a stepped bypass is performed, and the submodule with the higher capacitor voltage is selected for priority bypass; the termination condition for connection balancing is exceeding the ramp time of the trapezoidal waveform. That is, connection balancing includes: in the energy consumption phase, based on the sorting result of the capacitor voltages of all submodules within the bridge arm, the submodules are switched from the insertion state to the bypass state sequentially in descending order of capacitor voltage at equal time intervals.

[0026] Step S2: When the HBSM-DCC begins to withdraw from the lumped resistor, the HBSM-DCC performs the first-stage submodule capacitor voltage equalization-exit equalization: Based on the sorting result of the capacitor voltages of all submodules within the bridge arm, they are inserted into the DC system in a stepped manner, with submodules having lower capacitor voltages being inserted first. The termination condition for exiting equalization is exceeding the ramp time of the trapezoidal waveform. In other words, exiting equalization includes: during the energy dissipation phase, based on the sorting result of the capacitor voltages of all submodules within the bridge arm, submodules are switched from bypass state to insertion state sequentially at equal time intervals, according to the capacitor voltage from low to high.

[0027] Step S3: After the HBSM-DCC completes the centralized resistor exit, the HBSM-DCC performs the second-level submodule capacitor voltage equalization as fine-tuning equalization: based on the capacitor voltage sorting results of each submodule, some submodules with relatively high capacitor voltages are bypassed; the end conditions for fine-tuning equalization are: the difference between the maximum and minimum capacitor voltages of the submodule reaches the requirement, or the equalization time exceeds the limit, or the energy consumption current decays to 0.

[0028] In this embodiment, the first-stage submodule capacitor voltage balancing adopts a traditional submodule capacitor voltage balancing strategy. First, the charging characteristics of the submodule capacitors under trapezoidal wave modulation are analyzed. A typical schematic diagram of an offshore wind power transmission system with DCC via two-terminal MMC-HVDC is shown below. Figure 3 As shown, the DCC is installed on the receiving-end converter side. The topology diagram of the HBSM-DCC is as follows. Figure 4 As shown. In Figure 4 middle, For energy-consuming resistors, To buffer the inductor, It is an SM capacitor. Indicates the first j The capacitor voltage of each SM, and the number of sub-modules (SM) is denoted as . ; , , These correspond to the DC bus voltage, the output voltage of the energy-consuming bridge arm (the voltage across the cascaded sub-modules), and the voltage of the energy-consuming resistor, respectively. The current is the energy-consuming current. The circuit relationship of the energy-consuming branch is shown in equation (1).

[0029] (1) Figure 5 , Figure 6 The key electrical waveforms of the HBSM-DC and HBSM-DCC during the connection and disconnection processes are shown under trapezoidal wave modulation. Under this modulation method, all SMs switch at equal time intervals. The modulation target is all submodules within the HBSM-DCC bridge arm. Under trapezoidal wave modulation, the submodules within the bridge arm undergo a stepped gradual bypass and insertion process. This process is a transient process in the operation of the HBSM-DCC. Connection process: The number of submodules connected to the DC system in the bridge arm decreases from the rated value to 0, corresponding to the bridge arm output voltage decreasing from its maximum value to 0. Disconnection process: The opposite of the connection process. The number of submodules connected to the DC system in the bridge arm increases from 0 to the rated value, corresponding to the bridge arm output voltage rising from 0 to its maximum value. However, due to the nonlinear change in energy consumption current, the charging energy of each SM varies. Especially during the disconnection process, the connected SM will experience a larger energy consumption current, resulting in a significantly higher charging energy than during the connection process. Without voltage equalization control, some SMs may be damaged due to overcharging.

[0030] In an MMC-HVDC system scenario, a single HBSM-DCC may contain hundreds of SMs. To achieve trapezoidal wave modulation, these SMs typically operate in groups. SMs within the same group perform switching operations simultaneously. This study assumes that the groups are naturally balanced (i.e., submodules within the same group bypass or are simultaneously inserted into the circuit without any time difference, resulting in identical charging and discharging, and zero voltage difference between submodules). However, due to different switching times between groups, the capacitor voltages of SMs in different groups vary, especially during the gradual decommissioning process. To simplify the analysis, an equivalent SM can be used to represent all SMs connected in series within the same group, and its voltage is the sum of the voltages of all SMs within the group.

[0031] The capacitor voltage equalization control of the SM (Submodule Module) relies on managing the charging and discharging processes between different SMs. Under trapezoidal wave modulation, capacitor charging in the SM mainly occurs during the rising edge, falling edge, and current decay period of the waveform. Since the energy dissipation current is unidirectional during energy dissipation, capacitor discharging in the SM can only occur passively after the DCC (Digital Control Center) is completely deactivated, i.e., it can only happen when the bridge arm voltage is greater than the DC bus voltage. Therefore, in traditional submodule capacitor voltage equalization strategies, the rising and falling edges of the trapezoidal wave are the critical regions for capacitor voltage equalization control.

[0032] like Figure 7 As shown, the SM switching logic used for voltage balancing is determined by the sorting result and the current operating state of the HBSM-DCC. During the energy consumption process, the energy consumption current gradually increases from zero, and the SMs in the bridge arm transition from a fully inserted state to a fully bypassed state. The upper switch of the half-bridge submodule is on and the lower switch is off, which is the submodule insertion state; the upper switch is off and the lower switch is on, which is the submodule bypass state. During this process, the SMs in the insertion state continue to charge, while the bypassed SMs maintain their voltage, such as... Figure 5 As shown. Therefore, during the energy consumption phase, the SM with the higher capacitor voltage is preferentially bypassed, while the SM with the lower capacitor voltage is bypassed last. During the energy consumption decommissioning process, the energy consumption current gradually decreases from its rated value, and the SM switches from a fully bypassed state back to a fully inserted state. During this process, the SM capacitor in the bypassed state maintains its voltage, while the SM capacitor in the inserted state is rapidly charged, such as... Figure 6 As shown. Therefore, during the energy-consuming phase, the SM with the lower capacitor voltage will be switched on first, while the SM with the higher capacitor voltage will be switched on last.

[0033] Traditional SM (Signal Module) equalization strategies can reduce voltage deviations between SMs. However, since the rise and fall of energy-consuming current are nonlinear processes, such as... Figure 5 and 6As shown, even with equally spaced switching, it is difficult to achieve good submodule capacitor voltage balancing. Especially when the HBSM-DCC exits the energy consumption process, if there is a large initial capacitor voltage difference between the SMs, this deviation may continue to widen over a long period during subsequent operation, posing a reliability risk to the SMs with higher capacitor voltages. To achieve better submodule capacitor voltage balancing, it is necessary to introduce fine-tuning voltage balancing control on top of the traditional coarse-tuning voltage balancing strategy.

[0034] The two-stage submodule capacitor voltage balancing strategy is explained below.

[0035] (1) Time interval for voltage equalization In existing technology, theoretically, SM capacitor voltage equalization can be divided into equalization during charging and equalization during discharging. For example... Figure 5 and 6 As shown, during the periodic switching operation of the HBSM-DCC, its internal SM voltage also exhibits periodic fluctuations: 1) During the energy consumption phase, the voltage of the SM capacitor rises slightly; 2) During the steady-state energy consumption stage, ignoring the influence of leakage current, the voltage of the SM capacitor remains basically constant; 3) Upon exiting the energy consumption phase, the voltage of the SM capacitor rises significantly; 4) After exiting the energy consumption state, the SM capacitor discharges to the external DC system, and its voltage drops rapidly to the DC bus voltage level. It is then clamped by the DC system until the next energy consumption cycle begins.

[0036] Since the discharge process of the HBSM-DCC depends on the voltage difference between the power-consuming arm and the external DC system, equalization during discharge requires the SM with the lowest bypass voltage. However, under this condition, the power-consuming arm voltage may be lower than the DC bus voltage, causing the discharge process to fail. Therefore, equalization control during discharge may cause the HBSM-DCC to lose its discharge capability. Hence, this invention focuses on analyzing and discussing equalization control during charging.

[0037] The charging of HBSM-DCC submodules mainly involves three phases: the energy consumption process, the energy consumption process, and the process where the energy consumption current decays to zero after decommissioning. This describes the charging phase, not the discharging phase. Figure 5 and Figure 6The current and submodule capacitor voltage waveforms will be clearer. The first two charging equalization time windows have already been applied in the traditional submodule capacitor voltage equalization strategy, but the fineness of the equalization is relatively low. The proposed two-stage submodule capacitor voltage equalization control adds fine-tuned voltage equalization control (second stage) to the traditional SM capacitor voltage equalization strategy (first stage). The core of the second-stage equalization control is to utilize the current decay range after the HBSM-DCC operation to bypass the SM with higher capacitor voltage, while allowing the SM with lower capacitor voltage to continue charging, thereby reducing the voltage deviation between SMs.

[0038] The control logic for the two-stage SM capacitor voltage balancing proposed in this embodiment is as follows: Figure 8 Place.

[0039] 1) First, following the traditional SM voltage balancing strategy, perform a complete HBSM-DCC operation (including power consumption input, steady-state power consumption, and power consumption decommissioning processes). During the HBSM-DCC power-on process, each submodule switches from the insertion state to the bypass state one by one at equal time intervals, with the submodule with the higher capacitor voltage bypassing first. During steady-state power consumption, the HBSM-DCC submodules remain in the bypass state. During the HBSM-DCC power-off process, each submodule switches from the bypass state to the bypass state one by one at equal time intervals, with the submodule with the lower capacitor voltage inserting first.

[0040] 2) After the HBSM-DCC exits the power dissipation state, fine-tuning capacitor voltage equalization control is immediately initiated based on the SM sorting results and the current DCC state. During fault ride-through, the HBSM-DCC typically operates in a periodic switching mode. The HBSM-DCC remains continuously engaged only when the surplus power is greater than or equal to the rated power dissipation. To minimize the impact of fine-tuning voltage equalization control on the subsequent capacitor discharge process of submodules, a fine-tuning equalization time constraint is set. T max Generally, the step time can be set to be the same as that of the trapezoidal wave. Setting it too short results in poor submodule equalization; setting it too long improves submodule equalization but consumes more discharge time. When the highest capacitor voltage of all SMs in the energy-consuming bridge arm ( U Cmax ) and minimum capacitor voltage ( U Cmin The pressure difference exceeds the set threshold. dU Cmax The HBSM-DCC power consumption current is greater than zero, and the equalization duration is... T b When the upper limit is not reached, a signal is triggered. Trig fine Set the position to activate fine-tuning voltage equalization control, such as... Figure 9 As shown.

[0041] 3) Once the fine-tuning voltage equalization control is activated ( Trig fine =1), higher voltage x One SM will periodically switch between bypass and insertion states, while the rest ( - x Each SM remains in the inserted state after exiting power consumption. To reduce the impact of fine-tuned voltage equalization control on external systems, the number of dynamic equalization submodules is... x It shouldn't be too big, that is x ≤0.5 To accelerate the equilibrium process, one can select... x =2, meaning the two SMs with higher capacitor voltages undergo dynamic balancing. The specific switching logic is as follows: Figure 10 As shown.

[0042] Preferably, the step of periodically switching the bypass and insertion states of the submodules to be bypassed includes: generating a control signal for each submodule to be bypassed; performing a logical AND operation between each control signal and a square wave signal with a fixed frequency and a duty cycle of 0.5 to generate a lower switch drive signal for the corresponding submodule to be bypassed; and setting the upper switch drive signal for the corresponding submodule to be bypassed to zero. That is, the control signal for each selected SM... Trig SMj A logical AND operation is performed with a square wave of fixed frequency and duty cycle of 0.5 to generate the lower MOSFET drive signal, while the upper MOSFET drive signals of each SM are set to zero. The fine-tuning voltage equalization logic is shown in Table 1.

[0043] Table 1. Fine-tuning voltage equalization logic table

[0044] 4) When the voltage equalization time window ends or the maximum capacitor voltage deviation between SMs enters the allowable range, the fine-tuning voltage equalization control terminates. Subsequently, the DCC enters a passive discharge state, waiting for the next energy dissipation operation command.

[0045] Based on the above, the start condition for fine-tuning equalization is that the following conditions are simultaneously met: the difference between the highest and lowest capacitor voltages in all submodules exceeds a preset threshold; the energy consumption current is greater than zero; and the fine-tuning equalization duration does not reach the preset time limit. The end condition for fine-tuning equalization is that one of the following conditions is met: the difference between the highest and lowest capacitor voltages in all submodules narrows to an allowable range; the fine-tuning equalization duration reaches the preset time limit; and the energy consumption current decays to zero. Preferably, the preset time limit is the same as the step time of the trapezoidal wave.

[0046] To verify the effectiveness of the proposed two-stage submodule capacitor voltage balancing control strategy, a switching model of an HBSM-type centralized DCC was established based on the MMC-HVDC transmission system. To improve simulation speed, the number of half-bridge submodules in the DCC arm was set to 4. The simulation system referenced the relevant electrical parameters of the Rudong offshore wind power project in China, and the specific system parameters are shown in Figure 2. The simulation assumed that the wind farm output power remained constant during fault ride, and the DCC adopted a DC voltage hysteresis-based control method, with the upper and lower hysteresis limits set to 1.05 pu and 0.9 pu, respectively. A fault scenario was set where a three-phase-to-ground short-circuit fault occurred in the onshore AC grid, and the AC voltage dropped to 0.2 pu, with a fault duration of 625 ms.

[0047] Table 2 Key Circuit Parameters of MMC-HVDC Offshore Wind Power System with DCC

[0048] Figures 11-13 The relevant electrical waveforms of DCC are shown when only the traditional SM capacitor voltage balancing strategy is used. During fault ride-through, the highest SM capacitor voltage reaches 1.172 pu. After power consumption is stopped, due to the lack of fine-tuned voltage balancing control, the capacitor voltage distribution of each SM is relatively dispersed, with the highest and lowest SM capacitor voltages being 1.025 pu and 0.985 pu, respectively. Figures 14-16 Simulation results are presented using the proposed two-stage submodule capacitor voltage balancing strategy. During fault ride-through, the highest capacitor voltage of SM is 1.162 pu. After power consumption is deactivated, thanks to the two-stage voltage balancing control, the deviation of capacitor voltages in each submodule is significantly reduced, with the highest and lowest capacitor voltages being 1.005 pu and 1 pu, respectively.

[0049] contrast Figure 11 and Figure 14 It is clearly evident that the proposed voltage balancing strategy effectively reduces the SM capacitor voltage deviation from 0.04 pu to 0.005 pu. This method has minimal impact on the DC bus voltage. Figure 12 and Figure 15 As shown, the peak DC bus voltage is 1.07 pu in both cases. The main difference lies in the waveform shape—the DC voltage continuously decays under the traditional method, while the DC voltage decays within the allowable fluctuation range under the proposed strategy.

[0050] In terms of energy consumption current, such as Figure 13 and Figure 16 As shown, the waveforms of the two methods are basically similar, with only a slight difference in decay time. The current decay time is 965 μs under conventional control, while it is 1.04 ms under the proposed method. This small difference has little impact on the SM voltage and DC bus voltage.

[0051] In summary, the proposed two-stage submodule capacitor voltage balancing strategy is effective in achieving capacitor voltage balancing among DCC submodules, while having minimal impact on DC bus voltage and energy consumption current.

[0052] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

[0053] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0054] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for equalizing the voltage of submodule capacitors in an offshore wind power DC energy-consuming device, characterized in that, The method includes: Two-stage submodule capacitor voltage balancing is performed within each HBSM-DCC power consumption control cycle; wherein: The first-level submodule capacitor voltage equalization is a coarse equalization, which includes equalization input and equalization output. The second-level submodule capacitor voltage balancing is a fine-tuning balancing process, which starts after the power consumption phase is completed, and includes: Obtain the capacitor voltage of each submodule and sort them from high to low; Based on the sorting results, select the capacitor with the highest voltage. x Each submodule is designated as a submodule to be bypassed, among which... x are positive integers and x ≤0.5 , This represents the total number of submodules. The bypass submodule is periodically switched between bypass and insertion states, while the remaining submodules remain in the insertion state and continue charging until the fine-tuning and equalization termination conditions are met.

2. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 1, characterized in that, The step of periodically switching the bypass and insertion states of the submodule to be bypassed includes: Generate a control signal for each submodule to be bypassed; Each of the control signals is logically ANDed with a square wave signal of fixed frequency and duty cycle of 0.5 to generate the corresponding lower switch drive signal of the submodule to be bypassed. Set the drive signal of the upper switch transistor of the corresponding bypass submodule to zero.

3. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 2, characterized in that, The activation condition for the fine-tuning equalization is that the following conditions are met simultaneously: The difference between the highest and lowest capacitor voltages in all submodules exceeds a preset threshold. The energy consumption current is greater than zero; The fine-tuning duration did not reach the preset time limit.

4. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 3, characterized in that, The fine-tuning equalization process terminates when one of the following conditions is met: The difference between the highest and lowest capacitor voltages in all submodules is reduced to within the allowable range; The fine-tuning equalization duration reaches the preset time limit; The energy-consuming current decays to zero.

5. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 4, characterized in that, The preset time limit is the same as the step time of the trapezoidal wave.

6. The method for equalizing the voltage of submodule capacitors in an offshore wind power DC energy-consuming device according to any one of claims 1-5, characterized in that, The input equilibrium includes: During the energy consumption phase, based on the sorting results of the capacitor voltages of all sub-modules in the bridge arm, the sub-modules are switched from the insertion state to the bypass state in order of capacitor voltage from high to low at equal time intervals.

7. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 6, characterized in that, The exit from equilibrium includes: During the exit energy consumption phase, based on the sorting results of the capacitor voltages of all sub-modules in the bridge arm, the sub-modules are switched from the bypass state to the insertion state in order of capacitor voltage from low to high at equal time intervals.

8. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 7, characterized in that, The termination condition for input equilibrium is exceeding the ramp time of the trapezoidal wave.

9. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 8, characterized in that, The termination condition for exiting equilibrium is exceeding the ramp time of the trapezoidal wave.

10. The method for equalizing the voltage of submodule capacitors in a DC power consumption device for offshore wind power according to claim 6, characterized in that, x = 2。

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