A switching timing optimization method for a three-phase half-bridge power tube

Abstract

The application relates to the technical fields of motor drive control and embedded software, and provides a switching time sequence optimization method for a three-phase half-bridge power tube. The method establishes a unified time sequence reference based on a PWM timer, obtains an operating state quantity associated with PWM switching edges and / or commutation time, determines a switching edge safety margin and a commutation time sequence deviation, dynamically corrects a dead time, a commutation time and a PWM synchronization relationship according to the above, forms a joint switching time sequence correction quantity, performs safety constraint projection on a candidate switching time sequence, and obtains a target switching time sequence; corresponding timing parameters are written into a PWM timer shadow register and are synchronized to take effect when an update event occurs, and correction parameters are updated according to the feedback of the operating state quantity after execution. Therefore, the switching safety of the power tube and the time sequence adaptability of the position sensorless six-step commutation can be improved.

Description

Technical Field

[0001] This invention relates to the fields of motor drive control and embedded software technology, and in particular to a method for optimizing the switching timing of three-phase half-bridge power transistors. Background Technology

[0002] With the widespread application of brushless DC motors in sensorless control, their low noise and high efficiency make them the preferred power component for low-cost applications such as water pumps, fans, and electric fans. A brushless DC motor drive system typically includes a DC bus, a three-phase half-bridge power circuit consisting of six power transistors, a gate drive circuit, a controller, and detection circuits for acquiring signals such as phase terminal voltage, phase current, and bus voltage. The controller controls the three-phase half-bridge power transistors to conduct alternately according to a six-step commutation logic to form a rotating magnetic field.

[0003] To prevent the upper and lower power transistors of the same bridge arm from conducting simultaneously, existing controllers typically insert a fixed dead time between the turn-off of one power transistor and the turn-on of the other complementary power transistor. Simultaneously, the controller determines the commutation time based on the zero-crossing of the back EMF or a preset commutation angle, and generates the switching pulses for the power transistors using PWM comparison values. However, the actual turn-off process of the power transistors is not the same as the moment the controller outputs the turn-off command. Power transistor turn-off delay, gate drive propagation delay, parasitic capacitance charging and discharging, freewheeling paths, and load current direction all alter the actual commutation time of the bridge arm. The fixed dead time may be too short under some operating conditions, leading to shoot-through risk, or too long under other operating conditions, causing output voltage drop, additional switching losses, and current waveform distortion.

[0004] Furthermore, in sensorless BLDC six-step commutation, back EMF detection is typically affected by PWM switching noise, sample-and-hold delay, digital filtering delay, interrupt response delay, and controller calculation delay. The commutation timing directly derived from the detected event may be earlier or later than the actually appropriate commutation timing. These delays and commutation errors will also change when motor speed, load current, bus voltage, and power device temperature vary.

[0005] Existing solutions often handle dead time, commutation advance angle, or PWM pulse width separately, lacking a mechanism for joint calculation and safety constraint processing of dead time, commutation time, and PWM cycle boundaries under the same hardware timer base. When the commutation event is close to the PWM cycle boundary, or when commutation time correction and PWM edge correction occur simultaneously, updating a single timing parameter may cause changes in the event sequence, insufficient effective pulse width, or disruption of the safety interval between upper and lower bridge power transistors in the same bridge arm. Therefore, a switching timing optimization method suitable for real-time execution by embedded controllers is needed. Without changing the basic hardware topology of the three-phase half-bridge, a unified timing coordinate system should be established using existing detection signals. The dead time, commutation time, and PWM synchronization relationship should be jointly corrected based on the power transistor switching state and the commutation state without position sensors. Safety constraints should be applied before writing to the PWM timer, thereby balancing power transistor safety, commutation accuracy, and PWM switching timing stability. Summary of the Invention

[0006] The main objective of this invention is to provide a method for optimizing the switching timing of a three-phase half-bridge power transistor, a controller, a motor drive device, a computer device, and a computer-readable storage medium. This invention aims to solve the technical problems in the prior art where fixed dead zones and fixed commutation timing cannot adapt to different operating conditions, resulting in insufficient power transistor switching safety and commutation timing deviations without position sensors.

[0007] To achieve the above objectives, this invention provides a method for optimizing the switching timing of three-phase half-bridge power transistors, applied to a six-step commutation drive system for a sensorless brushless DC motor, including a three-phase half-bridge drive circuit and a controller. Each phase arm of the three-phase half-bridge drive circuit includes an upper bridge power transistor and a lower bridge power transistor. The method for optimizing the switching timing of the three-phase half-bridge power transistors includes the following steps: establishing a unified timing reference based on the PWM timer of the controller, and determining the basic switching timing according to the current PWM control cycle, the current six-step commutation interval, and the duty cycle instruction. The basic switching timing includes at least the PWM switching edge, commutation time, and other parameters of each phase arm. The fundamental dead time between the upper and lower power transistors of one bridge arm; acquiring at least one operating state quantity, including phase terminal voltage or back EMF, phase current, DC bus voltage or bus current, power device temperature, and control link delay, within a sampling window associated with the PWM switching edge and / or the commutation time; determining a switching edge safety margin based on the operating state quantity and the power transistor switching command, and determining a commutation timing deviation based on at least one of the phase terminal voltage or back EMF, phase current change, line voltage integral, and phase tracking quantity; dynamically correcting the dead time of at least one bridge arm based on the switching edge safety margin, and based on the commutation... The timing deviation and the control link delay dynamically correct the commutation time, and determine the PWM synchronization correction amount based on the position of the corrected commutation time relative to the PWM period boundary in the unified timing reference, to form a joint switching timing correction vector including dead time correction, commutation time correction, and PWM synchronization correction. The joint switching timing correction vector is applied to the base switching timing to obtain candidate switching timings, and a safety constraint projection is performed on the candidate switching timings to ensure that the projected switching timings satisfy the following conditions: the upper and lower bridge power transistors in the same bridge arm are prohibited from overlapping conduction, the dead time is not lower than the safety lower limit, and the effective PWM pulse width is not lower than the minimum effective pulse width. At least one constraint is required to ensure that the pulse width and the commutation switching event sequence are not reversed, thereby obtaining the target switching timing. The timing parameters corresponding to the target switching timing are written into the shadow register of the PWM timer, and the timing parameters are synchronously written into the active register when a preset timer update event arrives, so that the three-phase half-bridge power transistors perform switching actions according to the target switching timing. The switching edge safety margin, the commutation timing deviation, and / or the switching timing correction parameters are updated according to the operating state quantity obtained after executing the target switching timing, so as to continue to optimize the switching timing of the three-phase half-bridge power transistors in subsequent PWM control cycles and / or six-step commutation intervals.

[0008] In this invention, the operating state quantities are obtained, that is, at least one of the following operating state quantities is obtained: phase terminal voltage or back electromotive force, phase current, DC bus voltage or bus current, power device temperature and control link delay.

[0009] In this invention, the operating state quantity is determined based on the operating state quantity and the power transistor switching command.

[0010] In this invention, the determination is based on the operating state quantity, that is, based on at least one of the phase terminal voltage or back electromotive force, phase current change, line voltage integral and phase tracking quantity.

[0011] Furthermore, to achieve the above objectives, the present invention also provides a switching timing optimization controller for a three-phase half-bridge power transistor. The three-phase half-bridge power transistor switching timing optimization controller includes: a timing reference module, used to establish a unified timing reference based on a PWM timer and generate a basic switching timing; a state acquisition module, used to acquire at least one operating state quantity among phase terminal voltage or back electromotive force, phase current, DC bus voltage or bus current, power device temperature, and control link delay within a sampling window associated with the PWM switching edge and / or commutation time; a timing state calculation module, used to determine the switching edge safety margin and commutation timing deviation based on the operating state quantities; and a joint timing correction module, used to determine the switching edge safety margin and commutation timing deviation based on the... The following modules are defined: a dead-time correction amount is determined based on the switch edge safety margin; a commutation timing correction amount is determined based on the commutation timing deviation and control link delay; and a PWM synchronization correction amount is determined based on the relationship between the corrected commutation timing and the PWM period boundary. A safety constraint module is used to perform safety constraint projection on the jointly corrected candidate switch timing to generate a target switch timing. A timing execution module is used to write the target switch timing into the PWM timer shadow register and synchronously copy it to the active register when a timer update event arrives. A feedback update module is used to update the switch edge safety margin, commutation timing deviation, and / or switch timing correction parameters based on the running state variables after executing the target switch timing.

[0012] Furthermore, to achieve the above objectives, the present invention also provides a motor drive device, which includes a three-phase half-bridge power circuit, a gate drive circuit, a detection circuit, and a switching timing optimization controller for the aforementioned three-phase half-bridge power transistors; wherein, the controller generates a target switching timing based on the operating state data collected by the detection circuit, and controls the three-phase half-bridge power circuit to operate according to the target switching timing through the gate drive circuit.

[0013] In addition, to achieve the above objectives, the present invention also provides a computer device, the computer device including a processor, a memory, and a switching timing optimization program stored in the memory and executable by the processor, wherein when the switching timing optimization program is executed by the processor, the steps of the three-phase half-bridge power transistor switching timing optimization method described above are implemented.

[0014] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a switching timing optimization program, wherein when the switching timing optimization program is executed by a processor, the steps of the three-phase half-bridge power transistor switching timing optimization method described above are implemented.

[0015] This invention provides a method for optimizing the switching timing of a three-phase half-bridge power transistor. The method establishes a unified timing reference based on a PWM timer, determines the safety margin of the switching edges and the commutation timing deviation under the same time base coordinate system, and jointly corrects the dead time, commutation time, and PWM cycle boundary synchronization relationship accordingly. After projecting safety constraints such as shoot-through prevention, minimum dead time, minimum effective pulse width, and event sequence onto candidate switching timings, the events are updated atomically through shadow registers and timers, and the correction parameters are updated based on the execution feedback closed loop. Through this method, this invention jointly solves the coupling problem between the three timing quantities—dead time, commutation, and PWM synchronization—under a unified hardware time base. While ensuring the switching safety of the power transistor, it improves the adaptability of the sensorless commutation timing, solving the technical problem that fixed dead time and fixed commutation timing cannot adapt to different operating conditions in existing technologies.

[0016] Under the example operating conditions of 24V DC bus, 3000r / min, and 20kHz center-aligned PWM, compared with the control method using a fixed safety dead zone of 0.90μs, the average dead time during steady-state operation can be reduced from approximately 0.90μs to approximately 0.68μs, a reduction of approximately 0.22μs. Correspondingly, the effective duty cycle loss caused by the dead zone is reduced from approximately 3.60% to approximately 2.72%, a relative reduction of approximately 24%. Power device switching and freewheeling related losses can be reduced by approximately 6.5%. Simultaneously, the peak deviation of commutation time can be reduced from approximately ±20μs to approximately ±5μs, and the corresponding electrical angle error at 3000r / min is reduced from approximately ±1.44° to approximately ±0.36°. After PWM synchronization correction, the peak-to-peak voltage disturbance within the effective sampling window of the floating phase can be reduced from about 1.20V to about 0.45V, and the jitter at the zero-crossing detection time of the back EMF can be reduced from about 6.0μs to about 2.2μs, thereby improving the stability of sensorless commutation detection. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the three-phase half-bridge power transistor switching timing optimization system structure in this invention.

[0018] Figure 2 This is a block diagram and example parameter diagram of the 24V sensorless BLDC centrifugal water pump system in this invention.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The following detailed embodiments are used to illustrate the technical concept, implementation method, and achievable technical effects of the present invention, and are not intended to limit the scope of protection of the present invention. Equivalent substitutions or modifications made by those skilled in the art to the sampling method, controller type, parameter threshold, filtering algorithm, mapping table dimension, PWM frequency, power device type, and protection strategy without departing from the core technical concept of the present invention should all fall within the scope of protection of the present invention.

[0021] Unless otherwise stated, the time parameters, thresholds, gains, count values, filter coefficients, mapping relationships, and protection conditions mentioned below can be calibrated offline and / or updated online based on the power device model, gate drive capability, bus voltage, motor parameters, PWM frequency, controller timer resolution, detection link bandwidth, load characteristics, and thermal status.

[0022] This invention provides a method for optimizing the switching timing of three-phase half-bridge power transistors. This method can be implemented in microcontrollers, digital signal processors, field-programmable gate arrays, dedicated motor control chips, or other control devices with PWM timers, ADC interfaces, comparator interfaces, memory, and interrupt control units. The method is particularly suitable for six-step commutation drive systems of sensorless brushless DC motors, but is not limited to this; it can also be used in fans, pumps, compressors, blowers, fan lights, air circulation equipment, and other motor drive devices employing three-phase half-bridge power circuits.

[0023] I. System Architecture and Unified Timing Reference

[0024] Reference Figure 1 The motor drive system includes at least a three-phase half-bridge power circuit, a gate drive circuit, a detection circuit, and a controller. The three-phase half-bridge power circuit includes phase A, phase B, and phase C arms. Each phase arm includes an upper-bridge power transistor and a lower-bridge power transistor. The upper-bridge power transistors for phase A, phase B, and phase C are denoted as U... a U β And Uc; the A-phase lower bridge power transistor, the B-phase lower bridge power transistor, and the C-phase lower bridge power transistor are respectively denoted as L. a L β and L c The power transistor can be a MOSFET, IGBT, gallium nitride device, silicon carbide device, or other controllable semiconductor switching device.

[0025] The detection circuit is used to acquire at least one of the following operating state quantities: phase terminal voltages of phases A, B, and C; floating back electromotive force or phase terminal voltage processing results; phase current, bus current, or phase current estimated based on switch states; DC bus voltage; power device temperature and / or gate driver temperature; PWM switching edge timing, comparator toggle timing, ADC sampling timing; motor speed, electrical angular velocity, electrical angular period, or phase tracker output; and switching timing correction amount from the previous PWM control cycle. The controller establishes a unified physical time axis using a PWM timer. Let the PWM control cycle be T. p The minimum time resolution of the timer is T. q Let k be the kth PWM control cycle, and s be the current six-step commutation interval, where: All time values ​​to be written to the PWM timer, commutator comparator, or event trigger unit are preferably converted into timer count values. For any time value t, its corresponding timer count value N(t) can be obtained according to the following formula: Here, "round" indicates rounding to the nearest integer. In other implementations, rounding up, rounding down, or error-compensated quantization methods can also be used to ensure that safety constraints such as minimum dead zone and minimum event interval are not weakened by quantization.

[0026] For center-aligned PWM, the controller preferably maps the comparison values ​​of the upper and lower timer segments to the same physical time axis before performing dead-time calculation, commutation calculation, PWM edge adjustment, and safety constraint projection. This avoids event sequencing errors caused by the same comparison count value corresponding to different physical times under different counting directions.

[0027] II. Establishment of the Basic Event Table

[0028] In the sensorless BLDC six-step commutation mode, each commutation interval typically includes a high-side conducting phase, a low-side conducting phase, and a floating phase. The high-side conducting phase can be PWM modulated, the low-side conducting phase can be continuously conducting or PWM modulated synchronously, and the floating phase is used for back EMF detection, terminal voltage detection, or other commutation state observation. The controller generates a basic event table E0(k) based on the current PWM control period k, commutation interval s, duty cycle command D(k), and a preset six-step conduction table. The basic event table includes at least: the planned turn-on and planned turn-off times of the upper bridge power transistors of each bridge arm; the planned turn-on and planned turn-off times of the lower bridge power transistors of each bridge arm; the basic commutation time; the basic dead time; PWM edge events; the ADC sampling window or comparator valid window; the event priority, the PWM period number, and the commutation interval number.

[0029] The basic event table can be represented as: .in: For bridge arm The corresponding basic planned turn-on time of the power transistor; For bridge arm The corresponding power transistor's basic planned turn-off time; The basic commutation moment; Basic dead time; Used to identify bridge arm status, power transistor status, or event type; The basic event table is not the event table that is ultimately written into the PWM timer, but rather a unified benchmark for subsequent execution dead-time dynamic correction, commutation time correction, PWM synchronization correction, and safety constraint projection.

[0030] III. Acquisition of Operating Status Quantities and Data Preprocessing

[0031] The controller triggers ADC sampling within a sampling window associated with the PWM switching edge and / or commutation moment, or reads the outputs of the comparator, capture unit, phase tracker, and current sensing unit. The operating state vector z(k) can be represented as: in: , , These are the phase currents of phases A, B, and C, respectively. , , These are the phase terminal voltages or back electromotive forces of phases A, B, and C, respectively. This is the DC bus voltage; This refers to the DC bus current. For power device temperature; This refers to the gate driver temperature. Electric angular velocity; To control link latency; This represents the combined switching timing correction amount that has been executed or is yet to be executed in the previous PWM control cycle. For systems without independent three-phase current sampling capabilities, bus current, single-resistor shunt current, dual-resistor shunt current, or phase current estimated based on phase terminal voltage and PWM switching state can be used as substitutes. To reduce the impact of PWM switching spikes, parasitic ringing, ADC sampling jitter, and comparator false triggering, the sampling results are preferably subjected to the following sequential steps: physical range limiting; abnormal sample removal; median filtering, average filtering, or low-pass filtering; association and storage with the current bridge arm state, PWM cycle number, and commutation interval number; and validity marking.

[0032] The shielding time t after the power transistor switching event occurs blankWithin this system, the floating phase voltage is not used for back EMF zero-crossing detection. After the shielding time ends, back EMF characteristics or line voltage integral characteristics are extracted only within the phase voltage stabilization sampling window. This prevents PWM spikes, freewheeling switching fluctuations, and parasitic ringing from being mistakenly identified as back EMF zero-crossing events.

[0033] IV. Determining the Safety Margin at the Switch Edge

[0034] When complementary commutation occurs in bridge arm x, for example, when the upper bridge power transistor is turned off and the lower bridge power transistor is turned on, or when the lower bridge power transistor is turned off and the upper bridge power transistor is turned on, the controller records the time of the turn-off command of the first power transistor to be turned off. After the controller outputs the shutdown command, it determines the actual shutdown completion time by detecting phase terminal voltage, phase current, drain-source voltage, bridge arm midpoint voltage, or other quantities that can reflect the power transistor's shutdown state. In one implementation, the earliest time when the following conditions are met is determined as the turn-off completion time: the phase terminal voltage enters a preset stable range; the absolute value of the phase terminal voltage change rate is less than a stable threshold; the phase current commutation slope meets a preset termination condition; the bridge arm midpoint voltage reaches a preset threshold; the source voltage or collector-emitter voltage reaches a threshold corresponding to turn-off completion; and the comparator output remains stable for a preset time. First, the original turn-off interval between the actual turn-off completion and the planned turn-on of the complementary power transistor is calculated. : .in, This refers to the planned turn-on time of the complementary power transistor in this bridge arm.

[0035] After deducting additional safety margin To obtain an effective safety margin : Among them, additional safety margin It is used to cover uncertainties such as ADC sampling error, comparator / propagation error, timer quantization error, gate drive propagation time fluctuation, device parameter discreteness, temperature variation, and parasitic parameter fluctuation. When, it indicates that there is still a safety margin between the planned turn-on time of the complementary power transistor and the actual turn-off time of the first power transistor; when When the current candidate timing sequence fails to reliably detect an insufficient safety interval, an increased risk of bridge arm pass-through, or an insufficient dead zone, it indicates a risk. At that time, the turn-off delay can be estimated based on the pre-defined turn-off delay mapping relationship: .in: For turn-off delay mapping tables, fitting functions, or lookup interpolation models; This represents the absolute value of the corresponding phase current; This is the DC bus voltage; For power device temperature; Let x be the commutation direction of bridge arm. The estimated turn-off completion time can be expressed as: .in, This is an estimate of the gate drive propagation delay. To suppress frequent dead-time jumps caused by single-measurement noise, the effective safety margin is filtered. .in, For safety margin filter coefficients, the following must be satisfied: .

[0036] V. Direction-dependent dynamic dead zone correction

[0037] Because the lower bridge power transistor turns on after the upper bridge power transistor turns off, and the upper bridge power transistor turns on after the lower bridge power transistor turns off, there are different gate discharge paths, parasitic capacitance charging and discharging processes, freewheeling paths, body diode conduction states, and current direction effects. Therefore, this invention determines the dynamic dead time for the two commutation directions of the same bridge arm separately. For the commutation direction of bridge arm x from the upper bridge power transistor to the lower bridge power transistor, its dynamic dead time is... It can be represented as: .

[0038] For bridge arm x, the direction of commutation from the lower bridge power transistor to the upper bridge power transistor, its dynamic dead time It can be represented as: .in: Basic dead time; For the target effective safety margin; This is a correction factor for the direction of the upper bridge power transistor from turn-off to turn-on of the lower bridge power transistor; This is a correction factor for the direction from the turn-off of the lower bridge power transistor to the turn-on of the upper bridge power transistor; Minimum safe dead time; Maximum allowable dead time; This indicates that the input value is restricted to a specified range. When the effective safety margin after filtering is less than the target safety margin, i.e.: The controller increases the dynamic dead time in the corresponding direction; when the effective safety margin after filtering is greater than the target safety margin, and the stability condition is met for multiple consecutive PWM control cycles, the controller allows the dead time to be gradually reduced at a preset rate to reduce unnecessary freewheeling losses and output voltage drops. To prevent sudden changes in the dead time within a single cycle, it is preferable to limit its variation: .in, This represents the maximum change in dead time over a single cycle. When the absolute value of the phase current is below the zero current threshold... When a change in phase current direction is detected, it is not advisable to switch the dead-time correction direction solely based on a single sampling result. Continuous switching is preferred. The corresponding dead-time correction direction is switched only after all sampling periods have met the same current direction determination condition. During periods when the current direction is unstable, a preset safety dead time is used. e.

[0039] VI. Commutation Timing Deviation Detection and Control Link Delay Compensation

[0040] For the current six-step commutation interval, the controller first determines the floating phase and extracts at least one commutation observation feature within the effective detection window after the PWM shielding time ends. The commutation observation feature may include: the moment when the floating phase's back electromotive force crosses zero. The moment when the integral of the floating phase voltage or line voltage reaches the target threshold. The moment when the decreasing slope of the outflow phase current and the increasing slope of the inflow phase current reach equilibrium. The predicted timing output of a phase tracker, phase-locked loop, or observer. The feedback time corresponding to the current ripple, torque fluctuation, or speed fluctuation after commutation. When multiple observations are used, the deviation of each observation relative to its respective reference time can be converted into a unified time error, forming a weighted observation error: .in: Furthermore, all weights are greater than or equal to zero. If an observation is invalid, its corresponding weight can be reset to zero, and the weights of the remaining valid observations can be renormalized. Control link delay includes the delays of sampling, filtering, zero-crossing detection, interrupt response, timing calculation, PWM register update, and gate drive propagation, which can be expressed as: In this context, any non-existent delay element corresponds to a value of zero. If compensation is required based on electrical angles, the electrical angle corresponding to the control link delay can be expressed as: .in, Electric angular velocity. Fundamental commutation time. The basic offset corresponding to the observation reference time and the six-step commutation rule Determined. For example, for a six-step commutation control system that uses the zero-crossing of the back EMF as the observation reference, the ideal commutation point can be located after the zero-crossing point of the back EMF. The electric angle position corresponds to the time offset. The online commutation timing correction can be expressed as: .in: This is the commutation error correction coefficient; This is the maximum allowable advance correction amount; This is the maximum permissible hysteresis correction. The target commutation time is: By using the base offset With online correction amount Separate processing can avoid the inherent problems of the six-step commutation. The electrical angle reference offset is incorrectly included in the online correction limiting range, thereby improving the consistency of commutation calculation under different speed conditions. When the quality of the floating back electromotive force is insufficient, the effective sampling window is covered by PWM events, the observed features fail continuously, or the motor is in the startup phase, the controller can maintain the previous effective commutation correction amount, call the preset commutation parameter mapping table, or switch to the safe commutation timing.

[0041] VII. PWM Synchronization Correction and Commutation Edge Fine-tuning

[0042] To reduce sampling disturbances, switching stress fluctuations, and commutation instability caused by the random phase relationship between commutation events and PWM edges, this invention further optimizes the synchronization between the relative positions of commutation events and PWM cycle boundaries. Target commutation time. Minimum time distance between the nearest PWM cycle boundary It can be represented as: Where n is an integer. When: .in, To preset the PWM synchronization window, the controller will move the commutation switch event to the nearest PWM cycle boundary, or to a point with a preset phase offset relative to that PWM cycle boundary. The position. When: The controller does not force a large jump in the commutation event within the current PWM cycle. Instead, it retains the timing comparison commutation event within the current cycle and gradually corrects the PWM time base phase over subsequent PWM control cycles. Let the remaining phase error be... The remaining number of correction cycles is Then the synchronization correction amount for the j-th PWM cycle can be expressed as: .in, This is the maximum synchronization correction allowed per single PWM cycle. The remaining error after synchronization correction is updated as follows: For center-aligned PWM, the rising and falling edges of the same PWM pulse can be moved synchronously to shift the center of the PWM pulse while keeping the target effective pulse width unchanged or substantially unchanged. For edge-aligned PWM, it is preferable to adjust the edges that have less impact on the target effective pulse width; if the pulse width cannot be maintained, subsequent safety constraint projections should prioritize ensuring the minimum effective pulse width and the minimum dead time.

[0043] During commutation, the controller can also calculate the duration T of the drop in the outflow phase current. out and the duration of the rise of the inflow phase current T in .when: .in, To achieve the commutation balance threshold, the controller can apply fine-tuning to at least one PWM edge associated with the commutation process to reduce the imbalance between the decay of the outflow phase current and the establishment of the inflow phase current. This PWM edge fine-tuning cannot bypass the dead-time constraint or be written separately to the PWM activity register; instead, it must be included in the joint switching timing correction process along with dead-time correction, commutation timing correction, and PWM synchronization correction.

[0044] VIII. Joint Switching Timing Correction Vector and Candidate Event Table

[0045] This invention unifies dead-time correction, commutation timing correction, PWM synchronization correction, and optional commutation edge fine-tuning into a unified switching timing correction vector u(k). In one embodiment, the unified switching timing correction vector can be expressed as: .in: This is the dead-time correction amount when bridge arm x switches from the upper bridge power transistor to the lower bridge power transistor. This is the dead-time correction amount when bridge arm x switches from the lower bridge power transistor to the upper bridge power transistor. Online correction amount at commutation time; This is the PWM synchronization correction amount; This is the fine-tuning amount at the commutation edge.

[0046] The controller maps the joint switching timing correction vector to the basic event table based on the current bridge arm state, the six-step commutation interval, the PWM counting method, the power transistor conduction direction, and the event priority, thus forming a candidate event table: Wherein, F[ ] represents the event mapping rule, which is not a regular vector addition. The event mapping rule includes at least: determining the high-side PWM phase, low-side conduction phase, and floating phase in the current commutation interval; determining the power transistors that are turned off first and turned on later in each bridge arm; selecting the corresponding dynamic dead time according to the commutation direction; mapping the commutation time correction amount to the conduction and turn-off events of the relevant bridge arm; mapping the PWM synchronization correction amount to the PWM period boundary, PWM pulse center, or specified comparison event; mapping the commutation edge fine-tuning amount to the PWM edge related to the outflow or inflow phase; and performing timer counting quantization on all candidate event times.

[0047] IX. Safety Constraint Projection

[0048] After the candidate event table is formed, the controller does not directly write it into the PWM timer. Instead, it first performs safety constraint checks and projection corrections on the candidate event table. (Safety constraint set) At a minimum, this includes: the upper and lower power transistors of the same bridge arm must not overlap in conduction; the actual dead time must not be less than the minimum safe dead time. The effective pulse width of PWM must not be less than the minimum effective pulse width. The time interval between adjacent switching events must not be less than the minimum event interval. Commutation events, PWM edge events, dead-time end events, and sampling window events must not be in disallowed reverse order; all event times must meet the PWM timer's counting resolution; event updates must meet the shadow register update deadline requirements; preset overcurrent, overvoltage, undervoltage, temperature protection, and fault shutdown strategies must not be violated. The target event table can be represented as follows: .in, This indicates projecting the candidate event table onto the set of security constraints. The internal operation should prevent overlapping conduction of power transistors on the same bridge arm; meet the minimum safe dead time; meet the minimum effective PWM pulse width; maintain the sequence of events such as turn-off, dead time end, turn-on, and sampling; maintain the optimized commutation timing results; maintain the optimized PWM synchronization results; and maintain the fine-tuning results of commutation edges. For example, when candidate timing causes overlapping conduction intervals of power transistors on the upper and lower bridges, the later turn-on event should be postponed first, or the earlier turn-off event should be brought forward, but the overlap should not be eliminated by compressing the minimum safe dead time.

[0049] When the effective PWM pulse width is less than wmin, excessively narrow PWM pulses can be canceled, adjacent events can be merged, low-priority edges can be moved to the next allowed counting position, or a preset safe PWM strategy can be adopted. When a commutation event enters an unacceptable dead-time interval, sampling masking interval, or event protection interval, the controller moves the commutation event to the nearest allowed event position and recalculates or limits the PWM synchronization correction amount. After completing the first quantization and projection, it is preferable to perform a full safety constraint check again to avoid new dead-time insufficiency, event reversal, or pulse width insufficiency caused by time quantization. By unifying dead-time correction, commutation timing correction, and PWM synchronization correction into the same event table and performing safety constraint projection, the mutual interference problems that occur when modifying the dead-time, commutation angle, or PWM comparison value separately in the prior art can be avoided. This unified processing method can take into account the power transistor switching safety, commutation accuracy, and PWM timing stability under different operating conditions.

[0050] 10. Shadow Register Synchronization Update and Consistency Verification

[0051] The controller will project the target event table E after security. t (k) is converted into PWM compare value, dead-time register configuration value, commutation event compare value, and related control flags, and written to the corresponding shadow register. Timing update record R t (k) can be represented as: Where: k is the PWM cycle number corresponding to the target event table; CRC is the checksum; and valid is the timing update validity flag. When the preset PWM timer update event arrives, the target timing in the shadow register is copied to the active register only if the cycle number matches, the checksum is correct, the valid flag is valid, and no fault protection is triggered. Therefore, the PWM comparison value, dynamic dead-time configuration value, and commutation event value of the three-phase bridge arm take effect in the same update boundary atom, avoiding inconsistencies in timing caused by updating only some bridge arms, some dead-time parameters, or some comparison values ​​within the same PWM cycle. If the controller fails to complete the timing calculation before the update deadline, or if cycle number mismatch, check failure, sampling abnormality, or protection triggering occurs, the previous valid target event table is maintained, or the system switches to the preset safety event table.

[0052] XI. Closed-loop feedback update and parameter mapping

[0053] After the target switching sequence is executed, the controller continues to collect operating status quantities such as phase terminal voltage, phase current, bus voltage, temperature, and current fluctuations after commutation, and generates dead zone feedback error and commutation feedback error.

[0054] Dead zone feedback error It can be composed of at least one of the following quantities: the deviation between the phase-terminal voltage transition time and the target transition time; the freewheeling duration; the bridge arm voltage response during bridge switching; the commutation current spike; the phase current rate of change; the power device temperature change; and the estimated switching loss. Commutation feedback error. It can be composed of at least one of the following quantities: back EMF zero-crossing deviation; line voltage integral error; the difference between the slope of the outflow phase current and the slope of the inflow phase current; current fluctuations within multiple PWM cycles after commutation; speed fluctuations; torque pulsation estimation; phase tracking error.

[0055] Dead zone correction parameters The update method can be represented as: Commutation correction parameters The update method can be represented as: .in: Update the gain for the dead zone parameters; The gain is updated for commutation parameters; LPF represents low-pass filtering, moving average, or other smoothing processing; , , represents the allowable range for dead zone parameters; , The allowable range for commutation parameters is defined. It is preferable to limit the maximum change in parameters within a single PWM control cycle to reduce the risk of control oscillations caused by detection noise, load abrupt changes, or abnormal sampling. Updated parameters can be mapped using at least two dimensions: motor speed range, phase current range, bus voltage range, power device temperature range, and six-step commutation interval. For example, a four-dimensional mapping table of speed × phase current × power device temperature × commutation interval can be used. During operation, the controller reads the nearest calibration points corresponding to the current operating condition and obtains the initial dead-zone correction parameters and initial commutation correction parameters through linear interpolation, piecewise fitting, or table lookup, then superimposes the online incremental correction. This method can utilize offline calibration results and adapt to device aging, temperature changes, load changes, and bus voltage fluctuations.

[0056] 12. Abnormal Degradation and Dynamic Optimization Recovery

[0057] The controller sets dynamic timing optimization enable conditions and abnormal degradation conditions. When at least one of the following conditions is met, all or part of the dynamic timing optimization is stopped, and the system switches to the safety event table:

[0058] The following are examples of errors that may occur: failure to obtain valid phase terminal voltage, back electromotive force, or phase current sampling values ​​after a preset number of consecutive attempts; dynamic dead zone calculation value exceeding the preset safety range; commutation timing deviation exceeding the maximum allowable deviation; bus overvoltage, undervoltage, or abnormal voltage fluctuation; phase current exceeding the overcurrent protection threshold; power device temperature or driver temperature exceeding the temperature threshold; motor in start-up, reverse rotation, stall, stall, or abnormal acceleration state; PWM timer, ADC, comparator, or memory malfunction; timing optimization algorithm not completed before the PWM shadow register update deadline; target event table failing safety constraint verification or CRC verification.

[0059] The security incident log should include at least: fixed security dead zones. The system includes: preset commutation advance angle or preset commutation time; fixed PWM synchronization rules; prohibition of generating PWM pulses smaller than the minimum effective pulse width; preset maximum duty cycle or derating operation strategy; and maintaining the previous effective event table or entering protection shutdown state. After the abnormal state is cleared, the controller does not immediately restore all dynamic optimizations. Instead, it prioritizes requiring a preset number of consecutive PWM control cycles to meet the recovery conditions before gradually restoring dynamic dead-zone correction, commutation correction, and PWM synchronization correction according to a preset slope. During the recovery phase, safety constraint projection and single-cycle rate of change limits are still applied.

[0060] XIII. Application Example: 24V Sensorless BLDC Centrifugal Water Pump

[0061] like Figure 2As shown, the following description uses a 24V sensorless BLDC centrifugal water pump as an example to further illustrate the switching timing optimization method of the present invention. The following values ​​are merely exemplary calibration values ​​and do not constitute a limitation on the scope of protection.

[0062] (a) Hardware and control parameters

[0063] Table 1 Parameters

[0064] Application objects 24V DC powered centrifugal water pump Motor type Three-phase sensorless BLDC, six-step commutation Rated power (unit: W) 60.0 Extreme logarithm 4 Rated mechanical speed (unit: r / min) 3000 DC bus nominal voltage (unit: V) 24.0 Allowable bus voltage range (unit: V) 18 to 30 Normal range of phase current (unit: A) 0 to 3.5 Overcurrent protection threshold (unit: A) 5.0 Optimized temperature range for power devices (unit: °C) -20 to 100 Over-temperature degradation threshold (unit: °C) 105 PWM method Center-aligned PWM PWM frequency (unit: kHz) 20 <![CDATA[PWM period T p (Unit: μs)]]> 50 PWM timer clock (unit: MHz) 100 <![CDATA[Timer time resolution T q (Unit: ns)]]> 10 ADC sampling rate (unit: MS / s) 2 <![CDATA[basic dead zone d0 (unit: ns)]]> 600 <![CDATA[Minimum safe dead time d min (Unit: ns)]]> 300 <![CDATA[Maximum allowable dead time d max (Unit: ns)]]> 1500 <![CDATA[Safe dead zone d near zero current safe (Unit: ns)]]> 900 <![CDATA[Minimum effective pulse width w min (Unit: μs)]]> 2.0 <![CDATA[Minimum event interval g min (unit: μs)]]> 0.50 <![CDATA[PWM synchronization window W s (Unit: μs)]]> 2.0 <![CDATA[Maximum single-cycle synchronization correction amount r max (Unit: μs)]]> 0.25 <![CDATA[Masking time after PWM switching t blank (Unit: μs)]]> 2.5

[0065] As shown in Table 1, under the conditions of 3000 r / min and 4 pole pairs, the electrical angular frequency is approximately 200 Hz, and the electrical angular period is approximately 5 ms. A 60° electrical angular commutation interval is approximately 833.3 μs, which includes approximately 16 to 17 PWM control cycles.

[0066] (ii) Generation of basic event table

[0067] The controller configures the PWM timer to a 100MHz center-aligned counting mode. Since the timer resolution is 10ns, the following timer counts are calculated: a 600ns basic dead zone corresponds to 60 timer counts; a 300ns minimum safe dead zone corresponds to 30 timer counts; a 2.0μs minimum effective pulse width corresponds to 200 timer counts; and a 2.0μs synchronization window corresponds to 200 timer counts. Let the current PWM control period be k, the current six-step commutation interval be s=2, and the duty cycle instruction be 62%. The PWM period is 50μs, therefore the target effective on-time is 31.0μs. The controller determines the current high-side PWM phase, low-side continuously on phase, and floating phase based on the six-step on-time table and generates a basic event table E0(k). Each on-event, off-event, commutation event, dead-time event, and sampling window event is converted into a 10ns resolution timer count value.

[0068] (III) State sampling and validity determination

[0069] A 2.5μs shielding time is set after each PWM switching edge. After shielding, four ADC samples are continuously acquired within the floating phase stabilization window, with an interval of 0.5μs between adjacent samples. The controller performs median removal on the four samples and takes the average value as the floating phase terminal voltage for that window. The phase current is sampled once in the middle of the PWM cycle and once before and after the commutation event. The bus voltage is updated every four PWM cycles, and the power device temperature is updated every 10ms. In this embodiment, the effective range of the phase terminal voltage is set to -1V to 31V, and the effective range of the phase current is set to -5.5A to 5.5A. Sampled values ​​outside the physical range are directly marked as invalid. A first-order low-pass filter is applied to the valid samples, with a voltage filter coefficient of 0.70 and a current filter coefficient of 0.60. If no valid floating phase voltage is obtained for three consecutive sampling windows, the back EMF observation is marked as invalid, and the dynamic commutation correction based on the zero crossing of the back EMF is reduced or stopped.

[0070] (iv) Example of calculating the safety margin at the switch edge

[0071] Assume that phase A of the bridge arm is caused by U a Shut down to L a Commutation of conduction. Controller in U a After the shutdown command is issued, monitor the voltage and current at phase A. When the phase voltage enters the target stable range for two consecutive sampling points, and the rate of change of the phase voltage satisfies: When the first sample time that meets the condition is determined, the turn-off completion time is defined as the time when U is selected. a The shutdown command time was 12.000 μs; the detected shutdown completion time was 12.920 μs; L a The planned turn-on time is 13.400 μs; the additional safety margin is 0.150 μs. Therefore, the original turn-off interval is: The effective safety margin is: Let the safety margin filter coefficients be... for The filter safety margin of the previous PWM cycle is The safety margin after filtering in this cycle is: If a reliable turn-off completion characteristic is detected at the end of the current cycle, a lookup is performed from the turn-off delay mapping table according to the absolute value of the phase current, bus voltage, power device temperature, and commutation direction. For example, when: ; ; ℃; Reversal direction is to The estimated shutdown delay is obtained by looking up the table. The gate drive propagation delay is The estimated shutdown completion time is: .

[0072] (v) Example of dynamic dead zone correction

[0073] Let: Target effective safety margin for ; to Direction correction factor for Basic dead zone for Safety margin after filtering for The unlimited dynamic dead zone is then: After quantization, there are 68 timer counts, corresponding to an actual dead time of [number missing]. . to Direction uses independent correction factors For example, take The calculation is performed using the historical safety margin value corresponding to that direction. In this embodiment, the maximum change in dead time per cycle is... for Zero current threshold for Direction confirmation period Set as When the absolute value of the phase current is lower than If a change in current direction is detected but not confirmed three times consecutively, the controller will directly use a safety dead zone. .

[0074] (vi) Example of commutation observation and control link compensation

[0075] This embodiment uses the zero-crossing of the floating reverse electromotive force as the subjective measurement, and the line voltage integral and the commutation current slope as auxiliary observations. Under normal operating conditions, the weights are set as follows: When the back EMF waveform quality deteriorates, the back EMF zero-crossing weight can be reduced to 0.30, and the line voltage integral weight and commutation current slope weight can be adjusted to 0.40 and 0.30, respectively. At 3000 r / min, the electrical angle period is approximately 5 ms. The 30° electrical angle reference offset from the back EMF zero-crossing point to the ideal six-step commutation point is approximately 416.7 μs. Examples of control link delays are shown in Table 2.

[0076] Table 2 Example Table

[0077] ADC sampling delay 0.50 Digital filter delay 1.00 Zero-crossing determination delay 0.20 Interruption response delay 0.30 Timing computation delay 0.70 Register update delay 0.10 Gate drive propagation delay 0.15 Total control link delay 2.95

[0078] If the zero-crossing time of the back electromotive force is 125.000 ms, the overall observation error is +6.0 μs, and the commutation error correction coefficient K... ce If the value is 0.50, then the correction amount corresponding to the observation error is: The fundamental commutation time is: The online commutation timing correction is: Therefore, the target commutation time is: In this embodiment, the maximum lead and maximum lag of the commutation online correction are both set to 60 μs. If these values ​​are exceeded, the corresponding limiting value will be applied.

[0079] (vii) Examples of PWM synchronization correction and commutation edge fine-tuning

[0080] Assuming the target commutation time is 125.41675ms and the nearest PWM cycle boundary is 125.41600ms, then: .because: That is, the commutation time falls within the PWM synchronization window. Therefore, the controller moves the commutation event to a position with a preset phase offset of 0.20μs after the boundary of this cycle, i.e.: In another operating condition, if the commutation event is 6.5 μs away from the nearest PWM boundary, which is greater than the 2.0 μs synchronization window, the current PWM cycle will still perform a timing comparison of the commutation event at the target commutation position, instead of immediately forcing the commutation event to jump to the PWM boundary. Subsequently, the controller performs a gradual correction on the PWM time base phase for multiple subsequent PWM cycles, with the phase correction amount for each PWM cycle not exceeding ±0.25 μs. During the fine-tuning of the commutation edge, assuming the time for the outflow phase current to decrease from 90% to 10% is 18.0 μs and the time for the inflow phase current to increase from 10% to 90% is 15.5 μs, the difference between the two is: If the commutation balance threshold is 1.5μs, the controller applies a 0.20μs fine-tuning to the PWM edge related to the inflow phase setup current. This fine-tuning amount, along with the dead-time correction, commutation correction, and PWM synchronization correction, is incorporated into the joint switching timing correction vector.

[0081] (viii) Examples of joint corrections and secure projections

[0082] Suppose that within a certain PWM control cycle: Phase A U a To L a The directional dead zone correction is +0.08μs; there is no dead zone correction before phases B and C; the online correction for commutation timing is... PWM synchronization correction amount is The commutation edge fine-tuning amount is The combined switching timing correction vector can then be expressed as: The controller maps the joint correction vector to the basic event table to form a candidate event table, and then checks in sequence: whether the conduction intervals of the upper and lower bridge power transistors overlap; whether the actual dead time is less than... Is the effective PWM pulse width less than 1 / 3? Is the interval between adjacent events less than 1 / 3? Whether the commutation event, PWM edge, and dead-time end event occur in reverse order; whether any of the above conditions are violated again after timer quantization. For example, if the joint correction results in the remaining effective width of a certain PWM pulse being only... If the PWM pulse does not meet the minimum effective pulse width requirement, the controller will cancel the excessively narrow pulse or move the low-priority PWM edge to the next allowed position, rather than retaining the pulse by compressing the dead time. If the candidate timing causes the conduction intervals of the upper and lower bridge power transistors to overlap by 0.12μs, the controller will prioritize delaying the subsequent conduction event to restore the actual dead time to no less than 0.30μs.

[0083] (ix) Example of Atomic Update of Shadow Register

[0084] After safe projection, the timer count value is written to the PWM compare shadow register, dead-time configuration shadow register, and commutation event shadow register. After each write, the controller calculates a 16-bit CRC check value and simultaneously saves the PWM cycle number k and the valid flag. The timer only copies the entire contents of the shadow register to the active register when the next PWM update event arrives.

[0085] This embodiment requires the timing optimization algorithm to complete at least 2.0 μs before the PWM update event. If the controller determines that there is less than 2.0 μs remaining before the update event, or the CRC check fails, or the cycle number does not match, then the current cycle continues to execute the previous valid target event table, and some register updates are not performed.

[0086] (x) Example of feedback update and parameter mapping

[0087] After the target timing is executed, the dead-time feedback error is formed by the phase-terminal voltage transition time deviation and the commutation current spike. For example, if the target transition time is 1.0 μs and the measured transition time is 1.25 μs, then the normalized dead-time feedback error can be formed as follows: The commutation feedback error is obtained based on the difference between the peak-to-peak current value and the target value over the three PWM cycles after commutation. For example: The dead-zone parameter update gain is set to 0.04 μs / unit error, and the commutation parameter update gain is set to 0.50 μs / unit error. The maximum change in the dead-zone parameter per PWM cycle is limited to 0.02 μs, and the maximum change in the commutation parameter per PWM cycle is limited to 0.50 μs. The parameter mapping table uses a four-dimensional index of speed × phase current × power device temperature × commutation interval. Specifically: speed is divided into 0 to 1500 r / min, 1500 to 3000 r / min, and 3000 to 4500 r / min; phase current is divided into 0 to 1.0 A, 1.0 to 2.5 A, and 2.5 to 4.0 A; temperature is divided into below 60℃, 60℃ to 85℃, and 85℃ to 100℃; and the commutation interval includes intervals 1 to 6. The controller reads the adjacent calibration points of the current operating condition, performs linear interpolation to obtain the initial correction parameters, and then superimposes the online update values.

[0088] (xi) Examples of abnormal downgrade and recovery

[0089] This embodiment sets the following degradation conditions: no valid floating phase voltage for three consecutive sampling windows; dynamic dead zone calculation value exceeding 0.30μs to 1.50μs; commutation correction absolute value exceeding 60μs; bus voltage below 18V or above 30V; phase current exceeding 5.0A; power device temperature exceeding 105℃; motor stall detected; algorithm not completed within 2.0μs before PWM update event. When any degradation condition is met, the controller stops the corresponding dynamic optimization function and switches to safe timing. Safe timing includes a fixed dead zone of 0.90μs, prohibition of PWM pulses shorter than 2.0μs, fixed commutation rules, and PWM synchronization phase changes not exceeding 0.25μs / cycle. After the abnormal state is cleared, the controller requires 20 consecutive PWM control cycles to meet normal conditions before allowing dynamic optimization to resume. In the first 10 PWM control cycles after recovery, the upper limit of the increment of dead zone correction and commutation correction is limited to 50% of the normal upper limit; thereafter, the normal update rate is restored.

[0090] XIV. Other Implementation Scenarios

[0091] In addition to the aforementioned 24V sensorless BLDC centrifugal water pump, this invention can also be applied to fans, ventilators, air circulation equipment, oil pumps, fuel pumps, cooling pumps, blowers, compressors, and other motor drive devices employing three-phase half-bridge power circuits. In different applications, the basic dead zone d0 and minimum safe dead zone d can be adjusted based on the motor pole pair number, rated speed, load inertia, bus voltage, power device switching speed, driver propagation delay, controller clock frequency, and detection link bandwidth. min Maximum allowable dead zone d max Minimum effective pulse width w min Minimum event interval g min PWM synchronization window W sMaximum synchronization correction amount r max Shielding time t blank The control link delay and feedback update gain are recalibrated. Regardless of parameter adjustments, this invention achieves switching timing optimization through the following technical logic: establishing a basic event table under a unified PWM hardware time base; determining the switching edge safety margin based on the actual or estimated turn-off completion time; determining the commutation time correction based on commutation observation characteristics and control link delay; determining the PWM synchronization correction based on the positional relationship between the commutation event and the PWM cycle boundary; mapping dead-time correction, commutation correction, PWM synchronization correction, and edge fine-tuning into a unified candidate event table; performing safety constraint projections such as shoot-through prevention, minimum dead-time, minimum pulse width, event sorting, and timer quantization on the candidate event table; making the timing atomically effective for each bridge arm at the same update boundary through shadow registers; performing closed-loop updates to the parameter mapping table and online correction parameters based on execution feedback; switching to safe timing under abnormal operating conditions and gradually restoring dynamic optimization after recovery conditions are met. The above implementation method avoids the timing conflicts caused by independently modifying the dead time, commutation time and PWM edge in the traditional scheme. It enables the three-phase half-bridge power transistors to achieve better commutation timing and PWM synchronization relationship while meeting the switching safety constraints, even when the bus voltage, load current, speed, temperature and device parameters change.

Claims

1. A method for optimizing the switching timing of three-phase half-bridge power transistors, applied to a six-step commutation drive system for a sensorless brushless DC motor, including a three-phase half-bridge drive circuit and a controller, characterized in that... include: A unified timing reference is established based on the PWM timer of the controller, and the basic switching timing, including the PWM switching edge, commutation time and basic dead time, is determined according to the current PWM control cycle, the six-step commutation interval and the duty cycle instruction. Within a sampling window associated with the PWM switching edge and / or commutation time, operating status quantities are acquired. Switching edge safety margin and commutation timing deviation are determined based on the operating status quantities. Dead-time correction is determined based on the switching edge safety margin. Commutation time correction is determined based on the commutation timing deviation and control link delay. PWM synchronization correction is determined based on the positional relationship between the corrected commutation time and the PWM cycle boundary, forming a joint switching timing correction vector. The joint switching timing correction vector is applied to the basic switching timing to obtain candidate switching timings. The candidate switching timings are then corrected according to preset safety constraints to obtain the target switching timing. The timing parameters corresponding to the target switching timing are written into the shadow register of the PWM timer and synchronously written into the active register when the timer update event arrives; the switch edge safety margin, commutation timing deviation and / or switching timing correction parameters are updated according to the running state quantity after executing the target switching timing.

2. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The operating status quantities include at least one of the following: phase terminal voltage or back EMF, phase current, DC bus voltage or bus current, power device temperature, control link delay, motor speed, electrical angle period, back EMF zero-crossing characteristic, floating phase voltage, driver temperature, power transistor turn-on delay, power transistor turn-off delay, and switching timing correction of the previous PWM control cycle; the controller stores the operating status quantities in association with the corresponding sampling time, bridge arm state, and six-step commutation interval.

3. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The determination of the switching edge safety margin includes: after outputting a turn-off command to the target power transistor, acquiring the corresponding phase terminal voltage or phase current; determining the turn-off completion time based on at least one of the following: the phase terminal voltage enters a preset stable range, the phase terminal voltage change rate is lower than a stable threshold, or the phase current commutation slope meets the termination condition; and determining the switching edge safety margin based on the time difference between the turn-off completion time and the planned turn-on time of the corresponding complementary power transistor; when the turn-off completion time is not detected, determining the estimated turn-off delay from the turn-off delay mapping relationship based on the absolute value of the phase current, the DC bus voltage, the power device temperature, and the power transistor switching direction; and determining the switching edge safety margin based on the estimated turn-off delay, the gate drive propagation delay, and the additional safety margin.

4. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The determination of the dead-time correction amount includes: setting dead-time correction parameters for the first commutation direction (from upper bridge power transistor to lower bridge power transistor) and the second commutation direction (from lower bridge power transistor to upper bridge power transistor) of the same bridge arm, and determining the first dynamic dead-time and the second dynamic dead-time based on the corresponding power transistor turn-off delay, freewheeling state, phase current direction, and switching edge safety margin; limiting the first dynamic dead-time and the second dynamic dead-time between a preset lower dead-time limit and a preset upper dead-time limit; when the absolute value of the phase current is lower than the zero current determination threshold or the phase current direction changes, changing the dead-time correction direction related to the current direction after satisfying the current direction determination condition for at least two consecutive sampling cycles, and using a preset safe dead-time during the period when the current direction is not stable.

5. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The determination of commutation timing deviation and commutation time correction includes: determining at least one of the following: the time when the floating phase back EMF crosses zero, the time when the floating phase terminal voltage or line voltage reaches the target condition within a preset integration interval, the time when the slope of the outflow phase current decreases and the slope of the inflow phase current increases to meet the balance condition, and the phase tracker output phase; and comparing the corresponding observed commutation time with the commutation reference time to obtain the commutation timing deviation; the control link delay includes at least one of the following: ADC sampling delay, digital filtering delay, back EMF detection delay, control interrupt response delay, timing optimization calculation delay, PWM register update delay, and gate drive propagation delay; the controller converts the control link delay into a time compensation amount or an electrical angle compensation amount according to the current electrical angular velocity, and synthesizes the commutation time correction amount with the error obtained based on the observed commutation time.

6. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The determination of the PWM synchronization correction amount includes: calculating the time distance between the corrected commutation time and the nearest PWM cycle boundary; when the time distance is less than or equal to a preset synchronization window, moving the commutation switch event to the PWM cycle boundary or a position with a preset phase offset relative to the PWM cycle boundary; when the time distance is greater than the preset synchronization window, executing the commutation switch event through a timed comparison event within the current PWM cycle, and progressively correcting the PWM time base phase of subsequent multiple PWM cycles, wherein the phase correction amount of a single PWM cycle is not greater than a preset maximum synchronization correction amount; for center-aligned PWM, synchronously moving its rising and falling edges; for edge-aligned PWM, ... The PWM switching edges that do not change the target effective pulse width are corrected; within the commutation interval of the six-step commutation, the duration of the outflow phase current decrease and the duration of the inflow phase current rise are obtained, and when the difference between the two exceeds a preset commutation balance threshold, the commutation edge correction amount is determined based on the difference, wherein the joint switching timing correction vector also includes the commutation edge correction amount; at least one PWM switching edge related to the commutation process of the outflow phase and / or inflow phase is adjusted according to the commutation edge correction amount to reduce the difference; the adjustment of the PWM switching edge and the corrected dead time obtained according to the dead time correction amount are jointly determined under the unified timing reference and corrected according to the preset safety constraints.

7. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The step of correcting the candidate switch timing according to preset safety constraints includes: quantizing the candidate switch timing according to the PWM timer counting resolution; detecting whether the conduction time intervals of the upper and lower bridge power transistors in the same bridge arm overlap, whether the time interval between adjacent switch edges is less than the minimum switch interval, whether the effective PWM pulse width is less than the minimum effective pulse width, and whether the execution order between commutation events, PWM edge events, and dead-time end events meets the preset event priority; when any detection result does not meet the corresponding constraint, the candidate switch timing is projected and corrected according to the safety priority; wherein, the safety priority includes at least the constraint of preventing the upper and lower bridge power transistors in the same bridge arm from overlapping conduction, the constraint of meeting the minimum safe dead time, the constraint of meeting the minimum effective pulse width, the constraint of maintaining the event order, the constraint of commutation timing optimization, and the constraint of PWM synchronization.

8. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, The update based on the operating state quantities after executing the target switching sequence includes: forming a dead zone feedback error based on at least one of phase terminal voltage transition time, freewheeling duration, commutation current change, and power device temperature; forming a commutation feedback error based on at least one of back EMF zero-crossing deviation, line voltage integral error, slope difference between outflow and inflow currents, and post-commutation current fluctuation; filtering the dead zone feedback error and commutation feedback error, and updating the dead zone correction parameters and commutation correction parameters using an incremental method with amplitude limiting; storing the updated parameters as a parameter mapping table according to at least two dimensions of motor speed range, phase current range, DC bus voltage range, power device temperature range, and six-step commutation range; reading the initial correction parameters from the parameter mapping table according to the current operating state and then performing online incremental correction, while limiting the parameter change amount in a single PWM control cycle.

9. The method for optimizing the switching timing of three-phase half-bridge power transistors as described in claim 1, characterized in that, When a valid phase terminal voltage or phase current sampling value cannot be obtained for a consecutive preset number of times, the dynamic dead zone exceeds the safe range, the commutation timing deviation exceeds the maximum allowable deviation, the motor is in the starting stage or stall state, the motor drive system is in an overcurrent, overvoltage or undervoltage state, or the controller fails to complete the timing calculation before the timer update deadline, at least part of the dynamic timing optimization is stopped, and the system switches to a safety switching timing that includes at least a fixed safety dead zone and a preset commutation time. The dynamic timing optimization is resumed once the running state meets the dynamic optimization conditions again.

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