A six-step commutation circuit for brushless DC motor based on pure hardware combination logic and a starting method thereof

Abstract

The application discloses a kind of based on pure combinational logic gate array's brushless DC motor six-step commutation circuit and its starting method.Circuit includes: hall gating module (optional schmitt trigger), the commutation decoding module of pure combinational logic gate array, pre-drive interface (logic / power voltage decoupling) and MCU starting auxiliary module.MCU only in starting time, the hall code of next commutation state is forced by hall gating module, and it is exited after being forced to drag 1~2 electrical period (duty ratio 5%~15%), and commutation is autonomous by pure combination logic.Exempt from dead zone control.Power stage can be adapted to 5V-300V etc.low-voltage silicon MOS, also can be extended to 400V SiC, 690V IGBT.The application realizes pure hardware commutation, nanosecond commutation delay, exempt from dead zone control, EMI suppression, the running safety of medium and high power motor (3kw and above) and high-voltage motor (high-voltage safety is higher than FOC), MCU extremely low participation and voltage platform flexible expansion, can be applicable to various BLDC motor, high-voltage industrial scene and PMSM motor etc., especially suitable for fan, air compressor etc.high-speed BLDC drive scene.

Description

Technical Field

[0001] This invention relates to brushless DC motor (BLDC) control technology, specifically to a brushless DC motor using three-phase Hall sensors installed at 120° electrical angle intervals, a hardware commutation circuit and its startup method that uses a pure combinational logic gate array to achieve six-step commutation and dead-zone-free control, with the MCU only participating in the startup. Background Technology

[0002] Brushless DC motors (BLDC) are widely used in fans, pumps, power tools, and other fields. Traditional six-step commutation control is usually executed by an MCU (microcontroller) or a dedicated driver IC (such as the TI DRV8306 series). MCU solutions require processor resources. While dedicated driver ICs integrate commutation logic, they typically have built-in Hall comparators, digital state machines, and clocks, limiting their voltage rating (mostly below 100V) and making them inflexible for adapting to different power levels of MOSFETs / SiC / IGBTs. Furthermore, existing solutions often employ internal IC alignment or full MCU drag during startup, resulting in a high startup duty cycle (typically 30%~50%), which is detrimental to efficient startup under light loads.

[0003] Therefore, a simpler, lower-cost, more flexible, and production line-adjustment-free BLDC six-step commutation solution is needed. Summary of the Invention

[0004] The technical problem to be solved by the present invention

[0005] 1. Pure hardware logic commutation control, requiring no MCU self-learning or any software intervention for commutation.

[0006] 2. Dead-zone-free control eliminates the risk of up-and-down pass-through in the commutation logic, eliminates the need for dead-zone insertion, and ensures high safety.

[0007] 3. The propagation delay of the commutation output is at the gate circuit level (nanosecond level), and there is no dead time delay, which improves the stability of high-speed operation.

[0008] 4. Enable the MCU to only participate in startup (1~2 electrical cycles) and completely exit commutation control after operation, reducing MCU resource consumption (during operation, only the PWM duty cycle needs to be adjusted to control the speed as required).

[0009] 5. Achieve voltage decoupling between the logic control side and the power drive side. The logic side is fixed at 5V or 3.3V, while the power side can be adapted to medium and low voltage silicon MOS such as 5V-300V, and can also be extended to various power devices such as 400V SiC and 690V IGBT.

[0010] 6. Provides a simple and reliable starting method with a low duty cycle (generally 8%~15%), suitable for starting light loads of wind turbines.

[0011] 7. The commutation overlap control module makes the current waveform smoother, reduces commutation torque pulsation, suppresses EMI, and increases the stability of motor operation.

[0012] 8. In industrial applications such as "high voltage six-step" systems, the turn-off tail of high voltage power transistors such as SiC, GaN, and IGBT (typically 100ns-200ns, longer for IGBTs) is no longer a danger factor and may even be a beneficial effect.

[0013] 9. The torque ripple of the six-step commutation can be moderately smoothed or even significantly reduced in the case of industrial large mechanical inertia motors (high power, high inertia, large load) (high inertia cancels ripple).

[0014] 10. After the introduction of the commutation overlap control module, the operational safety can be increased when driving medium and high power (3kw and above) or high voltage. In terms of the high voltage sensitivity and safety-related dimension of "the impact on the power supply and the entire circuit at the moment of the bridge being fully shut down", this invention is superior to FOC.

[0015] Technical solution

[0016] This invention provides a BLDC pure hardware six-step commutation circuit, comprising:

[0017] Hall effect selection module: During normal motor operation, the three-phase Hall signals are directly input into the logic commutation gate circuit. During startup, the signals are forcibly input by the MCU, making it a two-to-one selection module. Optionally, after entering the gate, the Hall signals are first shaped by a Schmitt buffer stage, performing only edge shaping without requiring an external reference threshold.

[0018] Commutation decoding module: Constructed from a combinational logic gate array into a 6-step commutation table, which can be implemented using fixed-function logic chips (such as 74HC series chips) or programmable logic devices such as CPLD and FPGA; Taking H1 / H2 / H3 as inputs, each state corresponds to two phases being turned on and the other phase being controlled by high impedance; After the three-phase Hall signals enter the gate, the corresponding commutation sequence is decoded and output, and the propagation delay of the commutation output is at the gate circuit level (nanosecond level).

[0019] Pre-driver interface: The logic side outputs a commutation signal to the external pre-driver at a fixed 5V (or 3.3V) logic level. The power stage voltage is decoupled from the logic side. The power stage can be replaced with a 5V–300V low-voltage silicon MOS, and can also be extended to 400V SiC, 690VIGBT, etc.

[0020] MCU Startup Auxiliary Module: During the power-on initialization phase, the MCU reads the direction setting port latched direction configuration, reads the current three-phase Hall state, and queries the next commutation state corresponding to the current state once according to the pre-stored general forward or reverse six-step commutation sequence array in memory. The Hall code of the next commutation state is forcibly injected into the commutation decoding module through the Hall gating module, so that the decoding module outputs the two-phase conduction control corresponding to the next state to forcibly drive the rotor. After detecting the Hall state flip, the MCU cancels the forced setting and switches back to the true Hall input. The commutation process is completed autonomously by the commutation decoding module in hardware, and the MCU no longer participates.

[0021] Commutation overlap control module: Located between the output of the commutation decoding module and the pre-drive interface, it creates a brief three-phase overlap conduction region by applying an RC delay to the turn-off edge, transforming the original two-phase single path into a dual-path parallel connection during commutation, further smoothing out the commutation current dip of the six-step trapezoidal waveform; the two outputs of each phase HIN / LIN are connected to the logic power supply (5V) via a first-stage OC NOT gate (such as 74HC05 or a domestically produced OC NOT gate with the same function) after passing through the first-stage OC NOT gate (such as 74HC05 or a domestically produced OC NOT gate with the same function), and the output terminal is connected to the logic power supply (5V) via a pull-up resistor R_pullup. At the same time, this output terminal is directly connected to the input of the second-stage Schmitt trigger input NOT gate (74HC14) (the input and output of the two NOT gates are directly connected without any intermediate resistors); one end of R_series is connected to this direct connection point, and the other end is connected to capacitor C, with the other end of C grounded, forming an RC delay network in which R_series and C are connected in series to ground and the voltage is taken from the direct connection point; where: the input of the first-stage OC NOT gate is 1 (Input high transition 0-1) When the output is 0, its internal N-MOS is turned on, clamping the output terminal to near 0V. The second stage input is directly connected to this point, so the open edge is not affected by the discharge of the RC network. The second stage NOT gate directly outputs 1 (the original 0→1 turn-on edge is direct). When the first stage OC NOT gate input changes to 0 (input low transition 1-0), the N-MOS is turned off when the output is 1. The output terminal is pulled up by R_pullup. The initial voltage of C is 0. Through the combined action of the pull-up resistor R_pullup and R_series, the capacitor C is charged. When the voltage at this point slowly rises to the 74HC14 positive threshold Vt+≈2.3V@5V, the second stage NOT gate flips, generating a turn-off delay (the original 1→0 turn-off edge is delayed). The delay time is configured by the values ​​of the pull-up resistor R_pullup, R_series and C (generally, the delay time can be configured between 500ns-8us, which can be adjusted according to the actual motor conditions). The overlap time region (500ns-8us) of this module is borrowed from the high-impedance window of 60° electrical angle per phase, without intruding into the conduction window of 120° electrical angle in the same phase. During commutation, the old phase remains off while the new phase is on, forming a path connection of "old phase not off + new phase already on". This avoids the impact of the PWM idle area and commutation colliding simultaneously, which could cause a short-term circuit failure and the immediate return of the follow current surge to the power supply, thus reducing bus spikes and EMI. The upper and lower parts of the same bridge are still separated by high-impedance windows, so as not to introduce the risk of logic shoot-through.

[0022] Current sampling module (optional): A sampling resistor can be placed at the source-to-ground output of the bus or three-phase lower diode. The MCU reads the current for locked rotor / overcurrent / phase loss detection and protection, without entering the commutation hardware logic. At the 20° position of each 60° sector, the MCU calculates a compensation amount based on the speed and bus voltage, and raises the PWM duty cycle slightly in advance (generally 15%-25%, only above 600 RPM; no need to raise it at low speeds with low back EMF, and do not over-raise it; a 12%-13% current dip at 30° is normal), raising it by about 1-3 PWM cycles to prevent the current at the commutation midpoint at 30° from being overwhelmed by back EMF; at the same time, it samples the actual current at 30°, and can use PI slow-adjustment of the compensation coefficient to resist temperature changes, etc. This module is an optional function and is not enabled by default. It can be used if further current smoothing, ripple suppression, and EMI suppression are required.

[0023] Beneficial effects

[0024] 1. Pure hardware logic commutation control, requiring no MCU self-learning or any software intervention for commutation.

[0025] 2. The propagation delay of the commutation output is at the gate circuit level (nanosecond level), which is suitable for high-speed operation of the motor.

[0026] 3. Natural dead-time-free control (no external dead-time control required): In this circuit's six-step commutation conduction strategy, the cycle is "120° electrical angle per phase → 60° high-impedance electrical angle → another 120° electrical angle → 60° high-impedance electrical angle". The 60° electrical angle window between the upper and lower transistors of the same bridge provides high-impedance dual-zero output, eliminating the risk of shoot-through on the logic side. When using a half-bridge driver without built-in dead-time, such as the UCC27211A, the commutation interruption gap is reduced to the nanosecond level and filled by the motor's own coil, achieving continuous commutation current under the six-step commutation architecture.

[0027] 4. The MCU only participates in the startup process for 1-2 power cycles (duty cycle typically 8%-15%), and then completely exits after operation. A low-end MCU model can be selected or used for other tasks. The startup method is reliable, especially suitable for light loads such as fans, with minimal startup impact.

[0028] 5. The logic side and power side voltages are decoupled. The logic side is powered by 5V (3.3V optional), and the power side can be adapted to 5V-300V low-voltage silicon MOS, and can also be extended to 400V SiC, 690V IGBT, etc.

[0029] 6. The commutation overlap control module creates a brief three-phase overlap conduction region by applying an RC delay to the turn-off edge, transforming the original two-phase single path into a dual-path parallel connection during commutation. This further fills the commutation current dip of the six-step trapezoidal waveform, and the top bulge of the current curve approaches a sine wave. The overlap time for low-voltage (5V–48V) silicon MOS terminals can generally be configured to 500ns–5μs (or can be adjusted according to the actual motor conditions), balancing pulsation suppression and copper loss. The motor's running stability and commutation noise performance are superior to the traditional six-step solution (300–500ns of current interruption per commutation with no overlap). EMI suppression can be reduced by 20-30dB (impulse voltage Ldi / dt from 50ns hard turn-off -> 5us overlap). In scenarios such as 48V DC fans, server cooling, and automotive 48V auxiliary drives, it significantly improves motor operation and quietness, and the implementation is simple, robust, and cost-effective.

[0030] 7. In industrial applications such as "high voltage six-step" systems, the turn-off tail of high voltage power transistors such as SiC, GaN, and IGBT (typically 100ns-200ns, longer for IGBTs) is no longer a danger factor or even a beneficial factor.

[0031] 8. The torque ripple of the six-step commutation can be moderately smoothed or even significantly reduced in the case of industrial large mechanical inertia motors (high power, high inertia, large load) (high inertia cancels ripple).

[0032] 9. The commutation overlap control module enhances high-voltage surge safety: For medium-to-high power motors (above 3kW) and high-voltage motors such as 400V SiC / 690V IGBTs (overlap time is generally 500ns–8μs), the safety of this circuit is mainly to mitigate the impact of "PWM idle area + lower transistor commutation collision" causing a short-term circuit failure and immediate return of the follow current surge to the power supply. This risk corresponds to the architectural weakness of FOC SVPWM 111 zero vector (lower bridge fully off) which occurs every cycle (FOC algorithm layer cannot perform lower transistor delayed shutdown protection within 111). In this solution, the overlap is an independent hardware module, which can achieve this, and the commutation frequency is only 1 / 5–1 / 16 of that of FOC111 (approximately 4000 commutations per second for 2-pole 20000rpm air pressure range vs. FOC). At 20kHz, the surge occurs 20,000 times per second. The implementation path of this circuit is a three-way surge protection mechanism: "old phase lower diode delayed shutdown + new phase lower diode direct startup + old phase upper diode body diode" (unlike the single hard surge of the FOC111 where "three-phase upper diode body diodes immediately absorb the surge back to the bus"). The surge voltage of the body diode during the lower diode commutation is milder than that of the FOC, and the Ldi / dt surge voltage can drop significantly (dt changes from a 50ns hard shutdown to an 8us delay). In the high-voltage sensitive and safety-related dimension of "power surge during the moment the lower bridge is fully shut down," this invention is superior to the FOC.

[0033] 10. Furthermore, the turn-off tailing of SiC / GaN / IGBTs (approximately 100–200ns for SiC, 50–150ns for GaN, and even longer for IGBTs) falls precisely within the overlap window and the high-resistance 60° window in this solution. Since both the upper and lower transistors in the same bridge are fully off with no conduction path, there is no shoot-through risk. During the tailing period, the lower transistor of the old phase is slightly turned on, which is in the same direction as the "old phase delayed turn-off" mechanism of the overlap, effectively extending the effective overlap window and providing additional filling for commutation dips. Therefore, this solution can accommodate the tailing of SiC / GaN, IGBTs, etc., and is not considered a harmful factor in the FOC complementary PWM architecture. It is a non-harmful or even beneficial factor. Simultaneously, the switching frequency is low, resulting in less switching loss of the MOS, which is better than FOC and more energy-efficient. Therefore, this solution is suitable for industrial scenarios involving "high voltage six steps."

[0034] Explanation of the natural immune zone

[0035] This circuit uses a BLDC motor with three-phase Hall sensors installed at 120° electrical angle intervals. At this installation angle, in the six-step 120° conduction commutation strategy, each phase cycles through "conducting 120° electrical angle → high-impedance 60° electrical angle → conducting 120° electrical angle → high-impedance 60° electrical angle" within one electrical cycle. There is a constant 60° electrical angle window with high impedance double zero between the upper and lower transistors of the same bridge, so there is no risk of same-bridge shoot-through on the logic side.

[0036] During commutation, the "off phase" and the "on phase" are two phases of different bridges, and their logic path series are equivalent: taking state 1 (U+V-) → state 2 (W+V-) as an example, U+ raw 1→0 and W+ The raw 0→1 signals are simultaneously toggled by the decoder table at the same H1 / H2 / H3 state change. Both raw signals pass through gates of the same level and then enter the pre-drive HIN / LIN pins. Theoretically, U+... final falling edge and W+ The rising edge of the final phase flips simultaneously (without an overlap module). After the flip, phase W becomes high-side conducting, phase V remains low-side conducting, and phase U becomes a high-impedance state with double 0 output. However, the two flips do not belong to the same bridge, so there is no risk of shoot-through. If an overlap commutation module is introduced, the conduction of phase W will result in shoot-through, and the turn-off to high impedance of phase U will be delayed. However, the brief delay in turn-off overlap time falls within the 60-degree high-impedance state window, and the 60-degree electrical angle high-impedance state window with double 0 output always exists and is unaffected.

[0037] This solution does not include a dead-zone control module (the traditional six-step double dead-zone approach overlaps with the architecture layer pass-through feature of this solution).

[0038] Instructions for modifying the Hall effect signal of the "Six-Step High Voltage System"

[0039] For high-voltage BLDC or PMSM motors, the resolver sensing or sensorless (measuring back EMF at zero crossing +30 degrees electrical angle) scheme can be converted into a corresponding three-phase Hall effect sensor connection. This part of the circuit is not included in this scheme, but can be generated by a third-party module or a corresponding functional IC or MCU. This scheme will not elaborate on it. Attached Figure Description

[0040] Figure 1 This is an overall functional block diagram of the present invention.

[0041] Figure 2 This is a circuit schematic diagram of the gate-level feature segment of the present invention (excluding the power stage).

[0042] Figure 1 illustrate:

[0043] Hall signals H1 / H2 / H3 pass sequentially through [Schmitt Buffer (optional)] → [Hall SEL Module] → [Logic Decoding Module (6-state recognition)] → [Commutation Overlap Module] → [Pre-drive Interface (6-channel output to external pre-drive)].

[0044] The MCU is connected to the control input terminal (start-up forced bit SEL) of the Hall strobe module via the data bus, and reads the Hall state and the setting direction of the DIR port during the startup phase, looks up the table, and outputs the forced encoding to start.

[0045] The power stage (5V–300V low-voltage MOS / 400V SiC / 690V IGBT) is connected through a pre-driver interface, and the logic side is electrically isolated from the power side (voltage decoupling is achieved through pre-driver).

[0046] Figure 2 Explanation (Schematic diagram of gate-level characteristic segment circuit):

[0047] Hall Selector Module Description: The three-phase Hall signals H1 / H2 / H3 are shaped by Schmitt trigger and then enter three 2:1 selectors to form the Hall selector module. The A terminal of the selector is connected to the true Hall (after Schmitt trigger), the B terminal is connected to the forced encoding output by the MCU (H1_force / H2_force / H3_force), and the common terminal is output to the gate array decoder.

[0048] Logic Decoding Module Description: This module decodes three Hall effect signals (H1 / H2 / H3) and directly outputs six conduction sequence signals for the three-phase inverter bridge. It consists of six AND gates and six NOT gates (two outputs per phase). The inputs are the original or inverse codes of H1 / H2 / H3, and the outputs are six commutation identification signals S1~S6: S1: 100->A+B-, S2: 110->A+C-, S3: 010->B+C-, S4: 011->B+A-, S5: 001->C+A-; S6: 101->C+B-. H1 / H2 / H3 default to Ha / Hb / Hc correspondence. Changing the order of Ha, Hb, and Hc connections adapts to the Hall effect sequence and phase conduction sequence of different motors. A logic level of 1 for the six output signals indicates the corresponding MOSFET is on, and a logic level of 0 indicates the corresponding MOSFET is off. Commutation six-state decoder S1: 100->A+B-, when the input Hall effect sensor is H1 / H2 / H3=100, the corresponding six outputs are: A phase upper transistor on, lower transistor off (HINA=1 and LINA=0), B phase lower transistor on, upper transistor off (HINB=0 and LINB=1), C phase high impedance (HINC=0 and LINC=0); S2: 110->A+C-, when the input Hall effect sensor is H1 / H2 / H3=110, the corresponding six outputs are: A phase upper transistor on, lower transistor off (HINA=1 and LI). NA=0, phase B high impedance HINB=0 and LINB=0, phase C lower tube open and upper tube closed HINC=0 and LINC=1; S3:010->B+C-, input Hall effect is H1 / H2 / H3=010, corresponding to the six outputs: phase A high impedance HINA=0 and LINA=0, phase B upper tube open and lower tube closed HINB=1 and LINB=0, phase C lower tube open and upper tube closed HINC=0 and LINC=1; and so on, until the decoding of all six phase commutation steps is completed.

[0049] Overlap Commutation Overlap Module Description: Each phase's two output signals, after passing through a first-stage OC NOT gate (such as a 74HC05 or a domestically produced OC NOT gate with equivalent function), have their output connected to a logic power supply (5V) via a pull-up resistor R_pullup. Simultaneously, this output is directly connected to the input of a second-stage Schmitt trigger gate (74HC14) (the two NOT gates are directly connected by their inputs and outputs, with no intermediate resistors). One end of R_series is connected to this direct connection point, and the other end is connected to capacitor C. The other end of C is grounded, forming an RC delay network where R_series and C are connected in series to ground, and the voltage is taken from the direct connection point. Specifically, when the first-stage OC NOT gate's input changes to 1 (high-to-low transition from 0 to 1) and outputs 0, its internal N-MOS conducts, clamping the output to near 0V. The second-stage input is directly connected to this point. Therefore, the open edge is not affected by the discharge of the RC network, and the second-stage NOT gate directly outputs 1 (the original 0→1 turn-on edge is direct). When the input of the first-stage OC NOT gate changes to 0 (input low jump to 1→0) and outputs 1, the N-MOS is turned off. The output terminal is pulled up by R_pullup. The initial voltage of C is 0. Through the combined action of the pull-up resistors R_pullup and R_series, the capacitor C is charged. When the voltage at this point slowly rises to the positive threshold Vt+≈2.3V@5V of 74HC14, the second-stage NOT gate flips, generating a turn-off delay (the original 1→0 turn-off edge is delayed). The delay time is configured by the values ​​of the pull-up resistors R_pullup, R_series and C (generally, the delay time can be configured between 500ns and 8us, which can be adjusted according to the actual motor conditions).

[0050] Finally, the three-phase six-channel output signals are connected to the six corresponding input terminals of the pre-drive interface (the pre-drive and power stage are external modules and are not included in this solution), and then connected to the motor after controlling the corresponding power stage. Detailed Implementation

[0051] Example 1: Application of 5V–48V low-voltage general-purpose fans

[0052] The logic side is powered by 5V, the Hall motor has a built-in 120-degree mounting, and the Schmidt buffer uses 74HC14.

[0053] AND gate array: 2 74HC08 chips (4 AND gates per chip); NOT gate: 1 74HC04 chip.

[0054] Hall effect strobe module: 1 74HC157 (quad 2:1 multiplexer, using 3 of its channels), strobe signal is start strong set bit SEL.

[0055] Dead zone: The logic circuit has built-in dead zone avoidance control.

[0056] Direction configuration: Pull-up resistor to 5V (default forward rotation). If reverse rotation is required, ground the production line jumper.

[0057] MCU: Select STC8 series 51 chip or STM32G030 (M0+) series, etc., only used for reading DIR, reading Hall, looking up table, and outputting strong code during startup (1~2 electrical cycles, duty cycle 8%~10%). After startup, the MCU will go to sleep or perform other tasks.

[0058] Pre-driver: Prioritize short dead-time or no-built-in dead-time half-bridges such as UCC27211A, or domestic EG2134 / EG2132 series (with dead-time redundancy but does not affect use), logic input is compatible with 5V.

[0059] Power stage: Select MOS according to voltage level - SOT-23 small signal MOS (such as SI2302) for 5V system, LFPAK56 packaged MOS (such as 40V / 2mΩ) for 12V / 24V system, and TO-252 packaged MOS (such as 100V / 5mΩ) for 48V system.

[0060] Startup process:

[0061] Upon power-up, the MCU reads the DIR port (high level indicates forward rotation) to latch the direction.

[0062] The MCU reads the current Hall state (e.g., 100), looks up the positive sequence table in memory, and finds that the next state is 110 (corresponding to U+ and W- being turned on).

[0063] The MCU will set the start-up strong bit SEL to 1 and send the strong code (H1=1, H2=1, H3=0) to the B terminal of the Hall select module. At this time, the combinational logic output U+ will be activated. final=1、W- final=1 (PWM is output by the MCU and can be connected in parallel with the lower or upper transistor, with a duty cycle of 8-15% to start), and the output of the other phases is 0.

[0064] When the rotor rotates, the Hall effect sensor flips to 110. The MCU detects the change in Hall state (polling or external interrupt) and immediately clears SEL to 0 and locks it (writes it to the register). After that, the true Hall effect sensor is directly connected to the combinational logic, and commutation is autonomously controlled by hardware.

[0065] If the Hall effect sensor does not flip within 2 electrical cycles (locked rotor protection), the MCU will forcibly clear the SEL and report an error.

[0066] Example 2: 400V SiC Air Compressor Application (Voltage Extension Reference Example)

[0067] The logic side power supply remains constant at 5V. The pre-driver uses an isolated 2ED020I12-F2 (with Miller clamp), requiring a negative voltage shutdown (-5V). Alternatively, three 2ED2304-S (Infineon) half-bridge isolated drivers can be used, each with a complementary pair of IN pins (HIN / LIN), VB-VS = 1200V withstand voltage, and a gate drive power supply of +18V / −5V; one driver for each of the U / V / W phases, with HIN → the final pin of that phase, LIN → the final pin of that phase, and HO / LO pushing the SiC gate. For equivalent implementations using domestic chips, the Nanochip NSi6721 (dual-channel half-bridge, 1700V isolation withstand voltage, 5V input compatibility, driver side supports +18V / −5V) can be used, with a self-built external Miller clamp and negative voltage shutdown circuit, and the wiring method is the same as the 2ED2304-S.

[0068] Dead-time configuration: The logic circuit has built-in dead-time-free control.

[0069] Power stage: Wolfspeed 1200V SiC MOSFET or replace with domestic gallium nitride MOSFET with Innoscience 900V platform GaN (such as INN900D070A). When using GaN, the negative voltage turn-off should not be too large, -4V is sufficient (the -5V of SiC mode cannot be directly applied, as GaN Vgs negative voltage window is narrower). Miller clamping and other processing methods are the same as SiC mode. The pre-driver NSi6721 can be reused, and the PWM carrier can be increased to 50–100 kHz.

[0070] In addition, the turn-off tail of SiC / GaN (approximately 100–200ns for SiC and approximately 50–150ns for GaN) falls within the overlap window and the high-resistance 60° window in this scheme. Since the upper and lower transistors of the same bridge are completely off and there is no conduction path, there is no risk of shoot-through. During the tailing period, the lower transistor of the old phase is slightly turned on, which is in the same direction as the "old phase delayed turn-off" mechanism of overlap, effectively extending the effective overlap window and having an additional filling effect on the commutation depression. Therefore, the tolerance of SiC / GaN tailing in this scheme is much higher than that of the FOC complementary PWM architecture, which is a tolerable or even beneficial factor and is safer than FOC.

[0071] The rest of the structure is the same as in Example 1, except that the power devices and pre-drivers are replaced, and all logic side (Hall gate, decoder, DIR latch) is reused.

[0072] Example 3: 690V IGBT Industrial Fan Application (Voltage Extension Reference Example)

[0073] The logic side power supply remains unchanged at 5V, and the pre-driver is an isolated 1EDI20I12AH.

[0074] Dead-time configuration: The logic circuit has built-in dead-time-free control.

[0075] Power pre-drive: Three 2ED2304-S (Infineon) half-bridge isolated drivers are selected, each with a complementary IN pair (HIN / LIN), VB-VS=1200V withstand voltage, and gate drive power supply +15V / −8V; one each for U / V / W, HIN → the upper transistor of that phase. final, LIN → this phase Downpipe Finally, the HO / LO pushes the IGBT gate. The lower gate has a self-built external clamping circuit: the lower gate is connected to the −8V rail via a 22–47Ω + 1N4148, forming a pure external Miller clamp. For a domestically produced equivalent implementation, the Nanochip NSi6721 (dual-channel half-bridge, 1700V isolation withstand voltage, input compatible with 5V, driver side supports +15V / −8V) can be used, one each for three phases U / V / W, with the wiring as above, and the lower gate external clamping circuit is the same as above.

[0076] Power stage: 1200V IGBT (e.g., IKW40N120T2).

[0077] The logic side is the same as in Example 1.

[0078] The IGBT's turn-off tail is also compatible with this solution—the mechanism is the same as SiC / GaN (falling over the overlap window + being fully off in the high-resistivity state of the same bridge), only the tail is heavier (1–3μs), but the upper limit of 8μs of overlap is enough to cover it, and the excess part falls stably in the high-resistivity 60-degree angle sector without any shoot-through.

Claims

1. A BLDC pure hardware six-step commutation circuit, characterized in that... include: (a) Hall gating module: After the three-phase Hall signal is gated, it is connected to the logic gate level; optionally, after entering the gate, it is first shaped by the Schmitt buffer stage. The Schmitt buffer stage only performs edge shaping and has no external reference threshold. (b) Commutation decoding module: Constructed from a pure hardware combinational logic gate array into a 6-step commutation table, which can be implemented by fixed-function logic chips (such as the 74HC series) or by programmable logic devices such as CPLD and FPGA. With H1 / H2 / H3 as inputs, each state corresponds to two phase conduction control outputs, and the other phase is high impedance; after the three-phase Hall signals enter the gate, the hardware decodes and outputs the corresponding commutation sequence, and the propagation delay of the commutation output is at the gate circuit level; (c) During the power-on initialization phase, the MCU reads the direction setting port latching direction configuration; reads the current three-phase Hall state; according to the pre-stored general forward or reverse six-step commutation sequence array in memory, it queries the next commutation state corresponding to the current state once; through the Hall gating module, it forcibly sets the Hall code of the next commutation state into the commutation decoding module, so that the decoding module outputs the two-phase conduction control corresponding to the next state to forcibly drive the rotor, with a forcible pulse of 1~2 electrical cycles and a duty cycle of 8%~15%; after detecting the Hall state flip, the MCU cancels the forced setting and switches back to the true Hall gate, and the commutation process is completed autonomously by the hardware, and the MCU no longer participates. (d) Natural dead-time-free control (no need for external dead-time control): In the six-step commutation conduction strategy of this circuit, the circuit cycles through "conducting 120° electrical angle per phase → high impedance 60° electrical angle → conducting another 120° electrical angle → high impedance 60° electrical angle". The upper and lower transistors of the same bridge have a 60° electrical angle window with high impedance dual 0 output, so there is no shoot-through risk on the logic side. (e) Commutation overlap control is located between the output of the commutation decoding module and the pre-drive interface. By applying an RC delay to the turn-off edge, a brief three-phase overlap conduction region is formed, so that the original two-phase single path during commutation becomes a two-path parallel connection, further filling the commutation current trough of the six-step trapezoidal waveform; after each phase HIN_final / LIN_final passes through the first-stage OC NOT gate (such as 74HC05 or a domestic OC NOT gate with the same function), its output terminal is connected to the logic power supply (5V) through the pull-up resistor R_pullup. At the same time, this output terminal is directly connected to the input of the second-stage Schmitt input NOT gate (74HC14) (the input and output of the two NOT gates are directly connected without any intermediate resistor); one end of R_series is connected to this direct connection point, and the other end is connected to capacitor C. The other end of C is grounded, forming an R_series connected in series with C to ground, with the voltage taken from the direct connection point. C is a delay network; where: when the input of the first-stage OC NOT gate changes to 1 (high-to-low transition from 0 to 1) and the output is 0, its internal N-MOS turns on, clamping the output to near 0V. The input of the second-stage NOT gate is directly connected to this point, so the open edge is not affected by the discharge of the RC network (the original 0→1 turn-on edge is directly connected); when the input of the first-stage OC NOT gate is 0 and the output is 1, the N-MOS turns off, and the output is pulled up by R_pullup. The initial voltage of C is 0, and the capacitor C is charged by the combined action of the pull-up resistors R_pullup and R_series. When the voltage at this point slowly rises to the positive threshold Vt+≈2.3V@5V of 74HC14, the second-stage NOT gate flips, generating a turn-off delay (the original 1→0 turn-off edge is delayed). The delay time is configured by the values ​​of the pull-up resistors R_pullup, R_series, and C (generally, the delay time can be configured between 500ns and 8us). The overlap time region (500ns-8us) of this module is borrowed from the high-impedance window of 60° electrical angle per phase, without intruding into the conduction window of 120° electrical angle in the same phase. During commutation, the old phase remains off while the new phase is on, forming a path connection of "old phase not off + new phase already on", avoiding the impact of the PWM idle area and commutation colliding simultaneously, which would cause the circuit to be temporarily disconnected and the follow current surge to immediately return to the power supply. The upper and lower parts of the same bridge are still separated by high-impedance windows, which does not introduce the risk of logic shoot-through.

2. The BLDC pure hardware six-step commutation circuit according to claim 1, characterized in that, In the commutation decoding module (b), a 6-step commutation table is constructed from a pure hardware combinational logic gate array. The correspondence between H1 / H2 / H3 and the three phases U / V / W is configurable according to the phase of the Hall IC installed by the motor manufacturer. Through the physical wiring insertion sequence of the Hall selection module or the bit mapping configured by the CPLD, the six-state sequence of H1 / H2 / H3 is 100→110→010→011→001→101→100 or its cyclic offset or reverse. After entering the commutation decoding module, it outputs the correct two-phase conduction control and one-phase high resistance.

3. The BLDC pure hardware six-step commutation circuit according to claim 1, characterized in that, In the aforementioned natural dead-time-free control (d), there is no complementary PWM dead-time register inserted between the upper and lower transistors of the same bridge. The logic-side shoot-through risk is eliminated by the construction of "120° conduction per phase + 60° high impedance double 0 of the same bridge". The pre-driven HI / LI interlock is only used for redundancy and foolproof protection.

4. The BLDC pure hardware six-step commutation circuit according to claim 1, characterized in that, The overlap window delay (typically 500ns–8μs) configuration is determined by the values ​​of R_pullup·C and R_series, with the formula being t_delay ≈ 0.69·(R_pullup+R_series)·C. Users can flexibly configure each parameter according to actual needs and high / low voltage scenarios.

5. The BLDC pure hardware six-step commutation circuit according to claim 1, characterized in that, In the aforementioned commutation overlap control (e), the overlap window (500ns–8μs) is applied to medium-high power motors above 3kW and high-voltage scenarios of 400V SiC / 690V IGBT. It is used to catch the lower bridge full-shutdown impact of "PWM idle area and commutation simultaneously impacting the circuit to cause short-term circuit failure and freewheeling surge returning to the power supply". The turn-off tail of SiC, GaN and IGBT falls within the overlap window and the high-resistance 60° window. The micro-conduction of the old phase lower tube during the tailing period is in the same direction as the "old phase delayed turn-off" mechanism of overlap, which effectively extends the effective overlap window, has an additional filling effect on the commutation depression, and also increases the safety of high voltage.

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