A variable modulation low noise control method for 48v brushless gasoline pump

Abstract

The application provides a variable modulation low noise control method for a 48V brushless gasoline pump, which comprises the following steps: S1, calculating a current ripple coefficient sigma_iq; S2, judging an oil state grade according to the current ripple coefficient sigma_iq; S3, according to a current speed interval and the oil state grade, querying a preset modulation strategy matrix to determine a corresponding modulation mode, a switching frequency and a current amplitude limiting; S4, when the strategy matrix indicates that a random PWM is used, the carrier frequency of each PWM cycle is randomized according to f_k; S5, when the motor speed enters a preset pipeline resonance speed interval, the switching frequency is actively offset so that the PWM carrier does not overlap with the pipeline resonance frequency. The application extracts the cavitation characteristics through the current ripple coefficient by using the existing phase current sampling circuit of the motor control system, and does not need to additionally increase pressure or vibration sensors; the noise energy is dispersed from the concentrated frequency spectrum to a wide frequency band, and the audible noise peak value is reduced.

Description

Technical Field

[0001] This invention relates to the field of noise technology, and in particular to a variable modulation low-noise control method for a 48V brushless gasoline pump. Background Technology

[0002] With the acceleration of automotive electrification, the 48V low-voltage electrical architecture has become an important technical route for the transition from traditional fuel vehicles to hybrid and pure electric vehicles. In this architecture, the 48V brushless fuel pump, as the core actuator of the fuel supply system, directly affects the overall driving quality and NVH (noise, vibration, and harshness) level of the vehicle due to its control performance and noise characteristics. Summary of the Invention

[0003] This invention aims to at least solve the technical problems existing in the prior art, and in particular, it innovatively proposes a variable modulation low noise control method for a 48V brushless gasoline pump.

[0004] To achieve the above-mentioned objectives of this invention, this invention provides a variable modulation low-noise control method for a 48V brushless gasoline pump, comprising the following steps:

[0005] S1, collect the motor phase current, obtain the q-axis current through coordinate transformation, and calculate the current ripple coefficient σ_iq;

[0006] S2, the oil condition level is determined according to the current ripple coefficient σ_iq. The oil condition level includes three levels: normal oil supply, slight cavitation and severe cavitation.

[0007] S3, based on the current speed range and oil condition level, queries the preset modulation strategy matrix to determine the corresponding modulation method, switching frequency and current limit;

[0008] S4, when the strategy matrix indicates the use of random PWM, the carrier frequency of each PWM cycle is randomized according to f_k;

[0009] S5, when the motor speed enters the preset pipeline resonance speed range, actively offset the switching frequency to prevent the PWM carrier from overlapping with the pipeline resonance frequency.

[0010] In a preferred embodiment of the present invention, the expression for the current ripple coefficient in step S1 is:

[0011] σ_iq = std(iq) / mean(iq),

[0012] Where σ_iq represents the current ripple coefficient at the current moment;

[0013] std(iq) represents the standard deviation of the q-axis current;

[0014] mean(iq) represents the mean current along the q-axis.

[0015] In a preferred embodiment of the present invention, the oil condition level in step S2 includes oil condition level 1, oil condition level 2 and oil condition level 3.

[0016] When σ_iq < 5%, it is considered normal oil supply, which corresponds to oil condition level 1.

[0017] When 5%≤σ_iq<15%, it is considered slight cavitation, which belongs to the second level of oil condition.

[0018] When σ_iq≥15%, it is considered severe cavitation, which falls under the third level of oil condition.

[0019] In a preferred embodiment of the present invention, in step S3, the modulation strategy matrix is ​​a two-dimensional combination matrix of operating conditions and oil condition levels.

[0020] In a preferred embodiment of the present invention, in step S4, the frequency jitter amplitude Δf of the random PWM is 1 to 2 kHz, and the reference switching frequency f_base is 16 to 20 kHz.

[0021] In a preferred embodiment of the present invention, the expression for f_k in step S4 is:

[0022] f_k = f_base + Δf × ξ randomization, where f_k represents the randomized switching frequency of the current period, f_base represents the base switching frequency, Δf represents the frequency jitter amplitude, and ξ is a uniformly distributed random number in the range [-1, 1].

[0023] In a preferred embodiment of the present invention, pipeline resonance avoidance is as follows: when the motor speed enters the preset resonance speed range [n_res-Δn, n_res+Δn], the switching frequency is shifted to f_sw_shift=k×f_res, where n_res represents the pipeline resonance speed, Δn represents the half-width of the resonance speed range, f_sw_shift represents the shifted switching frequency, k represents the resonance shift coefficient, k≥3, and f_res represents the pipeline resonance frequency.

[0024] The present invention also discloses a computer system, comprising:

[0025] processor;

[0026] Memory used to store processor-executable instructions;

[0027] The processor is configured to implement the variable modulation low-noise control method for the 48V brushless gasoline pump when executing the executable instructions.

[0028] The present invention also discloses a computer-readable storage medium, comprising:

[0029] A memory on which computer programs are stored;

[0030] A processor is configured to execute the program in the memory to implement the variable modulation low-noise control method for the 48V brushless gasoline pump.

[0031] In summary, by adopting the above technical solutions, this invention utilizes the existing phase current sampling circuit of the motor control system to extract cavitation characteristics through the current ripple coefficient without the need for additional pressure or vibration sensors; it disperses noise energy from a concentrated spectrum to a wide frequency band, reducing audible noise peaks.

[0032] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0033] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0034] Figure 1 This is a schematic flowchart of the present invention. Detailed Implementation

[0035] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] This invention also discloses a variable modulation low-noise control method for a 48V brushless gasoline pump, such as... Figure 1 As shown, it includes the following steps:

[0037] S1, collect the motor phase current, obtain the q-axis current through coordinate transformation, and calculate the current ripple coefficient σ_iq;

[0038] S2, the oil condition level is determined according to the current ripple coefficient σ_iq. The oil condition level includes three levels: normal oil supply, slight cavitation and severe cavitation.

[0039] S3, based on the current speed range and oil condition level, queries the preset modulation strategy matrix to determine the corresponding modulation method, switching frequency and current limit;

[0040] S4, when the strategy matrix indicates the use of random PWM, the carrier frequency of each PWM cycle is randomized according to f_k;

[0041] S5, when the motor speed enters the preset pipeline resonance speed range, actively offset the switching frequency to prevent the PWM carrier from overlapping with the pipeline resonance frequency.

[0042] In a preferred embodiment of the present invention, the expression for the current ripple coefficient in step S1 is:

[0043] σ_iq = std(iq) / mean(iq),

[0044] Where σ_iq represents the current ripple coefficient at the current moment;

[0045] std(iq) represents the standard deviation of the q-axis current;

[0046] mean(iq) represents the mean current along the q-axis.

[0047] In a preferred embodiment of the present invention, the oil condition level in step S2 includes oil condition level 1, oil condition level 2 and oil condition level 3.

[0048] When σ_iq < 5%, it is considered normal oil supply, which corresponds to oil condition level 1.

[0049] When 5%≤σ_iq<15%, it is considered slight cavitation, which belongs to the second level of oil condition.

[0050] When σ_iq≥15%, it is considered severe cavitation, which falls under the third level of oil condition.

[0051] In a preferred embodiment of the present invention, in step S3, the modulation strategy matrix is ​​shown in Table 1. It is a two-dimensional combination matrix of operating conditions (start-up / low speed / high speed) and oil condition level (normal / slight cavitation / severe cavitation). Different combinations correspond to different modulation methods, switching frequencies and current limiting parameters.

[0052] Table 1 Modulation Strategy Matrix

[0053] Start-up phase High-frequency injection positioning + I / F soft start Same as left, price limit reduced by 20%. Same as left, price limit reduced by 40%. low speed operation SVPWM + 16kHz SVPWM + 16kHz + 10% Derating Random PWM + 20kHz + 30% Derating High-speed operation Random PWM + Switching frequency jitter ±1kHz Random PWM + 15% derating Random PWM + 40% Derating + RPM Limit

[0054] In a preferred embodiment of the present invention, in step S4, the frequency jitter amplitude Δf of the random PWM is 1kHz to 2kHz, and the reference switching frequency f_base is 16kHz to 20kHz.

[0055] In a preferred embodiment of the present invention, the expression for f_k in step S4 is:

[0056] f_k = f_base + Δf × ξ randomization, where f_k represents the randomized switching frequency of the current period, f_base represents the base switching frequency, Δf represents the frequency jitter amplitude, and ξ is a uniformly distributed random number in the range [-1, 1].

[0057] In a preferred embodiment of the present invention, the pipeline resonance avoidance is as follows: when the motor speed enters the preset resonance speed range [n_res-Δn, n_res+Δn], the switching frequency is shifted to f_sw_shift=k×f_res, where n_res represents the pipeline resonance speed, Δn represents the half-width of the resonance speed range, f_sw_shift represents the shifted switching frequency, k represents the resonance shift coefficient, k≥3, and f_res represents the pipeline resonance frequency.

[0058] Taking a 48V passenger car brushless fuel pump as an example, the motor is a 3-pole internal rotor permanent magnet synchronous motor with a rated speed of 6000rpm. The drive control module adopts the LKS32AT089XLN8Q9 series drive controller with a switching frequency reference value f_base=16kHz.

[0059] 1) Oil condition sensing

[0060] In FOC control, the q-axis current iq is acquired at a sampling rate of 10kHz, and the ripple coefficient σ_iq=std(iq) / mean(iq) is calculated every 100ms. To avoid transient interference, a first-order low-pass filter is applied to σ_iq: σ_iq_filt=0.9×σ_iq_filt_prev+0.1×σ_iq, where σ_iq_filt represents the filtered current ripple coefficient; σ_iq_filt_prev represents the current ripple coefficient at the previous moment; and σ_iq represents the current ripple coefficient.

[0061] 2) Modulation strategy switching

[0062] Speed ​​range division: startup phase (0-500 rpm), low-speed operation (500-3000 rpm), and high-speed operation (above 3000 rpm). Modulation parameters are determined by querying the strategy matrix in conjunction with the oil condition level. During strategy switching, the switching frequency transitions linearly over 10 PWM cycles to avoid current jumps caused by sudden frequency changes.

[0063] 3) Random PWM execution

[0064] The pseudo-random number generator uses a 16-bit linear feedback shift register (LFSR), with the output mapped to the [-1, 1] interval. With a frequency jitter amplitude Δf = 1.5kHz, the carrier frequency for each PWM cycle randomly varies within the range [14.5kHz, 17.5kHz].

[0065] 4) Pipeline resonance avoidance

[0066] The resonant speed of the pipeline was calibrated using NVH testing at n_res=200rpm and Δn=200rpm. When the speed entered the range of [4000, 4400]rpm, the switching frequency shifted to f_sw_shift=3×f_res=21kHz (f_res=n_res×number of pole pairs / 60×electrical cycle ratio). The shift process was completed smoothly within 50ms.

[0067] Reduced operating mode

[0068] When σ_iq detects slight cavitation (5% ≤ σ_iq < 15%), the current limit is reduced by 10% based on the current modulation strategy to limit the pump output flow and reduce the degree of cavitation, while also reducing noise. When σ_iq ≥ 15% (severe cavitation), the current limit is reduced by 30-40%, random PWM spread spectrum is enabled, and a cavitation alarm signal is sent to the vehicle controller via the CAN bus.

[0069] The present invention also discloses a 48V brushless gasoline pump system, including a motor and a drive controller, and a drive module connected to the motor and the drive controller;

[0070] The drive module includes a u-phase drive module, a v-phase drive module, and a w-phase drive module;

[0071] The u-phase drive module includes:

[0072] The input power supply voltage terminal VB1 of the drive controller is connected to the first terminal of capacitor C39 and the first terminal of resistor R37 respectively;

[0073] The second terminal of resistor R37 is connected to the negative terminal of diode D13. The positive terminal of diode D13 is connected to the first terminal of capacitor C42 and the 12V power supply. The second terminal of capacitor C42 is connected to the power supply ground.

[0074] The drive signal output terminal HO1 of the drive controller is connected to the negative terminal of diode D7 and the first terminal of resistor R40, respectively.

[0075] The positive terminal of diode D7 is connected to the first terminal of resistor R41;

[0076] The second terminals of resistor R40 and resistor R41 are connected to the first terminal of capacitor U4, the negative terminal of unidirectional transient suppression diode D16, and the gate of field-effect transistor Q4, respectively.

[0077] The drain of the field-effect transistor Q4 is connected to the power supply VDD-48V;

[0078] The drive signal output terminal LO1 of the drive controller is connected to the negative terminal of diode D8 and the first terminal of resistor R42, respectively.

[0079] The positive terminal of diode D8 is connected to the first terminal of resistor R43;

[0080] The second terminals of resistor R42 and resistor R43 are connected to the first terminal of capacitor U5, the cathode of unidirectional transient suppression diode D17, and the gate of field-effect transistor Q5, respectively.

[0081] The source of the field-effect transistor Q5 is connected to the first terminal of the resistor R56;

[0082] The bias voltage terminal VS1 of the drive controller is connected to the second terminal of capacitor C39, the second terminal of capacitor U4, the positive terminal of unidirectional transient suppression diode D16, the source of field-effect transistor Q4, and the drain of field-effect transistor Q5, respectively; the source of field-effect transistor Q4 is the U-phase drive output terminal;

[0083] The second terminal of capacitor U5, the positive terminal of unidirectional transient suppression diode D17, and the second terminal of resistor R56 are respectively connected to the first terminal of resistor R59, and the second terminal of resistor R59 is connected to the power supply ground.

[0084] The v-phase drive module includes:

[0085] The input power supply voltage terminal VB2 of the drive controller is connected to the first terminal of capacitor C40 and the first terminal of resistor R38, respectively.

[0086] The second terminal of resistor R38 is connected to the cathode of diode D14. The anode of diode D14 is connected to the first terminal of capacitor C43 and the 12V power supply. The second terminal of capacitor C43 is connected to the power supply ground.

[0087] The drive signal output terminal HO2 of the drive controller is connected to the negative terminal of diode D9 and the first terminal of resistor R44, respectively.

[0088] The positive terminal of diode D9 is connected to the first terminal of resistor R45;

[0089] The second terminals of resistor R44 and resistor R45 are connected to the first terminal of capacitor U6, the cathode of unidirectional transient suppression diode D18, and the gate of field-effect transistor Q6, respectively.

[0090] The drain of the field-effect transistor Q6 is connected to the power supply VDD-48V;

[0091] The drive signal output terminal LO2 of the drive controller is connected to the negative terminal of diode D10 and the first terminal of resistor R46, respectively.

[0092] The positive terminal of diode D10 is connected to the first terminal of resistor R47;

[0093] The second terminals of resistor R46 and resistor R47 are connected to the first terminal of capacitor U7, the negative terminal of unidirectional transient suppression diode D19, and the gate of field-effect transistor Q7, respectively.

[0094] The source of the field-effect transistor Q7 is connected to the first terminal of the resistor R57;

[0095] The bias voltage terminal VS2 of the drive controller is connected to the second terminal of capacitor C40, the second terminal of capacitor U6, the positive terminal of unidirectional transient suppression diode D18, the source of field-effect transistor Q6, and the drain of field-effect transistor Q7, respectively; the source of field-effect transistor Q6 is the V-phase drive output terminal;

[0096] The second terminal of capacitor U7, the positive terminal of unidirectional transient suppression diode D19, and the second terminal of resistor R57 are respectively connected to the first terminal of resistor R59;

[0097] The w-phase drive module includes:

[0098] The input power supply voltage terminal VB3 of the drive controller is connected to the first terminal of capacitor C41 and the first terminal of resistor R39, respectively.

[0099] The second terminal of resistor R39 is connected to the cathode of diode D15. The anode of diode D15 is connected to the first terminal of capacitor C44 and the 12V power supply. The second terminal of capacitor C44 is connected to the power supply ground.

[0100] The drive signal output terminal HO3 of the drive controller is connected to the negative terminal of diode D11 and the first terminal of resistor R48, respectively.

[0101] The positive terminal of diode D11 is connected to the first terminal of resistor R49;

[0102] The second terminals of resistor R48 and resistor R49 are connected to the first terminal of capacitor U8, the negative terminal of unidirectional transient suppression diode D20, and the gate of field-effect transistor Q8, respectively.

[0103] The drain of the field-effect transistor Q8 is connected to the power supply VDD-48V;

[0104] The drive signal output terminal LO3 of the drive controller is connected to the negative terminal of diode D12 and the first terminal of resistor R50, respectively.

[0105] The positive terminal of diode D12 is connected to the first terminal of resistor R51;

[0106] The second terminals of resistor R50 and resistor R51 are connected to the first terminal of capacitor U9, the cathode of unidirectional transient suppression diode D21, and the gate of field-effect transistor Q9, respectively.

[0107] The source of the field-effect transistor Q9 is connected to the first terminal of the resistor R58;

[0108] The bias voltage terminal VS3 of the drive controller is connected to the second terminal of capacitor C41, the second terminal of capacitor U8, the positive terminal of unidirectional transient suppression diode D20, the source of field-effect transistor Q8, and the drain of field-effect transistor Q9, respectively; the source of field-effect transistor Q8 is the W-phase drive output terminal;

[0109] The second terminal of capacitor U9, the positive terminal of unidirectional transient suppression diode D21, and the second terminal of resistor R58 are respectively connected to the first terminal of resistor R59;

[0110] The power module includes:

[0111] The power supply terminal VCC and the power input terminal VIN of the drive controller are respectively connected to the first terminal of capacitor C37, the first terminal of capacitor C38, the first terminal of capacitor C35, the first terminal of capacitor C36, the first terminal of capacitor C22, the first terminal of capacitor C23, the first terminal of resistor R22, and the 12V power supply.

[0112] The second terminals of capacitors C37, C38, C35, C36, C22, and C23 are connected to the power supply ground, respectively.

[0113] The second terminal of resistor R22 is connected to the enable terminal INH / EN of the drive controller;

[0114] The power ground terminal GND of the drive controller is connected to the power ground.

[0115] The power output module includes:

[0116] The power input terminal H1 of the power interface is connected to the first terminal of the bidirectional transient suppression diode D22, the first terminal of the capacitor C1, and the first terminal of the inductor L1, respectively.

[0117] The second terminal of inductor L1 is connected to the first terminal of capacitor C3, the first terminal of resistor R1, the first terminal of capacitor U14, and the first terminal of inductor L8, respectively; the second terminal of inductor L1 outputs power supply VDD-48V.

[0118] The second terminal of capacitor C1 is connected to the first terminal of capacitor C2;

[0119] The second terminal of capacitor C3 is connected to the first terminal of capacitor C4;

[0120] The second end of resistor R1 is connected to the first end of resistor R3, the gate of field-effect transistor Q1, the negative terminal of unidirectional transient suppression diode D2, and the first end of capacitor C6, respectively.

[0121] The power input terminal H2 of the power interface is connected to the second terminal of the bidirectional transient suppression diode D22, the second terminal of capacitor C2, the second terminal of capacitor C4, the first terminal of capacitor C5, and the drain of the field-effect transistor Q1.

[0122] The second terminal of capacitor C5 is connected to the first terminal of resistor R2;

[0123] The source of the field-effect transistor Q1, the positive terminal of the unidirectional transient suppression diode D2, the second terminal of resistor R2, the second terminal of resistor R3, the second terminal of capacitor C6, and the second terminal of capacitor U14 are connected to the power supply ground respectively.

[0124] The second terminal of inductor L8 is connected to the first terminal of capacitor C45, the power supply terminal VIN of power chip U11, and the enable terminal EN / UVLO of power chip U11, respectively.

[0125] The second terminal of capacitor C45 is connected to the power ground terminal GND and the power ground of power chip U11, respectively.

[0126] The on terminal RON of the power chip U11 is connected to the first terminal of resistor R63, and the second terminal of resistor R63 is connected to the power ground.

[0127] The pad EP of the power chip U11 is connected to the power ground.

[0128] The switching node SW of the power chip U11 is connected to the first terminal of capacitor C46, ​​the first terminal of resistor R64, and the first terminal of inductor U13, respectively.

[0129] The second terminal of capacitor C46 is connected to the bootstrap terminal BST of power chip U11.

[0130] The second terminal of resistor R64 is connected to the first terminal of capacitor C47 and the first terminal of capacitor C48, respectively.

[0131] The second terminal of capacitor C48 is connected to the first terminal of resistor R65, the first terminal of resistor R66, and the feedback terminal FB of power chip U11, respectively.

[0132] The second terminal of inductor U13 and the second terminal of capacitor C47 are respectively connected to the first terminal of capacitor C49, the first terminal of capacitor C50 and the second terminal of resistor R65; the second terminal of inductor U13 outputs 12V power.

[0133] The second terminals of capacitor C49, capacitor C50, and resistor R66 are connected to the power supply ground.

[0134] It also includes a bus module, which includes:

[0135] The bus terminal LIN of the drive controller is connected to the first terminal of capacitor C18 and the first terminal of bidirectional transient suppression diode D5, respectively.

[0136] The second terminal of capacitor C18 and the second terminal of bidirectional transient suppression diode D5 are connected to the power supply ground, respectively; the bus terminal LIN of the drive controller is the data terminal;

[0137] It also includes an input voltage sampling module, which includes:

[0138] The voltage acquisition terminal ADC_CH7 / P0.3 of the drive controller is connected to the first terminal of resistor R5, the first terminal of resistor R7, and the first terminal of capacitor C11, respectively.

[0139] The second terminal of resistor R5 is connected to the power supply VDD-48V;

[0140] The second terminal of resistor R7 and the second terminal of capacitor C11 are connected to the power supply ground, respectively.

[0141] It also includes a serial port module, which includes:

[0142] The data terminal SWDIO / P2.4 of the drive controller is connected to the data terminal of the serial interface;

[0143] The clock input SWCLK of the drive controller is connected to the clock input of the serial port interface;

[0144] The power supply terminal of the serial port interface is connected to the external power supply terminal AVDD of the drive controller, the first terminal of capacitor C24, and the first terminal of capacitor C25; the external power supply terminal AVDD of the drive controller outputs 5V power.

[0145] The power ground terminal of the serial port interface is connected to the power ground.

[0146] The second terminals of capacitors C24 and C25 are connected to the power supply ground, respectively.

[0147] The external power wake-up terminal WAKE_N of the drive controller is connected to the first terminal of resistor R31, and the second terminal of resistor R31 is connected to the power ground.

[0148] It also includes a reset module, which includes:

[0149] The reset terminal RSTN / P0.2 of the drive controller is connected to the first terminal of resistor R17, the first terminal of capacitor C20, and the first terminal of the reset button, respectively.

[0150] The second terminal of resistor R17 is connected to the 5V power supply;

[0151] The second terminal of capacitor C20 is connected to the power supply ground;

[0152] The second end of the reset button is connected to the power ground;

[0153] It also includes an output module, which includes:

[0154] The control terminal HALL_IN2 / P2.6 of the drive controller is connected to the first terminal of resistor R14;

[0155] The second end of resistor R14 is connected to the first end of resistor R13 and the gate of field-effect transistor Q2, respectively.

[0156] The drain of the field-effect transistor Q2 is connected to the first terminal of the resistor R9;

[0157] The second terminal of resistor R9 is connected to the first terminal of resistor R8 and the second terminal of bidirectional transient suppression diode D31, respectively; the first terminal of resistor R8 is the output terminal.

[0158] The second terminal of resistor R8 is connected to the power supply VDD-48V;

[0159] The second terminal of resistor R13, the source of field-effect transistor Q2, and the second terminal of bidirectional transient suppression diode D31 are connected to the power supply ground, respectively.

[0160] It also includes an input module, which includes:

[0161] The data terminal ADC_CH8 / P0.4 of the drive controller is connected to the first terminal of resistor R21, the first terminal of capacitor C29, and the source of field-effect transistor Q3;

[0162] The second terminal of resistor R21 is connected to the first terminal of capacitor C26 and the 5V power supply, respectively. The second terminal of capacitor C26 is connected to the power supply ground.

[0163] The gate of the field-effect transistor Q3 is connected to the first terminal of resistor R16 and the first terminal of resistor R20, respectively.

[0164] The second terminal of resistor R20, the source of field-effect transistor Q3, and the second terminal of capacitor C29 are connected to the power supply ground, respectively.

[0165] The second terminal of resistor R16 is connected to the first terminal of resistor R12 and the first terminal of resistor R15, respectively.

[0166] The second terminal of resistor R15 is connected to the cathode of diode D6, and the anode of diode D6 is connected to the power supply VDD-48V; the second terminal of resistor R15 is the output terminal.

[0167] The second terminal of resistor R12 is connected to the first terminal of bidirectional transient suppression diode D32, and the second terminal of bidirectional transient suppression diode D32 is connected to the power supply ground;

[0168] It also includes an indicator module, which includes:

[0169] The indicator terminal P2.12 of the drive controller is connected to the first terminal of resistor R62;

[0170] The second terminal of resistor R62 is connected to the first terminal of indicator LED1;

[0171] The second terminal of indicator LED1 is connected to the power ground;

[0172] It also includes an overcurrent sampling module, and the current sampling module includes:

[0173] The overcurrent sampling terminal ADC_CH15 / P0.11 of the drive controller is connected to the first terminal of resistor R27 and the first terminal of capacitor C30;

[0174] The second terminal of capacitor C30 is connected to the first terminal of resistor R23 and the power supply ground, respectively.

[0175] The second terminals of resistors R23 and R27 are respectively connected to the second terminal of resistor R58;

[0176] It also includes an encoder module, which includes:

[0177] The SPI clock pin ADC_CH14 / P2.1 of the drive controller is connected to the clock pin of the encoder interface;

[0178] The SPI data output terminals P0.15 / OSC_OUT / P3.9 of the drive controller are connected to the data input terminals of the encoder interface;

[0179] The SPI data input terminals P1.0, OSC_IN, and P2.8 of the drive controller are connected to the data output terminals of the encoder interface;

[0180] The ground terminal of the encoder interface is connected to the power ground.

[0181] It also includes a current sampling module, which includes a U-phase current sampling module, a V-phase current sampling module, and a W-phase current sampling module;

[0182] The u-phase current sampling module includes:

[0183] The current sampling terminal OPA1_IP / P3.0 of the drive controller is connected to the first terminal of capacitor C34 and the first terminal of resistor R32, respectively.

[0184] The current sampling terminal OPA1_IN / P3.1 of the drive controller is connected to the second terminal of capacitor C34 and the first terminal of resistor R34, respectively.

[0185] The second terminal of resistor R32 is connected to the first terminal of resistor R56, and the second terminal of resistor R34 is connected to the second terminal of resistor R56.

[0186] The phase v current sampling module includes:

[0187] The current sampling terminal OPA0_IP / P3.5 of the drive controller is connected to the first terminal of capacitor C33 and the first terminal of resistor R30, respectively.

[0188] The current sampling terminals OPA0_IN and P3.7 of the drive controller are connected to the second terminal of capacitor C33 and the first terminal of resistor R36, respectively.

[0189] The second terminal of resistor R30 is connected to the first terminal of resistor R57, and the second terminal of resistor R36 is connected to the second terminal of resistor R57.

[0190] The w-phase current sampling module includes:

[0191] The current sampling terminal OPA2_IP / P3.10 of the drive controller is connected to the first terminal of capacitor C32 and the first terminal of resistor R35, respectively;

[0192] The current sampling terminals P2.9 / OPA2_IN / P3.11 of the drive controller are connected to the second terminal of capacitor C32 and the first terminal of resistor R33, respectively;

[0193] The second terminal of resistor R35 is connected to the first terminal of resistor R58, and the second terminal of resistor R33 is connected to the second terminal of resistor R58.

[0194] It also includes a bus current sampling module, which includes:

[0195] The current sampling terminal OPA3_IP / P3.15 of the drive controller is connected to the first terminal of capacitor C31 and the first terminal of resistor R29, respectively;

[0196] The current sampling terminal OPA3_IN / P3.14 of the drive controller is connected to the second terminal of capacitor C31 and the first terminal of resistor R28, respectively.

[0197] The second terminal of resistor R29 is connected to the first terminal of resistor R59, and the second terminal of resistor R28 is connected to the second terminal of resistor R59.

[0198] It also includes a voltage sampling network, which includes a u-phase voltage sampling network, a v-phase voltage sampling network, and a w-phase voltage sampling network;

[0199] The u-phase voltage sampling network includes:

[0200] The first terminal of resistor Ru1 is connected to the source of field-effect transistor Q4;

[0201] The second end of resistor Ru1 is connected to the first end of resistor Ru2 and the first end of resistor Ru3;

[0202] The second terminal of resistor Ru2 is connected to the power supply ground;

[0203] The second end of resistor Ru3 is connected to the first end of capacitor Cu1 and the voltage sampling terminal CAN_RX / P0.12 of the drive controller, respectively;

[0204] The second terminal of capacitor Cu1 is connected to the power supply ground.

[0205] The phase-v voltage sampling network includes:

[0206] The first terminal of resistor Ru1 is connected to the source of field-effect transistor Q4;

[0207] The second end of resistor Ru1 is connected to the first end of resistor Ru2 and the first end of resistor Ru3;

[0208] The second terminal of resistor Ru2 is connected to the power supply ground;

[0209] The second end of resistor Ru3 is connected to the first end of capacitor Cu1 and the voltage sampling terminal CAN_RX / P0.12 of the drive controller, respectively;

[0210] The second terminal of capacitor Cu1 is connected to the power supply ground; the resistance values ​​of resistors Ru1, Ru2 and Ru3 are 47KΩ, 3.3KΩ and 100Ω respectively, and the capacitance value of capacitor Cu1 is 1nF.

[0211] The first terminal of resistor Rv1 is connected to the source of field-effect transistor Q6;

[0212] The second terminal of resistor Rv1 is connected to the first terminals of resistors Rv2 and Rv3.

[0213] The second terminal of resistor Rv2 is connected to the power supply ground;

[0214] The second end of resistor Rv3 is connected to the first end of capacitor Cv1 and the voltage sampling terminal CAN_TX / P0.13 of the drive controller, respectively;

[0215] The second terminal of capacitor Cv1 is connected to the power supply ground; the resistance values ​​of resistors Rv1, Rv2 and Rv3 are 47KΩ, 3.3KΩ and 100Ω respectively, and the capacitance value of capacitor Cv1 is 1nF.

[0216] The phase voltage sampling network includes:

[0217] The first terminal of resistor Rw1 is connected to the source of field-effect transistor Q8;

[0218] The second terminal of resistor Rw1 is connected to the first terminals of resistors Rw2 and Rw3;

[0219] The second terminal of resistor Rw2 is connected to the power supply ground;

[0220] The second terminal of resistor Rw3 is connected to the first terminal of capacitor Cw1 and the voltage sampling terminal CMP0_IP4 / P0.14 of the drive controller, respectively.

[0221] The second terminal of capacitor Cw1 is connected to the power supply ground; the resistance values ​​of resistors Rw1, Rw2 and Rw3 are 47KΩ, 3.3KΩ and 100Ω respectively, and the capacitance value of capacitor Cw1 is 1nF.

[0222] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A variable modulation low-noise control method for a 48V brushless gasoline pump, characterized in that, Includes the following steps: S1, collect the motor phase current, obtain the q-axis current through coordinate transformation, and calculate the current ripple coefficient σ_iq; S2, the oil condition level is determined according to the current ripple coefficient σ_iq. The oil condition level includes three levels: normal oil supply, slight cavitation and severe cavitation. S3, based on the current speed range and oil condition level, queries the preset modulation strategy matrix to determine the corresponding modulation method, switching frequency and current limit; S4, when the strategy matrix indicates the use of random PWM, the carrier frequency of each PWM cycle is randomized according to f_k; S5, when the motor speed enters the preset pipeline resonance speed range, actively offset the switching frequency to prevent the PWM carrier from overlapping with the pipeline resonance frequency.

2. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, The expression for the current ripple coefficient in step S1 is: σ_iq = std(iq) / mean(iq), Where σ_iq represents the current ripple coefficient at the current moment; std(iq) represents the standard deviation of the q-axis current; mean(iq) represents the mean current along the q-axis.

3. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, In step S2, the oil condition levels include oil condition level 1, oil condition level 2, and oil condition level 3; When σ_iq < 5%, it is considered normal oil supply, which corresponds to oil condition level 1. When 5%≤σ_iq<15%, it is considered slight cavitation, which belongs to the second level of oil condition. When σ_iq≥15%, it is considered severe cavitation, which falls under the third level of oil condition.

4. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, In step S3, the modulation strategy matrix is ​​a two-dimensional combination matrix of operating conditions and oil condition levels.

5. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, In step S4, the frequency jitter amplitude Δf of the random PWM is 1 to 2 kHz, and the reference switching frequency f_base is 16 to 20 kHz.

6. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, The expression for f_k in step S4 is: f_k = f_base + Δf × ξ randomization, where f_k represents the randomized switching frequency of the current period, f_base represents the base switching frequency, Δf represents the frequency jitter amplitude, and ξ is a uniformly distributed random number in the range [-1, 1].

7. The variable modulation low-noise control method for a 48V brushless gasoline pump according to claim 1, characterized in that, Pipeline resonance avoidance is as follows: when the motor speed enters the preset resonance speed range [n_res-Δn, n_res+Δn], the switching frequency is shifted to f_sw_shift=k×f_res, where n_res represents the pipeline resonance speed, Δn represents the half-width of the resonance speed range, f_sw_shift represents the shifted switching frequency, k represents the resonance shift coefficient, k≥3, and f_res represents the pipeline resonance frequency.

8. A computer system, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the variable modulation low noise control method for the 48V brushless gasoline pump as described in any one of claims 1 to 7 when executing the executable instructions.

9. A computer-readable storage medium, characterized in that, include: A memory on which computer programs are stored; A processor for executing the program in the memory to implement the variable modulation low noise control method for the 48V brushless gasoline pump according to any one of claims 1 to 7.

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