A low temperature drift relaxation oscillator based on dynamic element matching

Abstract

The application discloses a low-temperature drift relaxation oscillator based on dynamic element matching and belongs to the technical field of integrated circuit clock. The oscillator comprises a charge-discharge current mirror, a comparator, a logic control unit, a charge-discharge capacitor, a dynamic element matching module and a virtual voltage storage node; the symmetrical charge-discharge is realized by adopting a current sharing structure, the current source mismatch is eliminated by the dynamic element matching, the switch charge injection is absorbed by the virtual voltage storage node, and the saturation operation of the current mirror is maintained; the reference voltage difference and the charge-discharge current have the same temperature coefficient, and the oscillation frequency only depends on the resistance-capacitance parameter after the cancellation. The application has the characteristics of high precision, low noise and low temperature drift, reduces the layout design requirement and is suitable for wide-temperature working scenes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit clock generation technology, specifically relating to a low-temperature drift relaxation oscillator based on dynamic component matching. Background Technology

[0002] Relaxor oscillators are the core module of on-chip clock systems, widely used in microcontrollers, power management chips, IoT terminals, and other scenarios. They can generate the clock signal required by the system without the need for an external crystal oscillator. Existing relaxor oscillators are typically based on the principle of capacitor charging and discharging, using a comparator to detect the capacitor voltage threshold and logic circuits to achieve periodic oscillation.

[0003] The existing technology has the following drawbacks: First, the charging and discharging current source has process mismatch, resulting in asymmetrical charging and discharging current, low oscillation frequency accuracy, and extremely high requirements for layout matching design; Second, there are charge injection and clock feedthrough effects during the switching process, which can easily cause the current mirror tube to leave the saturation region, generating switching noise and setup error, and deteriorating phase noise performance; Third, the oscillation frequency is easily affected by temperature changes, with a large temperature drift coefficient, making it difficult to meet the clock accuracy requirements under a wide temperature range. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-temperature drift relaxor oscillator based on dynamic component matching. While improving current matching accuracy and reducing switching noise, it achieves an extremely low temperature drift coefficient, thereby improving clock stability and process adaptability.

[0005] A low-temperature drift relaxor oscillator based on dynamic element matching includes a charge / discharge current mirror module, a comparator, a logic control unit, a charge / discharge capacitor, a dynamic element matching (DEM) module, and a virtual voltage storage node.

[0006] The charge / discharge current mirror module adopts a current equalization structure to generate charging and discharging currents with equal amplitudes; the dynamic element matching module is connected to the current source array of the charge / discharge current mirror module to eliminate current source mismatch errors through dynamic rotation; the virtual voltage storage node is connected to the switching node of the current mirror to absorb the charge injection generated by switching, so that the current mirror remains in saturated working state during switching.

[0007] The first input terminal of the comparator is connected to the plate voltage of the charging and discharging capacitor, and the second input terminal is connected to the first reference voltage and the second reference voltage in a time-division manner. The difference between the first reference voltage and the second reference voltage, as well as the charging and discharging current, all have the same temperature coefficient, so that the frequency of the oscillator output clock has low temperature drift characteristics.

[0008] The logic control unit generates a switch control signal based on the output signal of the comparator to control the switching of the charging and discharging path and the switching of the reference voltage.

[0009] Furthermore, the current sharing structure includes a first NMOS transistor and a second NMOS transistor; their gates are interconnected, their sources are grounded, they have the same gate-source voltage and overdrive voltage, and their drain current amplitudes are equal, serving as the charging current and discharging current respectively.

[0010] Furthermore, the dynamic component matching module periodically rotates the access order of the current source array to evenly offset the size mismatch and threshold mismatch between each current source, thereby improving the current matching accuracy without increasing the layout requirements.

[0011] Furthermore, the virtual voltage storage node is a passive capacitor node, which maintains the drain-source voltage of the current mirror tube stable during the switching instant, so that it always works in the saturation region and eliminates the nonlinear noise caused by the switching setup process.

[0012] Furthermore, the first reference voltage is the bandgap reference voltage VR, and the second reference voltage is the emitter junction voltage VBE3 of the bipolar transistor; the difference between the two is a positive temperature coefficient, and the charging and discharging current is also a positive temperature coefficient. After dividing the two, the oscillation period is only related to the resistance and capacitance parameters. By selecting a low-temperature drift resistor and capacitor, a low-temperature drift clock output can be obtained.

[0013] Correspondingly, the present invention also provides a low-temperature drift relaxation oscillation method based on dynamic component matching, comprising: using dynamic component matching to eliminate current source mismatch, using a current equalization structure to generate symmetrical charging and discharging current; switching to charging state when the capacitor discharges to the lower threshold, and switching to discharging state when charging to the upper threshold, and oscillating in a cycle; maintaining current mirror saturation through virtual voltage storage nodes during the switching process to suppress switching noise; and using the voltage difference with the same temperature coefficient to cancel the current, thereby realizing low-temperature drift clock output.

[0014] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: High current matching accuracy: The dynamic component matching technology dynamically rotates the current source, eliminating process mismatch errors on an average basis over time. Highly consistent charging and discharging currents can be achieved without high-precision layout matching, reducing layout design difficulty and process sensitivity.

[0015] Low switching noise: By absorbing the switch charge injection through virtual voltage storage technology, the current mirror remains in saturated operation throughout the switching process, with no additional setup process and setup noise, significantly reducing the nonlinear noise caused by switching and optimizing phase noise performance.

[0016] Excellent temperature stability: By using the reference voltage difference with a positive temperature coefficient and the charging and discharging current with a positive temperature coefficient for calculation, the oscillation frequency depends only on the resistance and capacitance parameters. When paired with low-temperature drift resistors and capacitors, an extremely low temperature drift coefficient can be achieved, making it suitable for wide-temperature operating scenarios.

[0017] Good charge and discharge symmetry: The common-gate common-source current-sharing structure ensures that the amplitude of the charging current and the discharging current are strictly equal, thereby improving the symmetry of the oscillation waveform and the frequency accuracy. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall circuit structure of the low-temperature drift relaxation oscillator based on dynamic element matching according to an embodiment of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1 As shown, the low-temperature drift relaxation oscillator based on dynamic component matching in this embodiment mainly includes a charge / discharge current mirror module, a dynamic component matching DEM module, a virtual voltage storage node, a charge / discharge capacitor C, a comparator, a logic control unit, and a reference voltage generation branch.

[0021] The charge / discharge current mirror module consists of three parts: a reference current branch, a charging current mirror, and a discharging current equalization branch. It includes six core components: a reference resistor R1, a bipolar transistor Q3, a first PMOS transistor MP12, a second PMOS transistor MP13, a first NMOS transistor MN4, and a second NMOS transistor MN5.

[0022] Reference current branch: One end of the reference resistor R1 is connected to the power supply VDD, and the other end is connected to the collector, base, and gate bias node of the charging current mirror of transistor Q3; the emitter of transistor Q3 is grounded; this branch generates a reference current that is positively correlated with the thermal voltage, and outputs the transistor emitter junction voltage VBE3 as the lower limit reference voltage for oscillation.

[0023] Charging current mirror: MP12 and MP13 are P-channel MOSFETs. Their sources are connected to the power supply VDD, and their gates are interconnected and connected to the gate bias node of the reference current branch, forming a common source current mirror structure. MP12 is the reference replication transistor, and MP13 is the charging output transistor. The drain of MP13 is the charging current output terminal, and the output charging current is proportional to the reference current.

[0024] The discharge current is evenly distributed: MN4 and MN5 are N-channel MOSFETs with their sources grounded together. Their gates are interconnected and connected to a unified discharge bias node. Their overdrive voltages are completely identical, forming an evenly distributed current structure. MN4 is the reference transistor, with its drain connected to the output terminal of the charging current mirror to replicate the current amplitude. MN5 is the discharge output transistor, with its drain being the output terminal of the discharge current. Its drain current is strictly equal to that of MN4 to ensure that the charging and discharging current amplitudes are consistent.

[0025] The Dynamic Element Matching (DEM) module consists of three parts: an N-channel parallel sub-current source unit, a rotating switch array, and a DEM timing controller, which are connected in series in the gate bias path of the current mirror.

[0026] The N sub-current source units are connected in parallel between the reference current branch and the charging current mirror gate, and each sub-current source is connected in series with an independent switching switch. The control terminals of all rotating switches are uniformly connected to the parallel output terminal of the DEM timing controller; The clock input of the DEM timing controller is connected to the synchronous clock of the logic control unit. It outputs a rotating code at a fixed period to switch the connection status of each sub-current source in turn, and the static mismatch error of the current source is offset by the time averaging effect.

[0027] The core component of the virtual voltage storage node is the virtual storage capacitor CV, a passive capacitive node. The upper end of the virtual storage capacitor CV is connected to the current mirror switch switching node (the common node for the charging current output and the discharging reference tube), and the lower end is grounded. It is used to absorb the charge injection and extraction generated during switch switching, maintaining the stability of the current tube's drain voltage and ensuring the current mirror operates in the saturation region throughout its operation. 4. The core component of the charge / discharge capacitor module is the main charge / discharge capacitor C. The upper plate of the capacitor is the charge / discharge node VC, and the lower plate is grounded. The capacitor voltage rises and falls periodically during the charge / discharge process, making it the core energy storage and voltage generation component of the oscillator. 5. The core of the comparator module is the voltage comparator COMP, equipped with a reference voltage gating switch network; it includes three ports: a non-inverting input, an inverting input, and an output.

[0028] The non-inverting input of the comparator is fixedly connected to the charge / discharge node VC; The reference voltage gating switch network includes a first gating switch S1 and a second gating switch S2: one end of S1 is connected to the bandgap reference voltage VR, and one end of S2 is connected to the emitter junction voltage VBE3 of transistor Q3; the other ends of the two switches are connected to the inverting input of the comparator; the control terminals of the two switches are both connected to the logic control unit.

[0029] The logic control unit consists of five parts: RS flip-flops, inverters, delay shaping units, switch control logic, and DEM synchronization logic.

[0030] The set and reset terminals of the RS flip-flop are connected to the shaped signal output by the comparator. The inverter works in conjunction with the switch control logic to generate complementary control signals for the charge / discharge switch and the reference voltage gating switch; The DEM synchronous logic outputs a synchronous clock to the dynamic component matching module to match the current source switching rhythm and oscillation period. The unit's final output terminal outputs an oscillation clock signal CLK.

[0031] The working principle is as follows:

[0032] The working principle is as follows: The charge / discharge current mirror module comprises a current-sharing structure consisting of a first NMOS transistor MN4 and a second NMOS transistor MN5. MN4 and MN5 are interconnected at their gates and share a common ground, and both have identical gate-source voltages Vgs. Ignoring channel modulation effects, the drain current of the NMOS transistors operating in the saturation region satisfies: in The electron mobility in the channel, Gate oxide capacitance per unit area The aspect ratio of the MOSFET. Gate-source voltage, This is the threshold voltage.

[0033] Since the gates and sources of MN4 and MN5 are connected respectively, their overdrive voltages (Vgs-Vth) are exactly the same, and their drain currents are equal under the matching design. The drain current of MN4 is used as the charging current, and the drain current of MN5 is used as the discharging current, thereby ensuring that the amplitudes of the charging current and the discharging current are strictly equal, achieving current sharing.

[0034] Dynamic Component Matching DEM Module The dynamic component matching module is connected to the current source array input terminal of the current mirror. By periodically changing the access order of each sub-current source, the static mismatch error of each current source is transformed into a high-frequency dynamic error. The mean error caused by mismatch is offset by the time averaging effect, thereby improving the current matching accuracy and reducing the requirements for layout matching.

[0035] Virtual voltage storage node The virtual voltage storage node is a passive capacitor node set on the switching path of the current mirror switch. When the switch is charging and discharging, the charge injection and extraction effects of the node are absorbed by the virtual storage node, maintaining the drain-source voltage of the current mirror tube stable. This ensures that MN4 and MN5 always operate in the saturation region throughout the switching process, eliminating the need to re-establish the operating point, thus eliminating switching setup noise and nonlinear distortion, and improving the noise performance of the oscillator.

[0036] Low temperature drift oscillation core The threshold voltage and charge / discharge current of the oscillator are both generated based on the bandgap reference principle. The first reference voltage is the bandgap reference voltage VR, and the second reference voltage is the transistor emitter-junction voltage VBE3. The difference between the two is VR - VBE3 = VTlnN, where VT is the thermal voltage, which has a positive temperature coefficient; the charge / discharge current... It also has a positive temperature coefficient.

[0037] II. Oscillation Working Principle The logic control unit outputs two-phase non-overlapping control signals, where The core control signal is used, and the working process is divided into a discharge stage and a charging stage: Discharge phase: when When Vc is high, the non-inverting input of the comparator is connected to VBE3, and the charging / discharging capacitor C discharges to ground through the discharge path, causing the capacitor voltage Vc to continuously decrease. When Vc falls below VBE3, the comparator output flips, and the logic control unit... Set to low level to enter the charging phase.

[0038] Charging phase: when When the voltage level is low, VR is connected to the non-inverting input of the comparator, and the current source charges the charging capacitor C, causing Vc to rise continuously. When Vc is higher than VR, the comparator output flips again. Set to high level to return to the discharge phase.

[0039] This process repeats continuously, generating a periodic clock output.

[0040] III. Derivation of Low Temperature Drift Characteristics Let the amplitude of the charging and discharging current be I, the capacitance of the charging and discharging capacitor be C, the charging time be t1, and the discharging time be t2.

[0041] The charging process satisfies: The discharge process satisfies: Combining the expression for charging and discharging current: Substituting the above relationship into the periodic formula T=t1+t2, we get: After canceling out the positive temperature coefficient term, the oscillation period is: Output clock frequency: Therefore, the oscillation frequency is determined solely by the parameters of resistor R1 and capacitor C, and is independent of temperature and power supply voltage. By selecting resistors and capacitors with low temperature drift, a clock output with extremely low temperature drift can be obtained.

[0042] The above description is only for illustrating the concept and specific implementation of the present invention. Those skilled in the art can modify, supplement, or substitute the specific embodiments in a similar manner without departing from the concept or scope of the claims, and all such modifications and additions should fall within the protection scope of the present invention.

Claims

1. A low-temperature drift relaxor oscillator based on dynamic element matching, characterized in that, It includes a charge / discharge current mirror module, a comparator, a logic control unit, a charge / discharge capacitor, a dynamic component matching module, and a virtual voltage storage node; The charge / discharge current mirror module adopts a current equalization structure to generate charging current and discharging current with equal amplitude. The dynamic component matching module is connected to the current source array of the charge / discharge current mirror module and is used to eliminate current source mismatch error through dynamic rotation. The virtual voltage storage node is connected to the switching node of the current mirror and is used to absorb the charge injection generated by the switching, so that the current mirror remains in a saturated working state during the switching process. The first input terminal of the comparator is connected to the plate voltage of the charging and discharging capacitor, and the second input terminal is connected to the first reference voltage and the second reference voltage in a time-division manner; the difference between the first reference voltage and the second reference voltage, as well as the charging and discharging current, all have the same temperature coefficient, so that the frequency of the oscillator output clock has low temperature drift characteristics. The logic control unit generates a switch control signal based on the output signal of the comparator to control the switching of the charging and discharging path and the switching of the reference voltage.

2. The low-temperature drift relaxor oscillator based on dynamic element matching according to claim 1, characterized in that, The current-sharing structure includes a first NMOS transistor and a second NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected and their sources are grounded, and they have the same overdrive voltage and the same drain current amplitude; the drain current of the first NMOS transistor is the charging current, and the drain current of the second NMOS transistor is the discharging current.

3. The low-temperature drift relaxor oscillator based on dynamic component matching according to claim 1, characterized in that, The dynamic component matching module is a dynamic component matching DEM circuit. By periodically changing the access order of the current source array, it can evenly offset the size mismatch and threshold mismatch between the current sources, thereby improving the current matching accuracy.

4. The low-temperature drift relaxor oscillator based on dynamic element matching according to claim 1, characterized in that, The virtual voltage storage node is a passive capacitor node that maintains the drain-source voltage of the current mirror tube at the moment of switching, so that it always works in the saturation region and eliminates switching setup noise.

5. The low-temperature drift relaxor oscillator based on dynamic element matching according to claim 1, characterized in that, The first reference voltage is the bandgap reference voltage VR, and the second reference voltage is the transistor emitter junction voltage VBE3; the difference between the two is a positive temperature coefficient, the charging and discharging current is a positive temperature coefficient, and the oscillation period obtained by dividing the two is only related to the parameters of the resistor and capacitor.

6. The low-temperature drift relaxor oscillator based on dynamic element matching according to claim 5, characterized in that, The charging and discharging currents satisfy the following relationship: in, Thermoelectric voltage, This is the proportionality coefficient. Used as a reference resistor; The difference between the first reference voltage and the second reference voltage satisfies: ; Oscillation period Output clock frequency Where C is the capacitance value of the charging and discharging capacitor.

7. A low-temperature drift relaxation oscillation method based on dynamic element matching, characterized in that, The method, applied to the relaxor oscillator according to any one of claims 1 to 6, comprises: S1. Dynamic component matching technology is used to dynamically rotate the current source array to eliminate current source mismatch error; a current equalization structure is used to generate charging current and discharging current with equal amplitude. S2. When the switch control signal is at the first level, the charging and discharging capacitor discharges through the discharge current, and the second reference voltage is connected to the second input terminal of the comparator; when the voltage of the charging and discharging capacitor is lower than the second reference voltage, the comparator output flips, and the switch control signal switches to the second level. S3. When the switch control signal is at the second level, the charging and discharging capacitor is charged by the charging current, and the second input terminal of the comparator is connected to the first reference voltage; when the voltage of the charging and discharging capacitor is higher than the first reference voltage, the comparator output flips, and the switch control signal switches to the first level. S4. Repeat steps S2 to S3 to output a low-temperature drift clock signal; during the switching process, absorb charge injection through the virtual voltage storage node to maintain the saturated working state of the current mirror.

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