Low threshold adaptive acceleration operational amplifier output voltage setup time control circuit
Patent Information
- Application Number
- CN202610230146.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-26
- Publication Date
- 2026-10-27
AI Technical Summary
[0007]换一个角度说，上述现有技术均存在技术缺陷，比如，动态偏置技术：主要缺点是需要额外的动态偏置电路，运放会工作在两种不同静态工作点，在切换时输出电压会发生跳变，牺牲了运放的面积和功耗，不适用于低成本低功耗的应用领域；又如动态补偿技术：主要缺点是需要额外的检测电路、开关和控制逻辑，增加了设计的复杂性和版图面积，当负载高速连续变化时，补偿电容频繁切换反而引入了大量失真和噪声
[0014]本发明所提供的加速电路使输出电压建立速度提高了75%、对输出电压的恢复时间比无加速电路时提高了70%。本发明的加速电路成本低且可以达到比较好的技术效果，有良好市场场景。
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, particularly semiconductor chip technology, especially power management and power devices, and high-speed control systems. Specifically, it relates to accelerated operational amplifiers, and more specifically to control circuits for accelerating the output voltage settling time of operational amplifiers. Background Technology
[0002] Due to the presence of the output stage load capacitor, the op-amp must have a sufficiently fast response speed without increasing power consumption. Currently, the main approach to reducing the op-amp's settling time to the load is to reduce the large-signal settling time, which is primarily determined by the input stage tail current, compensation capacitors, and the output stage load capacitor.
[0003] Dynamic bias technology: During large signal transients, the tail current is increased to improve the slew rate, allowing the op-amp to charge and discharge the load capacitor more quickly, thus accelerating the establishment of the output voltage; after the output stabilizes, it switches to a small bias current to optimize the noise and power consumption of the op-amp.
[0004] Dynamic compensation technology: Dynamically detects changes in load current to switch the size of the compensation capacitor, so that the op-amp can obtain a larger bandwidth and a faster settling time with sufficient phase margin.
[0005] Figure 1 It is a traditional two-stage operational amplifier topology. The first stage is an op-amp with PMOS differential input and common-source cascode load output, and the second stage is a Class AB common-source output with a floating current source. Figure 1 Cmp and Cmn are Miller compensation capacitors, which provide phase compensation when the op-amp operates in a closed-loop negative feedback system to drive a capacitive load CL. Their specific structure is as follows: Figure 2 As shown. The non-inverting input VIP is the reference voltage, and the inverting input VIN is shorted to the output voltage VOUT, forming a negative feedback system. The high gain of the two-stage operational amplifier achieves VOUT=VIP. The underlying principle is essentially the operational amplifier's ability to amplify differential-mode signals and suppress common-mode signals. Assuming VOUT is much smaller than VIP, the tail current I0 flows entirely through the power transistor MP1, and is completely mirrored through the dynamic current mirrors NM3 and NM4. Figure 1 At point NG, discharge is applied to points NG and PG, causing power transistor MP9 to turn on quickly and charge the load, increasing the output voltage VOUT until VOUT = VIP, at which point the op-amp is in a steady state.
[0006] Therefore, if a step voltage occurs at the non-inverting input VIP or the output voltage VOUT changes, it indicates that... Figure 1The speed at which the voltages at the NG and PG points are established determines the establishment speed or recovery time of VOUT. The speed at which the voltages at the NG and PG points are established is limited by the tail current I0 transistor. To drive the load quickly, the static power consumption of the tail current I0 will inevitably increase. Therefore, this patent uses a comparator to detect the voltage difference between the input and output and controls the charging and discharging speeds of the NG and PG points to accelerate the establishment of VOUT, thereby accelerating the drive speed of the load while ensuring low power consumption.
[0007] In other words, all of the above-mentioned existing technologies have technical defects. For example, dynamic bias technology: the main drawback is that it requires an additional dynamic bias circuit. The op-amp will operate at two different static operating points, and the output voltage will jump when switching, sacrificing the op-amp's area and power consumption, making it unsuitable for low-cost and low-power applications. Another example is dynamic compensation technology: the main drawback is that it requires additional detection circuits, switches, and control logic, increasing the complexity of the design and the layout area. When the load changes rapidly and continuously, the frequent switching of the compensation capacitor introduces a lot of distortion and noise.
[0008] Therefore, the technical problem to be solved by the present invention is to accelerate the driving speed of the load without significantly increasing the cost, while not significantly increasing the circuit area of the operational amplifier. Summary of the Invention
[0009] To address the technical deficiencies of existing technologies, the purpose of this invention is to provide a low-threshold adaptive accelerated operational amplifier output voltage settling time control circuit. This circuit is used in a two-stage accelerated operational amplifier to control the output voltage settling time. It includes a first stage operational amplifier with PMOS differential input and cascode load output, and a second stage common-source AB output circuit. The second stage common-source AB output circuit includes Miller compensation capacitors Cmp and Cmn. The compensation capacitor Cmp affects the voltage settling time at its circuit connection point PG, and the compensation capacitor Cmn affects the voltage settling time at its circuit connection point NG. The invention is characterized by comprising a first positive acceleration circuit and a first negative acceleration circuit between the power supply of the two-stage accelerated operational amplifier and the first stage operational amplifier having a PMOS differential pair input and a common-source common-gate load output, and a positive hysteresis comparator and a negative hysteresis comparator after the second stage of the two-stage accelerated operational amplifier having a Class AB common-source output circuit; wherein the first positive acceleration circuit is at least used to accelerate the rise time of the output voltage VOUT of the accelerated transport amplifier to the target voltage; and the first negative acceleration circuit is at least used to accelerate the fall time of the output voltage VOUT of the accelerated transport amplifier to the target voltage.
[0010] Preferably, the first forward acceleration circuit includes at least a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, and a twelfth NMOS transistor MN12. The source of the twelfth NMOS transistor MN12 is grounded, its drain is connected to its gate and is also connected to the drain of the twelfth PMOS transistor MP12. The gate of the twelfth PMOS transistor MP12 is connected to the output of the forward hysteresis comparator CMP+. The source of the twelfth PMOS transistor MP12 is connected to the gate of MP9 in the transport amplifier, forming a discharge path from point PG to ground. The source of the tenth PMOS transistor MP10 is connected to a power supply, its gate is connected to a fixed bias voltage, and its drain is connected to the source of the eleventh PMOS transistor MP11. The gate of the eleventh PMOS transistor MP11 is connected to the output of the forward hysteresis comparator CMP+.
[0011] Preferably, the first negative acceleration circuit includes at least a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a thirteenth PMOS transistor MP13, and a thirteenth NMOS transistor MN13. The source of the thirteenth PMOS transistor MP13 is connected to a power supply, its drain and gate are connected together and connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the output of the negative hysteresis comparator CMP-, and the source of the thirteenth NMOS transistor MN13 is connected to the gate of MN9 in the transport amplifier, forming a charging path from the NG point to ground. The source of the tenth NMOS transistor MN10 is connected to a power supply, its gate is connected to a fixed bias voltage, its drain is connected to the source of the eleventh NMOS transistor MN11, and the gate of the eleventh NMOS transistor MN11 is connected to the output of the negative hysteresis comparator CMP-.
[0012] Preferably, the positive hysteresis comparator includes at least a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5. The first NMOS transistor M1 has its source grounded, its gate connected to a fixed bias voltage, and its drain connected to the sources of the second NMOS transistor M2 and the third NMOS transistor M3. The second NMOS transistor M2 has its gate connected to a non-inverting input voltage (+), and its drain connected to the gate and drain of the fourth PMOS transistor M4. The source of the fourth PMOS transistor M4 is connected to a power supply. The third NMOS transistor M3 has its gate connected to a negative input voltage (-), and its drain connected to the drain of the fifth PMOS transistor M5. The gate of the fifth PMOS transistor M5 is connected to the gate of the fourth PMOS transistor M4, and its source is connected to a power supply.
[0013] Preferably, the negative hysteresis comparator includes at least a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. The source of the sixth PMOS transistor M6 is connected to a power supply, its gate is connected to a fixed bias voltage, and its drain is connected together with the sources of the seventh PMOS transistor M7 and the eighth PMOS transistor M8. The gate of the seventh PMOS transistor M7 is connected to a non-inverting input voltage (+), and its drain is connected to the gate and drain of the ninth NMOS transistor M9. The source of the ninth NMOS transistor M9 is grounded. The gate of the eighth PMOS transistor M8 is connected to a negative input voltage (-), and its drain is connected to the drain of the tenth NMOS transistor M10. The gate of the tenth NMOS transistor M10 is connected to the gate of the ninth NMOS transistor M9, and its source is connected to a power supply.
[0014] The acceleration circuit provided by this invention increases the output voltage build-up speed by 75% and the output voltage recovery time by 70% compared to when there is no acceleration circuit. The acceleration circuit of this invention is low-cost and achieves good technical results, making it suitable for the market. Attached Figure Description
[0015] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a two-stage operational amplifier topology in the prior art is shown; Figure 2 It shows Figure 1 The diagram shown is a schematic of a system structure in the prior art where a two-stage operational amplifier operates under closed-loop negative feedback. Figure 3 A schematic diagram of the circuit structure of the low-threshold adaptive accelerated operational amplifier output voltage settling time control circuit according to a first embodiment of the present invention is shown. Figure 4 A schematic diagram of a positive hysteresis comparator CMP+ topology for accelerating the rise of the output voltage in a low-threshold adaptive accelerated operational amplifier output voltage settling time control circuit according to a first embodiment of the present invention is shown. Figure 5 A schematic diagram of a negative hysteresis comparator (CMP) topology for accelerating the drop in output voltage is shown in the low-threshold adaptive accelerated operational amplifier output voltage settling time control circuit according to a first embodiment of the present invention. Figure 6A schematic diagram showing the comparison of the settling time of the low threshold adaptive accelerated operational amplifier output voltage control circuit provided by the present invention with that of the accelerated operational amplifier of the prior art when the load voltage is driven positively is presented. Figure 7 A schematic diagram comparing the settling time of the low-threshold adaptive accelerated operational amplifier output voltage control circuit provided according to the present invention with that of the accelerated operational amplifier in the prior art when the load voltage is driven negatively is shown; and Figure 8 A schematic diagram showing a comparison of the output voltage settling time control circuit of the low threshold adaptive accelerated operational amplifier provided according to the present invention with the output voltage recovery time of the accelerated operational amplifier under load sink current is presented. Detailed Implementation
[0016] To better illustrate the technical solution of this invention, the invention will be further described below with reference to the accompanying drawings. (Reference) Figure 3 The illustrated embodiment presents an innovative structure for a two-stage operational amplifier with fully differential input and floating Class AB output in the prior art. Specifically, it demonstrates the circuit structure of a low-threshold adaptive acceleration operational amplifier output voltage settling-time control circuit according to the first embodiment of the present invention. As can be seen from the preceding analysis, Figure 1 The settling time of the NG and PG point voltages is affected by the values of the Miller compensation capacitors Cmp and Cmn. The larger Cmp and Cmn are, the longer the charging and discharging time of the tail current I0. Power transistors MP9 and MN9 are difficult to turn on quickly, slowing down the settling time of VOUT. To address this issue, this patent incorporates a positive drive load acceleration circuit consisting of a positive hysteresis comparator CMP+, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the twelfth NMOS transistor MN12 into the conventional operational amplifier. This accelerates the settling time of the output voltage VOUT to the target voltage. Additionally, a negative drive load acceleration circuit consisting of a negative hysteresis comparator CMP-, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, MP13, and the thirteenth NMOS transistor MN13 accelerates the settling time of the output voltage VOUT to the target voltage.
[0017] In the forward drive load acceleration circuit, the source of the twelfth NMOS transistor MN12 is grounded, the drain and the gate are connected together and connected to the drain of the twelfth PMOS transistor MP12, the gate of the twelfth PMOS transistor MP12 is connected to the output terminal of the forward hysteresis comparator CMP+, and the source is connected to the gate PG of MP9, forming a discharge path from the PG point to the ground, and the twelfth NMOS transistor MN12 functions to limit current; when VIP-VOUT>>Vhys+, the forward hysteresis comparator CMP+ outputs a low level, the twelfth PMOS transistor MP12 is fully turned on, a discharge current I1 is generated from the twelfth PMOS transistor MP12 to the twelfth NMOS transistor MN12 to discharge the PG point, pulling the PG voltage down to the ground, the VGS voltage of the power transistor MP9 is very large, generating a large output current to accelerate the rising speed of VOUT and speed up the settling time of the operational amplifier in the initial stage.
[0018] When VOUT rises to a hysteresis voltage Vhys+ lower than VIP, the output voltage of the forward hysteresis comparator CMP+ increases, and the twelfth PMOS transistor MP12 is turned off, at which point the initial acceleration circuit fails. To solve this problem, a low-threshold acceleration circuit is added, which is composed of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11. The source of the tenth PMOS transistor MP10 is connected to the power supply, the gate is connected to a fixed bias voltage, the drain is connected to the source of the eleventh PMOS transistor MP11, the gate of the eleventh PMOS transistor MP11 is connected to the output terminal of the forward hysteresis comparator CMP+, and the drain is connected to point P; when VIP-VOUT=Vhys+, the forward hysteresis comparator CMP+ outputs V+<VDD-VTH, turning on the eleventh PMOS transistor MP11, a charging current I2 is generated from the power supply through the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 to flow to point P, I2 is mirrored by the dynamic current mirrors MN3 and MN4 to discharge the NG and PG points, so that the power transistor MP9 is quickly turned on, generating a larger charging current for the load and accelerating the settling of VOUT.
[0019] When VOUT rises to a hysteresis voltage Vhys+ higher than VIP, the output of the forward hysteresis comparator CMP+ is VDD, turning off the initial acceleration circuit and the low-threshold acceleration circuit, which will not affect the static operating point of the operational amplifier in the steady state, and there is no additional power consumption. The hysteresis characteristic of the hysteresis comparator not only realizes the adaptive turn-on and turn-off of the acceleration circuit, but also the existence of the hysteresis threshold prevents the noise fluctuation of the output voltage VOUT from causing erroneous turn-on and turn-off of the acceleration circuit, improving the circuit reliability.
[0020] Under the action of the acceleration circuit, when the load voltage is driven in the forward direction, VOUT will quickly rise to the voltage of VIP-Vhys+, and when the load voltage is driven in the negative direction, VOUT will quickly fall to the voltage of VIP+Vhys-, the hysteresis comparator such as Figure 4 as shown in the figure, the magnitudes of the hysteresis voltages Vhys+ and Vhys- can be set to 100 mV through the ratio of the differential pair transistors. As the operational amplifier enters the small-signal state and starts to operate stably, VOUT infinitely approaches the reference voltage VIP, and the positive and negative load driving acceleration circuits are adaptively turned off, which does not affect the working state of the operational amplifier in the stable state and causes no additional power consumption.
[0021] In addition, when the operational amplifier switches the load, if VOUT < VIP-Vhys+ due to load current sinking or VOUT > VIP+Vhys- due to load current sourcing, the acceleration circuit of the present patent will be adaptively turned on to accelerate the recovery time or settling time of the operational amplifier.
[0022] Figure 6 and Figure 7 are respectively the comparison of the settling time of the output voltage VOUT with and without the acceleration circuit when the input voltage undergoes a positive step voltage and a negative step voltage in the present patent. It can be found that the acceleration circuit proposed by the present patent increases the settling speed of the output voltage by 75%; Figure 8 shows the comparison of results of adaptive turn-on and acceleration of the load driving acceleration circuit when the operational amplifier switches the load after the load driving acceleration circuit is adaptively turned off when the operational amplifier drives the load to a stable voltage value, and the output voltage reaches the threshold detection voltage due to the sinking and sourcing current. It can be found that the recovery time of the output voltage of the present patent is 70% shorter than that without the acceleration circuit.
[0023] The specific embodiments of the present invention are described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various variations or modifications within the scope of the claims, which do not affect the essential content of the present invention.
Claims
1. A low-threshold adaptive accelerated operational amplifier output voltage settling time control circuit, used to control the output voltage settling time in a two-stage accelerated operational amplifier, comprising a first stage operational amplifier with PMOS differential pair input and common-source common-gate load output, and a second stage common-source stage output circuit of class AB, wherein the second stage common-source stage output circuit includes Miller compensation capacitors Cmp and Cmn, wherein the compensation capacitor Cmp affects the voltage settling time at its circuit connection point PG, and the compensation capacitor Cmn affects the voltage settling time at its circuit connection point NG, characterized in that... A first positive acceleration circuit and a first negative acceleration circuit are provided between the power supply of the two-stage accelerated operational amplifier and the first stage operational amplifier which has a PMOS differential pair input and a common source cascode load output. A positive hysteresis comparator and a negative hysteresis comparator are provided after the second stage of the two-stage accelerated operational amplifier which has a Class AB common source stage output circuit. Wherein, the first positive acceleration circuit is used at least to accelerate the rise time of the output voltage VOUT of the accelerated transport amplifier to the target voltage; the first negative acceleration circuit is used at least to accelerate the fall time of the output voltage VOUT of the accelerated transport amplifier to the target voltage.
2. The control circuit according to claim 1, characterized in that, The first forward acceleration circuit includes at least a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, and a twelfth NMOS transistor MN12. The source of the twelfth NMOS transistor MN12 is grounded, its drain is connected to its gate and is also connected to the drain of the twelfth PMOS transistor MP12. The gate of the twelfth PMOS transistor MP12 is connected to the output of the forward hysteresis comparator CMP+. The source of the twelfth PMOS transistor MP12 is connected to the gate of MP9 in the transport amplifier, forming a discharge path from point PG to ground. The source of the tenth PMOS transistor MP10 is connected to a power supply, its gate is connected to a fixed bias voltage, and its drain is connected to the source of the eleventh PMOS transistor MP11. The gate of the eleventh PMOS transistor MP11 is connected to the output of the forward hysteresis comparator CMP+.
3. The control circuit according to claim 1, characterized in that, The first negative acceleration circuit includes at least a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a thirteenth PMOS transistor MP13, and a thirteenth NMOS transistor MN13. The source of the thirteenth PMOS transistor MP13 is connected to a power supply, its drain and gate are connected together and connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the output of the negative hysteresis comparator CMP-, and the source of the thirteenth NMOS transistor MN13 is connected to the gate of MN9 in the transport amplifier, forming a charging path from the NG point to ground. The source of the tenth NMOS transistor MN10 is connected to a power supply, its gate is connected to a fixed bias voltage, its drain is connected to the source of the eleventh NMOS transistor MN11, and the gate of the eleventh NMOS transistor MN11 is connected to the output of the negative hysteresis comparator CMP-.
4. The control circuit according to any one of claims 1 to 3, characterized in that, The positive hysteresis comparator includes at least a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5. The first NMOS transistor M1 has its source grounded, its gate connected to a fixed bias voltage, and its drain connected to the sources of the second NMOS transistor M2 and the third NMOS transistor M3. The second NMOS transistor M2 has its gate connected to a non-inverting input voltage (+), and its drain connected to the gate and drain of the fourth PMOS transistor M4. The source of the fourth PMOS transistor M4 is connected to a power supply. The third NMOS transistor M3 has its gate connected to a negative input voltage (-), and its drain connected to the drain of the fifth PMOS transistor M5. The gate of the fifth PMOS transistor M5 is connected to the gate of the fourth PMOS transistor M4, and its source is connected to a power supply.
5. The control circuit according to claim 4, characterized in that, The negative hysteresis comparator includes at least a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. The source of the sixth PMOS transistor M6 is connected to a power supply, its gate is connected to a fixed bias voltage, and its drain is connected together with the sources of the seventh PMOS transistor M7 and the eighth PMOS transistor M8. The gate of the seventh PMOS transistor M7 is connected to a non-inverting input voltage (+), and its drain is connected to the gate and drain of the ninth NMOS transistor M9. The source of the ninth NMOS transistor M9 is grounded. The gate of the eighth PMOS transistor M8 is connected to a negative input voltage (-), and its drain is connected to the drain of the tenth NMOS transistor M10. The gate of the tenth NMOS transistor M10 is connected to the gate of the ninth NMOS transistor M9, and its source is connected to a power supply.