High anti-interference operational amplifier circuit

Abstract

The application discloses a kind of high anti-interference operational amplifier circuit, belong to analog integrated circuit technical field, the circuit includes self-bias module, current detection module, voltage amplification module, output stage module and frequency compensation module.Current detection module uses common-source common-gate tail current source, and voltage amplification module constructs folding common-source common-gate topology, can effectively isolate high dv / dt common mode noise and strictly clamp drain potential.Voltage amplification module uses active load topology, in combination with the Miller compensation network of frequency compensation module, ensure sufficient phase margin and eliminate self-excitation oscillation.Output stage module realizes dynamic AB class push-pull drive by multistage active current mirror, gives operational amplifier high voltage slew rate and sub-microsecond transient response.Self-bias module constructs PVT adaptive reference source, dynamically locks transconductance and suppresses secondary misalignment drift.The application greatly improves the high-frequency common-mode rejection ratio, transient response speed and full-boundary detection accuracy of circuit.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a high anti-interference operational amplifier circuit. Background Technology

[0002] With the rapid development of high-voltage power semiconductor technology, operational amplifier circuits, as core analog units, are widely used in key functional modules such as overcurrent detection, short-circuit protection (e.g., DSAT protection), and current sampling feedback in the driving and protection of high-voltage power devices such as intelligent power modules (IPMs), motor drives, and new energy inverters. Especially within the gate drive chips of IGBTs and MOSFETs, the response speed and anti-interference capability of operational amplifier circuits directly determine the safety boundary of the entire power system.

[0003] However, traditional operational amplifier circuits often suffer from the following problems in complex electromagnetic environments involving high voltage and high current switching: 1. During the rapid switching process of high-voltage power devices, the drain voltage generates an extremely high transient rate of change (high dv / dt). Traditional operational amplifiers typically employ a single-transistor or ordinary drain-load tail current source structure, resulting in low high-frequency output impedance. Under high dv / dt conditions, high-voltage noise can easily couple to the common source of the input differential pair transistors through internal parasitic capacitances, disrupting the symmetry of the differential topology. This leads to a severe degradation of the circuit's high-frequency common-mode rejection ratio (CMRR), generating significant common-mode to differential-mode noise, which in turn causes overcurrent or short-circuit protection circuits to malfunction.

[0004] 2. To achieve sufficient detection gain under high-voltage conditions, traditional circuits often rely on high-resistance resistor networks or multi-stage amplification topologies. This not only significantly increases the chip's static power consumption and footprint but also introduces multiple useless poles, causing a sharp decrease in the op-amp's phase margin and making it highly susceptible to self-oscillation. Increasing the compensation capacitor to suppress oscillation directly sacrifices the op-amp's slew rate, resulting in an inability to achieve a fast transient response in the event of a short-circuit fault, thus delaying the activation time of the protection logic.

[0005] 3. Traditional operational amplifiers have a relatively simple bias network structure, and the static operating points of their internal transistors are highly sensitive to power supply voltage fluctuations, process variations, and operating temperature changes. When the internal junction temperature of the driver chip rises sharply due to high-power switching, the input offset voltage and open-loop gain will drift significantly, resulting in poor current detection accuracy and short-circuit protection threshold stability, thus reducing the overall reliability of the system. Summary of the Invention

[0006] One object of the present invention is to provide a high anti-interference operational amplifier circuit, including a self-biasing module, a current detection module, a voltage amplification module, an output stage module, and a frequency compensation module; The current detection module includes a differential input pair transistor of a first conductivity type and a common-source common-gate tail current source structure cascaded to the source of the differential input pair transistor; the common-source common-gate tail current source structure is connected between the first power supply terminal and the common source of the differential input pair transistor, and its gate is electrically connected to the self-biasing module to receive a first set of bias voltages; the gates of the differential input pair transistors serve as the first input terminal and the second input terminal of the operational amplifier circuit, respectively, and the drains of the differential input pair transistors serve as the first output terminal and the second output terminal of the current detection module, respectively. The voltage amplification module includes a first input terminal, a second input terminal, and a single-ended output node. Internally, the voltage amplification module incorporates a folded common-gate input transistor structure of the second conductivity type, a cascaded bias transistor structure, and an active current mirror network. The first and second input terminals of the voltage amplification module are electrically connected to the first and second output terminals of the current detection module, respectively, to form a folded common-source common-gate topology at the first and second input terminals. The gates of the folded common-gate input transistor structure, the cascaded bias transistor structure, and the active current mirror network are electrically connected to the self-biasing module to receive a second set of bias voltages, which are used to convert the differential current output by the current detection module into a single-ended voltage signal and output it from the single-ended output node. The self-biasing module includes a bias cascade branch and a reference resistor that match the current detection module and the voltage amplification module, for generating multiple bias voltages, which are supplied to the current detection module and the voltage amplification module respectively via the first set of bias voltages and the second set of bias voltages. The input terminal of the output stage module is electrically connected to the single-ended output node of the voltage amplification module, its bias terminal is electrically connected to the self-biasing module, and its output terminal serves as the final signal output terminal of the operational amplifier circuit. The frequency compensation module is connected between the single-ended output node of the voltage amplification module and the final signal output terminal of the output stage module.

[0007] Furthermore, the frequency compensation module includes a compensation capacitor and a compensation resistor connected in series; the first end of the compensation capacitor is electrically connected to the single-ended output node of the voltage amplification module, and the second end of the compensation capacitor is electrically connected to the final signal output terminal of the output stage module through the compensation resistor.

[0008] Furthermore, the first conductivity type is P-type, and the second conductivity type is N-type; the first power supply terminal is the power supply voltage VCC, and the second power supply terminal is the ground voltage VSS; The current detection module includes transistors MP1, MP2, MP3, and MP4: The transistors MP1 and MP2 constitute the differential input pair transistors, with their sources commonly connected to node D1, and their gates serving as the first and second input terminals of the operational amplifier circuit, respectively. The drain of transistor MP1 is connected to node D3 in the voltage amplifier module, and the drain of transistor MP2 is connected to node D2 in the voltage amplifier module. The cascaded transistors MP3 and MP4 form the common-source common-gate tail current source structure. The source of transistor MP3 is electrically connected to the first power supply terminal VCC, the drain is electrically connected to the source of transistor MP4, and the gate is used to receive the bias voltage vb1. The drain of transistor MP4 is electrically connected to the node D1, and the gate is used to receive the bias voltage vb2 in the bias voltage.

[0009] Furthermore, the self-biasing module includes transistors MP5, MP6, MP7, MP8, MN1, MN2, and resistor R1. The sources of transistors MP5 and MP7 are both electrically connected to the first power supply terminal VCC. The gate and drain of transistor MP7 are shorted to node D4 to output bias voltage vb1. The source of transistor MP6 is electrically connected to the drain of transistor MP5, the source of transistor MP8 is electrically connected to the drain of transistor MP7, the gate and drain of transistor MP8 are shorted at node D5 to output bias voltage vb2, and the drain of transistor MP8 is electrically connected to the second power supply terminal VSS through the first resistor R1. The drain and gate of transistor MN1 are shorted at node D6 and electrically connected to the drain of transistor MP6 to output bias voltage vb3. The drain and gate of transistor MN2 are shorted at node D7 to output bias voltage vb4, and node D7 is electrically connected to the source of transistor MN1. The source of transistor MN2 is electrically connected to the second power supply terminal VSS.

[0010] Furthermore, the voltage amplification module includes transistors MP9, MP10, MP11, MP12, MN3, MN4, MN5, and MN6. The source of transistor MN3 is electrically connected to node D2, the source of transistor MN4 is electrically connected to node D3, and the gates of transistors MN3 and MN4 are both electrically connected to node D6 of the self-biased module to receive the bias voltage vb3. The drain of transistor MN5 is electrically connected to node D2, the drain of transistor MN6 is electrically connected to node D3, the sources of transistors MN5 and MN6 are both electrically connected to the second power supply terminal VSS, and their gates are both electrically connected to node D7 of the self-biased module to receive the bias voltage vb4. The sources of transistors MP9 and MP10 are both electrically connected to the first power supply terminal VCC, and their gates are both electrically connected to node D13, and node D13 is electrically connected to the drain of transistor MP9. The source of transistor MP11 is electrically connected to the drain of transistor MP9, the source of transistor MP12 is electrically connected to the drain of transistor MP10, the gates of transistors MP11 and MP12 are electrically connected to node D14, the drain of transistor MP11 is electrically connected to the drain of transistor MN3 and is also connected to node D14, the drain of transistor MP12 is electrically connected to the drain of transistor MN4, and their common connection terminal serves as the single-ended output node D8.

[0011] Furthermore, the output stage module includes transistors MP13 to MP19, transistors MN7 to MN13, and resistors R2 and a third resistor R3; The gate of the transistor MP13 is used to receive the bias voltage vb1, the source is electrically connected to the first power supply terminal VCC, and the drain is electrically connected to node D9. The gates of transistors MN7 and MN8 are both electrically connected to node D9, the drain of transistor MN7 is electrically connected to node D9, and the drain of transistor MN8 is electrically connected to node D10; the source of transistor MN7 is electrically connected to the source of transistor MP15, and the source of transistor MN8 is electrically connected to the source of transistor MP16. The sources of transistors MP14 and MP19 are both electrically connected to the first power supply terminal VCC, and their gates are both electrically connected to the node D10; the drain of transistor MP14 is electrically connected to the node D10. The gates of transistors MP16 and MN10 are both electrically connected to the single-ended output node D8; the drain of transistor MP16 is electrically connected to the second power supply terminal VSS, the drain of transistor MN10 is electrically connected to the first power supply terminal VCC, and the source of transistor MN10 is electrically connected to the source of transistor MP18. The gates of transistors MP17 and MP18 are both electrically connected to node D11; the drain of transistor MP17 is electrically connected to node D11, and its source is electrically connected to the source of transistor MN9; the drain of transistor MP18 is electrically connected to node D12. The gate of the transistor MN11 is used to receive the bias voltage vb4, the drain is electrically connected to the node D11, and the source is electrically connected to the second power supply terminal VSS. The sources of transistors MN12 and MN13 are both electrically connected to the second power supply terminal VSS, and their gates are both electrically connected to the node D12; the drain of transistor MN12 is electrically connected to the node D12, the drain of transistor MN13 is electrically connected to the drain of transistor MP19, and their common connection node serves as the signal output terminal of the output stage module. The drain of transistor MN9 is electrically connected to the first power supply terminal VCC; the first terminal of resistor R2 is electrically connected to the first power supply terminal VCC, the second terminal of resistor R2 is electrically connected to the first terminal of resistor R3, and the second terminal of resistor R3 is electrically connected to the second power supply terminal VSS; the gate of transistor MP15 and the gate of transistor MN9 are both electrically connected to the common connection node of resistors R2 and R3.

[0012] Furthermore, the first conductivity type is N-type, and the second conductivity type is P-type; the first power supply terminal is ground voltage VSS, and the second power supply terminal is power supply voltage VCC; The current detection module includes transistors MN101, MN102, MN103, and MN104: The transistors MN101 and MN102 constitute the differential input pair transistors, with their sources commonly connected to node D101, and their gates serving as the first and second input terminals of the operational amplifier circuit, respectively. The drain of transistor MN101 is connected to the folded node D103 of the voltage amplifier module, and the drain of transistor MN102 is connected to the folded node D102 of the voltage amplifier module. The cascaded transistors MN103 and MN104 form the common-source common-gate tail current source structure. The source of transistor MN104 is electrically connected to the first power supply terminal VSS, and its gate is used to receive the bias voltage vb14. The source of transistor MN103 is connected to the drain of transistor MN104, and its drain is connected to the node D101. Its gate is used to receive the bias voltage vb13.

[0013] Furthermore, the self-biasing module includes transistors MP112, MP113, MN116, MN117, MN118, MN119, and resistor R14. The source of transistor MP112 is connected to the second power supply terminal VCC, and the drain is connected to the source of transistor MP113. The gate and drain of transistor MP112 are shorted at node D104 to output bias voltage vb11. The gate and drain of the transistor MP113 are shorted at node D105 to output a bias voltage vb12, and the drain of the transistor MP113 is electrically connected to the drain of the transistor MN118. The gates of transistors MN116 and MN118 are connected to a common node D106, and the drain and gate of transistor MN116 are shorted to node D106 to output a bias voltage vb13. The gates of transistors MN117 and MN119 are connected to a common node D107, and the drain and gate of transistor MN117 are shorted to node D107 to output a bias voltage vb14. The source of transistor MN116 is connected to the drain of transistor MN117, and the source of transistor MN117 is connected to the first power supply terminal VSS; the source of transistor MN118 is connected to the drain of transistor MN119, and the source of transistor MN119 is connected to the first power supply terminal VSS; the resistor R14 is connected between the second power supply terminal VCC and the node D106.

[0014] Furthermore, the voltage amplification module includes transistors MP101, MP102, MP103, MP104, MN105, MN106, MN107, and MN108. The sources of transistors MP103 and MP104 are electrically connected to the folded nodes D102 and D103 respectively to receive the output signal of the current detection module. Their gates are both connected to the bias voltage vb12, and their drains are electrically connected to the drains of transistors MN105 and MN106 respectively. The sources of transistors MP101 and MP102 are both connected to the second power supply terminal VCC, and their drains are respectively connected to the sources of transistors MP103 and MP104. Their gates are both connected to the bias voltage vb11. The transistors MN105 and MN106 form a first current mirror, with their gates connected to the node D113 where the drain of the transistor MN105 is located, and the drain of the transistor MN106 connected to the single-ended output node D108. The transistors MN107 and MN108 form a second current mirror, with their sources connected to the first power supply terminal VSS, their drains connected to the sources of the transistors MN105 and MN106 respectively, and their gates connected to the node D114 where the drain of the transistor MN107 is located.

[0015] Furthermore, the output stage module includes transistors MP105, MP106, MP107, MP108, MP109, MP110, MP111, MN109, MN110, MN111, MN112, MN113, MN114, MN115, and resistors R11 and R12; The source of the transistor MP105 is connected to the second power supply terminal VCC, the gate is used to receive the bias voltage vb11, and the drain is connected to node D109. The drain of transistor MN113 is connected to node D111, the source is connected to the first power supply terminal VSS, and the gate is used to receive the bias voltage vb14; the gates of transistors MP108 and MN112 are both electrically connected to the single-ended output node D108. The transistors MN109 and MN110 constitute a first active current mirror, with their gates connected to node D109. The drain of transistor MN109 is shorted to its gate at node D109, and the drain of transistor MN110 is connected to node D110. The source of the transistor MP106 is connected to the second power supply terminal VCC, and the drain and gate are shorted to the node D110. The source of transistor MP107 is connected to the source of transistor MN109, the drain is connected to the first power supply terminal VSS, and the gate is electrically connected to the common connection node of resistors R11 and R12. The source of transistor MP108 is connected to the source of transistor MN110, and the drain is connected to the first power supply terminal VSS. The drain of transistor MN111 is connected to the second power supply terminal VCC, the gate is electrically connected to the common connection node of resistors R11 and R12, and the source is connected to the source of transistor MP109. The drain of transistor MN112 is connected to the second power supply terminal VCC, and the source is connected to the source of transistor MP110; The transistors MP109 and MP110 constitute a second active current mirror, with their gates connected to the node D111. The drain of the transistor MP109 is shorted to the gate of the node D111, and the drain of the transistor MP110 is connected to the node D112. The drain and gate of the transistor MN114 are shorted to the node D112, and the source is connected to the first power supply terminal VSS. The source of transistor MP111 is connected to the second power supply terminal VCC, and the gate is electrically connected to the node D110; the source of transistor MN115 is connected to the first power supply terminal VSS, and the gate is electrically connected to the node D112. The drain of transistor MP111 is electrically connected to the drain of transistor MN115 to form a common output terminal, which serves as the signal output terminal of the output stage module. The first end of resistor R11 is electrically connected to the second power supply terminal VCC, the second end of resistor R11 is electrically connected to the first end of resistor R12, and the second end of resistor R12 is electrically connected to the first power supply terminal VSS.

[0016] The present invention has the following beneficial effects: This invention employs a cascaded common-source cascode tail current source structure in the current detection module. This structure significantly improves the high-frequency output impedance of the tail current source, effectively isolating common-mode noise coupled in through parasitic capacitance during rapid switching (high dv / dt) of high-voltage power devices. By constructing the current detection module and voltage amplification module as a folded common-source cascode topology, the drain potential of the input differential pair transistors is strictly clamped, thereby suppressing the conversion of high-frequency common-mode noise into differential-mode signals and significantly reducing the probability of malfunctions in subsequent protection logic.

[0017] The voltage amplification module of this invention employs a single-stage folded cascode active load topology, which reduces the number of poles in the main signal path while ensuring extremely high open-loop gain. Combined with the Miller compensation network of the frequency compensation module, which introduces dominant poles and zeros internally, it ensures sufficient phase margin in the closed-loop state and completely eliminates self-oscillation. Simultaneously, the output stage module implements a dynamic Class AB push-pull drive topology through multi-stage active current mirroring. This topology maintains extremely low power consumption in static conditions but can provide a large dynamic charging and discharging current to the load during transient input transitions, giving the op-amp an extremely high slew rate and ensuring a sub-microsecond transient response in the event of overcurrent or short-circuit faults.

[0018] The self-biasing module of this invention utilizes a cascaded current mirror network in conjunction with a reference resistor to construct a self-biasing reference source with PVT (production process, operating voltage, operating temperature) adaptive capability. This source can generate multiple precise bias voltages that adaptively slide with temperature and process deviations, accurately supplying the preceding current sensing and voltage amplification modules. This adaptive biasing mechanism ensures that the transconductance of the operational amplifier's core transistor is primarily determined by the reference resistor within the module, achieving dynamic locking and trend compensation between the core transconductance and the static operating point across the entire temperature and process domain. This not only stabilizes the circuit's open-loop gain and system bandwidth but also overcomes the bottleneck of severe operating point mismatch and exit from the saturation region caused by temperature under traditional biasing. It effectively suppresses secondary offset drift in the circuit, ensuring that the threshold accuracy of current sampling and short-circuit protection remains highly stable even when the chip operates at high power, junction temperature rises sharply, or power supply voltage fluctuates widely. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an operational amplifier circuit provided in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of an operational amplifier circuit based on a P-type input folded common-source cascode according to Embodiment 1 of the present invention.

[0021] Figure 3 This is a schematic diagram of an operational amplifier circuit based on N-type input folded common source cascode according to Embodiment 1 of the present invention.

[0022] In the diagram: 210, current detection module; 220, voltage amplification module; 230, output stage module; 240, frequency compensation module; 250, self-biasing module. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] In this application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. For example, the first terminal, second terminal, and control terminal of a PMOS transistor can be the source, drain, and gate (i.e., the control terminal), respectively, and the first terminal, second terminal, and control terminal of an NMOS transistor can be the drain, source, and gate, respectively.

[0025] Reference Figure 1The present invention discloses an operational amplifier circuit, comprising: a current detection module 210, a voltage amplification module 220, an output stage module 230, a frequency compensation module 240, and a self-biasing module 250.

[0026] The current detection module 210 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal are used to receive the non-inverting input voltage and the inverting input voltage, respectively. The current detection module 210 is used to perform a first-stage common-mode rejection on the non-inverting input voltage and the inverting input voltage. The first output terminal of the current detection module 210 is connected to the first input terminal of the voltage amplification module 220, and the second output terminal of the current detection module 210 is connected to the second input terminal of the voltage amplification module 220, so that the voltage amplification module 220 amplifies the voltage after the first-stage common-mode rejection. The current detection module 210 and the voltage amplification module 220 form a folded cascode structure.

[0027] The output of voltage amplifier module 220 is electrically connected to the input of output stage module 230, which outputs the final voltage signal. Frequency compensation module 240 is connected between the output node of voltage amplifier module 220 and the final output of output stage module 230 to improve the phase margin of the operational amplifier and prevent circuit self-oscillation. Self-biasing module 250 is connected to current detection module 210, voltage amplifier module 220, and output stage module 230 respectively, providing them with a stable bias voltage.

[0028] The operational amplifier circuit provided by this invention can be implemented through various circuit topologies. To further clarify the technical concept of this invention, two preferred circuit implementation methods are described in detail below with reference to the accompanying drawings: an operational amplifier circuit based on a P-type input folded cascode and a complementary operational amplifier circuit based on an N-type input folded cascode. It should be understood that the following embodiments are all constructed based on the overall connection method and system module division, and the signal flow and bias control logic between each module is universal.

[0029] Example 1

[0030] Reference Figure 2 This embodiment provides an operational amplifier circuit, specifically an operational amplifier circuit based on a P-type input folded common-source common-gate circuit.

[0031] The circuit includes a current detection module 210, a voltage amplification module 220, an output stage module 230, a frequency compensation module 240, and a self-biasing module 250.

[0032] 1. Current detection module 210 The current detection module 210 is connected between the power supply voltage VCC and the voltage amplification module 220, and is used to perform the first stage of common-mode rejection on the positive and negative input voltages.

[0033] The current detection module 210 includes transistors MP1, MP2, MP3 and MP4.

[0034] The input differential pair consists of transistors MP1 and MP2, whose sources are commonly connected to node D1. The gates of transistors MP1 and MP2 serve as the first and second input terminals of the current sensing module, respectively, to receive the positive input voltage and the inverted input voltage. The drain of transistor MP1 serves as the first output terminal of the current sensing module 210 and is electrically connected to node D3 of the voltage amplification module 220. The drain of transistor MP2 serves as the second output terminal of the current sensing module 210 and is electrically connected to node D2 of the voltage amplification module 220. This allows the voltage amplification module 220 to amplify the voltage after the first stage of common-mode rejection. The current sensing module 210 and the voltage amplification module 220 form a folded cascode structure.

[0035] The tail current source is composed of transistors MP3 and MP4 connected in series. The source of transistor MP3 is connected to the power supply voltage VCC, and its gate is connected to the bias voltage vb1 output from the bias module 250. The source of transistor MP4 is connected to the drain of transistor MP3, and its drain is connected to node D1. Its gate is connected to the bias voltage vb2 output from the bias module 250. This structure utilizes a common-source, common-gate current source to provide high output impedance and improve the small-signal gain of the differential pair.

[0036] 2. Voltage Amplification Module 220 The voltage amplification module 220 is connected between the power supply voltage VCC and the ground voltage VSS to realize differential to single-ended amplification.

[0037] The voltage amplification module 220 includes transistors MP9, MP10, MP11, MP12, MN3, MN4, MN5, and MN6.

[0038] Transistors MN3 and MN5 form a first cascode structure, and transistors MN4 and MN6 form a second cascode structure, which limits the variation range of the drain voltage of transistors MN5 and MN6, thereby reducing their channel length modulation effect and improving the output impedance of the amplifier stage. Transistors MP11 and MP12 form a first active current mirror, and transistors MP9 and MP10 form a second active current mirror, which improves the gain level of the amplifier stage and converts the output signal of the current detection module 210 from a dual-ended input to a single-ended output.

[0039] Common-source, common-gate structure: Transistors MN3 and MN4 serve as folded input transistors, and MN5 and MN6 serve as bottom current source loads. The sources of transistors MN3 and MN4 are electrically connected to nodes D2 and D3, respectively, to receive the differential input signal from the current detection module 210; the drains of transistors MN3 and MN4 are electrically connected to the active current mirror load, and their gates are both connected to the bias voltage vb3; the drains of transistors MN5 and MN6 are electrically connected to nodes D2 and D3, respectively, the sources of both are connected to the ground voltage VSS, and their gates are both connected to the bias voltage vb4.

[0040] Active current mirror load: Transistors MP11 and MP12 form the first current mirror. The drain of MP11 is connected to the drain of MN3 at node D14, and the drain of MP12 is connected to the drain of MN4 at node D8. The gates of transistors MP11 and MP12 are both connected to node D14. Transistors MP9 and MP10 form the second current mirror. Their sources are both connected to the power supply voltage VCC, and their drains are connected to the sources of MP11 and MP12, respectively. Their gates are both connected to node D13. Node D8 serves as the output terminal of the voltage amplification module 220, used to output the amplified single-ended voltage signal.

[0041] 3. Output stage module 230 The output stage module 230 is connected between the power supply voltage VCC and the ground voltage VSS for power amplification and driving.

[0042] The output stage module 230 includes transistors MP14, MP15, MP16, MP17, MP18, MP19, MN7, MN8, MN9, MN10, MN11, MN12, MN13, and resistors R2 and R3.

[0043] Transistors MP13 and MN11 are used to receive bias voltages to maintain the module's basic operating current. Transistors MN7 and MN8 form the first current mirror, transistors MP14 and MP19 form the second current mirror, transistors MP17 and MP18 form the third current mirror, and transistors MN12 and MN13 form the fourth current mirror. This structure achieves Class AB push-pull drive through multi-stage mirroring, improving the circuit's load-carrying capacity and dynamic response speed.

[0044] The source of transistor MP13 is connected to the power supply voltage VCC, the drain is connected to the first current mirror, and the gate is used to receive the bias voltage vb1. The drains of transistors MN7 and MN8 are connected to nodes D9 and D10, respectively, and their sources are connected to the sources of transistors MP15 and MP16, respectively. Their gates are connected to node D9. The sources of transistors MP14 and MP19 are connected to the power supply voltage VCC, and their drains are connected to the first current mirror and the drain of transistor MN13, respectively. Their gates are connected to node D10. The source of transistor MP15 is connected to the source of transistor MN7, and its drain is connected to the ground voltage VSS. Its gate is connected between resistors R2 and R3. The source of transistor MP16 is connected to the source of MN8, and its drain is connected to the ground voltage VSS. Its gate is used to receive the output of voltage amplification module 220. The drain of transistor MN9 is connected to the power supply voltage VCC, the source is connected to the source of transistor MP17, and the gate is connected between resistors R2 and R3. The drain of transistor MN10 is connected to the power supply voltage VCC, the source is connected to the source of transistor MP18, and the gate is used to receive the output of voltage amplifier module 220. The sources of transistors MP17 and MP18 are connected to the sources of transistors MN9 and MN10, the drains are connected to nodes D11 and D12, and the gate is connected to node D11. The drain of transistor MN11 is connected to node D11, the source is connected to ground voltage VSS, and the gate is used to receive bias voltage vb4. The drains of transistors MN12 and MN13 are connected to the drain of the third current mirror and transistor MP19, the sources are connected to ground voltage VSS, and the gates are connected to node D12.

[0045] Whether the circuit operates in Class B or Class AB mode is determined by the gate voltages of transistors MN8 and MP18. When the input is high, the current of transistor MP16 decreases, while the current of transistor MN10 increases. If the circuit operates in Class B mode, transistor MP16 is off. As the current of transistor MN10 increases, the current mirrored from transistor MN12 also increases, improving the circuit's current-carrying capacity. When the input is low, transistor MP19 can provide the output current. For design simplification, the width-to-length ratios of transistors MN10 and MP17, as well as those of transistors MN8 and MP16, can be set to be the same. Current control is primarily achieved through the gate voltages of transistors MN8 and MP18; a higher gate voltage results in a lower current draw.

[0046] 4. Frequency Compensation Module 240 The frequency compensation module 240 is connected between the ground voltage VSS and the power supply voltage VCC, and includes a resistor R4 and a capacitor C1. One end of the capacitor C1 is connected to node D8 of the voltage amplification module, and the other end is connected to one end of the resistor R4; the other end of the resistor R4 is electrically connected to the output terminal of the output stage module 230, namely the common drain node of MP19 and MN13. The resistor R4 and capacitor C1 constitute Miller compensation, which is used to increase the phase margin of the op-amp and improve its stability.

[0047] 5. Self-biasing module 250 The self-biasing module 250 includes transistors MP5, MP6, MP7, MP8, MN1, MN2, and resistor R1.

[0048] The self-biasing module 250 is connected between the ground voltage VSS and the power supply voltage VCC. Transistors MP5 and MP7 form a first current mirror, providing a bias voltage vb1 to the operational amplifier. Transistors MP6 and MP8 form a second current mirror, providing a bias voltage vb2 to the operational amplifier. Transistor MN1 and transistors MN3 and MN4 of the voltage amplification module 220 form a third current mirror, providing a bias voltage vb3 to the operational amplifier. Transistor MN2 and transistors MN5 and MN6 of the voltage amplification module 220 form a fourth current mirror, providing a bias voltage vb4 to the operational amplifier.

[0049] Specifically, the sources of transistors MP5 and MP7 are connected to the power supply voltage VCC, their drains are connected to the second current mirror, and their gates are connected to node D4. The gates of transistors MP6 and MP8 are connected to node D5. The source of transistor MP6 is connected to the drain of transistor MP5, and its drain is connected to the drain of transistor MN1. The source of transistor MP8 is connected to the drain of transistor MP7, and its drain is connected to resistor R1. Resistor R1 is connected between node D5 and ground voltage VSS. The drain of transistor MN1 is connected to the drain of transistor MP6, its source is connected to the drain of transistor MN2, and its gate is connected to node D6. The drain of transistor MN2 is connected to the source of transistor MN1, its source is connected to ground voltage VSS, and its gate is connected to node D7.

[0050] Example 2

[0051] Reference Figure 3 This embodiment provides an operational amplifier circuit, specifically a complementary operational amplifier circuit based on N-type input folded common source cascode.

[0052] The circuit includes a current detection module 210, a voltage amplification module 220, an output stage module 230, a frequency compensation module 240, and a self-biasing module 250. Its core technical feature is that the P-type input folding structure in Embodiment 1 is flipped into an N-type input folding structure to effectively cover the low common-mode input voltage range.

[0053] 1. Current detection module 210 The current detection module 210 is connected between the voltage amplification module 220 and the ground voltage VSS, and is used to perform the first stage of common-mode rejection on the positive and negative input voltages.

[0054] The current detection module 210 includes transistors MN101, MN102, MN103 and MN104.

[0055] The input differential pair consists of NMOS type transistors MN101 and MN102, whose sources are commonly connected to node D101. The gates of transistors MN101 and MN102 serve as the first and second input terminals of the current sensing module 210, respectively, to receive the positive input voltage (VIN+) and the negative input voltage (VIN-). The drain of transistor MN101 serves as the first output terminal of the current sensing module 210 and is electrically connected to the folded node D103 of the voltage amplification module 220. The drain of transistor MN102 serves as the second output terminal of the current sensing module 210 and is electrically connected to the folded node D102 of the voltage amplification module 220, so that the current sensing module 210 and the voltage amplification module 220 form an N-type complementary folded common source and common gate topology.

[0056] The tail current source is composed of NMOS transistors MN103 and MN104 connected in series. The source of transistor MN104 is connected to ground voltage VSS, and its gate is connected to the bias voltage vb14 output from the bias module 250. The source of transistor MN103 is connected to the drain of transistor MN104, and its drain is connected to node D101. Its gate is connected to the bias voltage vb13 output from the bias module 250. This structure utilizes the bottom common-source common-gate current source to provide high output impedance, thereby improving the small-signal gain and common-mode rejection ratio of the differential pair.

[0057] 2. Voltage Amplification Module 220 The voltage amplification module 220 is connected between the power supply voltage VCC and the ground voltage VSS to realize the conversion of differential current signal to single-ended voltage amplification.

[0058] The voltage amplification module 220 includes transistors MP101, MP102, MP103, MP104, MN105, MN106, MN107, and MN108.

[0059] Transistors MP103 and MP101 form a first cascode structure, and transistors MP104 and MP102 form a second cascode structure, which are used to reduce the channel length modulation effect and significantly improve the output impedance of the amplification stage; transistors MN105 and MN106 form a first active current mirror, and transistors MN107 and MN108 form a second active current mirror, which together form a complementary active load to convert the differential drain current of the current detection module 210 into a single-ended voltage signal output.

[0060] Common-source cascode structure: Transistors MP103 and MP104 serve as folded common-gate input transistors, while MP101 and MP102 serve as top active current sources. The sources of transistors MP103 and MP104 are electrically connected to folded nodes D103 and D102, respectively, to receive the drain current signal from the input differential pair; the drains of transistors MP103 and MP104 are electrically connected to the lower NMOS active current mirror load, and their gates are both connected to the bias voltage vb12; the drains of transistors MP101 and MP102 are electrically connected to the sources of MP103 and MP104, respectively, and their sources are both connected to the power supply voltage VCC, and their gates are both connected to the bias voltage vb11.

[0061] Active current mirror load: Transistors MN105 and MN106 form the first current mirror. The drain of MN105 is connected to the drain of MP103 at node D113, and the drain of MN106 is connected to the drain of MP104 at node D108. The gates of transistors MN105 and MN106 are both connected to node D113. Transistors MN107 and MN108 form the second current mirror. Their sources are both connected to ground voltage VSS, and their drains are connected to the sources of transistors MN105 and MN106 respectively. Their gates are both connected to node D114. Node D108 serves as the single-ended output terminal of voltage amplification module 220, used to output the amplified single-ended voltage signal to the subsequent stage.

[0062] 3. Output stage module 230 The output stage module 230 is connected between the power supply voltage VCC and the ground voltage VSS.

[0063] The output stage module 230 includes transistors MP105, MP106, MP107, MP108, MP109, MP110, MP111, MN109, MN110, MN111, MN112, MN113, MN114, MN115, and resistors R11 and R12.

[0064] Transistors MP105 and MN113 are used to receive bias voltages to maintain the basic quiescent operating current of the output stage module 230. Transistors MN109 and MN110 form the first current mirror, transistors MP106 and MP111 form the second current mirror, transistors MP109 and MP110 form the third current mirror, and transistors MN114 and MN115 form the fourth current mirror. This structure achieves Class AB push-pull drive through complementary-level multi-stage mirroring, improving the dynamic response speed of the circuit.

[0065] Bias and control structure: The source of transistor MP105 is connected to the power supply voltage VCC, the drain is connected to the first current mirror, and the gate is used to receive the bias voltage vb11; the drain of transistor MN113 is connected to node D111, the source is connected to the ground voltage VSS, and the gate is used to receive the bias voltage vb14. The gates of transistors MP108 and MN112 are both electrically connected to the single-ended output node D108 of the voltage amplifier module 220 to receive the drive signal after pre-amplification.

[0066] Transistors MN109 and MN110 form the first active current mirror, with their gates connected to node D109. The drain of MN109 is shorted to the gate of node D109, and the drain of MN110 is connected to node D110.

[0067] The source of transistor MP106 is connected to the power supply voltage VCC, and the drain and gate are shorted at node D110 to convert the control current into a pull-up drive voltage.

[0068] The source of transistor MP107 is connected to the source of MN109, the drain is connected to ground voltage VSS, and the gate is electrically connected to the common connection node of resistors R11 and R12.

[0069] The source of transistor MP108 is connected to the source of MN110, the drain is connected to ground voltage VSS, and the gate is electrically connected to the single-ended output node D108 of voltage amplifier module 220 to receive the differential drive signal after pre-amplification.

[0070] The drain of transistor MN111 is connected to the power supply voltage VCC, the gate is connected to the common connection node of resistors R11 and R12, and the source is connected to the source of MP109.

[0071] The drain of transistor MN112 is connected to the power supply voltage VCC, the gate is electrically connected to the single-ended output node D108 of voltage amplifier module 220, and the source is connected to the source of MP110.

[0072] Transistors MP109 and MP110 constitute a second active current mirror, with their gates connected to node D111. The drain of MP109 is shorted to its gate at node D111, and the drain of MP110 is connected to node D112.

[0073] The drain and gate of transistor MN114 are shorted at node D112, and the source is connected to ground voltage VSS to convert the control current into a pull-down drive voltage.

[0074] Transistor MP111 is used as a pull-up power transistor, with its source connected to the power supply voltage VCC and its gate connected to node D110; transistor MN115 is used as a pull-down power transistor, with its source connected to the ground voltage VSS and its gate connected to node D112.

[0075] The drain of transistor MP111 is electrically connected to the drain of transistor MN115 to form a common output terminal, which serves as the final signal output terminal of output stage module 230 to output a high-power drive signal to an external load.

[0076] 4. Frequency compensation module 240 The frequency compensation module 240 is connected between the ground voltage VSS and the power supply voltage VCC, and includes a resistor R13 and a capacitor C11.

[0077] One end of capacitor C11 is connected to the single-ended output node D108 of voltage amplifier module 220, and the other end is connected to one end of resistor R13; the other end of resistor R13 is electrically connected to the output terminal of output stage module 230. Resistor R13 and capacitor C11 together form a Miller compensation network, which is used to introduce dominant poles and compensation zeros inside the circuit, increase the phase margin of the operational amplifier, and ensure the closed-loop stability of the high anti-interference system.

[0078] 5. Self-biasing module 250 The self-biasing module 250 is connected between the ground voltage VSS and the power supply voltage VCC to generate a set of precision bias voltages that are adaptive to process and temperature.

[0079] The self-biasing module 250 includes transistors MP112, MP113, MN116, MN117, MN118, MN119, and resistor R14.

[0080] Inside the bias module 250, transistors MN116 and MN118 form a first current mirror, and transistors MN117 and MN119 form a second current mirror. Transistors MP112 and MP113 correspond to the PMOS transistors inside the current detection module 210 and the voltage amplification module 220, respectively, forming current mirror relationships. The first and second current mirrors are cascaded together and, in conjunction with resistor R14, form a Vth reference current source to establish bias voltages vb13 and vb14. The cascaded PMOS branch is responsible for establishing bias voltages vb11 and vb12.

[0081] The source of transistor MP112 is connected to the power supply voltage VCC, the drain of MP112 is connected to the source of MP113, the gate and drain of MP112 are shorted at node D104 to output bias voltage vb11; the gate and drain of MP113 are shorted at node D105 to output bias voltage vb12, and the drain of MP113 is electrically connected to the drain of the NMOS cascade branch below.

[0082] NMOS cascade path: The gates of transistors MN116 and MN118 are connected to a common node D106. The drain and gate of MN116 are shorted to node D106 to output the third bias voltage vb13. The gates of transistors MN117 and MN119 are connected to a common node D107. The drain and gate of MN117 are shorted to node D107 to output the bias voltage vb14. The source of MN116 is connected to the drain of MN117, and the source of MN117 is directly connected to ground voltage VSS. The drain of MN118 is connected to the drain of MP113, and the source of MN118 is connected to the drain of MN119. The source of MN119 is directly connected to ground voltage VSS. Resistor R14 is connected between the power supply voltage VCC and node D106 to set the core reference operating current of the bias network.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high anti-interference operational amplifier circuit, comprising a self-biasing module (250), a current detection module (210), a voltage amplification module (220), an output stage module (230), and a frequency compensation module (240), characterized in that, The current detection module (210) includes a differential input pair transistor of a first conductivity type and a common-source common-gate tail current source structure cascaded to the source of the differential input pair transistor; the common-source common-gate tail current source structure is connected between the first power supply terminal and the common source of the differential input pair transistor, and its gate is electrically connected to the self-biasing module (250) to receive a first set of bias voltages; the gates of the differential input pair transistors serve as the first input terminal and the second input terminal of the operational amplifier circuit, respectively, and the drains of the differential input pair transistors serve as the first output terminal and the second output terminal of the current detection module (210), respectively. The voltage amplification module (220) includes a first input terminal, a second input terminal, and a single-ended output node. The voltage amplification module (220) is internally provided with a folded common-gate input transistor structure of the second conductivity type, a cascaded bias transistor structure, and an active current mirror network. The first input terminal and the second input terminal of the voltage amplification module (220) are electrically connected to the first output terminal and the second output terminal of the current detection module (210), respectively, so as to form a folded common-source common-gate topology at the first input terminal and the second input terminal. The gates of the folded common gate input transistor structure, the cascaded bias transistor structure, and the active current mirror network are electrically connected to the self-biasing module (250) to receive the second set of bias voltages, which are used to convert the differential current output by the current detection module (210) into a single-ended voltage signal and output it from the single-ended output node. The self-biasing module (250) includes a bias cascade branch and a reference resistor that match the current detection module (210) and the voltage amplification module (220) to generate multiple bias voltages, which are supplied to the current detection module (210) and the voltage amplification module (220) respectively via the first set of bias voltages and the second set of bias voltages. The input terminal of the output stage module (230) is electrically connected to the single-ended output node of the voltage amplification module (220), its bias terminal is electrically connected to the self-biasing module (250), and its output terminal serves as the final signal output terminal of the operational amplifier circuit. The frequency compensation module (240) is connected between the single-ended output node of the voltage amplification module (220) and the final signal output terminal of the output stage module (230).

2. The high anti-interference operational amplifier circuit according to claim 1, characterized in that, The frequency compensation module (240) includes a compensation capacitor and a compensation resistor connected in series; the first end of the compensation capacitor is electrically connected to the single-ended output node of the voltage amplification module (220), and the second end of the compensation capacitor is electrically connected to the final signal output terminal of the output stage module (230) through the compensation resistor.

3. The high anti-interference operational amplifier circuit according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; the first power supply terminal is the power supply voltage VCC, and the second power supply terminal is the ground voltage VSS; The current detection module includes transistors MP1, MP2, MP3, and MP4: The transistors MP1 and MP2 constitute the differential input pair transistors, with their sources commonly connected to node D1, and their gates serving as the first and second input terminals of the operational amplifier circuit, respectively. The drain of transistor MP1 is connected to node D3 in the voltage amplifier module, and the drain of transistor MP2 is connected to node D2 in the voltage amplifier module. The cascaded transistors MP3 and MP4 form the common-source common-gate tail current source structure. The source of transistor MP3 is electrically connected to the first power supply terminal VCC, the drain is electrically connected to the source of transistor MP4, and the gate is used to receive the bias voltage vb1. The drain of transistor MP4 is electrically connected to the node D1, and the gate is used to receive the bias voltage vb2 in the bias voltage.

4. The high anti-interference operational amplifier circuit according to claim 3, characterized in that, The self-biasing module includes transistors MP5, MP6, MP7, MP8, MN1, MN2, and resistor R1. The sources of transistors MP5 and MP7 are both electrically connected to the first power supply terminal VCC. The gate and drain of transistor MP7 are shorted to node D4 to output bias voltage vb1. The source of transistor MP6 is electrically connected to the drain of transistor MP5, the source of transistor MP8 is electrically connected to the drain of transistor MP7, the gate and drain of transistor MP8 are shorted at node D5 to output bias voltage vb2, and the drain of transistor MP8 is electrically connected to the second power supply terminal VSS through the first resistor R1. The drain and gate of transistor MN1 are shorted at node D6 and electrically connected to the drain of transistor MP6 to output bias voltage vb3. The drain and gate of transistor MN2 are shorted at node D7 to output bias voltage vb4, and node D7 is electrically connected to the source of transistor MN1. The source of transistor MN2 is electrically connected to the second power supply terminal VSS.

5. The high anti-interference operational amplifier circuit according to claim 3, characterized in that, The voltage amplification module includes transistors MP9, MP10, MP11, MP12, MN3, MN4, MN5, and MN6. The source of transistor MN3 is electrically connected to node D2, the source of transistor MN4 is electrically connected to node D3, and the gates of transistors MN3 and MN4 are both electrically connected to node D6 of the self-biased module to receive the bias voltage vb3. The drain of transistor MN5 is electrically connected to node D2, the drain of transistor MN6 is electrically connected to node D3, the sources of transistors MN5 and MN6 are both electrically connected to the second power supply terminal VSS, and their gates are both electrically connected to node D7 of the self-biased module to receive the bias voltage vb4. The sources of transistors MP9 and MP10 are both electrically connected to the first power supply terminal VCC, and their gates are both electrically connected to node D13, and node D13 is electrically connected to the drain of transistor MP9. The source of transistor MP11 is electrically connected to the drain of transistor MP9, the source of transistor MP12 is electrically connected to the drain of transistor MP10, the gates of transistors MP11 and MP12 are electrically connected to node D14, the drain of transistor MP11 is electrically connected to the drain of transistor MN3 and is also connected to node D14, the drain of transistor MP12 is electrically connected to the drain of transistor MN4, and their common connection terminal serves as the single-ended output node D8.

6. The high anti-interference operational amplifier circuit according to claim 5, characterized in that, The output stage module includes transistors MP13 to MP19, transistors MN7 to MN13, and resistors R2 and a third resistor R3; The gate of the transistor MP13 is used to receive the bias voltage vb1, the source is electrically connected to the first power supply terminal VCC, and the drain is electrically connected to node D9. The gates of transistors MN7 and MN8 are both electrically connected to node D9, the drain of transistor MN7 is electrically connected to node D9, and the drain of transistor MN8 is electrically connected to node D10; the source of transistor MN7 is electrically connected to the source of transistor MP15, and the source of transistor MN8 is electrically connected to the source of transistor MP16. The sources of transistors MP14 and MP19 are both electrically connected to the first power supply terminal VCC, and their gates are both electrically connected to the node D10; the drain of transistor MP14 is electrically connected to the node D10. The gates of transistors MP16 and MN10 are both electrically connected to the single-ended output node D8; the drain of transistor MP16 is electrically connected to the second power supply terminal VSS, the drain of transistor MN10 is electrically connected to the first power supply terminal VCC, and the source of transistor MN10 is electrically connected to the source of transistor MP18. The gates of transistors MP17 and MP18 are both electrically connected to node D11; the drain of transistor MP17 is electrically connected to node D11, and its source is electrically connected to the source of transistor MN9; the drain of transistor MP18 is electrically connected to node D12. The gate of the transistor MN11 is used to receive the bias voltage vb4, the drain is electrically connected to the node D11, and the source is electrically connected to the second power supply terminal VSS. The sources of transistors MN12 and MN13 are both electrically connected to the second power supply terminal VSS, and their gates are both electrically connected to the node D12; the drain of transistor MN12 is electrically connected to the node D12, the drain of transistor MN13 is electrically connected to the drain of transistor MP19, and their common connection node serves as the signal output terminal of the output stage module (230). The drain of transistor MN9 is electrically connected to the first power supply terminal VCC; the first terminal of resistor R2 is electrically connected to the first power supply terminal VCC, the second terminal of resistor R2 is electrically connected to the first terminal of resistor R3, and the second terminal of resistor R3 is electrically connected to the second power supply terminal VSS; the gate of transistor MP15 and the gate of transistor MN9 are both electrically connected to the common connection node of resistors R2 and R3.

7. The high anti-interference operational amplifier circuit according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; the first power supply terminal is ground voltage VSS, and the second power supply terminal is power supply voltage VCC; The current detection module includes transistors MN101, MN102, MN103, and MN104: The transistors MN101 and MN102 constitute the differential input pair transistors, with their sources commonly connected to node D101, and their gates serving as the first and second input terminals of the operational amplifier circuit, respectively. The drain of transistor MN101 is electrically connected to the folded node D103 of the voltage amplifier module (220), and the drain of transistor MN102 is electrically connected to the folded node D102 of the voltage amplifier module (220). The cascaded transistors MN103 and MN104 form the common-source common-gate tail current source structure. The source of transistor MN104 is electrically connected to the first power supply terminal VSS, and its gate is used to receive the bias voltage vb14. The source of transistor MN103 is connected to the drain of transistor MN104, and its drain is connected to the node D101. Its gate is used to receive the bias voltage vb13.

8. The high anti-interference operational amplifier circuit according to claim 7, characterized in that, The self-biasing module includes transistors MP112, MP113, MN116, MN117, MN118, MN119, and resistor R14. The source of transistor MP112 is connected to the second power supply terminal VCC, and the drain is connected to the source of transistor MP113. The gate and drain of transistor MP112 are shorted at node D104 to output bias voltage vb11. The gate and drain of the transistor MP113 are shorted at node D105 to output a bias voltage vb12, and the drain of the transistor MP113 is electrically connected to the drain of the transistor MN118. The gates of transistors MN116 and MN118 are connected to a common node D106, and the drain and gate of transistor MN116 are shorted to node D106 to output a bias voltage vb13. The gates of transistors MN117 and MN119 are connected to a common node D107, and the drain and gate of transistor MN117 are shorted to node D107 to output a bias voltage vb14. The source of transistor MN116 is connected to the drain of transistor MN117, and the source of transistor MN117 is connected to the first power supply terminal VSS; the source of transistor MN118 is connected to the drain of transistor MN119, and the source of transistor MN119 is connected to the first power supply terminal VSS; the resistor R14 is connected between the second power supply terminal VCC and the node D106.

9. The high anti-interference operational amplifier circuit according to claim 7, characterized in that, The voltage amplification module (220) includes transistors MP101, MP102, MP103, MP104, MN105, MN106, MN107 and MN108. The sources of transistors MP103 and MP104 are electrically connected to the folded nodes D102 and D103 respectively to receive the output signal of the current detection module (210), and their gates are connected to the bias voltage vb12, and their drains are electrically connected to the drains of transistors MN105 and MN106 respectively. The sources of transistors MP101 and MP102 are both connected to the second power supply terminal VCC, and their drains are respectively connected to the sources of transistors MP103 and MP104. Their gates are both connected to the bias voltage vb11. The transistors MN105 and MN106 form a first current mirror, with their gates connected to the node D113 where the drain of the transistor MN105 is located, and the drain of the transistor MN106 connected to the single-ended output node D108. The transistors MN107 and MN108 form a second current mirror, with their sources connected to the first power supply terminal VSS, their drains connected to the sources of the transistors MN105 and MN106 respectively, and their gates connected to the node D114 where the drain of the transistor MN107 is located.

10. The high anti-interference operational amplifier circuit according to claim 9, characterized in that, The output stage module includes transistors MP105, MP106, MP107, MP108, MP109, MP110, MP111, MN109, MN110, MN111, MN112, MN113, MN114, MN115, and resistors R11 and R12. The source of the transistor MP105 is connected to the second power supply terminal VCC, the gate is used to receive the bias voltage vb11, and the drain is connected to node D109. The drain of transistor MN113 is connected to node D111, the source is connected to the first power supply terminal VSS, and the gate is used to receive the bias voltage vb14; the gates of transistors MP108 and MN112 are both electrically connected to the single-ended output node D108. The transistors MN109 and MN110 constitute a first active current mirror, with their gates connected to node D109. The drain of transistor MN109 is shorted to its gate at node D109, and the drain of transistor MN110 is connected to node D110. The source of the transistor MP106 is connected to the second power supply terminal VCC, and the drain and gate are shorted to the node D110. The source of transistor MP107 is connected to the source of transistor MN109, the drain is connected to the first power supply terminal VSS, and the gate is electrically connected to the common connection node of resistors R11 and R12. The source of transistor MP108 is connected to the source of transistor MN110, and the drain is connected to the first power supply terminal VSS. The drain of transistor MN111 is connected to the second power supply terminal VCC, the gate is electrically connected to the common connection node of resistors R11 and R12, and the source is connected to the source of transistor MP109. The drain of transistor MN112 is connected to the second power supply terminal VCC, and the source is connected to the source of transistor MP110; The transistors MP109 and MP110 constitute a second active current mirror, with their gates connected to the node D111. The drain of the transistor MP109 is shorted to the gate of the node D111, and the drain of the transistor MP110 is connected to the node D112. The drain and gate of the transistor MN114 are shorted to the node D112, and the source is connected to the first power supply terminal VSS. The source of transistor MP111 is connected to the second power supply terminal VCC, and the gate is electrically connected to the node D110; the source of transistor MN115 is connected to the first power supply terminal VSS, and the gate is electrically connected to the node D112. The drain of transistor MP111 is electrically connected to the drain of transistor MN115 to form a common output terminal, which serves as the signal output terminal of the output stage module (230). The first end of resistor R11 is electrically connected to the second power supply terminal VCC, the second end of resistor R11 is electrically connected to the first end of resistor R12, and the second end of resistor R12 is electrically connected to the first power supply terminal VSS.

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