Low temperature low noise amplifier and superconducting nanowire single photon detector readout system

Abstract

The application discloses a low-temperature low-noise amplifier and a superconducting nanowire single-photon detector reading system, and belongs to the technical field of integrated circuits. The low-temperature low-noise amplifier comprises: a first-stage amplification circuit, the base of a first-stage transistor is an input end, the collector of the first-stage transistor is an output end of the first-stage amplification circuit, and a first feedback circuit is electrically connected between the collector and the base of the first-stage transistor; a second-stage amplification circuit, the base of a second-stage transistor is electrically connected to the collector of the first-stage transistor, the collector of the second-stage transistor is an output end, and a second feedback circuit is electrically connected between the collector and the base of the second-stage transistor; and an inter-stage coupling circuit electrically connected between the collector of the first-stage transistor and the base of the second-stage transistor. The low-temperature low-noise amplifier and the superconducting nanowire single-photon detector reading system can realize comprehensive optimization of broadband matching, ultra-low noise and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-temperature, low-noise amplifier and a readout system for a superconducting nanowire single-photon detector. Background Technology

[0002] Superconducting nanowire single-photon detectors (SNSPDs) are key devices in quantum information applications. When SNSPDs are used in extremely low-temperature environments of 4K, the low-noise amplifier (LNA), as the core module of the SNSPD readout link, needs to provide high gain, ultra-low noise, and mild and stable 50Ω wideband input matching to suppress pulse reflection and waveform distortion, thereby ensuring the system's high count rate and high-fidelity readout capability.

[0003] However, commercial process design kits only model and verify operating conditions at 300K ambient temperature. They cannot accurately predict the dramatic increase in current gain and sudden drop in on-state voltage of silicon-germanium heterojunction bipolar transistors (SGNBTs) at the extremely low temperature of 4K, leading to difficulties in design iteration. Secondly, the parasitic capacitance of the electrostatic discharge (ESD) protection structure introduced to resist ESD events will degrade broadband input matching at the extremely low temperature of 4K. Furthermore, multi-channel SNSPD readout systems require single-channel power consumption to be controlled at the milliwatt level, making it difficult to simultaneously achieve optimal gain flatness, noise level, and power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a low-temperature, low-noise amplifier and a superconducting nanowire single-photon detector readout system that can achieve comprehensive optimization of broadband matching, ultra-low noise, and low power consumption.

[0005] This invention provides a low-temperature, low-noise amplifier, comprising at least: The first-stage amplifier circuit includes a first-stage transistor and a first feedback circuit. The base of the first-stage transistor is the input terminal of the low-temperature low-noise amplifier, the emitter of the first-stage transistor is grounded, the collector of the first-stage transistor is the output terminal of the first-stage amplifier circuit, and the first feedback circuit is electrically connected between the collector and the base of the first-stage transistor. The second-stage amplifier circuit includes a second-stage transistor and a second feedback circuit. The base of the second-stage transistor is electrically connected to the collector of the first-stage transistor. The collector of the second-stage transistor is the output terminal of the low-temperature, low-noise amplifier. The emitter of the second-stage transistor is grounded. The second feedback circuit is electrically connected between the collector and base of the second-stage transistor. An interstage coupling circuit is electrically connected between the collector of the first-stage transistor and the base of the second-stage transistor. The emitter area of ​​the first-stage transistor is larger than that of the second-stage transistor.

[0006] In one embodiment of the present invention, the first stage amplifier circuit includes a first collector load resistor and a first inductor, which are connected in series between the first bias voltage input terminal of the low-temperature low-noise amplifier and the collector of the first stage transistor.

[0007] In one embodiment of the present invention, the first feedback circuit includes a first feedback resistor and a first feedback capacitor. One end of the first feedback capacitor is electrically connected to the common terminal of the first collector load resistor and the first inductor, and the other end of the first feedback capacitor is electrically connected to the first feedback resistor. One end of the first feedback resistor is electrically connected to the first feedback capacitor, and the other end of the first feedback resistor is electrically connected to the base of the first stage transistor.

[0008] In one embodiment of the present invention, the first-stage amplifier circuit includes a first bypass capacitor and a first resistor. The first resistor is electrically connected between the second bias voltage input terminal of the low-temperature low-noise amplifier and the base of the first-stage transistor, and the first bypass capacitor is electrically connected between the second bias voltage input terminal and the ground terminal.

[0009] In one embodiment of the present invention, the second-stage amplifier circuit includes a second collector load resistor, which is electrically connected between the third bias voltage input terminal of the low-temperature low-noise amplifier and the collector of the second-stage transistor.

[0010] In one embodiment of the present invention, the second feedback circuit includes a second feedback resistor and a second feedback capacitor. One end of the second feedback capacitor is electrically connected to the common terminal of the second collector load resistor and the collector of the first stage transistor. The other end of the first feedback capacitor is electrically connected to the second feedback resistor. One end of the second feedback resistor is electrically connected to the second feedback capacitor. The other end of the second feedback resistor is electrically connected to the base of the second stage transistor.

[0011] In one embodiment of the present invention, the second-stage amplifier circuit includes a second bypass capacitor and a second resistor. The second resistor is electrically connected between the fourth bias voltage input terminal of the low-temperature low-noise amplifier and the base of the first-stage transistor, and the second bypass capacitor is electrically connected between the fourth bias voltage input terminal and the ground terminal.

[0012] In one embodiment of the present invention, the interstage coupling circuit includes an interstage capacitor, an interstage inductor, and an interstage resistor, wherein the interstage capacitor, the interstage inductor, and the interstage resistor are connected in series between the collector of the first stage transistor and the base of the second stage transistor.

[0013] In one embodiment of the present invention, the low-temperature low-noise amplifier includes an input inductor and an output resistor. The input inductor is electrically connected between the input terminal of the low-temperature low-noise amplifier and the base of the first-stage transistor, and the output resistor is electrically connected between the collector of the second-stage transistor and the output terminal of the low-temperature low-noise amplifier.

[0014] In one embodiment of the present invention, the low-temperature low-noise amplifier includes a plurality of electrostatic protection structures, the electrostatic protection structures being electrically connected between each port of the low-temperature low-noise amplifier and a ground terminal, and the ports of the low-temperature low-noise amplifier including an input terminal, an output terminal and a bias voltage input terminal.

[0015] In one embodiment of the present invention, the electrostatic protection structure includes an electrostatic capacitor and an electrostatic resistor, wherein the electrostatic capacitor and the electrostatic resistor are connected in parallel.

[0016] The present invention also provides a superconducting nanowire single-photon detector readout system, comprising at least: The low-temperature, low-noise amplifier described in any of the above-mentioned items; A nanowire detector, electrically connected between the input terminal and the ground terminal of the cryogenic low-noise amplifier, generates a pulse signal and inputs the pulse signal into the cryogenic low-noise amplifier; and The back-end circuit is electrically connected to the output terminal of the low-temperature, low-noise amplifier, and the back-end circuit reads out the pulse signal amplified by the low-temperature, low-noise amplifier.

[0017] In summary, this invention provides a low-temperature, low-noise amplifier and a readout system for a superconducting nanowire single-photon detector. The low-temperature, low-noise amplifier employs a two-stage common-emitter topology and a cascaded multi-stage architecture to mitigate parameter dispersion in low-temperature devices. The two amplifier stages each provide independent bias voltage input ports, enabling stage-by-stage transconductance optimization and milliwatt-level single-channel power consumption control. At the input, the electrostatic protection structure is equivalent to a grounded parallel capacitor, forming a resonant network with the input inductor to achieve broadband matching recovery under low-temperature conditions. The first-stage transistor achieves ultra-low noise temperature with a large emitter area, while the second-stage transistor significantly reduces power consumption with a small emitter area, maintaining high gain while keeping total power consumption in the milliwatt range. The first and second feedback circuits broaden the input matching bandwidth and reduce closed-loop sensitivity caused by increased current gain at low temperatures. The interstage coupling circuit uses an interstage inductor to compensate for high-frequency gain roll-off and improve gain flatness. A shunt peak is achieved by connecting the first collector load resistor in series with the first inductor, extending the high-frequency bandwidth without additional DC power consumption. By combining the second collector load resistor with the output resistor and tuning it in conjunction with the equivalent parallel impedance of the electrostatic protection structure, broadband output return loss can be improved, and pulse reflection and ringing can be reduced. In addition, the first collector load resistor, the second collector load resistor, and the interstage resistor all use n+ diffused resistors, which can achieve predictability of DC bias and interstage impedance at low temperatures, ensuring reliable operation across the entire temperature range from room temperature to 4K.

[0018] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the small-signal equivalent circuit of a silicon-germanium heterojunction bipolar transistor in one embodiment.

[0021] Figure 2 This is a schematic diagram of a superconducting nanowire single-photon detector readout system in one embodiment.

[0022] Figure 3 This is a schematic diagram of a low-temperature, low-noise amplifier in one embodiment. Detailed Implementation

[0023] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0025] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Similarly, the terms "high" and "low," indicating degree, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a high or low position, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] With the rapid development of cutting-edge technologies such as quantum information science, deep-space laser communication, and radio astronomy, single-photon-level weak signal detection technology has become a core means of information acquisition. In these systems, superconducting nanowire single-photon detectors are widely used due to their excellent detection efficiency and time resolution. To maintain superconductivity, superconducting nanowire single-photon detectors are typically deployed in extremely low-temperature environments of 4K or even lower. When the detector captures a photon, it generates a weak transient radio frequency pulse signal at the sub-millivolt level. To reduce the probability of this weak signal being submerged by cable thermal noise during long-distance transmission across temperature zones, a low-noise amplifier is usually placed in the extremely low-temperature environment close to the detector for signal pre-amplification. However, in the 4K extremely low-temperature environment, the physical characteristics of semiconductor devices change drastically, such as a sharp increase in transistor transconductance and impedance drift in passive devices, which poses a significant challenge to the design of low-noise amplifiers. Therefore, this invention provides a low-temperature low-noise amplifier to improve the problems of broadband matching degradation, uncontrollable power consumption, and gain unevenness caused by impedance drift in extremely low-temperature environments, achieving comprehensive optimization of broadband matching, ultra-low noise, and low power consumption.

[0027] Please see Figure 1As shown, when the transistor in the low-noise amplifier is a silicon-germanium heterojunction bipolar transistor, the small-signal equivalent circuit of the silicon-germanium heterojunction bipolar transistor includes the base resistor R. b (T), Emitter resistance R e (T), collector parasitic resistance R c (T), Base-emitter junction capacitance C be Base-collector junction capacitance C bc Voltage-controlled current source g m V be Base-emitter conductance g be and substrate parasitic capacitance C sub Base resistance R b (T) Electrically connected to the outside of the base, base-emitter conductance g be With base-emitter junction capacitance C be They are connected in parallel, sharing a common electrical connection between the internal base and emitter. Voltage-controlled current source g m V be The base-collector junction is electrically connected between the internal collector and emitter, with current flowing from the collector to the emitter. The base-collector junction capacitance C... bc It is electrically connected between the internal base and collector. The collector parasitic resistance R... c (T) Electrically connected to the outside of the collector, emitter resistance R e (T) Electrically connected to the outside of the emitter. Substrate parasitic capacitance C sub Electrically connected to the collector parasitic resistance R c (T) and emitter resistance R e Between (T). When in an extremely low temperature environment of 4K, the base resistance R b (T), Emitter resistance R e (T) and collector parasitic resistance R c (T) will decrease due to lattice scattering freezing. The temperature dependence of resistance can be described using Masison's rule, and the specific formula is as follows: R(T) = R0 + R ph (T); Where R0 is the residual resistance, R ph (T) represents the contribution of lattice scattering.

[0028] The relationship between low-temperature resistance and room-temperature resistance is described using the residual resistivity ratio (RRR). The specific formula is as follows: RRR = R(300K) / R(4K); Among them, the base resistance R b The residual resistance ratio RRR of (T) is, for example, 1.2~1.5, representing the base resistance R at 4K temperature. bThe resistance of (T) decreases by, for example, 15% to 30% compared to 300K. Emitter resistor R e (T) and collector parasitic resistance R c The residual resistance ratio RRR of (T) is, for example, 1.05~1.15, representing the emitter resistance R at 4K temperature. e (T) and collector parasitic resistance R c The resistance value of (T) decreases by, for example, 5% to 13% compared to 300K. This overall decrease in resistance value alters the gain, DC bias, and interstage matching of the low-noise amplifier, thus requiring active compensation in the circuit design. Simultaneously, the transconductance g at low temperatures... m The current gain is significantly enhanced due to the substantial reduction in thermal voltage, providing favorable conditions for low-power designs.

[0029] Please see Figure 2 As shown, this invention provides a superconducting nanowire single-photon detector readout system, which includes a low-temperature low-noise amplifier (CLNA), a nanowire detector (SNSPD), and a back-end circuit (DBE). The nanowire detector (SNSPD) is electrically connected between the input terminal and ground terminal of the CLNA. The SNSPD generates a pulse signal and inputs it to the CLNA. The back-end circuit (DBE) is electrically connected to the output terminal of the CLNA and reads out the amplified pulse signal. The DBE is a room-temperature signal processing and data acquisition circuit. A bias current is input to the CLNA. In an extremely low-temperature environment of 4K, the CLNA can provide high gain, ultra-low noise, and mild and stable broadband input matching, such as 50Ω, to suppress pulse reflection and waveform distortion.

[0030] Please see Figure 2As shown, the superconducting nanowire single-photon detector readout system also includes a bias resistor R0, a coupling capacitor C0, and a voltage source V0. The bias resistor R0 and coupling capacitor C0 are connected in series between the voltage source V0 and the cryogenic low-noise amplifier CLNA. One end of the bias resistor R0 is electrically connected to the voltage source V0, and the other end is electrically connected to the coupling capacitor C0. One end of the coupling capacitor C0 is electrically connected to the bias resistor R0, and the other end is electrically connected to the cryogenic low-noise amplifier CLNA. One end of the voltage source V0 is electrically connected to the bias resistor R0, and the other end is grounded. The voltage source V0 provides the fundamental electromotive force, and the bias resistor R0 converts the voltage into a stable bias current. The bias resistor R0 and the voltage source V0 provide a stable operating state for the nanowire detector SNSPD, enabling it to have photon response capability. One end of the nanowire detector SNSPD is electrically connected to the common terminal of the bias resistor R0 and the coupling capacitor C0, and the other end is grounded. A coupling capacitor C0 is connected in series between the nanowire detector SNSPD and the cryogenic low-noise amplifier CLNA. Utilizing the physical characteristic of capacitors blocking DC and passing AC, the transmission of DC bias voltage from the nanowire detector SNSPD side to the cryogenic low-noise amplifier CLNA side can be blocked. Simultaneously, for the sub-nanosecond high-frequency transient pulse signal generated by the nanowire detector SNSPD, the coupling capacitor C0 exhibits a low AC impedance, allowing the RF pulse to couple into the cryogenic low-noise amplifier CLNA with low loss, thus achieving a combination of DC isolation and RF signal transmission.

[0031] Please see Figure 3 As shown, this invention provides a low-temperature low-noise amplifier (CLNA). The CLNA includes a first-stage amplifier circuit, a second-stage amplifier circuit, and an interstage coupling circuit. The first-stage amplifier circuit includes a first-stage transistor Q1 and a first feedback circuit. The base of the first-stage transistor Q1 is the input terminal of the CLNA, the emitter of the first-stage transistor Q1 is grounded, and the collector of the first-stage transistor Q1 is the output terminal of the first-stage amplifier circuit. The first feedback circuit is electrically connected between the collector and base of the first-stage transistor Q1. The second-stage amplifier circuit includes a second-stage transistor Q2 and a second feedback circuit. The base of the second-stage transistor Q2 is electrically connected to the collector of the first-stage transistor Q1, the collector of the second-stage transistor Q2 is the output terminal of the second-stage amplifier circuit, and the emitter of the second-stage transistor Q2 is grounded. The second feedback circuit is electrically connected between the collector and base of the second-stage transistor Q2. The interstage coupling circuit is connected in series between the collector of the first-stage transistor Q1 and the base of the second-stage transistor Q2. The emitter area of ​​the first-stage transistor Q1 is larger than the emitter area of ​​the second-stage transistor Q2.

[0032] Please see Figure 3As shown, in one embodiment of the present invention, the low-temperature low-noise amplifier (CLNA) includes multiple electrostatic discharge (ESD) protection structures. These ESD protection structures are electrically connected between each port of the CLNA and the ground terminal. The ports of the CLNA include an input terminal IN, a bias voltage input terminal, and an output terminal OUT. The bias voltage input terminal includes a first bias voltage input terminal V. C1 Second bias voltage input terminal V B1 Third bias voltage input terminal V C2 and the fourth bias voltage input terminal V B2 The first bias voltage input terminal V C1 Second bias voltage input terminal V B1 Third bias voltage input terminal V C2 and the fourth bias voltage input terminal V B2 The input bias voltage is used to establish a stable quiescent operating point for the transistor. The electrostatic discharge (ESD) protection structure includes an electrostatic resistor R. ESD and electrostatic capacitance C ESD electrostatic resistance R ESD and electrostatic capacitance C ESD Parallel connection. By setting independent bias voltage input ports, the coupling between the preceding and following stages on the DC bias can be cut off, achieving independent optimization of transconductance stage by stage, which helps to control the total power consumption of a single channel to below the milliwatt level. Each bias voltage input port is connected to an electrostatic discharge (ESD) protection structure, which can provide ESD protection while maintaining low noise and low power consumption of the bias branch. In this embodiment, the first bias voltage input terminal V C1 Second bias voltage input terminal V B1 Third bias voltage input terminal V C2 and the fourth bias voltage input terminal V B2 Different bias voltages can be input, and you can set them according to your specific needs.

[0033] Please see Figure 3 As shown, in one embodiment of the present invention, the low-temperature low-noise amplifier CLNA further includes an input inductor L. IN Input inductance L IN The circuit is electrically connected between the input terminal IN of the low-temperature low-noise amplifier CLNA and the base of the first-stage transistor Q1. After the signal enters through the input terminal IN, it first passes through the electrostatic discharge (ESD) protection structure. The ESD protection structure is equivalent to a grounded parallel capacitor in the RF path, participating in impedance calculations as part of the input matching network, thus eliminating its degrading effect on wideband input matching without weakening the ESD protection capability. Subsequently, the signal passes through the input inductor L... IN The input is fed into the base of the first-stage transistor Q1. Input inductor L INThe input capacitance of the first-stage transistor Q1 resonates in series at the target frequency, precisely canceling the imaginary part of the capacitance and pulling the input impedance toward purely resistive, laying the foundation for achieving, for example, 50Ω low-noise matching.

[0034] Please see Figure 3 As shown, in one embodiment of the present invention, the first-stage amplifier circuit further includes a first bypass capacitor C1 and a first resistor R1. The first resistor R1 is electrically connected to the second bias voltage input terminal V of the low-temperature low-noise amplifier CLNA. B1 Between the base of the first-stage transistor Q1 and the second bias voltage input terminal V, the first bypass capacitor C1 is electrically connected. B1 Between the base and ground. The first resistor R1 provides a small and stable DC bias current to the base of the first-stage transistor Q1, establishing the correct quiescent operating point for Q1. The first bypass capacitor C1 grounds the base to the RF signal AC, ensuring that the low-temperature low-noise amplifier CLNA operates in common-emitter configuration, while short-circuiting the thermal noise and power supply ripple introduced by the first resistor R1, preventing them from degrading the noise figure and gain. The second bias voltage input terminal V B1 The generated DC current is injected into the base of the first-stage transistor Q1 through the first resistor R1. The first bypass capacitor C1 is equivalent to a short circuit to ground at the target high frequency, so that the base bias domain of the first-stage transistor Q1 only undertakes the DC setting function and does not participate in any AC signal transmission.

[0035] Please see Figure 3 As shown, in one embodiment of the present invention, the first-stage amplifier circuit further includes a first collector load resistor R. C1 And the first inductor L1, the first collector load resistor R C1 The first inductor L1 is connected in series with the first bias voltage input terminal V of the low-temperature low-noise amplifier CLNA. C1 Between the collector of the first-stage transistor Q1 and the first-stage transistor Q1. Specifically, the first collector load resistor R... C1 One end is electrically connected to the first bias voltage input terminal V. C1 The first collector load resistor R C1 The other end is electrically connected to the first inductor L1. One end of the first inductor L1 is electrically connected to the first collector load resistor R. C1 The other end of the first inductor L1 is electrically connected to the collector of the first-stage transistor Q1. The first bias voltage input terminal V... C1 Through the first collector load resistor R C1 The first inductor L1 provides the main current energy to the collector of the first-stage transistor Q1, and independently controls the power consumption and output swing of this stage. In this embodiment, the first collector load resistor R... C1 An n+ diffusion resistor is used, with a residual resistance ratio (RRR) of, for example, 1.1~1.4. The transconductance g of the first-stage transistor Q1 at low temperature...m A significant increase in voltage gain will cause an abnormal rise and lead to DC operating point drift. An n+ diffusion resistor is selected as the first collector load resistor R. C1 Subsequently, the resistance of the n+ diffusion resistor decreases at an extremely low temperature of 4K, thereby offsetting the transconductance g. m The increment ensures that the overall voltage gain remains flat over a wide temperature range. Simultaneously, the collector parasitic resistance R... c (T) and the first collector load resistor R C1 Both are n+ doped materials, with identical temperature coefficients, and their impedance variations in the collector branch are matched throughout, avoiding additional errors caused by thermal mismatch. This is achieved through the first collector load resistor R. C1 The first inductor L1 is connected in series to provide gain peak compensation at high frequencies, while the first collector load resistor R... C1 Losses are introduced to lower the resonant Q value, thereby gaining a wider flat bandwidth and higher stability.

[0036] Please see Figure 3 As shown, in one embodiment of the present invention, the first-stage amplifier circuit further includes a first feedback circuit, which includes a first feedback resistor R. F1 and the first feedback capacitor C F1 The first feedback capacitor C F1 One end is electrically connected to the first collector load resistor R. C1 The common terminal of the first inductor L1, and the first feedback capacitor C F1 The other end is electrically connected to the first feedback resistor R. F1 First feedback capacitor C F1 It can block DC and pass AC, keeping the DC bias unaffected. First feedback resistor R. F1 One end is electrically connected to the first feedback capacitor C. F1 First feedback resistor R F1 The other end is electrically connected to the base of the first-stage transistor Q1. The first feedback resistor R... F1 The depth of the feedback is determined. The input to the first feedback circuit is the output voltage of the collector of the first-stage transistor Q1. The first feedback circuit samples this voltage and converts it into a feedback current, which is injected in reverse into the base of the first-stage transistor Q1 to form a voltage-current negative feedback. This can expand the input-output matching bandwidth, improve circuit stability, and reduce the closed-loop sensitivity to the increase in current gain at low temperatures.

[0037] Please see Figure 3 As shown, in one embodiment of the present invention, an interstage coupling circuit is electrically connected between the first-stage amplifier circuit and the second-stage amplifier circuit. The interstage coupling circuit includes an interstage capacitor C. A Interstage inductance L A and interstage resistance R A Interstage capacitance CA Interstage inductance L A and interstage resistance R A It is connected in series between the collector of the first-stage transistor Q1 and the base of the second-stage transistor Q2. Specifically, the interstage capacitance C... A One end is electrically connected to the collector of the first-stage transistor Q1, and the interstage capacitance C A The other end is electrically connected to the interstage inductor L. A Interstage capacitance C A Used for DC blocking and AC coupling. Interstage inductance L A One end is electrically connected to the interstage capacitor C A Interstage inductance L A The other end is electrically connected to the interstage resistor R. A Interstage inductance L A Used to compensate for high-frequency gain roll-off. Interstage resistance R A One end is electrically connected to the interstage inductor L A Interstage resistance R A The other end is electrically connected to the base of the second-stage transistor Q2. Interstage resistance R A Used to improve impedance matching, enhance stability, and prevent self-oscillation. In this embodiment, the interstage resistance R... A An n+ diffusion resistor is used. The base-emitter input impedance of the second-stage transistor Q2 decreases at low temperatures due to transconductance g. m Increases and decreases significantly, interstage resistance R A By using an n+ diffusion resistor, its resistance decreases in the same direction as the temperature decreases, automatically following the changing trend of the base-emitter input impedance of the second-stage transistor Q2, so that the interstage impedance ratio remains relatively constant over the entire temperature range, thereby stabilizing the cascade gain and return loss.

[0038] Please see Figure 3 As shown, in one embodiment of the present invention, the second-stage amplifier circuit further includes a second bypass capacitor C2 and a second resistor R2, the second resistor R2 being electrically connected to the fourth bias voltage input terminal V of the low-temperature low-noise amplifier CLNA. B2 Between the base of the second-stage transistor Q2, the second bypass capacitor C2 is electrically connected to the fourth bias voltage input terminal V. B2 Between the ground terminal and the base terminal. The second resistor R2 provides a small and stable DC bias current to the base of the second-stage transistor Q2, establishing the correct quiescent operating point for Q2. The second bypass capacitor C2 grounds the base of the second-stage transistor Q2 to the RF signal AC ground, ensuring that the low-temperature low-noise amplifier CLNA operates in common-emitter configuration, while short-circuiting the thermal noise and power supply ripple introduced by the second resistor R2, preventing them from degrading the noise figure and gain. The fourth bias voltage input terminal V B2The generated DC current is injected into the base of the second-stage transistor Q2 through the second resistor R2. The second bypass capacitor C2 is equivalent to a short circuit to ground at the target high frequency, so that the base bias domain of the second-stage transistor Q2 only undertakes the DC setting function and does not participate in any AC signal transmission.

[0039] Please see Figure 3 As shown, in one embodiment of the present invention, the second-stage amplifier circuit further includes a second collector load resistor R. C2 The second collector load resistor R C2 Electrically connected to the third bias voltage input terminal V of the low-temperature, low-noise amplifier CLNA. C2 Between the collector of the second-stage transistor Q2 and the third voltage input bias voltage input terminal V. C2 The generated DC current flows through the second collector load resistor R C2 Injecting into the collector of the second-stage transistor Q2 provides a flat, wideband gain and DC bias, improving circuit stability. In this embodiment, the second collector load resistor R... C2 An n+ diffusion resistor is used. At the extremely low temperature of 4K, the resistance of the n+ diffusion resistor decreases, thereby offsetting the transconductance g. m The increment makes the overall voltage gain remain flat over a wide temperature range.

[0040] Please see Figure 3 As shown, in one embodiment of the present invention, the second-stage amplifier circuit further includes a second feedback circuit, which includes a second feedback resistor R. F2 Second feedback capacitor C F2 The second feedback capacitor C F2 One end is electrically connected to the second collector load resistor R. C2 The common terminal of the collector of the first-stage transistor Q1, and the second feedback capacitor C F2 The other end is electrically connected to the second feedback resistor R. F2 The second feedback capacitor C F2 It can block DC and pass AC, keeping the DC bias unaffected. Second feedback resistor R F2 One end is electrically connected to the second feedback capacitor C. F2 The second feedback resistor R F2 The other end is electrically connected to the base of the second-stage transistor Q2. The second feedback resistor R... F2 The depth of the feedback is determined. The input to the second feedback circuit is the output voltage of the collector of the second-stage transistor Q2. The second feedback circuit samples this voltage and converts it into a feedback current, which is injected in reverse into the base of the second-stage transistor Q2 to form a voltage-current negative feedback. This can expand the input-output matching bandwidth, improve circuit stability, and reduce the closed-loop sensitivity to the increase in current gain at low temperatures.

[0041] Please see Figure 3As shown, in one embodiment of the present invention, the low-temperature low-noise amplifier CLNA further includes an output resistor R. OUT Output resistance R OUT The circuit is electrically connected between the collector of the second-stage transistor Q2 and the output terminal OUT of the low-temperature, low-noise amplifier CLNA. The output resistor R... OUT Second collector load resistor R C2 The equivalent parallel impedance of the ESD protection structure at the output terminal OUT is considered as a whole, along with the second collector load resistor R. C2 Provides flat broadband gain and DC bias, with output resistance R. OUT By widening the output impedance to approximately 50Ω through lossy matching, while absorbing reflections and providing high reverse isolation, the return loss of the wideband output is improved and pulse reflections and ringing are reduced.

[0042] Please see Figure 3 As shown, in one embodiment of the present invention, the low-temperature low-noise amplifier CLNA is implemented using, for example, a 130nm silicon-germanium bipolar complementary metal-oxide-semiconductor process. At an extremely low temperature of 4K, the input terminal IN receives a sub-millivolt input signal. The first and second stage amplifier circuits inside the CLNA amplify the sub-millivolt input signal to a millivolt output signal, achieving a transient gain of, for example, above 20dB. During the amplification process, the first-stage transistor Q1, with its large emitter area, can reduce the base resistance R. b (T) is used to achieve ultra-low noise temperature and complete the primary voltage amplification of the signal. The second-stage transistor Q2 uses a smaller emitter area and utilizes the low-temperature transconductance g m The enhanced efficiency enables stable output matching with lower current, thereby keeping the total power consumption at the milliwatt level. This completes the secondary amplification and impedance transformation of the signal, achieving comprehensive optimization of wideband matching, ultra-low noise, and low power consumption.

[0043] This invention provides a low-temperature, low-noise amplifier and a readout system for a superconducting nanowire single-photon detector. The low-temperature, low-noise amplifier employs a two-stage common-emitter topology and a cascaded multi-stage architecture to mitigate parameter dispersion in low-temperature devices. The two amplifier stages each provide independent bias voltage input ports, enabling stage-by-stage transconductance optimization and milliwatt-level single-channel power consumption control. At the input, the electrostatic protection structure is equivalent to a grounded parallel capacitor, forming a resonant network with the input inductor to achieve broadband matching recovery under low-temperature conditions. The first-stage transistor achieves ultra-low noise temperature with a large emitter area, while the second-stage transistor significantly reduces power consumption with a small emitter area, maintaining high gain while keeping total power consumption in the milliwatt range. The first and second feedback circuits broaden the input matching bandwidth and reduce closed-loop sensitivity caused by increased current gain at low temperatures. The interstage coupling circuit uses an interstage inductor to compensate for high-frequency gain roll-off and improve gain flatness. A shunt peak is achieved by connecting the first collector load resistor in series with the first inductor, extending the high-frequency bandwidth without additional DC power consumption. By combining the second collector load resistor with the output resistor and tuning it in conjunction with the equivalent parallel impedance of the electrostatic protection structure, broadband output return loss can be improved, and pulse reflection and ringing can be reduced. In addition, the first collector load resistor, the second collector load resistor, and the interstage resistor all use n+ diffused resistors, which can achieve predictability of DC bias and interstage impedance at low temperatures, ensuring reliable operation across the entire temperature range from room temperature to 4K.

[0044] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A low-temperature, low-noise amplifier, characterized in that, At least including: The first-stage amplifier circuit includes a first-stage transistor and a first feedback circuit. The base of the first-stage transistor is the input terminal of the low-temperature low-noise amplifier, the emitter of the first-stage transistor is grounded, the collector of the first-stage transistor is the output terminal of the first-stage amplifier circuit, and the first feedback circuit is electrically connected between the collector and the base of the first-stage transistor. The second-stage amplifier circuit includes a second-stage transistor and a second feedback circuit. The base of the second-stage transistor is electrically connected to the collector of the first-stage transistor. The collector of the second-stage transistor is the output terminal of the low-temperature low-noise amplifier. The emitter of the second-stage transistor is grounded. The second feedback circuit is electrically connected between the collector and the base of the second-stage transistor. as well as An interstage coupling circuit is electrically connected between the collector of the first-stage transistor and the base of the second-stage transistor. The emitter area of ​​the first-stage transistor is larger than that of the second-stage transistor.

2. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The first stage amplifier circuit includes a first collector load resistor and a first inductor, which are connected in series between the first bias voltage input terminal of the low-temperature low-noise amplifier and the collector of the first stage transistor.

3. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The first feedback circuit includes a first feedback resistor and a first feedback capacitor. One end of the first feedback capacitor is electrically connected to the common terminal of the first collector load resistor and the first inductor. The other end of the first feedback capacitor is electrically connected to the first feedback resistor. One end of the first feedback resistor is electrically connected to the first feedback capacitor. The other end of the first feedback resistor is electrically connected to the base of the first stage transistor.

4. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The first-stage amplifier circuit includes a first bypass capacitor and a first resistor. The first resistor is electrically connected between the second bias voltage input terminal of the low-temperature low-noise amplifier and the base of the first-stage transistor. The first bypass capacitor is electrically connected between the second bias voltage input terminal and the ground terminal.

5. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The second-stage amplifier circuit includes a second collector load resistor, which is electrically connected between the third bias voltage input terminal of the low-temperature low-noise amplifier and the collector of the second-stage transistor.

6. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The second feedback circuit includes a second feedback resistor and a second feedback capacitor. One end of the second feedback capacitor is electrically connected to the common terminal of the second collector load resistor and the collector of the first stage transistor. The other end of the second feedback capacitor is electrically connected to the second feedback resistor. One end of the second feedback resistor is electrically connected to the second feedback capacitor. The other end of the second feedback resistor is electrically connected to the base of the second stage transistor.

7. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The second-stage amplifier circuit includes a second bypass capacitor and a second resistor. The second resistor is electrically connected between the fourth bias voltage input terminal of the low-temperature low-noise amplifier and the base of the first-stage transistor. The second bypass capacitor is electrically connected between the fourth bias voltage input terminal and the ground terminal.

8. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The interstage coupling circuit includes an interstage capacitor, an interstage inductor, and an interstage resistor, which are connected in series between the collector of the first-stage transistor and the base of the second-stage transistor.

9. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The low-temperature, low-noise amplifier includes an input inductor and an output resistor. The input inductor is electrically connected between the input terminal of the low-temperature, low-noise amplifier and the base of the first-stage transistor, and the output resistor is electrically connected between the collector of the second-stage transistor and the output terminal of the low-temperature, low-noise amplifier.

10. The low-temperature, low-noise amplifier according to claim 1, characterized in that, The low-temperature, low-noise amplifier includes multiple electrostatic protection structures, which are electrically connected between each port of the low-temperature, low-noise amplifier and the ground terminal. The ports of the low-temperature, low-noise amplifier include the input terminal, the output terminal, and the bias voltage input terminal.

11. The low-temperature, low-noise amplifier according to claim 10, characterized in that, The electrostatic protection structure includes an electrostatic capacitor and an electrostatic resistor, which are connected in parallel.

12. A readout system for a superconducting nanowire single-photon detector, characterized in that, The superconducting nanowire single-photon detector readout system includes at least: The low-temperature, low-noise amplifier as described in any one of claims 1 to 11; A nanowire detector, electrically connected between the input terminal and the ground terminal of the cryogenic low-noise amplifier, generates a pulse signal and inputs the pulse signal into the cryogenic low-noise amplifier; and The back-end circuit is electrically connected to the output terminal of the low-temperature, low-noise amplifier, and the back-end circuit reads out the pulse signal amplified by the low-temperature, low-noise amplifier.

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