biasing circuit

Abstract

The application provides a bias circuit, which comprises a current mirror circuit, a resistance array and a starting circuit, the starting circuit is arranged to control the closing and opening of the current mirror circuit, the switching of an enable signal from a first level signal to a second level signal can open the current mirror circuit, so that the bias circuit starts and is in a normal working state, the design of the resistance array can realize high-precision adjustment of multiple levels of output current of the current mirror circuit, not only can flexibly support the bandwidth adjustment of a low-noise amplifier and the current configuration of a driving buffer, but also has good power supply rejection characteristics, and significantly reduces the influence of power supply fluctuation on the output current.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bias circuit. Background Technology

[0002] In neurophysiological signal processing, low-noise amplifiers (LNAs) require flexible bandwidth adjustment in addition to amplifying signal amplitude. Traditional methods typically change bandwidth by adjusting the load capacitance. However, due to the low frequency of neural signals, amplifier bandwidth needs to be as low as several hundred hertz, often necessitating extremely large load capacitances and significantly increasing chip area. Therefore, a more common approach now is to adjust the bandwidth by regulating the amplifier's bias current, making the bias current generation module a crucial component.

[0003] Furthermore, in neural signal amplification links, a drive buffer is typically used to drive the analog-to-digital converter. The drive current of this buffer is often designed to be flexibly adjustable so that an appropriate drive capability level can be selected in practical applications.

[0004] Therefore, it is essential to provide a bias circuit that can generate high-precision current. Summary of the Invention

[0005] This invention provides a bias circuit that can achieve bias output independent of power supply and achieve high-precision adjustment of bias current at multiple levels.

[0006] To solve the above-mentioned technical problems, the present invention provides a bias circuit, which includes:

[0007] A current mirror circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor and the second PMOS transistor constitute a PMOS current mirror, and the first to fourth NMOS transistors constitute a common-source, common-gate current mirror. The first NMOS transistor and the second NMOS transistor are connected with a common gate, and the third NMOS transistor and the fourth NMOS transistor are connected with a common gate. A branch formed by the first PMOS transistor, the first NMOS transistor, and the third NMOS transistor connected in series is connected between the power supply voltage and the reference ground. A branch formed by the second PMOS transistor, the second NMOS transistor, and the fourth NMOS transistor connected in series is connected between the power supply voltage and the reference ground.

[0008] A resistor array is provided, through which the fourth NMOS transistor is connected to a reference ground, and the resistance value of the resistor array is adjustable.

[0009] The startup circuit controls the current mirror circuit to turn off or on according to the enable signal. The switching of the enable signal from a first level signal to a second level signal will turn on the current mirror circuit, so that the bias circuit starts up and is in normal working condition.

[0010] Optionally, the startup circuit includes:

[0011] A signal conversion module, which outputs a first control signal and a second control signal according to the enable signal;

[0012] A first switching module, one end of which is connected to the gate of the first NMOS transistor, and the second end of which is connected to a reference ground;

[0013] The second switching module has one end connected between the first NMOS transistor and the first PMOS transistor, and the other end connected between the second PMOS transistor and the second NMOS transistor.

[0014] When the enable signal is a first level signal, the first control signal controls the first switch module to turn on, and the second control signal controls the second switch module to turn on, thereby turning on the second PMOS transistor; when the enable signal is a second level signal, the first control signal controls the first switch module to turn off, and the second control signal controls the second switch module to turn off.

[0015] Optionally, the signal conversion module includes an inverter chain consisting of at least two cascaded inverters. The input terminal of the inverter chain receives the enable signal, one node of the inverter chain outputs the first control signal, and the other node of the inverter chain outputs the second control signal.

[0016] Optionally, the first switching module includes a seventh NMOS transistor.

[0017] Optionally, the second switching module includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The branch formed by the third PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor connected in series is connected between the power supply voltage and the reference ground. The gate of the fifth NMOS transistor is connected between the first PMOS transistor and the first NMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are connected to the second control signal. The gate of the sixth NMOS transistor is connected between the fourth PMOS transistor and the fifth NMOS transistor. The drain of the sixth NMOS transistor is connected between the second PMOS transistor and the second NMOS transistor. The source of the sixth NMOS transistor is connected to the reference ground.

[0018] Optionally, the resistor array includes a switch array module and a resistor string. The resistor string includes multiple resistors connected in series. The connection nodes between two adjacent resistors and the connection nodes at both ends of the resistor string are all connected to the switch array module. The switch array module controls its own on / off state according to a control signal, thereby short-circuiting at least one resistor in the resistor string.

[0019] Optionally, the switch array module includes multiple switch arrays, the switch arrays having 2 N One first connection end and two corresponding to each first connection end N There are two second connection terminals, one of which is switch array A, and the remaining switch arrays are switch arrays B, with N switch arrays B in total. The resistor string comprises N*2 N A resistor, all first connection terminals of the switch array A are connected to the source of the fourth NMOS transistor; all second connection terminals of the switch array B are sequentially connected to different connection nodes of the resistor string, and the first connection terminals of the switch array B are connected to the second connection terminals of the switch array A one by one;

[0020] The control signal is used to control the on / off state between the first and second connection terminals of the switch array A and the first connection terminal and the corresponding second connection terminal of the switch array B; N is an integer greater than or equal to 2.

[0021] Optionally, N is 4, the first connection terminals of the switch array are D0~D15 sequentially, the second connection terminals of the switch array are S0~S15 sequentially, the connection nodes of the resistor string are Ri0~Ri63 sequentially, and the switch arrays B are switch arrays B0~B3 respectively, wherein:

[0022] The first connection terminals D0~D15 of each of the switch arrays B1 and B3 are sequentially connected to the second connection terminals S0~S15 of the switch array A; the first connection terminals D0~D15 of each of the switch arrays B0 and B2 are sequentially connected to the second connection terminals S15~S0 of the switch array A; the second connection terminals S15~S0 of the switch array B3 are sequentially connected to the connection nodes Ri0~Ri15 of the resistor string; the second connection terminals S15~S0 of the switch array B2 are sequentially connected to the connection nodes Ri16~Ri31 of the resistor string; the second connection terminals S15~S0 of the switch array B1 are sequentially connected to the connection nodes Ri32~Ri47 of the resistor string; and the second connection terminals S15~S0 of the switch array B0 are sequentially connected to the connection nodes Ri48~Ri63 of the resistor string.

[0023] Optionally, the switch array includes N switching transistors, with the first connection terminal and the second connection terminal being the two ends of each switching transistor.

[0024] Optionally, the number of resistor arrays is at least two, and they are arranged in series.

[0025] The bias circuit described above can control the current mirror circuit to turn on or off by setting a startup circuit. When the enable signal switches from the first level signal to the second level signal, the bias circuit will be activated, so that the bias circuit is in normal working condition. The resistor array design can realize high-precision adjustment of the output current of the current mirror circuit at multiple levels. It can not only flexibly support the bandwidth adjustment of the low noise amplifier and the current configuration of the drive buffer, but also has good power supply rejection characteristics, which significantly reduces the impact of power supply fluctuations on the output current. Attached Figure Description

[0026] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0027] Figure 1 This is a schematic diagram of a bias circuit according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a switch array module of a resistor array according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of a resistor string in a resistor array according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of a switch array A according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of a switch array B according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] Figure 1 This is a schematic diagram of a bias circuit according to an embodiment of the present invention. (See attached diagram.) Figure 1This invention provides an illustrative bias circuit, which includes a current mirror circuit, a startup circuit, and a resistor array. The current mirror circuit includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first NMOS transistor Mn1, a second NMOS transistor Mn2, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4. The first PMOS transistor Mp1 and the second PMOS transistor Mp2 constitute a PMOS current mirror, and the first NMOS transistors Mn1 to the fourth NMOS transistors Mn4 constitute a common-source common-gate current mirror. The first NMOS transistor Mn1 and the second NMOS transistor Mn2 are connected in a common-gate configuration, and the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4 are also connected in a common-gate configuration. The branch formed by the first PMOS transistor Mp1, the first NMOS transistor Mn1, and the third NMOS transistor Mn3 connected in series is connected between the power supply voltage VDD and the reference ground VSS. The branch formed by the second PMOS transistor Mp2, the second NMOS transistor Mn2, and the fourth NMOS transistor Mn4 connected in series is also connected between the power supply voltage VDD and the reference ground VSS. The fourth NMOS transistor Mn4 is connected to the reference ground VSS through the resistor array, the resistance of which is adjustable. The startup circuit controls the current mirror circuit to turn off or on according to the enable signal. The switching of the enable signal from the first level signal to the second level signal will turn on the current mirror circuit, so that the bias circuit starts up and is in normal working state. For example, when the enable signal switches from low level to high level, it will start the bias circuit and make the bias circuit in normal working state.

[0035] Among them, the width-to-length ratio of the fourth NMOS transistor Mn4 is k times that of the third NMOS transistor Mn3. Generally, the lengths of the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4 are relatively large, which results in better matching. Ignoring body effects, assuming that the V of the third NMOS transistor Mn3... THn3 and the V of the fourth NMOS transistor Mn4 THn4 If the values ​​are the same, and the equivalent resistance of the resistor array is Rs, then the current flowing through the first PMOS transistor Mp1 and the second PMOS transistor Mp2 is:

[0036]

[0037] As can be seen from the formula above, the output current Iout is only related to the process parameters of the MOSFET, the width-to-length ratio of the MOSFET, the ratio k of the width-to-length ratio of the fourth NMOS transistor Mn4 and the third NMOS transistor Mn3, and the resistance value Rs of the resistor array. Therefore, the output current value can be adjusted by adjusting the resistance value Rs.

[0038] This invention incorporates a startup circuit that controls the current mirror circuit to turn on or off based on an enable signal. When the enable signal switches from a first-level signal to a second-level signal, the current mirror circuit is activated, enabling the bias circuit to start and operate normally. The resistor array design allows for high-precision adjustment of the output current of the current mirror circuit at multiple levels. It not only flexibly supports bandwidth adjustment of the low-noise amplifier and current configuration of the drive buffer, but also possesses excellent power supply suppression characteristics, significantly reducing the impact of power supply fluctuations on the output current.

[0039] See Figure 1 The startup circuit includes a signal conversion module, a first switch module, and a second switch module. The signal conversion module outputs a first control signal ENB and a second control signal ENA according to the enable signal EN. One end of the first switch module is connected to the gate of the first NMOS transistor Mn1, and the second end of the first switch module is connected to the reference ground VSS. One end of the second switch module is connected between the first NMOS transistor Mn1 and the first PMOS transistor Mp1, and the other end of the second switch module is connected between the second PMOS transistor Mp2 and the second NMOS transistor Mn2. When the enable signal is a first-level signal, the first control signal ENB controls the first switch module to turn on, and the second control signal ENA controls the second switch module to turn on, causing the second PMOS transistor Mp2 to turn on and replicate current to the first PMOS transistor Mp1. When the enable signal is a second-level signal, the first control signal ENB controls the first switch module to turn off, and the second control signal ENA controls the second switch module to turn off, thus ensuring that the bias circuit enters normal operating condition after startup.

[0040] In one embodiment, the signal conversion module includes an inverter chain consisting of at least two cascaded inverters INV. The input of the inverter chain receives the enable signal EN. One node of the inverter chain outputs the first control signal ENB, and the other node of the inverter chain outputs the second control signal ENA.

[0041] In one embodiment, the first switching module includes a seventh NMOS transistor, Mn7.

[0042] In one embodiment, the second switching module includes a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a fifth NMOS transistor Mn5, and a sixth NMOS transistor Mn6. The branch formed by the third PMOS transistor Mp3, the fourth PMOS transistor Mp4, and the fifth NMOS transistor Mn5 connected in series is connected between the power supply voltage VDD and the reference ground VSS. The gate of the fifth NMOS transistor Mn5 is connected between the first PMOS transistor Mp1 and the first NMOS transistor Mn1. The gates of the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4 are connected to the second control signal ENA. The gate of the sixth NMOS transistor Mn6 is connected between the fourth PMOS transistor Mp4 and the fifth NMOS transistor Mn5. The drain of the sixth NMOS transistor Mn6 is connected between the second PMOS transistor Mp2 and the second NMOS transistor Mn2. The source of the sixth NMOS transistor Mn6 is connected to the reference ground VSS.

[0043] Thus, when the enable signal EN is low, the first control signal ENB is high, the second control signal ENA is low, the gate of the seventh NMOS transistor Mn7 is pulled high, the gate of the fifth NMOS transistor Mn5 is pulled low, and the gate of the sixth NMOS transistor Mn6 is pulled high, thereby turning on the sixth NMOS transistor Mn6. The drain of the sixth NMOS transistor Mn6 is pulled to ground. At this time, the second PMOS transistor Mp2 will turn on, thereby replicating current to the first PMOS transistor Mp1. When the enable signal EN switches to high, the bias circuit starts, and the gates of the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4 are pulled high, thereby turning off the sixth NMOS transistor Mn6 and the seventh NMOS transistor Mn7. The entire bias circuit is in normal working condition.

[0044] See Figure 2 and Figure 3 Furthermore, the resistor array includes a switch array module and a resistor string. The resistor string includes multiple resistors connected in series. The connection nodes between two adjacent resistors and the connection nodes at both ends of the resistor string are all connected to the switch array module. The switch array module controls its own on / off state according to the control signal, thereby short-circuiting at least one resistor in the resistor string. This allows adjustment of the resistance in the circuit, thereby adjusting the resistance value Rs of the equivalent resistance of the resistor array and realizing the regulation of the output current of the current mirror circuit.

[0045] See Figure 2 In one embodiment, the switch array module includes multiple switch arrays, the switch arrays having 2 N One first connection end and two corresponding to each first connection end NThere are two second connection terminals, one of which is switch array A, and the remaining switch arrays are switch arrays B, with N switch arrays B in total. The resistor string comprises N*2 N A resistor is used to connect all the first connection terminals of the switch array A to the source of the fourth NMOS transistor Mn4; all the second connection terminals of the switch array B are sequentially connected to different connection nodes of the resistor string, and the first connection terminals of the switch array B are connected to the second connection terminals of the switch array A one by one; the control signal is used to control the on / off state between the first connection terminals and the second connection terminals of the switch array A and to control the on / off state between the first connection terminal and the corresponding second connection terminal of the switch array B; N is an integer greater than or equal to 2.

[0046] See Figures 2 to 5 For example, N is 4, the first connection terminals of the switch array are D0~D15 in sequence, the second connection terminals of the switch array are S0~S15 in sequence, the connection nodes of the resistor string are Ri0~Ri63 in sequence, and the switch arrays B are switch arrays B0~B3 respectively. Specifically, the first connection terminals D0~D15 of each of the switch arrays B0 and B2 are sequentially connected to the second connection terminals S15~S0 of the switch array A; the first connection terminals D0~D15 of each of the switch arrays B1 and B3 are sequentially connected to the second connection terminals S0~S15 of the switch array A; the second connection terminals S15~S0 of the switch array B3 are sequentially connected to the connection nodes Ri0~Ri15 of the resistor string; the second connection terminals S15~S0 of the switch array B2 are sequentially connected to the connection nodes Ri16~Ri31 of the resistor string; the second connection terminals S15~S0 of the switch array B1 are sequentially connected to the connection nodes Ri32~Ri47 of the resistor string; and the second connection terminals S15~S0 of the switch array B0 are sequentially connected to the connection nodes Ri48~Ri63 of the resistor string.

[0047] This embodiment illustrates the use of switch array A and switch arrays B0~B3, where 64 resistors are connected in series to form a resistor string, enabling 64 adjustable current output levels. For special needs or applications requiring more precise current output, at least two resistor arrays can be connected in series to achieve even more levels of current output adjustment. For example, simply connecting two... Figure 2 By connecting resistor arrays in series, 128 adjustable current output levels can be achieved.

[0048] In one embodiment, the switch array includes N switching transistors, with the first connection terminal and the second connection terminal being the two ends of each switching transistor. The switching transistors here can be, for example, NMOS transistors.

[0049] In this configuration, switch array A is controlled by a 16-bit signal OUTA<15:0>, which controls the on / off state of the second connection terminals corresponding to the first connection terminals in switch array A, i.e., controls the on / off state of each switch transistor in switch array A. Switch arrays B0~B3 are controlled by a 4-bit signal OUTB<3:0>, which controls the on / off state of each switch array B, i.e., controls the on / off state of the switch transistors in each switch array B. OUTA<15:0> and OUTB<3:0> are obtained by decoding the 6-bit control signal RCTL<5:0>, with the following decoding relationship:

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[0070] It can be seen that each OUTA <n>Both are OR operations of two complementary extreme codewords: the left side of the equation is the code corresponding to the forward RCTL<4:0> count; the right side is the code corresponding to the reverse (complementary) RCTL<4:0> count. This design is to allow the switch array A to still use the same set of 5-bit code values ​​to correctly select the corresponding nodes simultaneously from two different directions, even when the resistor string is symmetrically connected at both ends, thus adapting to... Figure 2 A complex wiring structure with cross-connection between A and B0~B3.

[0071] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.< / n>

Claims

1. A bias circuit, characterized in that, include: A current mirror circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor and the second PMOS transistor constitute a PMOS current mirror, and the first to fourth NMOS transistors constitute a common-source, common-gate current mirror. The first NMOS transistor and the second NMOS transistor are connected with a common gate, and the third NMOS transistor and the fourth NMOS transistor are connected with a common gate. A branch formed by the first PMOS transistor, the first NMOS transistor, and the third NMOS transistor connected in series is connected between the power supply voltage and the reference ground. A branch formed by the second PMOS transistor, the second NMOS transistor, and the fourth NMOS transistor connected in series is connected between the power supply voltage and the reference ground. A resistor array is provided, through which the fourth NMOS transistor is connected to a reference ground, and the resistance value of the resistor array is adjustable. The startup circuit controls the current mirror circuit to turn off or on according to the enable signal. The switching of the enable signal from a first level signal to a second level signal will turn on the current mirror circuit, so that the bias circuit starts up and is in normal working condition.

2. The bias circuit according to claim 1, characterized in that, The startup circuit includes: A signal conversion module, which outputs a first control signal and a second control signal according to the enable signal; A first switching module, one end of which is connected to the gate of the first NMOS transistor, and the second end of which is connected to a reference ground; The second switching module has one end connected between the first NMOS transistor and the first PMOS transistor, and the other end connected between the second PMOS transistor and the second NMOS transistor. When the enable signal is a first level signal, the first control signal controls the first switch module to turn on, and the second control signal controls the second switch module to turn on, thereby turning on the second PMOS transistor; when the enable signal is a second level signal, the first control signal controls the first switch module to turn off, and the second control signal controls the second switch module to turn off.

3. The bias circuit according to claim 2, characterized in that, The signal conversion module includes an inverter chain consisting of at least two cascaded inverters. The input terminal of the inverter chain receives the enable signal, one node of the inverter chain outputs the first control signal, and the other node of the inverter chain outputs the second control signal.

4. The bias circuit according to claim 2, characterized in that, The first switching module includes a seventh NMOS transistor.

5. The bias circuit according to claim 2, characterized in that, The second switching module includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The branch formed by the third PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor connected in series is connected between the power supply voltage and the reference ground. The gate of the fifth NMOS transistor is connected between the first PMOS transistor and the first NMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are connected to the second control signal. The gate of the sixth NMOS transistor is connected between the fourth PMOS transistor and the fifth NMOS transistor. The drain of the sixth NMOS transistor is connected between the second PMOS transistor and the second NMOS transistor. The source of the sixth NMOS transistor is connected to the reference ground.

6. The bias circuit according to claim 1, characterized in that, The resistor array includes a switch array module and a resistor string. The resistor string includes multiple resistors connected in series. The connection nodes between two adjacent resistors and the connection nodes at both ends of the resistor string are all connected to the switch array module. The switch array module controls its own on / off state according to the control signal, thereby short-circuiting at least one resistor in the resistor string.

7. The bias circuit according to claim 6, characterized in that, The switch array module includes multiple switch arrays, each switch array having 2 N One first connection end and two corresponding to each first connection end N There are two second connection terminals, one of which is switch array A, and the remaining switch arrays are switch arrays B, with N switch arrays B in total. The resistor string comprises N*2 N A resistor, all first connection terminals of the switch array A are connected to the source of the fourth NMOS transistor; all second connection terminals of the switch array B are sequentially connected to different connection nodes of the resistor string, and the first connection terminals of the switch array B are connected to the second connection terminals of the switch array A one by one. The control signal is used to control the on / off state between the first and second connection terminals of the switch array A and the first connection terminal and the corresponding second connection terminal of the switch array B; N is an integer greater than or equal to 2.

8. The bias circuit according to claim 7, characterized in that, N is 4, the first connection terminals of the switch array are D0~D15 sequentially, the second connection terminals of the switch array are S0~S15 sequentially, the connection nodes of the resistor string are Ri0~Ri63 sequentially, and the switch arrays B are B0~B3 respectively, wherein: The first connection terminals D0~D15 of each of the switch arrays B1 and B3 are sequentially connected to the second connection terminals S0~S15 of the switch array A; the first connection terminals D0~D15 of each of the switch arrays B0 and B2 are sequentially connected to the second connection terminals S15~S0 of the switch array A; the second connection terminals S15~S0 of the switch array B3 are sequentially connected to the connection nodes Ri0~Ri15 of the resistor string; the second connection terminals S15~S0 of the switch array B2 are sequentially connected to the connection nodes Ri16~Ri31 of the resistor string; the second connection terminals S15~S0 of the switch array B1 are sequentially connected to the connection nodes Ri32~Ri47 of the resistor string; and the second connection terminals S15~S0 of the switch array B0 are sequentially connected to the connection nodes Ri48~Ri63 of the resistor string.

9. The bias circuit according to claim 7, characterized in that, The switch array includes N switching transistors, with the first connection terminal and the second connection terminal at each end of the switching transistor.

10. The bias circuit according to claim 1, characterized in that, The number of resistor arrays is at least two, and they are arranged in series.

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