Rail-to-rail input circuit and high-speed high-bandwidth operational amplifier

Abstract

The application discloses a rail-to-rail input circuit and a high-speed high-bandwidth operational amplifier, and the rail-to-rail input circuit comprises an input stage, a common-mode detection circuit, an adaptive current compensation circuit and a sub-threshold correction circuit. The common-mode voltage of the input is detected in real time through the parallel connection of the duplicate differential pairs, first and second control voltages which continuously change are generated, and the compensation circuit is driven to continuously and adaptively compensate the working differential pair, thereby replacing the fixed proportion compensation scheme in the prior art. The sub-threshold correction circuit automatically eliminates the transconductance overshoot when the differential pair is in the sub-threshold transition zone. The application realizes continuous adaptive constant of the transconductance, significantly reduces the harmonic distortion and improves the stability of the frequency compensation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a rail-to-rail input circuit and a high-speed, high-bandwidth operational amplifier. Background Technology

[0002] Operational amplifiers (OPAs) are key circuits in analog and mixed-signal integrated circuits, and different applications impose different performance requirements on them. In wide-swing applications, OPAs are required to have a high signal-to-noise ratio and a large input range; therefore, rail-to-rail OPAs are commonly used in wide-swing applications. However, the input transconductance of traditional rail-to-rail OPAs varies significantly with the input signal. When the input range is large, rail-to-rail OPAs can exhibit increased harmonic distortion, affecting their performance. Therefore, how to enable rail-to-rail OPAs to possess both a large input range and good performance has become a pressing technical problem for those skilled in the art.

[0003] Existing technology CN111294001B discloses a solution: when one differential pair is off, a compensation current is injected into the other differential pair through a fixed triple current mirror; when the differential pair is in a subthreshold state, excess current is extracted by adjusting the branch. The core compensation mechanism of this solution relies on a switching transistor controlled by a fixed bias voltage, and the compensation ratio is a fixed value, which cannot be continuously adjusted according to the actual transconductance deviation. In addition, the control signals for its compensation current injection and extraction are directly taken from the source node of the differential pair, making it susceptible to signal fluctuations. Summary of the Invention

[0004] To address these issues, this application proposes a rail-to-rail input circuit and a high-speed, high-bandwidth operational amplifier. This operational amplifier uses parallel-connected replica differential pairs to detect the input common-mode voltage in real time, generating continuously varying first and second control voltages. These voltages drive a compensation circuit to continuously and adaptively compensate the current of the working differential pairs, replacing the fixed-ratio compensation scheme in existing technologies and achieving the technical effect of continuous, adaptive, and constant transconductance.

[0005] According to one aspect of this application, a rail-to-rail input circuit is proposed, comprising an input stage circuit, a common-mode detection circuit, an adaptive current compensation circuit, and a subthreshold correction circuit. The input stage circuit includes a first conductivity type differential pair and a second conductivity type differential pair connected in parallel for converting a differential input voltage into a differential current. The common-mode detection circuit includes a replica differential pair connected in parallel with the input stage circuit for detecting the input common-mode voltage and generating a continuously varying first control voltage and a second control voltage. The adaptive current compensation circuit includes a first compensation branch and a second compensation branch. The first compensation branch is controlled by the first control voltage and injects a first compensation current into the first conductivity type differential pair when the second conductivity type differential pair is turned off. The first compensation current continuously varies with the first control voltage. The second compensation branch... The branch is controlled by the second control voltage. When the first conductivity type differential pair is turned off, a second compensation current is injected into the second conductivity type differential pair. The second compensation current changes continuously with the second control voltage. The subthreshold correction circuit includes a first correction branch and a second correction branch. When the second conductivity type differential pair is in a subthreshold state, the first correction branch detects its subthreshold current and subtracts a portion proportional to the subthreshold current from the first compensation current. The second correction branch detects its subthreshold current when the first conductivity type differential pair is in a subthreshold state and subtracts a portion proportional to the subthreshold current from the second compensation current. In the above scheme, the input common-mode voltage is detected in real time by parallel replica differential pairs, generating continuously varying first and second control voltages. These voltages drive the compensation circuit to continuously and adjustablely inject current into the working differential pairs, replacing the fixed three-fold compensation scheme in existing technologies. Its advantages are: the compensation amount automatically adjusts according to the degree of common-mode deviation, so that when the input common-mode voltage approaches any power rail, the current of the working differential pair can adaptively increase to approximately four times the reference current, raising its transconductance to approximately twice the reference transconductance. This keeps the total input transconductance essentially constant across the entire common-mode range, significantly reducing harmonic distortion and improving the stability of frequency compensation. Simultaneously, the subthreshold correction circuit automatically eliminates transconductance overshoot caused by subthreshold current superposition when the differential pair is in the subthreshold transition region, making the total transconductance curve smoother in the transition region.

[0006] In an optional embodiment, a first conductivity type differential pair is replicated, including a first replicating transistor and a second replicating transistor, the size of which is 1 / K of the transistor corresponding to the first conductivity type differential pair, and the value of K ranges from 5 to 50; the sources of the first replicating transistor and the second replicating transistor are connected to a first replication tail current source, the gates of the first replicating transistor and the second replicating transistor are connected to the positive input terminal and the negative input terminal respectively, and the drains of the first replicating transistor and the second replicating transistor are connected to the drain of the first replication load transistor. The first replica load transistor includes a second conductivity type MOS transistor. The source of the first replica load transistor is connected to a second power supply. The control terminal of the first replica load transistor is shorted to its drain. The voltage at the control terminal of the first replica load transistor is used as the first control voltage. The second conductivity type differential pair is replicated, including a third replica transistor and a fourth replica transistor, the size of which is 1 / K of the corresponding transistor of the second conductivity type differential pair; the sources of the third replica transistor and the fourth replica transistor are connected to the second replication tail current source, the gates of the third replica transistor and the fourth replica transistor are connected to the positive input terminal and the negative input terminal respectively, and the drains of the third replica transistor and the fourth replica transistor are connected to the drain of the second replication load transistor; the currents of the first replication tail current source and the second replication tail current source are 1 / K of the corresponding main tail current source; The second replica load transistor includes a first conductivity type MOS transistor. The source of the second replica load transistor is connected to a first power supply. The control terminal of the second replica load transistor is shorted to its drain. The voltage at the control terminal of the second replica load transistor is used as the second control voltage.

[0007] In the above scheme, the size of the replicated differential pair is reduced to 1 / K of the main differential pair, and the load transistor uses a diode connection to convert the change in common-mode voltage into a continuously changing gate control voltage. The common-mode detection circuit does not load the main signal path, resulting in extremely low power consumption; the control voltage is directly generated by the diode-connected load transistor, exhibiting a continuous and monotonic relationship with the common-mode voltage, providing a continuously adjustable control signal for the subsequent compensation circuit; and the detection process is unaffected by the fluctuation of the differential signal, with the control voltage only reflecting the slow change in the common-mode voltage, thus improving detection accuracy and anti-interference capability.

[0008] In a further example, the first compensation branch includes: The first compensation driving transistor includes a second conductivity type MOS transistor. The control terminal of the first compensation driving transistor receives the first control voltage, and the source of the first compensation driving transistor is connected to the second power supply. The first compensation mirror transistor includes a first conductivity type MOS transistor, the source of the first compensation mirror transistor is connected to the first power supply, the control terminal of the first compensation mirror transistor is shorted to its drain, and the drain of the first compensation mirror transistor is connected to the drain of the first compensation driving transistor. The first compensation output transistor includes a first conductivity type MOS transistor, the source of the first compensation output transistor is connected to the first power supply, the control terminal of the first compensation output transistor is connected to the control terminal of the first compensation mirror transistor, and the drain of the first compensation output transistor is connected to the common source node of the first conductivity type differential pair. The first compensation switch includes a second conductivity type MOS transistor. The source of the first compensation switch is connected to the common source node of the second conductivity type differential pair. The drain of the first compensation switch is connected to the drain of the first compensation drive transistor. The control terminal of the first compensation switch receives a first switch bias voltage.

[0009] In the above scheme, the first compensation switch is turned on when the second conductivity type differential pair is off, guiding its tail current to the branch containing the first compensation drive transistor and the first compensation mirror transistor. The first compensation drive transistor is controlled by a continuously changing first control voltage, and its conduction degree is continuously adjusted according to the deviation of the common-mode voltage. The first compensation mirror transistor and the first compensation output transistor form a current mirror, injecting the compensation current into the common source node of the first conductivity type differential pair. The magnitude of the compensation current changes continuously with the first control voltage, thereby matching the transconductance deviation under different common-mode voltages and achieving a flatter transconductance curve.

[0010] In a further example, the second compensation branch includes: The second compensation driving transistor includes a first conductivity type MOS transistor, the control terminal of the second compensation driving transistor receives the second control voltage, and the source of the second compensation driving transistor is connected to the first power supply. The second compensation mirror transistor includes a second conductivity type MOS transistor. The source of the second compensation mirror transistor is connected to the second power supply. The control terminal of the second compensation mirror transistor is shorted to its drain. The drain of the second compensation mirror transistor is connected to the drain of the second compensation driving transistor. The second compensation output transistor includes a second conductivity type MOS transistor, the source of the second compensation output transistor is connected to the second power supply, the control terminal of the second compensation output transistor is connected to the control terminal of the second compensation mirror transistor, and the drain of the second compensation output transistor is connected to the common source node of the second conductivity type differential pair. The second compensation switch includes a first conductivity type MOS transistor, the source of the second compensation switch is connected to the common source node of the first conductivity type differential pair, the drain of the second compensation switch is connected to the drain of the second compensation drive transistor, and the control terminal of the second compensation switch receives a second switch bias voltage.

[0011] The second compensation branch is symmetrical in circuit structure to the first compensation branch and works on the same principle. It is used to continuously inject compensation current into the second conductivity type differential pair when the first conductivity type differential pair is cut off.

[0012] In an optional embodiment, the first corrected branch includes: The first detection tube and the second detection tube include a second conductivity type MOS transistor. The sources of the first detection tube and the second detection tube are connected to the common source node of the second conductivity type differential pair. The control terminals of the first detection tube and the second detection tube are respectively connected to the positive input terminal and the negative input terminal. The drains of the first detection tube and the second detection tube are connected to the drain of the first correction mirror transistor. The first corrected mirror transistor includes a first conductivity type MOS transistor, the source of the first corrected mirror transistor is connected to a first power supply, and the control terminal of the first corrected mirror transistor is shorted to its drain. The second correction mirror includes a first conductivity type MOS transistor, the source of the second correction mirror is connected to the first power supply, the control terminal of the second correction mirror is connected to the control terminal of the first correction mirror, and the drain of the second correction mirror is connected to the drain of the first compensation drive transistor in the first compensation branch. The width-to-length ratio of the first detection tube and the second detection tube is a times the value of the transistor corresponding to the second conductivity type differential pair, where the value of a ranges from 0.05 to 0.5.

[0013] In the above scheme, the first and second detection tubes are scaled-down replicas of the second conductivity type differential pair. When the second conductivity type differential pair is in a subthreshold state, a weak subthreshold current also flows through the detection tube. This current is mirrored by the first correction mirror tube, increasing the conductivity of the second correction mirror tube. The second correction mirror tube injects current from the first power supply to the drain node of the first compensation drive tube, raising the potential of the drain node. Since the first compensation mirror tube is a diode connected and its drain is connected to the drain node, the increased potential of the drain node reduces the conductivity of the first compensation mirror tube, and the mirror reference current flowing through the first compensation mirror tube decreases accordingly. This automatically subtracts the portion of the compensation current injected by the first compensation output tube into the first conductivity type differential pair that is proportional to the subthreshold current. In the subthreshold transition region, the first correction branch can automatically eliminate the transconductance overshoot caused by the subthreshold current superimposed on the compensation current, making the total transconductance curve smoother in the transition region and avoiding the problem of large transconductance error in the prior art.

[0014] In an optional embodiment, the second correction branch includes: a third detection transistor and a fourth detection transistor, the third and fourth detection transistors being MOS transistors of a first conductivity type, the sources of the third and fourth detection transistors being connected to the common source node of the first conductivity type differential pair, the control terminals of the third and fourth detection transistors being connected to the positive input terminal and the negative input terminal respectively, and the drains of the third and fourth detection transistors being connected to the drain of the third correction mirror transistor; the third correction mirror transistor is a MOS transistor of a second conductivity type, the source of the third correction mirror transistor being connected to the second power supply, and the control terminal of the third correction mirror transistor being shorted to its drain; the fourth correction mirror transistor is a MOS transistor of a second conductivity type, the source of the fourth correction mirror transistor being connected to the second power supply, the control terminal of the fourth correction mirror transistor being connected to the control terminal of the third correction mirror transistor, and the drain of the fourth correction mirror transistor being connected to the drain of the second compensation driving transistor in the second compensation branch; the width-to-length ratio of the third and fourth detection transistors is a times the size of the transistor corresponding to the first conductivity type differential pair, and the value of a ranges from 0.05 to 0.5.

[0015] The second correction branch is symmetrical to the first correction branch. It is used to detect the subthreshold current of the first conductivity type differential pair when it is in the subthreshold state and subtract the part proportional to the subthreshold current from the second compensation current to eliminate the transconductance overshoot in the subthreshold transition region of the PMOS differential pair, so that the total transconductance curve is smoother in the full common mode range.

[0016] According to a second aspect of this application, a high-speed, high-bandwidth operational amplifier is proposed, comprising an amplification stage circuit, an output stage circuit, and a rail-to-rail input circuit as described above. The amplification stage circuit is configured to amplify the output of the rail-to-rail input circuit and output it to the output stage circuit. The output stage circuit is configured to drive a load based on the output of the amplification stage circuit.

[0017] The advantages of this application are: First, by replicating the differential pair to detect the common-mode voltage and generating a continuously changing control voltage, continuous adaptive adjustment of the compensation current is achieved, replacing the fixed three-fold compensation scheme in the existing technology. This keeps the total input transconductance basically constant across the entire common-mode range, significantly reducing harmonic distortion and improving the stability of frequency compensation. Second, by setting up a subthreshold correction circuit, when the differential pair is in the subthreshold transition region, a compensation current component proportional to the subthreshold current is automatically extracted, which eliminates transconductance overshoot and makes the total transconductance curve smoother in the transition region. Attached Figure Description

[0018] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0019] Figure 1 A schematic block diagram of a rail-to-rail input circuit according to Embodiment 1 of this application is shown; Figure 2 Detailed circuit diagrams of the input stage circuit, common-mode detection circuit, adaptive current compensation circuit, and subthreshold correction circuit are shown in a specific example according to Embodiment 1. Figure 3 A schematic block diagram of a high-speed, high-bandwidth operational amplifier according to this application is shown.

[0020] Figure label: 100 - Input stage circuit; 200 - Common-mode detection circuit; 300 - Adaptive current compensation circuit; 400 - Subthreshold correction circuit; 500 - Amplification stage circuit; 600 - Output stage circuit; PM1 - First P-type MOSFET; PM2 - Second P-type MOSFET; NM1 - First N-type MOSFET; NM2 - Second N-type MOSFET; PTAIL - First tail current transistor; NTAIL - Second tail current transistor; PM1C - Copy of first P-type MOSFET; PM2C - Copy of second P-type MOSFET; NM1C - Copy of third N-type MOSFET; NM2C - Copy of fourth N-type MOSFET; PTAIL - Copy of first tail current transistor; NTAIL - Copy of second tail current transistor; NLOAD1 - First copy of load PLOAD2 - Second replication load transistor; PD1 - First compensation drive transistor; PD2 - First compensation mirror transistor; PD3 - First compensation output transistor; NS1 - First compensation switch transistor; ND1 - Second compensation drive transistor; ND2 - Second compensation mirror transistor; ND3 - Second compensation output transistor; PS1 - Second compensation switch transistor; NSD1 - First subthreshold detection transistor; NSD2 - Second subthreshold detection transistor; PCD1 - First correction mirror transistor; PCD2 - Second correction mirror transistor; PSD1 - Third subthreshold detection transistor; PSD2 - Fourth subthreshold detection transistor; NCD1 - Third correction mirror transistor; NCD2 - Fourth correction mirror transistor; VD - First power supply; VSS - Second power supply; Vin+ - Positive input terminal; Vin- - Negative input terminal. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the relevant application and not intended to limit the application. Furthermore, it should be noted that, for ease of description, only the parts relevant to the application are shown in the accompanying drawings.

[0022] In the description of this application, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. The term "connection" should be interpreted broadly, and can refer to a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] In this application, the first conductivity type is P-type and the second conductivity type is N-type, as an example for illustration. Those skilled in the art will understand that by reversing the overall circuit polarity, the first and second conductivity types can be interchanged, and still fall within the protection scope of this application. It should be noted that in each embodiment of this application, the control terminal refers to the gate. The second power supply VSS is the ground potential; grounding as mentioned in the specification refers to connection to the second power supply VSS. It is worth mentioning that, in order to make the circuit diagram more concise, this application has omitted some specific resistors and capacitors that may be needed in the embodiments.

[0024] Figure 1 Here is a schematic block diagram of a rail-to-rail input circuit according to this application, as follows: Figure 1 As shown, this embodiment provides a rail-to-rail input circuit, including an input stage circuit 100, a common-mode detection circuit 200, an adaptive current compensation circuit 300, and a subthreshold correction circuit 400. The input stage circuit 100 employs a complementary differential pair structure to receive differential input signals Vin+ and Vin- and convert them into differential currents. The common-mode detection circuit 200 detects the input common-mode voltage and generates a first control voltage VCN and a second control voltage VCP. The adaptive current compensation circuit 300, controlled by VCN and VCP, continuously injects compensation current into the working differential pair when the input common-mode voltage approaches the power rail. The subthreshold correction circuit 400 subtracts a portion proportional to the subthreshold current from the corresponding compensation current when any differential pair is in a subthreshold state.

[0025] Figure 2 This is the overall circuit diagram of the input stage circuit 100, common-mode detection circuit 200, adaptive current compensation circuit 300, and subthreshold correction circuit 400. The following is a combination of... Figure 2 Provide a detailed description of the connection relationships between the various components.

[0026] The input stage circuit 100 includes a PMOS differential pair, which is composed of a first P-type MOS transistor PM1 and a second P-type MOS transistor PM2. The sources of PM1 and PM2 are connected to the drain of the first tail current transistor PTAIL. The gate of PM1 is the positive input terminal Vin+, and the gate of PM2 is the negative input terminal Vin-. The drains of PM1 and PM2 serve as the first output terminal OUT1 and the second output terminal OUT2 of the input stage circuit 100, respectively.

[0027] The first tail current transistor, PTAIL, is a PMOS transistor. Its source is connected to the first power supply VD, and its gate is connected to the first fixed bias voltage VBP. The first tail current transistor, PTAIL, provides a reference current Id to the PMOS differential pair.

[0028] The NMOS differential pair consists of a first N-type MOSFET NM1 and a second N-type MOSFET NM2. The sources of NM1 and NM2 are connected to the drain of the second tail current transistor NTAIL. The gate of NM1 is electrically connected to the gate of PM1, and the gate of NM2 is electrically connected to the gate of PM2. The drains of NM1 and NM2 serve as the third and fourth output terminals of the input stage circuit 100, respectively.

[0029] The second tail current transistor, NTAIL, is an NMOS transistor. Its source is connected to the second power supply VSS (ground), and its gate is connected to the second fixed bias voltage VBN. The second tail current transistor NTAIL provides a reference current Id to the NMOS differential pair.

[0030] The above-mentioned input stage adopts a complementary differential pair parallel structure, which can achieve input common-mode voltage coverage across the entire power supply range from VSS to VD, meeting the requirements of rail-to-rail input.

[0031] The common-mode detection circuit 200 includes a replica PMOS differential pair and a replica NMOS differential pair, both of which are 1 / K the size of the main differential pair (K is usually 10 to 20).

[0032] The replicated PMOS differential pair includes a replicated first P-type MOS transistor PM1C and a replicated second P-type MOS transistor PM2C. The sources of PM1C and PM2C are connected to the drain of the replicated first tail current transistor PTAILC. PTAILC is a PMOS transistor, with its source connected to VD and its gate connected to VBP. The gate of PM1C is connected to Vin+, and the gate of PM2C is connected to Vin-. The drains of PM1C and PM2C are connected to the drain of the first replicated load transistor NLOAD1. The currents of the replicated first tail current transistor and the replicated second tail current transistor are each 1 / K of the corresponding main tail current source.

[0033] The first replica load transistor, NLOAD1, is an NMOS transistor with its source connected to the second power supply VSS (ground) and its gate shorted to its drain. The gate voltage of NLOAD1 serves as the first control voltage, VCN.

[0034] The replicated NMOS differential pair includes a replicated third N-type MOSFET NM1C and a replicated fourth N-type MOSFET NM2C. The sources of NM1C and NM2C are connected to the drain of the replicated second tail current transistor NTAILC. NTAILC is an NMOS transistor with its source grounded and its gate connected to VBN. The gate of NM1C is connected to Vin+, and the gate of NM2C is connected to Vin-. The drains of NM1C and NM2C are connected to the drain of the replicated second load transistor PLOAD2.

[0035] The second replica load transistor, PLOAD2, is a PMOS transistor with its source connected to VD and its gate shorted to its drain. The gate voltage of PLOAD2 serves as the second control voltage, VCP.

[0036] The principle of common-mode control voltage generation: When the input common-mode voltage is close to VSS, the replicated PMOS differential pair operates in the saturation region, with a large current flowing through NLOAD1 and a high VCN; simultaneously, the replicated NMOS differential pair is cut off, the current in PLOAD2 is almost zero, and VCP is close to VD. When the input common-mode voltage is close to VD, the situation is symmetrical, VCN is close to ground, and VCP is low. When the input common-mode voltage is in the middle, both replicated differential pairs have current, and VCN and VCP are at intermediate values.

[0037] At this point, the size of the replicated differential pair is only 1 / K of the main differential pair, resulting in extremely low power consumption. The control voltages VCN and VCP are directly generated by the load transistor connected by diodes (a specific connection method for MOSFETs, where the gate and drain of the MOSFET are shorted), and they exhibit a continuous and monotonic relationship with the common-mode voltage, providing a continuously adjustable control signal for the subsequent compensation circuit. Furthermore, the common-mode detection does not load the main signal path and does not affect the normal amplification of the differential signal.

[0038] The adaptive compensation circuit 300 includes a first compensation branch and a second compensation branch. The first compensation branch includes a first compensation drive transistor PD1, a first compensation mirror transistor PD2, a first compensation output transistor PD3, and a first compensation switch transistor NS1.

[0039] The first compensation driving transistor PD1 is an NMOS transistor with its source grounded, its gate connected to the first control voltage VCN, and its drain connected to the drain of the first compensation switching transistor NS1.

[0040] The first compensation mirror transistor PD2 is a PMOS transistor, with its source connected to VD, its gate shorted to its drain, and its drain electrically connected to the drain of the first compensation drive transistor PD1.

[0041] The first compensation output transistor PD3 is a PMOS transistor, with its source connected to VD, its gate electrically connected to the gate of the first compensation mirror transistor PD2, and its drain connected to the common source node of PM1 / PM2.

[0042] The first compensation switch NS1 is an NMOS transistor, with its source connected to the common source node of NM1 / NM2, its drain connected to the drain of the first compensation drive transistor PD1, and its gate inputting the first switch bias voltage VSW1.

[0043] When the NMOS differential pair is off, its source common node potential decreases, the gate-source voltage of NS1 increases, and NS1 turns on. The current Id of the second tail current source NTAIL flows from the source to the drain through NS1, merges with the current of PD1, and flows through PD2 (diode connected). PD2 mirrors this current to PD3. PD3 injects the mirrored current into the source common node of the PMOS differential pair, forming the first compensation current. PD1 is continuously controlled by VCN, and its conduction level changes continuously with the deviation of the common-mode voltage. After being mirrored by the current mirror of PD2 / PD3, the compensation current is continuously and adjustablely injected into the source common node of the PMOS differential pair, so that the compensation amount can match the transconductance deviation under different common-mode voltages.

[0044] The second compensation branch includes the second compensation drive transistor ND1, the second compensation mirror transistor ND2, the second compensation output transistor ND3, and the second compensation switch transistor PS1.

[0045] The second compensation drive transistor ND1 is a PMOS transistor, with its source connected to VD, its gate connected to the second control voltage VCP, and its drain connected to the drain of the second compensation switch transistor PS1.

[0046] The second compensation mirror transistor ND2 is an NMOS transistor with its source grounded, its gate shorted to its drain, and its drain electrically connected to the drain of the second compensation drive transistor ND1.

[0047] The second compensation output transistor ND3 is an NMOS transistor with its source grounded. Its gate is electrically connected to the gate of the second compensation mirror transistor ND2, and its drain is connected to the common source node of NM1 / NM2.

[0048] The second compensation switch PS1 is a PMOS transistor, with its source connected to the common source node of PM1 / PM2, its drain connected to the drain of the second compensation drive transistor ND1, and its gate inputting the second switch bias voltage VSW2.

[0049] The second compensation branch is symmetrical to the first compensation branch and is used to continuously inject compensation current into the NMOS differential pair when the PMOS differential pair is turned off.

[0050] The subthreshold correction circuit 400 includes a first subthreshold correction branch and a second subthreshold correction branch. The first subthreshold correction branch includes a first subthreshold detection transistor NSD1, a second subthreshold detection transistor NSD2, a first correction mirror transistor PCD1, and a second correction mirror transistor PCD2.

[0051] The first subthreshold detector NSD1 and the second subthreshold detector NSD2 are NMOS transistors with the same dimensions. Their width-to-length ratio is a times that of the principal differential pair NM1 / NM2 (where a ranges from 0.1 to 0.3). The sources of NSD1 and NSD2 are connected to the common source node of NM1 / NM2. The gate of NSD1 is electrically connected to the gate of NM1. The gate of NSD2 is electrically connected to the gate of NM2. The drains of NSD1 and NSD2 are connected to the drain of the first correction mirror transistor PCD1.

[0052] The first corrected mirror transistor PCD1 is a PMOS transistor, with its source connected to VD and its gate shorted to its drain.

[0053] The second corrected mirror transistor PCD2 is a PMOS transistor, with its source connected to VD, its gate electrically connected to the gate of PCD1, and its drain connected to the drain of the first compensation drive transistor PD1 (i.e., the common node A of PD1 and NS1).

[0054] When the NMOS differential pair is in the subthreshold state, a subthreshold current proportional to it flows through NSD1 / NSD2. This current, mirrored by PCD1, increases the conduction level of PCD2. PCD2 injects current from VD into node A, raising the potential of node A. Since PD2 is a diode-connected PMOS transistor, the increased potential of node A reduces the conduction level of PD2, correspondingly reducing the mirror reference current flowing through PD2. This, in turn, automatically reduces the portion of the compensation current injected into the PMOS differential pair by PD3 that corresponds to the subthreshold current, eliminating the transconductance overshoot caused by the superposition of the compensation current and subthreshold current in the subthreshold transition region, making the total transconductance curve smoother in the transition region.

[0055] The second subthreshold correction branch is structurally symmetrical to the first subthreshold correction branch, and includes a third subthreshold detection tube PSD1, a fourth subthreshold detection tube PSD2, a third correction mirror tube NCD1, and a fourth correction mirror tube NCD2.

[0056] The third subthreshold detector PSD1 and the fourth subthreshold detector PSD2 are PMOS transistors with the same dimensions. Their width-to-length ratio is a times that of the main differential pair PM1 / PM2 (where a ranges from 0.1 to 0.3). The sources of PSD1 and PSD2 are connected to the common source node of PM1 / PM2. The gate of PSD1 is electrically connected to the gate of PM1. The gate of PSD2 is electrically connected to the gate of PM2. The drains of PSD1 and PSD2 are connected to the drain of the third correction mirror transistor NCD1.

[0057] The third corrected mirror transistor, NCD1, is an NMOS transistor with its source grounded and its gate shorted to its drain.

[0058] The fourth corrective mirror transistor NCD2 is an NMOS transistor with its source grounded, its gate electrically connected to the gate of NCD1, and its drain connected to the drain of the second compensation drive transistor ND1 (i.e., the common node B of ND1 and PS1).

[0059] When the PMOS differential pair is in the subthreshold state, a subthreshold current flows through PSD1 / PSD2 proportional to it. This current, mirrored by NCD1, increases the conduction of NCD2. NCD2 draws current from node B to ground, lowering the potential of node B. Since ND2 is a diode-connected NMOS transistor, the decrease in node B potential reduces the conduction of ND2, correspondingly reducing the mirror reference current flowing through ND2. This, in turn, automatically reduces the portion of the compensation current injected into the NMOS differential pair by ND3 corresponding to the subthreshold current, eliminating transconductance overshoot in the subthreshold transition region of the PMOS differential pair and making the total transconductance curve smoother across the entire common-mode range.

[0060] The high-speed, high-bandwidth operational amplifier proposed in this application undergoes the following state transitions during circuit operation: State 1: Input common-mode voltage is close to VSS (PMOS differential pair is on, NMOS differential pair is off) When the input common-mode voltage is very low (close to ground potential), both PM1 and PM2 operate in the saturation region, while both NM1 and NM2 are cut off. The first tail current transistor PTAIL provides the reference current Id to the PMOS differential pair.

[0061] At this time, the replicated PMOS differential pair (PM1C, PM2C) is turned on due to the low common-mode voltage, and a large current flows through NLOAD1, resulting in a high VCN. The replicated NMOS differential pair (NM1C, NM2C) is turned off, and the current in PLOAD2 is almost zero, with VCP close to VD.

[0062] Because the NMOS differential pair is off, the common source node potential of NM1 / NM2 is pulled low, increasing the gate-source voltage of NS1 and turning it on. The current Id from the second tail current source NTAIL flows into the drain node of PD1 through NS1. Simultaneously, the gate of PD1 is controlled by VCN; a higher VCN results in stronger PD1 conduction. The currents from PD1 and NS1 merge and flow through PD2 (diode connected), mirroring this current to PD3. PD3 injects the mirrored current into the common source node of PM1 / PM2, forming the first compensation current.

[0063] During design, the ratio of the width-to-length ratios of PD3 and PD2 is set to satisfy: when the common-mode voltage is exactly VSS, the compensation current injected by PD3 is 3Id. Therefore, the total current flowing through the PMOS differential pair is Id + 3Id = 4Id. According to the transconductance formula, when the current increases from Id to 4Id, the transconductance gmp of the PMOS differential pair increases from gm0 to 2gm0. At this time, the NMOS differential pair has no current, and the total input transconductance gmtot = gmp = 2gm0.

[0064] In the first subthreshold correction branch, NSD1 / NSD2 have no current and do not operate because the NMOS differential pair is turned off.

[0065] State 2: The input common-mode voltage gradually rises, and the NMOS differential pair enters the subthreshold state As the common-mode voltage increases, the NMOS differential pair transitions from the off state to the subthreshold state, and a subthreshold current xId flows through NM1 and NM2 (0<x<1). At this time, the PMOS differential pair is still in saturated conduction, the potential of its common source node remains relatively low, and NS1 remains conductive.

[0066] VCN decreases slightly as the common-mode voltage rises, reducing the current of PD1. At the same time, subthreshold current also flows through NSD1 and NSD2, this current is mirrored to PCD2 via PCD1, the conduction of PCD2 is enhanced, and current is injected from VD to the drain node A of PD1, raising the potential of node A; the rise in the potential of node A reduces the conduction degree of the diode-connected PD2, and the mirrored reference current flowing through PD2 decreases accordingly. The magnitude of the correction effect is proportional to the subthreshold current of the NMOS differential pair.

[0067] Therefore, the total current flowing through PD2 is further reduced, and the compensation current injected by PD3 into the PMOS differential pair decreases accordingly. Finally, the total current flowing through the PMOS differential pair is slightly less than 4Id, which automatically compensates for the extra contribution of the subthreshold current of the NMOS differential pair to the total transconductance, keeping the total transconductance near 2gm0.

[0068] State 3: The input common-mode voltage is at the middle level (both differential pairs are conductive) When the common-mode voltage is in the middle region, both the PMOS differential pair and the NMOS differential pair operate in the saturation region, each contributing a transconductance of gm0.

[0069] At this time, the potential of the common source node of the NMOS rises, turning off NS1. The potential of the common source node of the PMOS decreases, turning off PS1. Therefore, both the first adaptive current compensation branch and the second adaptive current compensation branch are turned off, and no compensation current is injected.

[0070] The current flowing through the PMOS differential pair is Id, with a transconductance of gm0; the current flowing through the NMOS differential pair is Id, with a transconductance of gm0. The total input transconductance is 2gm0.

[0071] State 4: The input common-mode voltage continues to rise, and the PMOS differential pair enters the subthreshold state Symmetric to State 2, at this time the current of the PMOS differential pair is x×Id (0<x<1), and the NMOS differential pair is turned on in saturation with a current of Id.

[0072] PS1 is turned on as the potential of the PMOS source rises. The gate of ND1 is controlled by VCP, and the low VCP turns on ND1. ND2 mirrors this current, and ND3 injects a compensation current into the common source node of the NMOS differential pair.

[0073] Meanwhile, the third subthreshold detection transistor PSD1 and the fourth subthreshold detection transistor PSD2 detect the subthreshold current of the PMOS differential pair, and draw current from the drain node B of ND1 via NCD1 and NCD2, lowering the potential of node B, reducing the conduction degree of ND2, and correspondingly reducing the compensation current of ND3.

[0074] Finally, the total current flowing through the NMOS differential pair is an accurate value less than 4Id, and the total transconductance remains around 2gm0.

[0075] State 5: The input common-mode voltage is close to VD (the PMOS differential pair is turned off, and the NMOS differential pair is turned on) When the common-mode voltage is very high (close to VD), the PMOS differential pair is turned off, and the NMOS differential pair is turned on in saturation. The second tail current transistor NTAIL provides the reference current Id.

[0076] PS1 is turned on, the current Id of the first tail current transistor PTAIL flows into ND1 through PS1, ND1 is controlled by VCP (the low VCP makes ND1 conduct more strongly), and the current is mirrored to ND3 via ND2, and ND3 injects a compensation current into the common source node of the NMOS differential pair. The design makes the compensation current equal to 3Id when the common-mode voltage is exactly VD, the total current flowing through the NMOS differential pair is 4Id, and the transconductance is 2gm0.

[0077] In summary, no matter which region the input common-mode voltage is in, the total input transconductance is basically maintained at 2gm0, and the variation range of transconductance in the full common-mode range is significantly reduced, thereby reducing harmonic distortion and improving the stability of frequency compensation.

[0078] As Figure 3 shown, according to a second aspect of the present application, a high-speed high-bandwidth operational amplifier is proposed, which includes an amplification stage circuit 500, an output stage circuit 600, and the rail-to-rail input circuit as described above. The amplification stage circuit 500 is configured to perform gain amplification on the output of the rail-to-rail input circuit and then output the amplified result to the output stage circuit 600, and the output stage circuit 600 is configured to drive a load according to the output of the amplification stage circuit 500.

[0079] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0080] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described application concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A rail-to-rail input circuit, characterized in that, include: The input stage circuit includes a first conductivity type differential pair and a second conductivity type differential pair connected in parallel, used to convert differential input voltage into differential current; A common-mode detection circuit includes a replica differential pair connected in parallel with the input stage circuit, used to detect the input common-mode voltage and generate a continuously varying first control voltage and a second control voltage; An adaptive current compensation circuit includes a first compensation branch and a second compensation branch. The first compensation branch is controlled by a first control voltage and injects a first compensation current into the first conductivity type differential pair when the second conductivity type differential pair is turned off. The first compensation current changes continuously with the first control voltage. The second compensation branch is controlled by a second control voltage and injects a second compensation current into the second conductivity type differential pair when the first conductivity type differential pair is turned off. The second compensation current changes continuously with the second control voltage. The subthreshold correction circuit includes a first correction branch and a second correction branch. When the second conduction type differential pair is in a subthreshold state, the first correction branch detects its subthreshold current and subtracts a portion proportional to the subthreshold current from the first compensation current. When the first conduction type differential pair is in a subthreshold state, the second correction branch detects its subthreshold current and subtracts a portion proportional to the subthreshold current from the second compensation current.

2. The rail-to-rail input circuit according to claim 1, characterized in that, The replicated differential pair connected in parallel with the input stage circuit specifically includes: The first conductivity type differential pair is replicated, including a first replicating transistor and a second replicating transistor, the size of which is 1 / K of the transistor corresponding to the first conductivity type differential pair, and the value of K is in the range of 5 to 50; the sources of the first replicating transistor and the second replicating transistor are connected to the first replication tail current source, the gates of the first replicating transistor and the second replicating transistor are connected to the positive input terminal and the negative input terminal respectively, and the drains of the first replicating transistor and the second replicating transistor are connected to the drain of the first replication load transistor. The first replica load transistor is a MOS transistor of the second conductivity type. The source of the first replica load transistor is connected to the second power supply. The control terminal of the first replica load transistor is shorted to its drain. The voltage at the control terminal of the first replica load transistor is used as the first control voltage. The second conductivity type differential pair is replicated, including a third replica transistor and a fourth replica transistor, the size of which is 1 / K of the corresponding transistor of the second conductivity type differential pair; the sources of the third replica transistor and the fourth replica transistor are connected to the second replication tail current source, the gates of the third replica transistor and the fourth replica transistor are connected to the positive input terminal and the negative input terminal respectively, and the drains of the third replica transistor and the fourth replica transistor are connected to the drain of the second replication load transistor; the currents of the first replication tail current source and the second replication tail current source are 1 / K of the corresponding main tail current source; The second replica load transistor is a first conductivity type MOS transistor. The source of the second replica load transistor is connected to the first power supply. The control terminal of the second replica load transistor is shorted to its drain. The voltage at the control terminal of the second replica load transistor is used as the second control voltage.

3. The rail-to-rail input circuit according to claim 2, characterized in that, The first compensation branch includes: The first compensation driving transistor includes a second conductivity type MOS transistor. The control terminal of the first compensation driving transistor receives the first control voltage, and the source of the first compensation driving transistor is connected to the second power supply. The first compensation mirror transistor includes a first conductivity type MOS transistor, the source of the first compensation mirror transistor is connected to the first power supply, the control terminal of the first compensation mirror transistor is shorted to its drain, and the drain of the first compensation mirror transistor is connected to the drain of the first compensation driving transistor. The first compensation output transistor includes a first conductivity type MOS transistor, the source of the first compensation output transistor is connected to the first power supply, the control terminal of the first compensation output transistor is connected to the control terminal of the first compensation mirror transistor, and the drain of the first compensation output transistor is connected to the common source node of the first conductivity type differential pair. The first compensation switch includes a second conductivity type MOS transistor. The source of the first compensation switch is connected to the common source node of the second conductivity type differential pair. The drain of the first compensation switch is connected to the drain of the first compensation drive transistor. The control terminal of the first compensation switch receives a first switch bias voltage.

4. The rail-to-rail input circuit according to claim 2, characterized in that, The second compensation branch includes: The second compensation driving transistor includes a first conductivity type MOS transistor, the control terminal of the second compensation driving transistor receives the second control voltage, and the source of the second compensation driving transistor is connected to the first power supply. The second compensation mirror transistor includes a second conductivity type MOS transistor. The source of the second compensation mirror transistor is connected to the second power supply. The control terminal of the second compensation mirror transistor is shorted to its drain. The drain of the second compensation mirror transistor is connected to the drain of the second compensation driving transistor. The second compensation output transistor includes a second conductivity type MOS transistor, the source of the second compensation output transistor is connected to the second power supply, the control terminal of the second compensation output transistor is connected to the control terminal of the second compensation mirror transistor, and the drain of the second compensation output transistor is connected to the common source node of the second conductivity type differential pair. The second compensation switch includes a first conductivity type MOS transistor, the source of the second compensation switch is connected to the common source node of the first conductivity type differential pair, the drain of the second compensation switch is connected to the drain of the second compensation drive transistor, and the control terminal of the second compensation switch receives a second switch bias voltage.

5. A rail-to-rail input circuit according to claim 1, characterized in that, The first corrected branch includes: The first detection tube and the second detection tube include a second conductivity type MOS transistor. The sources of the first detection tube and the second detection tube are connected to the common source node of the second conductivity type differential pair. The control terminals of the first detection tube and the second detection tube are respectively connected to the positive input terminal and the negative input terminal. The drains of the first detection tube and the second detection tube are connected to the drain of the first correction mirror transistor. The first corrected mirror transistor includes a first conductivity type MOS transistor, the source of the first corrected mirror transistor is connected to a first power supply, and the control terminal of the first corrected mirror transistor is shorted to its drain. The second correction mirror includes a first conductivity type MOS transistor, the source of the second correction mirror is connected to the first power supply, the control terminal of the second correction mirror is connected to the control terminal of the first correction mirror, and the drain of the second correction mirror is connected to the drain of the first compensation drive transistor in the first compensation branch. The width-to-length ratio of the first detection tube and the second detection tube is a times the value of the transistor corresponding to the second conductivity type differential pair, where the value of a ranges from 0.05 to 0.

5.

6. The rail-to-rail input circuit according to claim 1, characterized in that, The second corrected branch includes: The third and fourth detection transistors include a first conductivity type MOS transistor. The sources of the third and fourth detection transistors are connected to the common source node of the first conductivity type differential pair. The control terminals of the third and fourth detection transistors are respectively connected to the positive input terminal and the negative input terminal. The drains of the third and fourth detection transistors are connected to the drain of the third correction mirror transistor. The third correction mirror includes a second conductivity type MOS transistor, the source of the third correction mirror is connected to the second power supply, and the control terminal of the third correction mirror is shorted to its drain; the fourth correction mirror includes a second conductivity type MOS transistor, the source of the fourth correction mirror is connected to the second power supply, the control terminal of the fourth correction mirror is connected to the control terminal of the third correction mirror, and the drain of the fourth correction mirror is connected to the drain of the second compensation drive transistor in the second compensation branch; The width-to-length ratio of the third and fourth detection tubes is a times that of the transistor corresponding to the first conductivity type differential pair, where the value of a ranges from 0.05 to 0.

5.

7. A high-speed, high-bandwidth operational amplifier, comprising an amplification stage circuit, an output stage circuit, and a rail-to-rail input circuit as described in any one of claims 1 to 6, wherein the amplification stage circuit is configured to amplify the output of the rail-to-rail input circuit and output it to the output stage circuit, and the output stage circuit is configured to drive a load according to the output of the amplification stage circuit.

Images