Broadband receiver architecture

Abstract

In one embodiment, an apparatus comprises a single-ended low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the single-ended LNA having a common gate configuration, and a first transimpedance amplifier (TIA) to receive the amplified RF signal and convert a current of the amplified RF signal to a voltage of the amplified RF signal.

Description

Background Technology

[0001] With advancements in wireless technology, some protocols operate at extremely high frequencies. For example, advanced Wi-Fi protocols such as Wi-Fi 5 and 6e operate at frequencies between approximately 5 and 7 GHz. Furthermore, these wireless receivers are typically part of a system-on-a-chip (SoC) and are susceptible to various noise and / or interference sources. Differential architectures are generally used for better immunity to interference / noise. However, differential architectures consume significant current and reduce battery life. Additionally, such differential circuit modules increase circuit area, especially with baluns. Single-ended architectures offer lower power operation and a smaller area, but are more sensitive to noise / interference. Frequency notch circuits can be used to filter interference / noise, but making them tunable over a wide frequency range (e.g., 5 GHz–7 GHz) makes this approach impractical. Summary of the Invention

[0002] In one aspect, an apparatus includes: a single-ended low-noise amplifier (LNA) for receiving and amplifying a radio frequency (RF) signal, the single-ended LNA having a common-gate configuration; and a first transimpedance amplifier (TIA) for receiving the amplified RF signal and converting the current of the amplified RF signal into the voltage of the amplified RF signal.

[0003] In one implementation, the single-ended LNA includes a current-reusing LNA. The single-ended LNA can be a broadband amplifier operating over a bandwidth of at least 2 GHz. The single-ended LNA can be coupled to a first reference voltage node referencing a first reference voltage, and the first TIA can be coupled to a second reference voltage node referencing a second reference voltage, which is different from the first reference voltage.

[0004] In one implementation, the single-ended LNA includes: a first metal-oxide-semiconductor field-effect transistor (MOSFET) having a first terminal for receiving an RF signal from an antenna and a second terminal for providing an amplified RF signal to a first TIA; and a second MOSFET having a first terminal for receiving an RF signal from an antenna and a second terminal for providing an amplified RF signal to the first TIA. The device may further include a bias circuit for providing a first bias voltage to the gate terminal of the first MOSFET and a second bias voltage to the gate terminal of the second MOSFET, wherein the bias circuit includes a filter circuit. The filter circuit prevents noise from the voltage regulator from coupling to the single-ended LNA. The bias circuit may be coupled to a third reference voltage node.

[0005] In implementation, the device further includes a dedicated connection for coupling the third reference voltage node to the paddle ground, and a filter circuit for decoupling the first bias voltage and the second bias voltage from the paddle ground. The device may also include: a first choke inductor having a first terminal coupled to a first terminal of a first MOSFET and a second terminal coupled to a voltage regulator; and a second choke inductor having a first terminal coupled to a first terminal of a second MOSFET and a second terminal coupled to the paddle ground. The filter circuit may include: a first RC circuit coupled to the third reference voltage node, the first RC circuit having an inter-filter node to provide a first bias voltage to the gate terminal of the first MOSFET; and a second RC circuit coupled to the third reference voltage node, the second RC circuit having an inter-filter node to provide a second bias voltage to the gate terminal of the second MOSFET.

[0006] In one implementation, the device further includes a passive mixer coupled to a first TIA to downconvert an amplified RF signal to a second frequency signal. The passive mixer includes resistors and a plurality of switches rotatably supplying current of the second frequency signal to a complex path of the second frequency TIA, which converts the current of the second frequency signal into a voltage of the second frequency signal.

[0007] In implementation, the device further includes: an antenna for receiving RF signals; a mixer coupled to a first TIA to down-convert the amplified RF signal to an intermediate frequency (IF) signal; and an IF TIA for receiving the IF signal and converting the current of the IF signal into the voltage of the IF signal. The IF TIA can be configured as a feedforward compensated operational amplifier (op-amp) having: a first main path transconductor; a second main path transconductor coupled to the output of the first main path transconductor; at least one feedforward transconductor coupled between the input of the first main path transconductor and the output of the second main path transconductor; and an output stage including the second main path transconductor and at least one feedforward transconductor, wherein the output of the output stage is rail-to-rail oscillation.

[0008] In another aspect, an apparatus includes: a passive mixer for downconverting a first signal under RF to a second frequency, the second frequency being significantly lower than RF; the passive mixer includes: a resistor coupled to the output of an RF TIA to receive a first voltage of the first signal under RF; and a plurality of switches coupled to the resistor, each of the plurality of switches being controllable to rotatably couple the resistor to one of a non-inverting TIA and a quadrature-phase TIA to deliver a first current at the second frequency to the one of the non-inverting TIA and the quadrature-phase TIA.

[0009] In one implementation, each of the plurality of switches includes a MOSFET, the MOSFET including a first terminal for receiving a first current and a second terminal for providing the first current to one of the in-phase TIA and the quadrature-phase TIA. The MOSFET of each of the plurality of switches may further include a gate terminal for receiving a selected phase of a clock signal, such that the MOSFET delivers the first current to one of the in-phase TIA and the quadrature-phase TIA.

[0010] In the implementation, the passive mixer is configured to convert a first voltage into a first current and downconvert the RF frequency to a second frequency that includes the intermediate frequency. Resistors are used to suppress impedance switching effects.

[0011] In another aspect, one method includes: receiving and amplifying an RF signal in a single-ended LNA; and receiving the amplified RF signal in an RF TIA and converting the current of the amplified RF signal into the voltage of the amplified RF signal.

[0012] In one embodiment, the method further includes down-converting the amplified RF signal to a second frequency signal in a passive mixer coupled to an RF TIA, the passive mixer including resistors and a plurality of switches rotatably supplying current of the second frequency signal to a complex path of the second frequency TIA. The method may also include converting the current of the second frequency signal into a voltage of the second frequency signal via the second frequency TIA, the second frequency TIA including an operational amplifier with a feedforward compensation structure.

[0013] In one aspect, a device includes: a first operational amplifier (operational amplifier) ​​having a first feedforward compensation structure, the first operational amplifier being configured to receive a first current and output a first voltage; and a second operational amplifier having a second feedforward compensation structure, the second operational amplifier being configured to receive a second current based on the first voltage and output a second voltage. The first operational amplifier can operate with a first current consumption, and the second operational amplifier can operate with a second current consumption lower than the first current consumption.

[0014] In one implementation, the first operational amplifier includes a transimpedance amplifier (TIA) for receiving a first current at the down-conversion frequency and outputting a first voltage at the down-conversion frequency. The device may also include a filter coupled to the TIA, the filter including a second operational amplifier for receiving a second current at the down-conversion frequency. The filter may be a dual second-order filter, further including a third operational amplifier with a third feedforward compensation structure for receiving a third current based on the second voltage and outputting a third voltage. The first operational amplifier may operate at a first noise performance level, and the second operational amplifier may operate at a second noise performance level, which is higher than the first noise performance level.

[0015] In an implementation, the first operational amplifier includes: a plurality of transconductors; and at least one feedforward transconductor coupled to at least some of the transconductors. The at least one feedforward transconductor shares current with at least one of the plurality of transconductors. The plurality of transconductors may include at least three main path transconductors, and the at least one feedforward transconductor may include a first feedforward transconductor and a second feedforward transconductor. The second feedforward transconductor may be configured to provide compensation to at least one of the three main path transconductors when the output signal swings from a first rail to a second rail.

[0016] In another aspect, a device includes: a feedforward compensated operational amplifier having: a first main path transconductor; a second main path transconductor coupled to the first main path transconductor; and a feedforward path coupled between the input of the first main path transconductor and the output of the second main path transconductor, the feedforward path including at least one feedforward transconductor. At least one of the first and second main path transconductors can reuse current from at least one feedforward transconductor.

[0017] In one implementation, at least one feedforward transconductor cancels at least one pole of either the first or second main-path transconductor. The feedforward compensation operational amplifier can be an intermediate-frequency (IF) transimpedance amplifier (TIA) to receive the IF current and output the IF voltage.

[0018] In one implementation, the device further includes a filter coupled to the IF TIA. The filter may include: a plurality of main path transconductors; and at least one feedforward transconductor coupled between the input of a first main path transconductor of the plurality of main path transconductors and the output of a last main path transconductor of the plurality of main path transconductors.

[0019] In the implementation, the feedforward compensated operational amplifier further includes: a third main path transconductor coupled between the output of the first main path transconductor and the input of the second main path transconductor; and at least one feedforward transconductor comprising the first feedforward transconductor and the second feedforward transconductor. The outputs of the second main path transconductor and the second feedforward transconductor can be configured to oscillate rail-to-rail. The first feedforward transconductor can be configured to share current with at least the third main path transconductor.

[0020] In another aspect, a method includes: receiving a first current and outputting a first voltage in a first operational amplifier having a first feedforward compensation structure and operating with a first current consumption; and receiving a second current based on the first voltage and outputting a second voltage in a second operational amplifier having a second feedforward compensation structure and operating with a second current consumption lower than the first current consumption.

[0021] In one implementation, the method further includes receiving a first current at a sub-conversion frequency and outputting a first voltage at a sub-conversion frequency in a first operational amplifier including a TIA. The method may also include filtering a second current at a sub-conversion frequency, the second operational amplifier including a filter coupled to the TIA. The method may further include receiving a third current based on the second voltage in a third operational amplifier having a third feedforward compensation structure and outputting a third voltage. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the receiver architecture according to an embodiment.

[0023] Figure 2 This is a schematic diagram of the bias circuit according to an embodiment.

[0024] Figure 3 This is a schematic diagram of the feedforward compensation structure according to an embodiment.

[0025] Figure 4 This is a schematic diagram of a feedforward compensation structure according to another embodiment.

[0026] Figure 5 This is a schematic diagram of a current reuse operational amplifier according to an embodiment.

[0027] Figure 6 This is a graphical illustration of the loop gain implemented using a feedforward compensated operational amplifier according to an embodiment.

[0028] Figure 7 This is a block diagram of a representative integrated circuit according to an embodiment.

[0029] Figure 8 This is a high-level graph of the network according to an embodiment. Detailed Implementation

[0030] In various embodiments, the receiver is configured to operate over a wide bandwidth while providing a single-ended architecture to reduce power consumption and chip area, and simultaneously avoiding additional circuitry modules such as certain front-end filters and balun circuitry. Furthermore, embodiments provide receiver architectures with multiple transimpedance amplifiers operating at different frequencies. In some implementations, at least one of these transimpedance amplifiers can be implemented using an operational amplifier with a feedforward compensation structure. This structure can also be used in certain filter circuitry modules to provide the desired linearity while reducing power consumption. These different feedforward compensation structures can be implemented with devices of varying sizes to balance power consumption and linearity. Further details will become apparent from the discussion below.

[0031] Now for reference Figure 1 This diagram illustrates a receiver architecture according to an embodiment. Figure 1 In a high-level view, most of the circuitry of receiver 100 can be implemented on a single semiconductor die, such as one suitable for a given integrated circuit (IC) package. Figure 1 As shown, receiver 100 is configured to receive an input radio frequency (RF) signal, process it along a signal processing path to obtain a digitized sample, and then provide the sample to an additional processing circuitry module, such as a digital signal processor (DSP). (For ease of illustration, in...) Figure 1 (Not shown in the image).

[0032] The input RF signal is received via antenna 105. Antenna 105 is coupled to a pair of capacitors C1 and C2, through which the RF signal is coupled. The thus separated RF signal is provided to low-noise amplifier (LNA) 110 via a path having a parallel coupled inductor coupled to the input of LNA 110.

[0033] More specifically, as shown, a first choke inductor (Lchoke 1) is coupled between pad 108 of the semiconductor die and the base island ground. This base island ground is the lowest ground or reference voltage level of receiver 100 and can be implemented as the ground voltage received via a ground voltage node on a printed circuit board, including the IC package of receiver 100 suitable for this printed circuit board. In turn, another choke inductor (Lchoke 2) is coupled between pad 107 and the voltage regulator node. These choke inductors can be implemented to provide high impedance to guide RF signals to LNA 110. Although in Figure 1 The diagram shows these choke inductors formed by off-chip inductors, but in another embodiment, these choke inductors can be integrated on the same semiconductor die as the remaining circuitry of receiver 100.

[0034] In embodiments, LNA 110 can be implemented as a wideband common-gate LNA. While embodiments are not limited in this respect, LNA 110 can be configured as a current-reuse LNA. While embodiments are not limited in this respect, LNA 110 can be configured to operate within a bandwidth of at least 2 GHz. For example, in one implementation, LNA 110 can be configured for wideband operation to accommodate Wi-Fi signals with extended Wi-Fi capabilities (e.g., Wi-Fi 6e and Wi-Fi 7), where the RF signal can be in the range of approximately 4.9 GHz to 7.125 GHz. Therefore, LNA 110 can be configured to operate within a bandwidth where the highest frequency exceeds the lowest frequency by at least approximately 1.4x. Of course, other wideband ranges are possible in other implementations. For the purposes of this discussion, the term "wideband" refers to a bandwidth of at least 1.5 GHz.

[0035] Still referencing Figure 1 The separated RF signals are coupled to the corresponding metal-oxide-semiconductor field-effect transistors (MOSFETs) M1 and M2 of the LNA 110 via pads 107 and 108 of the semiconductor die. More specifically, MOSFET M1 is implemented as a p-channel MOSFET (PMOS), and MOSFET M2 is implemented as an n-channel MOSFET (NMOS). As shown, MOSFETs M1 and M2 are implemented in a common-gate configuration, wherein the input RF signal is provided to the corresponding source terminal of the MOSFET, and the amplified RF signal is output via the drain terminal of the MOSFET.

[0036] In sequence, the gate terminals of MOSFETs M2 and M1 are configured to receive corresponding bias voltages Vbp and Vbn, respectively. As will be further described herein, these bias voltages, and therefore these gate terminals themselves, can be decoupled from the noise chip ground. In an embodiment, a bias circuit with a filtering circuit module can generate these bias voltages. By maintaining these bias voltages and decoupling LNA 110 from the chip ground, noise introduced via LNA 110 is reduced. Through this decoupling, regulator noise can be suppressed across the operating bandwidth of LNA 110 without the need for a notch filter.

[0037] As described above, in some embodiments, the LNA 110 can be implemented using a current reuse architecture, thereby reducing power consumption. In this configuration, the PMOS device M1 and the NMOS device M2 operate using the same current from the power supply. In other words, the current of the PMOS device M1 also flows through and biases the NMOS device M2, and thus the current is reused. Note that, depending on the implementation, there can be several ways to bias (i.e., generate Vbn and Vbp for it) the current reuse structure.

[0038] Further reference Figure 1 The amplified RF signal output from LNA 110 is coupled via capacitor C3 to an RF transimpedance amplifier (TIA) 120 with input node 118, which can be at a virtual ground level. Note that this virtual ground DC potential is at a different ground level than the island ground. The loop gain of the RF TIA 120 contributes to high linearity without requiring a differential circuit module in the receiver front end. Note that for large input frequencies (e.g., up to approximately 10 GHz), the virtual ground impedance at node 118 is low.

[0039] RF TIA 120 is configured to convert the input current of an amplified RF signal into a voltage. As illustrated, RF TIA 120 is implemented using corresponding MOSFETs, namely PMOS device M3 and NMOS device M4. The RF signal is coupled to the gate terminal of MOSFET M4 / M3 and output via the drain terminal of the corresponding MOSFET. Further illustrated, the source terminal of NMOS device M4 is coupled to a local ground node, which can be at a ground or reference level different from the base island ground and another ground level of the bias circuit. The source terminal of PMOS device M3 is coupled to voltage regulator 115. The voltage level output from RF TIA 120 is converted into current via resistors R1 and R2. This current is supplied to mixer 130, which is implemented as a single-balanced mixer to downconvert the RF signal to a lower frequency signal. More specifically, mixer 130 can be configured to downconvert RF signals to intermediate frequency (IF), which in one example could be approximately 10 MHz.

[0040] As shown, mixer 130 includes resistor R2 and multiple MOSFETs, namely NMOS devices M5-M8, each MOSFET being coupled to receive a corresponding clock signal, namely a 25% duty cycle local oscillator (LO) signal, via its gate terminal. MOSFETs M5-M8 also have a drain terminal for receiving RF current and a source terminal for outputting the down-converted IF current. In this way, mixer 130 is configured to rotatably couple resistor R2 to output node 135 of mixer 130. 1-4 As shown, output node 135 is coupled to the corresponding inputs of separate in-phase and quadrature-phase (I / Q) paths, each implemented as a differential signal processing path. Resistor R2 is also used to suppress impedance transformation effects.

[0041] The current of the IF signal is coupled to the IF TIA 140. I，Q The input (which can be at a different virtual ground level than the RF TIA 120 input, i.e., the IF virtual ground level). For example... Figure 1 As shown in the high-level view, the IF TIA 140 is implemented as an operational amplifier (op-amp). In embodiments further described herein, these operational amplifiers can be implemented using a feedforward compensation structure, and in certain embodiments, a current reuse configuration can be used to reduce power consumption. With this arrangement, maximum loop gain can be achieved at interference frequencies while maintaining high linearity. Figure 1 In the diagram, note the resistive / capacitive feedback structure that couples the input and output of the operational amplifier.

[0042] If the TIA 140 is configured to convert input current into voltage, then resistor R3... IP-QN A current is generated, which is then supplied to the corresponding biquad filter 150. I，Q As shown, each dual second-order filter 150 includes a pair of series-coupled operational amplifiers 154. I 156 I and 154 Q 156 Q In implementation, these operational amplifiers can also be implemented using a feedforward compensation structure. As shown, these series-coupled operational amplifiers have corresponding resistors R4 coupled between them. IP-QN To generate electric current.

[0043] For embodiments that use the same feedforward compensation structure to implement the IF TIA 140 and the dual second-order filter 150, different trade-offs can be made in the design of these different structures for different use cases in the receiver 100.

[0044] More specifically, for Figure 1 In the configuration described, noise issues are more relevant for the IF TIA 140 than for the filter 150. However, linearity issues are relevant for the filter 150. Figure 1In some implementations, larger (and therefore more power-consuming) devices can be used for the first stage of the feedforward compensation structure of the operational amplifier in the IF TIA 140 compared to those present in filter 150. For example, in one implementation, the MOSFETs of the first stage of the IF TIA 140 can have a first size, while the MOSFETs present in filter 150 can have a second size smaller than the first size. In one example, the first size can be four times the second size. For a typical implementation, this sizing approach results in a reduction in the current consumption of filter 150 from 8.5mA to 3.5mA without any performance degradation. Similarly, the current consumption of TIA 140 using this feedforward compensation scheme results in a reduction in its current from 4mA to approximately 2mA. This means at least a 2x saving in current in the analog baseband chain, thereby extending battery life. In some implementations, operational amplifiers 154 and 156 can also be sized differently, where operational amplifier 154 has a MOSFET of a larger sizing than the MOSFET of operational amplifier 156. In other implementations, the MOSFETs of operational amplifiers 154 and 156 can have the same size.

[0045] Still referencing Figure 1 The resulting filtered IF signal is then provided to the digital converter, namely the analog-to-digital converter (ADC) 160. I，Q In an embodiment, ADC 160 can be implemented as a successive approximation (SAR) ADC to provide an N-bit output that can be further digitally processed.

[0046] Utilize, such as Figure 1 The arrangement shown, due to the single-ended configuration of the LNA 110, achieves reduced power consumption. Furthermore, the single-ended configuration avoids the circuit area and power consumption associated with on-chip baluns and notch filters. Although in Figure 1 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0047] As described above, regulator noise can be suppressed by providing a bias circuit module that generates a bias voltage for the LNA 110 in a manner decoupled from the rest of the chip and coupled to a clean base island ground. Now refer to... Figure 2 The diagram shown is a schematic of a bias circuit according to an embodiment. Figure 2 As shown, bias circuit 200 is configured to generate a bias voltage that will be provided to the gate terminal of the MOSFET of a single-ended common-gate LNA as described herein.

[0048] As shown, bias circuit 200 is configured to be decoupled from the rest of the chip and instead coupled to a clean base island ground 210. As shown, bias circuit 200 is coupled to pad 220 of the semiconductor die. Pad 220 is coupled to base island ground 210 via bonding line 215, which may be a dedicated bonding line that only couples these components together.

[0049] The bias circuit 200 is implemented using a filter circuit module, namely an RC filter, shown as a series-coupled resistor and capacitor, namely the series-coupled devices C5 / R5 and C6 / R6. These filter circuits therefore decouple the bias voltages (Vbn and Vbp) obtained at the inter-device nodes 230 and 235 from the base island ground 210. Note that the bias voltages coupled to resistors R5 and R6 (Vbn and Vbp) are decoupled from the base island ground 210. NMOS and V PMOS The voltage can be provided by an additional bias circuit module, which is not shown for clarity. Furthermore, it is understood that other implementations of the bias circuit, including the filter circuit module, can be implemented.

[0050] As mentioned above, IF TIA and dual second-order filters can be implemented using operational amplifiers (more specifically, operational amplifiers with feedforward compensation structures). Now refer to Figure 3 This diagram illustrates a feedforward compensation structure according to an embodiment. As shown, in Figure 3 In this circuit, circuit 300 can be implemented as an operational amplifier. As shown, the main path includes a first transconductor 310 (G m1 ) and the second transconductor 320 (G m2 As further shown, the RC circuits are coupled in parallel to the outputs of these transconductors (i.e., the parallel coupling resistors R1, C1 and R2, C2). In some implementations, these RC circuits can be implemented as parasitic. For example, R1 and R2 might come from G. m The output impedance of the transistor in the stage. However, it is understood that there may be some intentional resistors / capacitors present.

[0051] To provide feedforward compensation, a feedforward path exists and couples between the input of the first transconductor 310 and the output of the second transconductor 320. Therefore, as shown, a feedforward transconductor 330 (G...) is provided. m2' The feedforward transconductor 330 introduces a zero, which cancels out the pole of the first transconductor 310. This zero, introduced at the unity-gain frequency (UGF) of the first transconductor 310, can be eliminated by the ratio between the feedforward transconductor and the second main-path transconductor (i.e., G). m2' / G m2 Use ) to scale.

[0052] use Figure 3 The configuration shown allows the following pass functions to be implemented: Conversely, in the absence of a feedforward path according to the embodiment, the transfer function would be: .

[0053] Therefore, in the embodiment, the zero introduced at the UGF of the first transconductor 310 is proportional to the ratio of the additional transconductor. Essentially, by providing this feedforward compensation structure, linearity is maintained even when power consumption is traded off. Although in Figure 3 The embodiments are shown at this high level, but variations and alternatives are possible.

[0054] For example, it is possible to provide an N-stage feedforward compensation structure with multiple feedforward components. Now refer to Figure 4 The diagram shown is a schematic representation of a feedforward compensation structure according to another embodiment. Figure 4 In the circuit 400, the above-mentioned features are present. Figure 3 The feedforward compensation structure described herein (typically shown in box 405; however, it is referred to as the "400" series instead of...) Figure 3 The "300" series is used to list the components of box 405. For example... Figure 4 As further shown, an additional main path transconductor 440 (G) is coupled between the input of the first main path transconductor 410 and the output of the third main path transconductor 440. m3 ) and another feedforward transconductor 450 (G m3' ).

[0055] With this arrangement, there are three poles and two zeros because the zeros introduced by the feedforward transconductor 450 cancel out the poles of the second main path transconductor 420. Typically, this feedforward compensation structure can be extended to N stages, with N main path transconductors and N-1 feedforward transconductors. More generally, the N stages can have a unity-gain frequency according to the following: As mentioned above, in some implementations, current reuse arrangements can be implemented to reduce power consumption by sharing current among multiple transconductor stages. And utilizing... Figure 4The configuration shown achieves reduced power consumption in the first transconductor 410 by splitting it into PMOS and NMOS halves, with each half sharing current with the other half. Similarly, transconductor 420 can be implemented as an NMOS-only structure, and transconductor 430 as a PMOS-only structure, with each structure sharing current with the other. Transconductors 440 and 450 are each split into PMOS and NMOS halves, with each half sharing current with the other half. This method of implementing a feedforward compensated operational amplifier by splitting the transconductor into PMOS / NMOS halves and sharing current between the halves, or by combining two transconductors into a current-sharing path, results in significant current savings.

[0056] Now for reference Figure 5 The diagram shown is a schematic of a current reuse operational amplifier according to an embodiment. Figure 5 As shown, circuit 500 is implemented with three main path transconductors (G). m1 -G m3 ) and two feedforward transconductors (G m2' G m3' This is a three-stage feedforward compensated operational amplifier. This arrangement allows for a tradeoff between maintaining high linearity and noise, and allows for the design of internal poles / zeros to achieve maximum loop gain at interference frequencies.

[0057] Generally, each transconductor is implemented using a differential amplifier. See Transconductor G for details. m1 NMOS devices M10 and M11 and PMOS devices M12 and M13 receive input differential signals (inp, inm) and provide amplified output signals (om1, om2) at their drain terminals. As shown, the common-coupled source terminals of NMOS devices M10 and M11 are coupled to a reference current level via another NMOS device M14, and in turn, the common-coupled source terminals of PMOS devices M12 and M13 are coupled to a power supply voltage level via another PMOS device M15. Note the presence of capacitor C10 coupled between the drain terminals of NMOS devices M10-M13. In this embodiment, capacitor C10 can be implemented as an adjustable capacitor, which can be controlled to optimize performance based on the frequency of interest.

[0058] In sequence, transconductor G m1 The output is coupled to the transconductor G. m2 The input, i.e., the gate terminals of the corresponding NMOS devices M16 and M17, amplifies the signal and outputs the amplified signal (op2, om2) at its drain terminals. As shown, the drain terminals of NMOS devices M16 and M17 are coupled to the additional main path transconductance G. m3The corresponding gate terminals of NMOS devices M19-20 and M23-24. Note the presence of capacitor C11 coupled between the drain terminals of NMOS devices M16-M17. In this embodiment, capacitor C11 can also be implemented as an adjustable capacitor.

[0059] transconductor G m3 The output (i.e., om, op, the output signal of operational amplifier 500) is provided via the common drain terminals of PMOS devices M19, M24 and PMOS devices M21, M25. As shown, PMOS devices M21, M25 have gate terminals common to PMOS devices M22, M26, which are diode-coupled devices coupled to the power supply voltage node via resistors R11, R13 coupled to their source terminals. Note that this implementation of G... m3 The transconductance approach results in a Class AB output stage for the operational amplifier, which in turn helps achieve better linearity for a given current. As mentioned earlier, by using G... m2 Implemented as an NMOS-only structure (formed by NMOS devices M16, M17, and M18), while G m2' Implemented as a PMOS-only structure (formed by PMOS devices M27, M28, and M29), and G m2' With G m2 Sharing the current further saves electricity. Although in Figure 5 The image shown is G. m2' It is implemented as a PMOS structure, and G m2 It is implemented as an NMOS structure, but it should be understood that the reverse is also possible (G). m2' It is implemented as an NMOS structure, and G m2 (Implemented as a PMOS structure). By splitting the current into PMOS and NMOS halves, the current is stored in G. m3 Therefore, PMOS device M21 and NMOS device M19 share current with each other, while PMOS device M25 and NMOS device M24 share current.

[0060] Still referencing Figure 5 The feedforward path includes a first feedforward transconductor Gm2' implemented using PMOS devices M27 and M28. As shown, PMOS devices M27 and M28 receive the input signal at their gate terminals and provide an amplified output signal at their drain terminals, which are typically coupled to the main path transconductor Gm2'. m2 The drain terminals of the NMOS devices M16 and M17 (and therefore also coupled to the main stage transconductance G) m3(Input). As further shown, the source terminals of the PMOS devices M27 and M28, which are co-coupled, are coupled to the power supply voltage node via another PMOS device M29.

[0061] Finally, referring to the feedforward transconductance Gm3', a current reuse configuration is shown. More specifically, the gate terminals of NMOS devices M30 and M31 are coupled together via series resistors R14 and R15, which generate the bias voltage for biasing NMOS devices M14 and M18. Similarly, the gate terminals of PMOS devices M32 and M33 are coupled together via series resistors R16 and R17, which generate the bias voltage for biasing PMOS devices M15 and M29.

[0062] As further shown, the gate terminals of NMOS devices M30, M31 and PMOS devices M32, M33 receive input signals via capacitive coupling through corresponding capacitors C12-C15, and output amplified output signals to the main path transconductance G. m3 Same output path.

[0063] Note that by utilizing the output stage configuration of the operational amplifier 500, the output signal can oscillate rail-to-rail. In this way, linearity is improved, especially at higher power levels close to saturation. Specifically, the transconductance G... m3 and G m3 Rail-to-rail oscillation, in which transconductor G m3 It acts as the output stage, and the transconductance G m3 Ensure the operational amplifier is adequately compensated even when the signal swings from one rail to another. Despite... Figure 5 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0064] Now for reference Figure 6 The diagram illustrates a graphical representation of the loop gain implemented using a feedforward compensated operational amplifier according to an embodiment. More specifically, as shown... Figure 6As shown in Figure 600, the loop gain of the feedforward compensated operational amplifier, indicated by curve 610, provides a greater loop gain at a lower UGF compared to a conventional Miller operational amplifier. At this point, curve 630 shows the equivalent loop gain of such a conventional Miller operational amplifier, which has a lower gain and would require a 16 GHz UGF for the equivalent gain. Therefore, a greater loop gain of 24 dB can be achieved at 10 MHz using the feedforward compensated operational amplifier as described herein (example 640). While the Miller operational amplifier has a linear loop gain maintained at the 20 dB / decade line (including at the frequency of interest), better linearity and higher loop gain are achieved by providing feedforward compensation structures for the IF TIA and filters as described herein, while simultaneously achieving lower power consumption. Therefore, as shown by curve 610, the loop gain of the example is enhanced, optimizing the gain versus UGF relationship. The loop gain phase of the feedforward compensated operational amplifier is shown at curve 620.

[0065] Now for reference Figure 7 The diagram shown is a block diagram of a representative integrated circuit 700 including the broadband receiver architecture described herein. Figure 7 In the embodiments shown, the integrated circuit 700 may be, for example, a multi-mode wireless transceiver that operates according to one or more wireless protocols, or other devices that can be used in various use cases. In one or more embodiments, Figure 7 The circuit module of the integrated circuit 700 shown can be implemented on a single semiconductor die, or on a separate die of other IP boxes required for wireless communication, MCU computing, external flash memory, and / or to perform various functionalities.

[0066] Integrated circuit 700 can be included in a range of devices, but for the purposes of discussion, it can be incorporated into an IoT device. In the illustrated embodiment, integrated circuit 700 includes a memory system 710, which may include volatile memory devices such as RAM and non-volatile memory devices such as flash memory. Flash memory is a non-transitory storage medium capable of storing instructions and data. Integrated circuit 700 may also include a memory controller 790.

[0067] The memory system 710 is coupled to one or more digital cores 720 via a bus 750. The digital cores 720 may include one or more cores and / or microcontrollers that act as processing units of an integrated circuit. The digital cores 720 may be coupled to a clock generator 730, which may provide one or more phase-locked loops or other clock generator circuit modules to generate various clocks for use by the circuit modules of the IC.

[0068] As further shown, IC 700 also includes a power circuit module 740. Depending on the specific implementation, additional circuit modules may be present to provide various functionalities and interaction with external devices. Such circuit modules may include an interface circuit module 760, which provides a digital communication interface with the additional circuit modules (such as another IC that can be coupled to IC 700 via link 795). IC 700 may also include a security circuit module 770 that implements wireless security technologies.

[0069] In addition, such as Figure 7 As shown, a transceiver circuit module 780 can be provided to transmit and receive wireless signals, for example, according to one or more local or wide-area wireless communication schemes, such as Matter, Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. The transceiver circuit module 780 may include at least one wideband receiver with a single-ended common-gate LNA, and RF and IF TIA implemented using an operational amplifier with a feedforward compensation structure as described herein. It is understood that, although shown at this high level, many variations and alternatives are possible.

[0070] As mentioned above, ICs such as those described herein can be implemented in a wide variety of different devices. Now refer to... Figure 8 This is a high-level diagram of a network according to an embodiment. Figure 8 As shown, network 800 includes various devices, including IoT devices and other wireless devices that may include broadband receiver architectures as described herein.

[0071] exist Figure 8 In embodiments, the wireless mesh network 805 exists, for example, having multiple wireless devices 810. 0-n In the building. As shown, a wireless device 810, which may be an IoT or other wireless device, is coupled to an access point 830, which in turn communicates with a remote service provider 860 via a wide area network 850 (e.g., the Internet). It is understood that, although in Figure 8 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0072] Although this disclosure has been described with respect to a limited number of implementations, many modifications and variations will be apparent to those skilled in the art upon which this disclosure is made. The appended claims are intended to cover all such modifications and variations.

Claims

1. An apparatus comprising: A single-ended low-noise amplifier (LNA) for receiving and amplifying radio frequency (RF) signals, wherein the single-ended LNA has a common-gate configuration; and The first transimpedance amplifier (TIA) is used to receive the amplified RF signal and convert the current of the amplified RF signal into the voltage of the amplified RF signal.

2. The device according to claim 1, wherein, The single-ended LNA includes a current-reuse LNA.

3. The device according to claim 1, wherein, The single-ended LNA is coupled to a first reference voltage node that references a first reference voltage, and the first TIA is coupled to a second reference voltage node that references a second reference voltage, the second reference voltage being different from the first reference voltage.

4. The device according to claim 1, wherein, The single-ended LNA includes: A first metal-oxide-semiconductor field-effect transistor (MOSFET) has a first terminal for receiving the RF signal from an antenna and a second terminal for providing the amplified RF signal to the first TIA; and The second MOSFET has a first terminal for receiving the RF signal from the antenna and a second terminal for providing the amplified RF signal to the first TIA.

5. The device of claim 4 further includes a biasing circuit for providing a first bias voltage to the gate terminal of the first MOSFET and a second bias voltage to the gate terminal of the second MOSFET, wherein the biasing circuit includes a filter circuit.

6. The device according to claim 5, wherein, The bias circuit is coupled to the third reference voltage node.

7. The device of claim 6, further comprising a dedicated junction line coupling the third reference voltage node to the base island ground, wherein the filter circuit decouples the first bias voltage and the second bias voltage from the base island ground.

8. The device of claim 1, further comprising a passive mixer coupled to the first TIA to downconvert the amplified RF signal to a second frequency signal, the passive mixer comprising a resistor and a plurality of switches rotatably configured to provide current of the second frequency signal to a complex path of the second frequency TIA, the second frequency TIA being configured to convert the current of the second frequency signal into a voltage of the second frequency signal.

9. The device according to claim 1, further comprising: A mixer coupled to the first TIA to downconvert the amplified RF signal to an intermediate frequency (IF) signal; and IF TIA is used to receive the IF signal and convert the current of the IF signal into the voltage of the IF signal.

10. The device according to claim 9, wherein, The IF TIA includes a feedforward compensated operational amplifier, which comprises: First main path transconductor; A second main path transconductor coupled to the output of the first main path transconductor; At least one feedforward transconductor coupled between the input of the first main path transconductor and the output of the second main path transconductor; and An output stage comprising the second main path transconductor and the at least one feedforward transconductor, wherein the output of the output stage is a rail-to-rail oscillation.

11. The device according to claim 9, wherein, The IF TIA includes a feedforward compensated operational amplifier, which comprises: First main path transconductor; The second main path transconductor coupled to the first main path transconductor; and A feedforward path coupled between the input of the first main path transconductor and the output of the second main path transconductor, the feedforward path including at least one feedforward transconductor, wherein at least one of the first main path transconductor and the second main path transconductor reuses current from the at least one feedforward transconductor.

12. The device according to claim 11, wherein, The at least one feedforward transconductor is used to cancel at least one pole of the first main path transconductor or the second main path transconductor.

13. A method comprising: Receive and amplify radio frequency (RF) signals in a single-ended low-noise amplifier (LNA); and An amplified RF signal is received in an RF transimpedance amplifier (TIA), and the current of the amplified RF signal is converted into the voltage of the amplified RF signal.

14. The method of claim 13, further comprising downconverting the amplified RF signal to a second frequency signal in a passive mixer coupled to an RF TIA, the passive mixer comprising a plurality of switches and resistors rotatably supplying current of the second frequency signal to a complex path of the second frequency TIA.

15. The method of claim 14, further comprising converting the current of the second frequency signal into a voltage of the second frequency signal via the second frequency TIA, the second frequency TIA comprising an operational amplifier having a feedforward compensation structure.

16. The method of claim 13, further comprising: The amplified RF signal is received in the RF TIA, the RF TIA including a first operational amplifier having a first feedforward compensation structure and operating with a first current consumption; and In a filter coupled to the RF TIA, a second current based on the voltage is received and a second voltage is output. The filter includes a second operational amplifier having a second feedforward compensation structure and operating with a second current consumption lower than that of the first current.

17. The method of claim 16, further comprising receiving a third current based on the second voltage and outputting a third voltage in a third operational amplifier having a third feedforward compensation structure.

18. An apparatus comprising: A first operational amplifier (operational amplifier) ​​having a first feedforward compensation structure, the first operational amplifier being used to receive a first current and output a first voltage; and A second operational amplifier having a second feedforward compensation structure, the second operational amplifier being used to receive a second current based on the first voltage and output a second voltage, wherein the first operational amplifier will operate with a first current consumption, and the second operational amplifier will operate with a second current consumption, the second current consumption being lower than the first current consumption.

19. The device according to claim 18, wherein, The first operational amplifier includes a transimpedance amplifier (TIA) for receiving the first current at a frequency of downconversion and outputting the first voltage at a frequency of downconversion.

20. The device of claim 19, further comprising a filter coupled to the TIA, the filter including the second operational amplifier for receiving the second current at the down-conversion frequency.

21. The device according to claim 20, wherein, The filter includes a dual second-order filter, which further includes a third operational amplifier with a third feedforward compensation structure. The third operational amplifier is used to receive a third current based on the second voltage and output a third voltage.

22. The device according to claim 18, wherein, The first operational amplifier includes: Multiple transconductors; and At least one feedforward transconductor coupled to at least some of the transconductors in the plurality of transconductors.

23. The device according to claim 22, wherein, The at least one feedforward transconductor will share current with at least one of the plurality of transconductors.

24. The device according to claim 22, wherein, The plurality of transconductors includes at least three main path transconductors, and the at least one feedforward transconductor includes a first feedforward transconductor and a second feedforward transconductor.

25. The device according to claim 24, wherein, When the output signal swings from the first track to the second track, the second feedforward transconductor will provide compensation to at least one of the at least three main path transconductors.

Images