High-frequency signal gain adjustable light driving circuit and regulation method thereof

Abstract

The application discloses a high-frequency signal gain adjustable optical drive circuit and a regulation method thereof. The circuit comprises an operational amplifier, an optical coupling device, a weight resistor array composed of a first switch tube to a sixth switch tube, an enable tube and a feedback sampling point. The operational amplifier constitutes a voltage negative feedback loop with phase compensation, and the feedback sampling point is connected to the inverting input end through a second resistor. The weight resistor array is connected between the feedback sampling point and the ground, and the 64-stage gain adjustment is realized by changing the equivalent load of the feedback loop through the switch tube. The source electrode of the enable tube is directly connected to the feedback sampling point, and the drain electrode is grounded. When the enable tube is turned on, the feedback sampling point is directly connected to the ground, the weight array is bypassed, and the enable tube works in the fixed gain mode. The application eliminates the switch glitch and isolates the parasitic parameters by the negative feedback sampling point load adjustment and the enable tube direct connection clamping bypass, and is suitable for high-frequency oscilloscopes, signal collection, waveform output and other scenes.

Description

Technical Field

[0001] This invention relates to the field of optical driving circuit technology, specifically to a high-frequency signal gain adjustable optical driving circuit and its control method based on an operational amplifier voltage positive feedback loop and an NMOS weighted resistor array. It is applicable to applications requiring high-precision gain adjustment and low-noise amplification, such as high-frequency oscilloscopes, high-speed signal acquisition, waveform output, shaping triggering, and fiber optic communication. Background Technology

[0002] In modern electronic measurement and communication systems, optical drive circuits serve as a crucial interface between electrical and optical signals, and are widely used in fields such as fiber optic communication, optical ranging, optical signal processing, and high-speed data transmission. As signal frequencies continue to increase and application scenarios become more diverse, increasingly stringent requirements are being placed on the gain adjustment accuracy, response speed, noise performance, and mode switching smoothness of optical drive circuits.

[0003] Traditional optical drive circuits typically employ transistor amplification architectures with fixed gain designs, or achieve gain adjustment through analog or digital potentiometers. Fixed-gain circuits cannot adapt to the requirements of different input signal amplitudes, and in applications with a large dynamic range of input signals, they are prone to insufficient amplification of small signals or saturation distortion of large signals. Analog potentiometers have low adjustment precision and poor repeatability, and are subject to mechanical wear and contact noise, making them unsuitable for high-frequency and high-precision applications. While digital potentiometers can achieve digital control, their step resolution is limited, and their parasitic capacitance and resistance are large, which can severely affect the high-frequency characteristics of the signal in high-frequency applications, leading to signal attenuation, phase distortion, and bandwidth reduction.

[0004] Existing technologies also employ multiple analog switches in conjunction with resistor networks to achieve gain adjustment. This approach typically uses the resistor network as the amplifier's feedback or load resistor, and the gain is changed by selecting different resistors through the analog switches. While this achieves high adjustment accuracy, it suffers from the following inherent drawbacks: First, during switching, the simultaneous operation of multiple switches generates significant switching glitches and intermediate transient states. These transient interferences are directly superimposed on the high-frequency signal, causing signal distortion. Second, when gain adjustment is not required, the resistor network and switches remain connected in the signal path, and their parasitic parameters continuously affect the high-frequency signal, leading to increased circuit noise and a decreased signal-to-noise ratio. Third, the analog switches directly switch the AC signal path, and the charge injection and clock feedthrough effects of the switches cause signal offset and distortion.

[0005] Operational amplifiers (OPAs) are widely used in high-frequency signal processing. In existing technologies, OPA gain adjustment is typically achieved by changing the feedback resistor at the inverting input, i.e., changing the ratio of the feedback resistor to the input resistance. The problem with this approach is that the feedback resistor is directly in the AC signal path; switching the feedback resistor directly causes output signal jumps and distortion. Furthermore, the parasitic parameters of the feedback resistor network directly affect the amplifier's frequency response and stability. When using a binary weighted resistor network for OPA gain adjustment, it is usually directly connected as the feedback resistor network between the output and inverting input. The switching transistor is directly in the AC feedback path, and its parasitic capacitance and on-resistance directly affect the amplifier's performance.

[0006] On the other hand, existing optical driving circuits typically input a mixture of baseband and high-frequency signals, lacking an independent operating point adjustment mechanism. The DC operating point and AC gain are coupled, making adjustment inconvenient. In optical driving applications, the DC operating point determines the bias current of the optocoupler, directly affecting the average power and stability of the optical output, while the AC gain determines the modulation depth. Both should be adjusted independently to achieve optimal performance.

[0007] Furthermore, negative feedback loops are widely used in linear amplifiers to stabilize gain, broaden bandwidth, and reduce distortion. However, in existing technologies, binary weighted resistor networks are typically used as the feedback resistors or input resistors of the amplifier, and the gain is adjusted by changing the ratio of the feedback resistor to the input resistor. Connecting the binary weighted resistor network between the feedback sampling point (A) of the negative feedback loop and ground, and adjusting the negative feedback depth by changing the equivalent load of the feedback sampling point, is a novel approach not yet reported in existing technologies. In existing technologies, binary weighted resistor networks are commonly used in digital-to-analog converters (DACs) to convert digital signals into analog voltage or current outputs, or as the feedback resistor network of a programmable gain amplifier. Connecting it to the feedback sampling point of a negative feedback loop to adjust the equivalent load represents a completely new circuit topology.

[0008] Therefore, there is an urgent need for a novel optical drive circuit with adjustable high-frequency signal gain and its control method, which can effectively suppress the effects of switching glitches and parasitic parameters while achieving high-precision, multi-level gain adjustment, providing a low-noise fixed-gain working mode, having independent baseband operating point adjustment and high-frequency gain adjustment mechanisms, and achieving smooth transition of mode switching through an innovative positive feedback loop topology. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-frequency signal gain adjustable optical driving circuit and its control method to solve the following technical problems in the prior art: (1) insufficient gain adjustment accuracy or limited adjustment resolution; (2) glitches and intermediate transition states are generated during the switching process; (3) in the fixed gain mode, the parasitic parameters of the resistor network still affect the high-frequency signal, resulting in increased noise; (4) the switching transistor directly switches the AC signal path, causing switching distortion and charge injection; (5) the mixed input of baseband signal and high-frequency signal causes the DC operating point and AC gain to be coupled to each other; (6) there is a lack of a stable fixed gain mode that can be used as a self-calibration reference; (7) in the existing operational amplifier gain adjustment scheme, the parasitic parameters of the feedback resistor network directly affect the amplifier performance.

[0010] To achieve the above objectives, the present invention adopts the following technical solution: A high-frequency signal gain-adjustable optical driving circuit includes a baseband input module, an input module, a feedback module, an operational amplifier module, a gain adjustment module, an enable module, and a photoelectric output module. The entire circuit is divided into three main parts: the operational amplifier main control feedback loop, the photoelectric load, and the NMOS resistor weight array. All grounding terminals are common ground.

[0011] The baseband input module includes a DC reference voltage input terminal (Vb) and a first resistor (R1). The DC reference voltage (Vb) is connected to the non-inverting input terminal of the operational amplifier (U13) via the first resistor (R1) to set the DC operating point of the non-inverting input terminal.

[0012] The input module includes a first high-frequency input terminal (HF+), a second high-frequency input terminal (HF-), an input signal terminal (V-in), and a first capacitor (C1). The first high-frequency input terminal (HF+) is connected to the inverting input terminal of the operational amplifier (U13); the second high-frequency input terminal (HF-) is directly connected to the non-inverting input terminal of the operational amplifier (U13); the input signal terminal (V-in) is connected to the non-inverting input terminal of the operational amplifier (U13) via the first capacitor (C1). The first high-frequency input terminal (HF+) and the second high-frequency input terminal (HF-) are paired signals connected to the two terminals of the high-frequency signal, and the two signals are identical. The non-inverting input terminal of the operational amplifier (U13) is also grounded through a fifth resistor (R5).

[0013] The feedback module includes a preset gain adjustment signal terminal (FB1), a third resistor (R3), and a fifth capacitor (C5). The non-inverting input terminal of the operational amplifier (U13) is connected in series with the fifth capacitor (C5) and the third resistor (R3) and then connected to the preset gain adjustment signal terminal (FB1). The fifth capacitor (C5) and the third resistor (R3) form a phase compensation network to prevent the voltage negative feedback loop from self-oscillating at high frequencies.

[0014] The operational amplifier module includes an operational amplifier (U13). The inverting input of the operational amplifier (U13) is connected to the feedback sampling point (A) via a second resistor (R2), with point A being a common potential point. The positive power supply pin of the operational amplifier (U13) is connected to +5V, the negative power supply pin is connected to -5V, and the heat sink (EP) pin is connected to common ground (GND). The output of the operational amplifier (U13) outputs a high-frequency output signal (HF1+) via a fourth resistor (R4).

[0015] The photoelectric output module includes an optocoupler (U4). The high-frequency output signal (HF1+) passes sequentially through the anode and cathode of the optocoupler (U4) and is then connected to the feedback sampling point (A). The optocoupler (U4) simultaneously serves as both a photoelectric conversion and a voltage negative feedback path.

[0016] The gain adjustment module includes the first switch (Q13) to the sixth switch (Q18) and the thirteenth resistor (R13) to the eighteenth resistor (R18). (The connection method and resistance values ​​remain unchanged. The source of the NMOS transistor is connected to the feedback sampling point A via the weighted resistor, and the drain is grounded; feedback sampling point A is connected in parallel with R6 and R7 to ground.) The enabling module includes an enable transistor (Q20). The enable transistor (Q20) is an NMOS transistor, with its gate (pin 1) connected to the enable control signal (En), its drain (pin 2) connected to common ground (GND), and its source (pin 3) directly connected to the feedback sampling point (A). No resistor is connected in series between the source and the feedback sampling point (A). It is important to note that the source of the enable transistor (Q20) is directly connected to the feedback sampling point (A), while the sources of the first switching transistor (Q13) to the sixth switching transistor (Q18) are all connected to the feedback sampling point (A) through their respective weighted resistors. This is the key difference between the enable transistor (Q20) and the weighted array switching transistors in terms of connection method. When the enable control signal (En) is high, the enable transistor (Q20) is turned on, and the feedback sampling point (A) is directly grounded through the extremely low on-resistance of the enable transistor (Q20), and the weight resistor array is bypassed; when the enable control signal (En) is low, the enable transistor (Q20) is turned off, and the equivalent load of the feedback sampling point (A) is determined by the sixth resistor (R6), the seventh resistor (R7), and the weight resistor branch that is turned on in the gain adjustment module.

[0017] The present invention also provides a method for controlling a high-frequency signal gain adjustable optical driving circuit, comprising the following steps: S1. Input DC reference voltage (Vb), which sets the DC operating point of the non-inverting input terminal of the operational amplifier (U13) through the first resistor (R1); S2. Input high-frequency paired signals HF+ and HF-, HF+ is connected to the inverting input terminal, and HF- is connected to the non-inverting input terminal. At the same time, the input signal V-in is connected to the non-inverting input terminal through the first capacitor (C1). S3. Input the preset gain adjustment signal (FB1), which is connected to the non-inverting input terminal through the fifth capacitor (C5) and the third resistor (R3) to perform initial gain adjustment and stabilize the voltage negative feedback loop; S4. After the circuit is working stably, FB1 remains a fixed value and no longer changes. S5. When gain adjustment is required, the enable control signal (En) turns off the enable transistor (Q20), and at the same time, the control signals s1-s6 output the corresponding digital signals to turn on the corresponding switch transistor. The corresponding weight resistor is connected to the feedback sampling point (A) to change the equivalent load of the voltage negative feedback loop and realize 64-level gain adjustment. S6. When gain adjustment is not required, the enable control signal (En) turns on the enable transistor (Q20), the feedback sampling point (A) is directly grounded through the low on-resistance of the enable transistor (Q20), the weight resistor array is bypassed, and the gain is determined by FB1. Beneficial effects

[0018] Compared with the prior art, the present invention has the following beneficial effects: First, in fixed gain mode, the weighted resistor array is completely bypassed, parasitic parameters are isolated, and signal integrity is significantly improved. The underlying principle is that when the enable transistor (Q20) is turned on, its source is directly connected to the feedback sampling point (A), and its drain is grounded. The on-resistance between the source and drain is extremely low (Rds(on) of an NMOS transistor is typically tens of milliohms to a few ohms), directly connecting the feedback sampling point (A) to ground. Since there is no series resistance between the source of the enable transistor (Q20) and the feedback sampling point (A), there is no additional series impedance. When the enable transistor (Q20) is turned on, the impedance from the feedback sampling point (A) to ground is only the on-resistance of the enable transistor (Q20) itself, which can reach the milliohm level. The clamping effect is far superior to the series resistor solution. At this point, resistors thirteen (R13) to eighteen (R18) and transistors 1 to 6 (Q18) are all bypassed by the low-impedance path of the enable transistor (Q20), and their parasitic parameters such as parasitic capacitance, parasitic inductance, and junction capacitance are completely isolated from the voltage negative feedback loop. Compared with the prior art where the resistor network is always connected to the signal path, this invention significantly reduces the number of components in the negative feedback loop in fixed gain mode, reduces parasitic capacitance by more than an order of magnitude, and effectively suppresses high-frequency signal attenuation and phase distortion. This effect is particularly critical in high-frequency oscilloscope front-end amplification and high-speed signal acquisition, because the frequency response unevenness caused by parasitic parameters directly leads to measurement errors and waveform distortion. Second, the single-transistor switching mode eliminates the glitches caused by multiple transistors switching simultaneously. The technical principle is that the switching between fixed gain mode and adjustable gain mode is completed by turning on or off only one transistor (Q20). At the moment of switching, the states of transistors 1 to 6 (Q18) remain unchanged. Existing technologies using simultaneous switching of multiple analog switches suffer from uncertain intermediate impedance states due to slight differences in the switching times of each switch, resulting in sharp glitches in the output signal, with amplitudes reaching 5%-15% of the signal amplitude. The single-transistor switching scheme of this invention simplifies the switching transient to the conduction / cutoff process of a single NMOS transistor, making the switching characteristics deterministic and predictable. By rationally designing the gate drive circuit of the enable transistor (Q20), the switching rate can be controlled, further suppressing transient interference. Experiments show that the mode switching glitches of this invention can be reduced to less than 1 / 10 of those in existing technologies.

[0019] Third, the fixed-gain mode exhibits excellent low-noise characteristics. Its technical principle lies in the fact that the gain adjustment module is completely bypassed in fixed-gain mode. The voltage negative feedback loop contains only the operational amplifier (U13), the second resistor (R2), the sixth resistor (R6), the seventh resistor (R7), the optocoupler (U4), and the feedback module. The active devices are only the operational amplifier (U13) and the optocoupler (U4), minimizing the number of noise sources. Simultaneously, because the weighted resistor network is isolated, resistor thermal noise and NMOS transistor shot noise no longer contribute to the output noise. Compared to existing solutions where the resistor network is always connected, the output noise voltage density in the fixed-gain mode of this invention can be reduced by 30%-50%. In high-sensitivity signal acquisition applications, the low-noise front-end directly determines the minimum detectable signal of the system. The fixed-gain mode of this invention is particularly suitable as a low-noise amplification front-end for weak high-frequency signals.

[0020] Fourth, the fixed gain mode can serve as a high-precision self-calibration reference. The technical principle is as follows: the preset gain adjustment signal (FB1) remains fixed after the circuit stabilizes, and the gain adjustment module is completely bypassed in fixed gain mode. Therefore, the gain value in this mode is determined only by the parameters of the operational amplifier (U13), the second resistor (R2), the sixth resistor (R6), the seventh resistor (R7), and the feedback module parameters, and is unaffected by digital control signals and the state of the switching transistors, exhibiting extremely high stability and repeatability. The system can utilize this known and stable gain as a calibration reference. During each power-on or periodic calibration, it first switches to fixed gain mode to measure the reference gain, and then switches to adjustable gain mode to perform point-by-point calibration of the 64-level gain, establishing a gain correction table. Compared to existing solutions that require an external calibration signal source, this invention achieves self-calibration without additional hardware, and the calibration reference is completely identical to the measured signal path, eliminating calibration errors caused by path differences.

[0021] Fifth, gain adjustment is indirectly achieved by changing the equivalent load of the feedback sampling point in the voltage negative feedback loop, thus avoiding switching distortion. The technical principle is as follows: the first to sixth switches (Q18) control the connection and disconnection of the weighting resistor between the feedback sampling point (A) and ground. By changing the equivalent load impedance of the feedback sampling point (A), the negative feedback depth fed back to the inverting input of the operational amplifier (U13) through the second resistor (R2) is changed, thereby indirectly adjusting the circuit gain. The switching transistors are not directly in the AC signal path; their sources are connected to the weighting resistor rather than directly to the signal terminal. Therefore, the switching action does not directly cut off or connect the AC signal. In existing technologies, analog switches directly switch the AC feedback path, causing the output voltage to jump at the moment of switching due to the charge injection effect of the switching transistor, and the clock feedthrough effect coupling the control signal to the output terminal. The indirect adjustment method of this invention fundamentally avoids these problems, ensuring that the signal waveform remains consistent before and after gain adjustment, without transient distortion or DC offset.

[0022] Sixth, the architecture of separating the DC reference voltage and high-frequency signal input improves the stability and adjustment flexibility of the operating point. The technical principle is as follows: the DC reference voltage (Vb) independently sets the DC operating point of the operational amplifier (U13)'s inverting input through the first resistor (R1); the second high-frequency input (HF-) is directly connected to the inverting input; and the input signal (V-in) is AC-coupled through the first capacitor (C1). These three components are functionally separated in the circuit. Adjusting the DC operating point does not affect the input amplitude of the high-frequency signal, and changes in the amplitude of the high-frequency signal do not disturb the DC operating point. Compared with the existing scheme of mixed baseband and high-frequency input, this invention can first precisely adjust the DC reference voltage to make the optocoupler (U4) operate at the optimal bias current point, and then input the high-frequency signal for gain adjustment. The operation process is clear and does not interfere with each other. In optical drive applications, a stable DC bias current means stable optical output power, which is crucial for ensuring optical communication quality and measurement accuracy.

[0023] Seventh, the two-stage adjustment architecture, consisting of pre-adjustment using a preset gain adjustment signal and fine-tuning using an NMOS weight array, balances adjustment range and resolution. Its technical principle is as follows: the first stage performs coarse adjustment using a preset gain adjustment signal (FB1) to set the circuit gain near the target range; the second stage performs fine-tuning using a 6-bit NMOS weight resistor array, achieving 64 levels of fine adjustment within the coarse adjustment range. Existing technologies that rely solely on binary networks require increasing the number of bits to cover a wide gain range, leading to increased circuit complexity, parasitic parameters, and switching glitches. This invention's two-stage architecture separates coarse and fine adjustment functions. FB1 handles wide-range coverage, while the weight array handles high-precision adjustment within a small range, ensuring both a wide dynamic range and fine adjustment steps, while simultaneously controlling circuit size and parasitic parameters.

[0024] Eighth, the voltage negative feedback loop topology achieves a high gain-bandwidth product and multiplexing of photoelectric conversion and feedback paths. Its technical principle is as follows: This invention uses an operational amplifier (U13) to form a voltage negative feedback loop. The feedback sampling point (A) is connected to the inverting input terminal through a second resistor (R2). The output signal is fed back to the feedback sampling point (A) via an optocoupler (U4), forming negative feedback. This negative feedback topology can stabilize and improve the overall gain-bandwidth product of the circuit without increasing the gain burden on the operational amplifier. Furthermore, the optocoupler (U4) simultaneously plays the dual role of photoelectric conversion and negative feedback path, simplifying the circuit structure. Compared to the traditional negative feedback operational amplifier gain adjustment scheme that places the gain adjustment element directly in the feedback resistor network, the negative feedback topology of this invention moves the gain adjustment element to the feedback sampling point, avoiding the direct load effect of the feedback resistor network on the operational amplifier input terminal, which is beneficial for maintaining stable gain and phase margin at high frequencies. Attached Figure Description

[0025] Figure 1 This is the overall circuit schematic diagram of the high-frequency signal gain adjustable optical driving circuit of the present invention; Figure 2 This is a flowchart of the control method of the present invention. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0027] like Figure 1 As shown, a high-frequency signal gain adjustable optical driving circuit includes a baseband input module (10), an input module (20), a feedback module (30), an operational amplifier module (40) including an operational amplifier (U13), a gain adjustment module (50), an enable module (60), and an optoelectronic output module (70). The entire circuit is divided into three main parts: the operational amplifier main control feedback loop, the optoelectronic load, and the NMOS resistor weight array. All grounding terminals are common ground.

[0028] The baseband input module (10) includes a DC reference voltage input terminal (Vb) and a first resistor (R1); the input module (20) includes a first high-frequency input terminal (HF+), a second high-frequency input terminal (HF-), an input signal terminal (V-in), and a first capacitor (C1).

[0029] The feedback module (30) includes a preset gain adjustment signal terminal (FB1), a third resistor (R3) and a fifth capacitor (C5) to prevent the voltage negative feedback loop from self-oscillating at high frequencies.

[0030] In this embodiment, the inverting input of the operational amplifier (U13) is connected to the feedback sampling point (A) through the second resistor (R2), and the marked point A is the common potential point. The optoelectronic output module (70) includes an optocoupler (U4). The optocoupler (U4) plays a dual role in both photoelectric conversion and voltage negative feedback. This embodiment provides a high-frequency signal gain adjustable optical driving circuit. The entire circuit is divided into three main parts: the operational amplifier main control feedback loop, the optocoupler load (U4), and the NMOS resistor weight array. All GNDs are common ground. The operational amplifier main control feedback loop is centered on the operational amplifier (U13). The operational amplifier (U13) is a PD operational amplifier, which is a high-speed, low-noise operational amplifier with a unity-gain bandwidth greater than 100MHz and a slew rate greater than 500V / μs to ensure sufficient amplification capability and response speed under high-frequency signals. The positive power supply pin of the operational amplifier (U13) is connected to a +5V DC power supply, the negative power supply pin is connected to a -5V DC power supply, and the heat sink (EP) pin is connected to the common ground (GND) to provide good heat dissipation and electromagnetic shielding.

[0031] The non-inverting input pin of operational amplifier (U13) is connected to the following four branches: First, the DC reference voltage (Vb) is connected to the non-inverting input pin via a first resistor (R1). The first resistor (R1) has a resistance of 10kΩ and is used to convert the DC reference voltage into the bias current of the non-inverting input pin, while also providing isolation and current limiting. Second, the second high-frequency input pin (HF-) is directly connected to the non-inverting input pin and is used to input the inverting component of the high-frequency paired signal. Third, the input signal pin (V-in) is connected to the non-inverting input pin via a first capacitor (C1). At the phase input terminal, the first capacitor (C1) has a capacitance of 100pF, which serves to block DC and pass AC, preventing the DC component of the input signal (V-in) from entering the non-inverting input terminal while allowing high-frequency AC signals to pass through. Fourth, the non-inverting input terminal is grounded through the fifth resistor (R5), which has a resistance of 10kΩ. This provides a DC path to ground for the non-inverting input terminal, ensuring that the DC potential of the non-inverting input terminal is determined by the voltage division of the first resistor (R1) and the fifth resistor (R5), while also providing a DC discharge path for the first capacitor (C1).

[0032] The inverting input pin of operational amplifier (U13) is connected to the following branches: First, the first high-frequency input (HF+) is directly connected to the inverting input, used to input the positive inverting component of the high-frequency paired signal; second, the inverting input is connected to marker A via the second resistor (R2), marker A being a common potential point, i.e., the feedback sampling point. The first high-frequency input (HF+) and the second high-frequency input (HF-) are paired signals connected to the two terminals of the high-frequency signal, and the two signals are identical.

[0033] The non-inverting input of the operational amplifier (U13) is connected in series with a fifth capacitor (C5) and a third resistor (R3) to the feedback network labeled FB1. FB1 is the preset gain adjustment signal, which is an external input signal. The fifth capacitor (C5) has a capacitance of 1nF, and the third resistor (R3) has a resistance of 1kΩ. The fifth capacitor (C5) and the third resistor (R3) are connected in series to form a phase compensation network. The fifth capacitor (C5) plays the role of blocking DC and passing AC and providing phase compensation, preventing the voltage negative feedback loop from generating self-oscillation at high frequencies. At the same time, it allows the DC component and low-frequency component of the preset gain adjustment signal (FB1) to act on the non-inverting input through the third resistor (R3).

[0034] The output pin of the operational amplifier (U13) outputs a high-frequency output signal (HF1+) via the fourth resistor (R4). The fourth resistor (R4) has a resistance of 50Ω and serves to limit current and isolate the signal, limiting the maximum current flowing through the LED of the optocoupler (U4) and preventing the output of the operational amplifier (U13) from directly driving a capacitive load, which could cause oscillation.

[0035] The optoelectronic load is an optocoupler (U4). A high-frequency output signal (HF1+) is connected to the anode of the optocoupler (U4), and the cathode of the optocoupler (U4) is connected to marker point A (feedback sampling point). The optocoupler (U4) internally contains a light-emitting diode (LED) and a photodetector. The anode of the LED receives the high-frequency output signal (HF1+), and the cathode is connected to the feedback sampling point (A). When current flows through the LED, the intensity of the emitted light changes with the current, thereby converting the high-frequency electrical signal into an optical signal output. The optocoupler (U4) is also in a voltage negative feedback path, and the voltage drop across its terminals participates in the operation of the feedback loop.

[0036] Marker point A (feedback sampling point) is a key common node in the voltage negative feedback loop and also serves as a common terminal for the following connections: First, it is connected to the inverting input of the operational amplifier (U13) through the second resistor (R2); second, it is connected to the cathode of the optocoupler (U4); third, it serves as the common upper terminal of the NMOS weighted resistor array; fourth, it is grounded through the sixth resistor (R6) and the seventh resistor (R7) connected in parallel, both of which have a resistance of 68Ω, and their equivalent resistance after parallel connection is 34Ω, providing a fixed load to ground for the feedback sampling point (A); fifth, it is directly connected to the source of the enable transistor (Q20), and there is no series resistance between the source of the enable transistor (Q20) and marker point A.

[0037] The NMOS resistor weighting array includes a first switch (Q13), a second switch (Q14), a third switch (Q15), a fourth switch (Q16), a fifth switch (Q17), and a sixth switch (Q18), and resistors connected in series with them: a thirteenth resistor (R13), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), and an eighteenth resistor (R18). All six switches are N-channel enhancement-mode MOSFETs (NMOS transistors), with pins defined as follows: pin 1 is the gate (G), pin 2 is the drain (D), and pin 3 is the source (S). The drains (pin 2) of all six switches are connected to a common ground (GND). The gates (pin 1) of each NMOS transistor are driven by external control signals s1, s2, s3, s4, s5, and s6, respectively. The sources (pin 3) of each NMOS transistor are connected in series with their corresponding weighting resistors and then aggregated to mark point A.

[0038] The specific connections are as follows: The gate (pin 1) of the first switching transistor (Q13) is connected to the first control signal (s1). The source (pin 3) of the first switching transistor (Q13) is connected to one end of the thirteenth resistor (R13), which has a resistance of 3.4kΩ. The other end of the thirteenth resistor (R13) is connected to mark point A. The drain (pin 2) of the first switching transistor (Q13) is connected to GND. The gate of the second switching transistor (Q14) is connected to the second control signal (s2). The source is connected to one end of the fourteenth resistor (R14), which has a resistance of 1.7kΩ. The other end of the fourteenth resistor (R14) is connected to mark point A. The drain is connected to GND. The gate of the third switching transistor (Q15) is connected to the third control signal (s3). The source is connected to one end of the fifteenth resistor (R15), which has a resistance of 850Ω. The other end of the fifteenth resistor (R15) is connected to mark point A. The drain is connected to GND. The gate of the fourth switch (Q16) is connected to the fourth control signal (s4), the source is connected to one end of the sixteenth resistor (R16), the resistance of the sixteenth resistor (R16) is 425Ω, the other end of the sixteenth resistor (R16) is connected to mark point A, and the drain is connected to GND. The gate of the fifth switch (Q17) is connected to the fifth control signal (s5), the source is connected to one end of the seventeenth resistor (R17), the resistance of the seventeenth resistor (R17) is 212.5Ω, the other end of the seventeenth resistor (R17) is connected to mark point A, and the drain is connected to GND. The gate of the sixth switch (Q18) is connected to the sixth control signal (s6), the source is connected to one end of the eighteenth resistor (R18), the resistance of the eighteenth resistor (R18) is 106.25Ω, the other end of the eighteenth resistor (R18) is connected to mark point A, and the drain is connected to GND.

[0039] The six weighted resistors are set in a binary decreasing ratio: the thirteenth resistor (R13) is 3.4kΩ (reference), the fourteenth resistor (R14) is 1.7kΩ (half of R13), the fifteenth resistor (R15) is 850Ω (quarter of R13), the sixteenth resistor (R16) is 425Ω (eighth of R13), the seventeenth resistor (R17) is 212.5Ω (1 / 16 of R13), and the eighteenth resistor (R18) is 106.25Ω (32 / 13 of R13). Since the weighted resistors are connected between point A and the source of the switching transistor, and the drain of the switching transistor is grounded, when a switching transistor is turned on, the corresponding weighted resistor is connected in parallel between point A and ground. The smaller the resistance value, the greater the impact on the total equivalent resistance after parallel connection. Therefore, the eighteenth resistor (R18) (minimum resistance value 106.25Ω) corresponds to the highest bit control signal (s6), and the thirteenth resistor (R13) (maximum resistance value 3.4kΩ) corresponds to the lowest bit control signal (s1).

[0040] When the first control signal (s1) to the sixth control signal (s6) output different binary codes, the corresponding switch is turned on, and the corresponding weighted resistor is connected between the mark point A and ground. The total equivalent resistance from the mark point A to ground is the parallel value of the sixth resistor (R6) and the seventh resistor (R7) (34Ω), the enable transistor branch impedance, and the parallel value of all the turn-on weighted resistors. For example, when the code is 000001, only the first switch (Q13) is turned on, and the thirteenth resistor (R13) (3.4kΩ) is connected in parallel to the 34Ω resistor, resulting in a total equivalent resistance of approximately 33.66Ω. When the code is 100000, only the sixth switch (Q18) is turned on, and the eighteenth resistor (R18) (106.25Ω) is connected in parallel to the 34Ω resistor, resulting in a total equivalent resistance of approximately 25.76Ω. When the code is 111111, all six switches are turned on, and all six weighted resistors are connected in parallel, resulting in a parallel equivalent resistance of approximately 50.8Ω. This parallel equivalent resistance, combined with the 34Ω resistor, results in a total equivalent resistance of approximately 20.5Ω. Through this binary weighting method, the 6-bit control signal can generate 64 different equivalent load impedance values, thereby achieving 64 levels of positive feedback depth and gain adjustment.

[0041] The enabling module includes an enabling transistor (Q20). The enabling transistor (Q20) is an N-channel enhancement-mode MOSFET (NMOS transistor). Its drain (pin 2) is connected to common ground (GND), its gate (pin 1) receives the enable control signal (En), and its source (pin 3) is directly connected to marker A. There is no series resistor between the source and marker A. It is important to emphasize the fundamental difference in connection between the enabling transistor (Q20) and the first to sixth switching transistors (Q13 to Q18): the sources of the first to sixth switching transistors (Q13) are indirectly connected to marker A through their respective weighted resistors (the thirteenth resistor R13 to the eighteenth resistor R18), while the source of the enabling transistor (Q20) is directly connected to marker A without any series components in between. This distinction allows the enable transistor (Q20) to clamp the marker point A to ground potential with minimal impedance when it is turned on, while the weight array switches provide different equivalent loads to the marker point A through their respective weight resistors when they are turned on. The on-resistance (Rds(on)) of the enable transistor (Q20) is designed to be very small, less than 100mΩ in this embodiment. When the enable control signal (En) is high (greater than the threshold voltage Vgs of the enable transistor (Q20), typically 1V-2V), the enable transistor (Q20) is turned on, and the marker point A is directly connected to ground through the extremely low on-resistance of the enable transistor (Q20). At this time, regardless of the state of the first switch (Q13) to the sixth switch (Q18), the potential of the marker point A is forcibly pulled down to near ground potential by the enable transistor (Q20), and the weight resistor array is completely bypassed, no longer affecting the operation of the voltage negative feedback loop. When the enable control signal (En) is low (less than the threshold voltage), the enable transistor (Q20) is turned off, and the low-impedance path between marker A and ground is broken. At this time, the equivalent load of marker A is determined by the sixth resistor (R6), the seventh resistor (R7), and the weight resistor branch that is turned on in the gain adjustment module.

[0042] The working process of the circuit in this embodiment is described in detail below, such as... Figure 2 : S1. Setting the DC Operating Point. After connecting the +5V and -5V power supplies, first input the DC reference voltage through the DC reference voltage input terminal (Vb). The DC reference voltage is applied to the non-inverting input terminal of the operational amplifier (U13) through the first resistor (R1), and works with the fifth resistor (R5) to determine the DC potential of the non-inverting input terminal. Due to the virtual short characteristic of the operational amplifier (U13) when operating in the linear region, the potential of the inverting input terminal follows the potential of the non-inverting input terminal. Then, through the second resistor (R2) and the voltage negative feedback loop, the DC potential of the marker point A is determined, and finally, the DC bias current flowing through the LED of the optocoupler (U4) is determined. Adjust the magnitude of the DC reference voltage (Vb) so that the LED of the optocoupler (U4) operates at a suitable bias current point, usually slightly higher than the light emission threshold current, to ensure good modulation linearity and luminous efficiency.

[0043] S2. Input High-Frequency Signal. After setting the DC operating point, input a pair of high-frequency signals through the first high-frequency input terminal (HF+) and the second high-frequency input terminal (HF-). The first high-frequency input terminal (HF+) is directly connected to the inverting input terminal of the operational amplifier (U13), and the second high-frequency input terminal (HF-) is directly connected to the non-inverting input terminal. Simultaneously, the input signal terminal (V-in) is AC-coupled to the non-inverting input terminal via the first capacitor (C1). The high-frequency signal is superimposed on the DC operating point, amplified by the operational amplifier (U13), and output from the output terminal. It then drives the LED of the optocoupler (U4) through the fourth resistor (R4), converting the high-frequency electrical signal into an optical signal.

[0044] S3. Input the preset gain adjustment signal and stabilize the loop. Simultaneously, input the preset gain adjustment voltage through the preset gain adjustment signal terminal (FB1). The preset gain adjustment signal, via the third resistor (R3) and the fifth capacitor (C5), acts on the non-inverting input of the operational amplifier (U13), jointly determining the closed-loop gain of the circuit with the voltage negative feedback loop. The phase compensation network formed by the fifth capacitor (C5) and the third resistor (R3) ensures that the voltage negative feedback loop has sufficient phase margin under all gain settings, preventing self-oscillation. Adjust the voltage of FB1 to bring the circuit gain to the target range, and complete the initial gain setting after the output signal stabilizes. During this stage, the enable control signal (En) remains high, the enable transistor (Q20) is turned on, and the weighted resistor array is bypassed.

[0045] S4. Stable operation in fixed gain mode. After the circuit stabilizes, the preset gain adjustment signal (FB1) remains at a fixed value and no longer changes. At this time, the circuit operates in fixed gain mode, and the gain value is jointly determined by the FB1 voltage, the operational amplifier (U13) parameters, the second resistor (R2), the sixth resistor (R6), the seventh resistor (R7), and the optocoupler (U4) parameters. Since the enable transistor (Q20) is turned on, the marker point A is directly clamped to near ground potential, and the weighted resistor array and all six switching transistors are bypassed. Their parasitic parameters are completely isolated from the voltage negative feedback loop, and the circuit has the characteristics of low noise and high signal integrity.

[0046] S5. Adjustable Gain Mode Gain Adjustment. When the system needs to change the gain, the enable control signal (En) is first switched from high to low, the enable transistor (Q20) is turned off, and the clamping of marker point A is released. Then, the first control signal (s1) to the sixth control signal (s6) output a 6-bit binary code corresponding to the target gain. When a control signal is high, the corresponding switch is turned on, connecting the corresponding weight resistor in parallel between marker point A and ground; when the control signal is low, the corresponding switch is turned off, and the corresponding weight resistor is disconnected. The equivalent load impedance from marker point A to ground changes with the binary code, changing the negative feedback depth to the inverting input through the second resistor (R2), thereby adjusting the closed-loop gain of the circuit. There are 64 combinations of 6-bit binary codes, corresponding to 64 gain levels.

[0047] S6. Restore Fixed Gain Mode. When gain adjustment is not required, the enable control signal (En) is switched from low to high, turning on the enable transistor (Q20). Marker point A is again directly grounded through the low on-resistance of the enable transistor (Q20), and the weighting resistor array is bypassed. At this time, regardless of the encoding output by control signals s1-s6, the circuit gain will not be affected, and the circuit reverts to the fixed gain mode determined by FB1. During mode switching, only the enable transistor (Q20) operates, and the states of the six switching transistors remain unchanged, preventing glitches caused by simultaneous switching of multiple transistors.

[0048] The differences between this invention and the prior art, and the resulting technical effects, are as follows: An NMOS weighted resistor array is connected to the feedback sampling point (A) of the voltage negative feedback loop, adjusting the gain by changing the equivalent load of the feedback sampling point. This invention innovatively connects the weighted resistor array between the feedback sampling point (A) and ground in the voltage negative feedback loop. By changing the equivalent load impedance at point A, the negative feedback depth fed back to the inverting input through the second resistor (R2) is altered, thereby indirectly adjusting the gain. This design ensures that the switching transistors (Q13-Q18) are not directly in the AC signal path. One end of the weighted resistors (R13-R18) is connected to the feedback sampling point (A), and the other end is grounded through the NMOS transistor. The switching action only changes the DC / AC load at point A, without directly cutting off or connecting the AC signal, fundamentally avoiding problems such as switching distortion, charge injection, and clock feedthrough. Existing technologies typically equate operational amplifier gain adjustment with switching the feedback resistor or input resistor. This invention breaks this conventional thinking, utilizing the inherent relationship between the load of the feedback sampling point and the negative feedback depth in the negative feedback loop, achieving gain adjustment by adjusting the load of the sampling point—a non-obvious innovation.

[0049] The invention employs a clamping bypass architecture where the source of the enable transistor (Q20) is directly connected to the feedback sampling point (A) and the drain is grounded. Existing binary weighted resistor network gain adjustment schemes always connect the resistor network to the circuit, making it impossible to completely disconnect even when adjustment is not needed, or requiring switches on each branch to disconnect them individually. This invention uses only one enable transistor (Q20), directly connecting its source between the feedback sampling point (A) and ground (drain grounded). By turning on the enable transistor, point A is directly pulled to ground potential, thus completely bypassing the entire weighted resistor array. It is particularly noteworthy that no resistor is connected in series between the source of the enable transistor (Q20) and the feedback sampling point (A), which contrasts sharply with the connection method where the sources of the first to sixth switches (Q18) in the weighted array are all connected in series with weighted resistors. The direct connection of the enable transistor (Q20) ensures that when it is turned on, the impedance from the feedback sampling point (A) to ground is only the on-resistance of the NMOS transistor itself (on the order of milliohms), resulting in a thorough clamping effect and complete bypassing of the weight array. The unexpected benefits of this design are: the parasitic parameters of the weight resistor array are completely isolated in fixed-gain mode, significantly reducing circuit noise and greatly improving signal integrity; and the bypassing of the entire array is achieved with only one transistor, resulting in a simple circuit and superior bypassing performance compared to individual branch switching methods. Existing technologies typically require multiple transistors or complex switching matrices to bypass a resistor network, but this invention utilizes the common node characteristics of the feedback sampling points, achieving full array bypassing simply by directly grounding the source of a single transistor—a concise and ingenious design.

[0050] The optocoupler (U4) serves a dual role as both a photoelectric conversion device and a voltage negative feedback path. In existing technologies, optocouplers typically function only as photoelectric conversion output devices, with their output terminals not participating in the amplification loop feedback. This invention connects the optocoupler (U4) in series between the output of the operational amplifier (U13) and the feedback sampling point (A). The light-emitting diode (LED) of the optocoupler acts both as a photoelectric conversion element, converting the electrical signal into optical output, and as part of the voltage negative feedback path, with its voltage drop participating in the feedback loop. In this invention, the nonlinearity and temperature drift of the optocoupler are contained within the voltage negative feedback loop. The negative feedback characteristics of the loop can compensate for the nonlinearity of the optocoupler to a certain extent, improving the linearity and stability of the optical output. Simultaneously, it eliminates the need for additional feedback path components, simplifying the circuit structure.

[0051] This invention presents a two-stage adjustment architecture: pre-adjustment using a preset gain adjustment signal (FB1) and fine-tuning using an NMOS weight array. In existing technologies, gain adjustment is typically accomplished by a single mechanism. This invention uses FB1 as the first-stage coarse adjustment and the weight array as the second-stage fine adjustment, with both stages working in tandem. In this configuration, using a 6-bit weight array, both a wide gain range and fine adjustment steps are achieved, while simultaneously controlling circuit size and parasitic parameters.

[0052] In summary, this invention solves the long-standing technical problems in the prior art, such as switching glitches, parasitic parameter interference, and contradictions between regulation accuracy and range, through innovative designs such as load regulation at the feedback sampling point of the voltage negative feedback loop, single-tube clamping bypass with direct connection of the enable tube source, optocoupler multiplexing, and two-stage regulation architecture.

[0053] The circuit of this invention can be widely applied in the following scenarios: In high-frequency oscilloscopes, as a front-end variable gain amplifier, the fixed gain mode provides low-noise, high-fidelity amplification for the most sensitive range, while the adjustable gain mode achieves precise range matching for other ranges; In high-speed signal acquisition, the fixed gain mode is used for high-sensitivity acquisition of weak signals, while the adjustable gain mode is used for automatic range switching of signals with a large dynamic range, and the self-calibration reference function ensures measurement accuracy; In waveform output applications, 64 levels of gain adjustment enable fine control of the output waveform amplitude, and the indirect gain adjustment method ensures consistent waveform shape at different gain levels; In shaping trigger circuits, the low-noise fixed gain mode amplifies weak trigger signals, improving trigger sensitivity and stability; In fiber optic communication systems, as an optical driver, the DC reference voltage sets the optocoupler bias current, the high-frequency paired signal is the data signal, and the gain adjustment function adapts to the loss compensation requirements of optical fibers of different lengths.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-frequency signal gain adjustable optical driving circuit, characterized in that, include: Baseband input module, input module, feedback module, operational amplifier module, gain adjustment module, enable module, and optoelectronic output module; The baseband input module is used to input a DC reference voltage to set the DC operating point of the non-inverting input terminal of the operational amplifier module; the input module is used to input high-frequency paired signals; the feedback module is used to input a preset gain adjustment signal and form a voltage negative feedback loop with phase compensation; the operational amplifier module is used to amplify the input signal; the gain adjustment module includes a switchable NMOS weighted resistor array connected to the feedback sampling point of the voltage negative feedback loop, used to change the equivalent load of the feedback loop in adjustable gain mode to adjust the circuit gain; The enabling module is used to switch between a fixed gain mode and an adjustable gain mode. When the enabling module is in the first state, the gain adjustment module is bypassed, and the circuit gain is determined by the preset gain adjustment signal of the feedback module. When the enabling module is in the second state, the gain adjustment module is connected to the feedback loop, and the gain is adjusted by changing the equivalent load of the feedback sampling point through a digital control signal. The photoelectric output module is used to convert the amplified high-frequency electrical signal into an optical signal for output.

2. The high-frequency signal gain adjustable optical driving circuit according to claim 1, characterized in that, The operational amplifier module includes an operational amplifier (U13); the non-inverting input terminal of the operational amplifier (U13) is connected to the baseband input module and the input module, and the inverting input terminal of the operational amplifier (U13) is connected to the feedback sampling point (A) through a second resistor (R2). The positive power supply pin of the operational amplifier (U13) is connected to +5V, the negative power supply pin is connected to -5V, and the heat sink pin is grounded; the feedback sampling point (A) is the common potential point of the voltage negative feedback loop.

3. The high-frequency signal gain adjustable optical driving circuit according to claim 2, characterized in that, The baseband input module includes a DC reference voltage input terminal (Vb) and a first resistor (R1). The DC reference voltage input terminal (Vb) is connected to the non-inverting input terminal of the operational amplifier (U13) through the first resistor (R1). The input module includes a first high-frequency input terminal (HF+), a second high-frequency input terminal (HF-), an input signal terminal (V-in), and a first capacitor (C1). The first high-frequency input terminal (HF+) is connected to the inverting input terminal of the operational amplifier (U13), the second high-frequency input terminal (HF-) is directly connected to the non-inverting input terminal of the operational amplifier (U13), and the input signal terminal (V-in) is connected to the non-inverting input terminal of the operational amplifier (U13) through the first capacitor (C1). The non-inverting input terminal of the operational amplifier (U13) is also grounded through a fifth resistor (R5).

4. The high-frequency signal gain adjustable optical driving circuit according to claim 2, characterized in that, The feedback module includes a preset gain adjustment signal terminal (FB1), a third resistor (R3), and a fifth capacitor (C5); the non-inverting input terminal of the operational amplifier (U13) is connected to the preset gain adjustment signal terminal (FB1) after being connected in series with the fifth capacitor (C5) and the third resistor (R3), and the fifth capacitor (C5) and the third resistor (R3) form a phase compensation network.

5. The high-frequency signal gain adjustable optical driving circuit according to claim 1, characterized in that, The gain adjustment module includes a first switch (Q13), a second switch (Q14), a third switch (Q15), a fourth switch (Q16), a fifth switch (Q17), a sixth switch (Q18), and a thirteenth resistor (R13), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), and an eighteenth resistor (R18). The first switch (Q13) through the sixth switch (Q18) are all NMOS transistors, with the drain of each NMOS transistor grounded, and the gate of each NMOS transistor receiving the first control signal (s1) through the sixth control signal (s6). One end of the thirteenth resistor (R13) is connected to the feedback sampling point (A), and the other end is connected to the... The source of the first switching transistor (Q13) is connected to the first switching transistor (Q13); one end of the fourteenth resistor (R14) is connected to the feedback sampling point (A), and the other end is connected to the source of the second switching transistor (Q14); one end of the fifteenth resistor (R15) is connected to the feedback sampling point (A), and the other end is connected to the source of the third switching transistor (Q15); one end of the sixteenth resistor (R16) is connected to the feedback sampling point (A), and the other end is connected to the source of the fourth switching transistor (Q16); one end of the seventeenth resistor (R17) is connected to the feedback sampling point (A), and the other end is connected to the source of the fifth switching transistor (Q17); one end of the eighteenth resistor (R18) is connected to the feedback sampling point (A), and the other end is connected to the source of the sixth switching transistor (Q18).

6. The high-frequency signal gain adjustable optical driving circuit according to claim 5, characterized in that, The thirteenth resistor (R13) has a resistance of 3.4kΩ, the fourteenth resistor (R14) has a resistance of 1.7kΩ, the fifteenth resistor (R15) has a resistance of 850Ω, the sixteenth resistor (R16) has a resistance of 425Ω, the seventeenth resistor (R17) has a resistance of 212.5Ω, and the eighteenth resistor (R18) has a resistance of 106.25Ω. The resistance values ​​of the six weighted resistors are set in a binary decreasing ratio relationship.

7. The high-frequency signal gain adjustable optical driving circuit according to claim 2, characterized in that, The enabling module includes an enabling transistor (Q20), which is an NMOS transistor. The drain of the enabling transistor (Q20) is grounded, and the gate of the enabling transistor (Q20) receives an enabling control signal (En). The source of the enabling transistor (Q20) is directly connected to the feedback sampling point (A) without any series resistor. The optoelectronic output module includes an optocoupler (U4) and a fourth resistor (R4). The output terminal of the operational amplifier (U13) outputs a high-frequency output signal (HF1+) through the fourth resistor (R4). The high-frequency output signal (HF1+) passes through the anode and cathode of the optocoupler (U4) in sequence and is then connected to the feedback sampling point (A). The feedback sampling point (A) is also grounded through a sixth resistor (R6) and a seventh resistor (R7) connected in parallel. The resistance values ​​of the sixth resistor (R6) and the seventh resistor (R7) are both 68Ω.

8. A method for controlling a high-frequency signal gain adjustable optical driving circuit, characterized in that, The optical driving circuit with adjustable high-frequency signal gain as described in claim 1 includes an operational amplifier (U13), an optocoupler (U4), a first switch (Q13) to a sixth switch (Q18), an enable transistor (Q20), and a feedback sampling point (A); the control method includes the following steps: S1. Input a DC reference voltage (Vb) and set the DC operating point of the non-inverting input terminal of the operational amplifier (U13) through the first resistor (R1); S2. Input high-frequency paired signals. The first high-frequency input terminal (HF+) is connected to the inverting input terminal of the operational amplifier (U13), and the second high-frequency input terminal (HF-) is connected to the non-inverting input terminal of the operational amplifier (U13). At the same time, the input signal terminal (V-in) is connected to the non-inverting input terminal of the operational amplifier (U13) through the first capacitor (C1). S3. Input a preset gain adjustment signal (FB1). The non-inverting input terminal of the operational amplifier (U13) is connected to the preset gain adjustment signal (FB1) via the fifth capacitor (C5) and the third resistor (R3) to perform initial gain adjustment and stabilize the voltage negative feedback loop. S4. After the circuit is working stably, the preset gain adjustment signal (FB1) remains at a fixed value and no longer changes. S5. When gain adjustment is required, the enable control signal (En) turns off the enable transistor (Q20), and at the same time, the first control signal (s1) to the sixth control signal (s6) output the corresponding digital signal, so that the corresponding transistors among the first switch transistors (Q13) to the sixth switch transistors (Q18) are turned on, and the corresponding weight resistors among the thirteenth resistors (R13) to the eighteenth resistors (R18) are connected to the feedback sampling point (A), changing the equivalent load of the voltage negative feedback loop and realizing 64-level gain adjustment; S6. When gain adjustment is not required, the enable control signal (En) turns on the enable transistor (Q20), the feedback sampling point (A) is directly grounded through the low-impedance path of the enable transistor (Q20), the weight resistor array is bypassed, and the gain is determined by the preset gain adjustment signal (FB1), operating in fixed gain mode. The high-frequency signal output by the operational amplifier (U13) is converted into an optical signal output through the fourth resistor (R4) and the optocoupler (U4).

9. The control method according to claim 8, characterized in that, In step S5, the binary encoding range of the first control signal (s1) to the sixth control signal (s6) is 000000 to 111111, corresponding to a total of 64 gain levels; the resistance values ​​of the thirteenth resistor (R13) to the eighteenth resistor (R18) are set according to a binary decreasing ratio, and each binary encoding level corresponds to a unique equivalent load impedance value from the feedback sampling point (A) to ground, thereby corresponding to a unique negative feedback depth and circuit gain value.

10. The control method according to claim 8, characterized in that, When switching between fixed gain mode and adjustable gain mode, the mode switching is completed only by turning on and off the enable transistor (Q20). The first switch transistor (Q13) to the sixth switch transistor (Q18) do not perform switching actions during the mode switching process, so as to avoid signal glitches and intermediate transition states caused by multiple switch transistors switching at the same time.

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