An integrated power amplifier, a radio frequency front-end module and a communication device

Abstract

The application discloses an integrated power amplifier, a radio frequency front end module and a communication device, which comprise an input matching network, a power amplifier transistor, an output matching network connected in sequence, and a gate bias network and a drain bias network for providing bias voltage for the power amplifier transistor respectively; the output end of the input matching network is connected with the gate of the power amplifier transistor, and the drain of the power amplifier transistor is connected with the input end of the output matching network; the output matching network comprises a harmonic control network and a filter matching integrated network connected in cascade; the harmonic control network is used for controlling the second harmonic out of the passband; and the filter matching integrated network is configured as an improved double-path parallel structure based on a fourth-order band-pass filter, and is used for realizing wideband impedance matching and harmonic suppression by generating a transmission zero point.

Description

Technical Field

[0001] This invention relates to an integrated power amplifier, a radio frequency front-end module, and a communication device, belonging to the field of radio frequency communication technology. Background Technology

[0002] With the rapid development of 5G mobile communication and next-generation wireless communication technologies, RF front-end systems place increasingly stringent demands on the output efficiency, linearity, and integration of power amplifiers. In power amplifier design, the output matching network not only needs to transform the optimal load impedance of the transistors to the standard 50-ohm system impedance, but also must precisely control the second and third harmonics to achieve high-efficiency switching or continuous operation modes. Currently, mainstream designs typically employ a discrete cascaded architecture, cascading independent filter structures or harmonic trap circuits on top of the fundamental matching circuit. However, this approach, which separates the matching and filtering functions into different physical structures, results in an excessively large overall physical size of the RF link, a significant increase in insertion loss, and is highly detrimental to the high integration of active integrated antennas or front-end modules for high-frequency bands. Simultaneously, traditional low-pass filter topologies typically have a narrow transition band. When cascaded after the matching network, they often introduce additional parasitic reactance, causing a shift in the fundamental matching point, limiting the power amplifier's operating bandwidth, and drastically degrading its efficiency in the power back-off region. Furthermore, existing design methods typically treat the matching network and harmonic control as two independent design variables. Constrained by the physical length of traditional microstrip lines, designers find it difficult to precisely control the harmonic impedance within a specific region of the Smith chart while ensuring optimal fundamental matching, making it difficult to achieve the theoretical efficiency limit of the power amplifier. It is worth noting that although filter structures such as stepped impedance resonators or multimode resonators have been widely used in various RF filters to achieve compact size and good frequency selectivity, current technologies have not yet attempted to deeply integrate their unique multimode resonant characteristics with the output matching and harmonic control requirements of power amplifiers. Those skilled in the art typically only focus on their performance in small-signal filtering scenarios, neglecting the fact that under large-signal excitation, through specific impedance transformation ratio design, this structure can simultaneously achieve lossless transmission of fundamental energy and efficient recovery of harmonic energy. Therefore, a novel impedance matching network structure is urgently needed to break the traditional separation of matching and filtering, using a single physical structure to simultaneously achieve fundamental matching and multi-order harmonic control, thereby significantly improving the overall performance of the power amplifier while reducing circuit size. Summary of the Invention

[0003] The technical problem to be solved by this invention is that, in view of the fact that the output matching network and harmonic suppression circuit of existing power amplifiers usually adopt a discrete cascaded structure, resulting in a large circuit size, high insertion loss and difficulty in achieving harmonic control in the broadband range, the invention provides an integrated power amplifier, RF front-end module and communication device, which achieves deep integration of fundamental frequency matching and harmonic control by using the multimode resonance characteristics of multiplexed filters.

[0004] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution:

[0005] A first aspect: An integrated power amplifier, comprising an input matching network, a power amplifying transistor, and an output matching network connected in sequence, and a gate bias network and a drain bias network providing bias voltages to the power amplifying transistor respectively; the output terminal of the input matching network is connected to the gate of the power amplifying transistor, and the drain of the power amplifying transistor is connected to the input terminal of the output matching network;

[0006] The output matching network includes a cascaded harmonic control network and an integrated filter matching network; the harmonic control network is used to control the second harmonic outside the passband.

[0007] The integrated filtering and matching network is configured as a dual-path parallel structure based on an improved fourth-order bandpass filter, which is used to achieve harmonic suppression by generating transmission zeros while realizing broadband impedance matching.

[0008] Optionally, the integrated filtering and matching network includes a first signal transmission path and a second signal transmission path connected in parallel;

[0009] The first signal transmission path includes microstrip line 31, microstrip line 32 and microstrip line 33 cascaded in sequence. The input end of microstrip line 31 serves as the input end of the first signal transmission path, and the output end of microstrip line 33 serves as the output end of the first signal transmission path. The overall transfer matrix of the first signal transmission path is the product of the matrices of each cascaded microstrip line and is converted into an admittance parameter matrix.

[0010] The second signal transmission path includes a series compensation line and a short-circuit cross-coupled microstrip line 1 in the middle. The series compensation line includes microstrip line 30 and microstrip line 34. The input end of microstrip line 30 serves as the input end of the second signal transmission path and is connected to microstrip line 29. The output end of microstrip line 29 is connected to microstrip line 31 and microstrip line 30. The output end of microstrip line 34 serves as the output end of the second signal transmission path. The output end of microstrip line 30 is connected to one end of the short-circuit cross-coupled microstrip line 1. The other end of the short-circuit cross-coupled microstrip line 1 is connected to the input end of microstrip line 34. Microstrip line 34 and microstrip line 33 are connected to microstrip line 35.

[0011] The integrated filtering and matching network compensates for the parasitic parameters of the junction by adjusting the physical lengths of microstrip line 30 and microstrip line 34, and makes the amplitudes of the two paths equal and the phases opposite at a specific frequency, resulting in completely destructive interference and thus generating a transmission zero.

[0012] Optionally, the input impedance Z of the integrated filtering and matching network A The following relationship must be satisfied:

[0013] (1);

[0014] in, and These are the characteristic impedance and electrical length of microstrip line 18, respectively. The input impedance of the impedance-matched filter integrated network. Let j be the admittance at point A, and j be an imaginary number satisfying j 2 =-1.

[0015] Optionally, the design steps of the integrated filtering and matching network include:

[0016] Suppose that the integrated filtering and matching network is composed of path 1 and path 2 connected in parallel. Path 1 is composed of microstrip line 31, microstrip line 32 and microstrip line 33 cascaded together. Path 2 is composed of a series compensation line and a short-circuited cross-coupled microstrip line 1 in the middle. The series compensation line includes microstrip line 30 and microstrip line 34.

[0017] Let the characteristic impedance of the i-th microstrip line be Z. i Admittance is ,and The electrical lengths of microstrip lines 31, 32, and 33 along the uplink path are: Then the overall transition matrix of this path The product of the matrices of each series of microstrip lines:

[0018] (2);

[0019] According to the two-port network theory, using formulas (2) to (4), the transfer matrix is ​​transformed into an admittance parameter matrix to obtain the positive transfer admittance of path 1. With port admittance Represented as:

[0020] (3);

[0021] (4);

[0022] (5);

[0023] = (6);

[0024] Assume the odd and even mode eigenadmittances of coupling line one are respectively The electrical length of the coupling line in the downlink path is Due to the cross-grounding of the ports, the equivalent intrinsic admittance matrix is... The formula is, where , Each is a matrix The elements in the formula are shown in equation (9):

[0025] (7);

[0026] (8);

[0027] = (9);

[0028] Will Transform into a transition matrix Simultaneously, it is cascaded with the compensation microstrip lines 30 and 34 on both sides to obtain the overall transfer matrix of path 2. ;

[0029]

[0030] (10);

[0031] The global admittance matrix of path 2 is obtained from equations (3), (4), and (5) above.

[0032] (11)

[0033] Therefore, the positive transfer admittance of path 2 is obtained as follows:

[0034] (12);

[0035] According to formulas (10) and (11), the admittance matrices of path 1 and path 2 are added together to obtain the total system admittance matrix, and the total forward transfer admittance matrix is ​​obtained. The sum of the admittance matrices of the two paths:

[0036] (13);

[0037] Therefore, the total forward transfer admittance It is a linear superposition of the transfer admittances of two parallel branches:

[0038] (14);

[0039] The change in electrical length represents the ratio between the center frequency and a specific frequency. By adjusting the physical lengths of the fourth microstrip line (30) and the fifth microstrip line (34), the ratio at a specific frequency can be achieved. At that point, that is, the electric length is transformed into When the filtering equation (13) is satisfied: This generates transmission zeros, enabling highly selective out-of-band filtering;

[0040] (15);

[0041] Combining equation (13), we can obtain the filtering equation:

[0042] (16);

[0043] Based on this filtering, the network is obtained through formula (13):

[0044] (17);

[0045] Set the equivalent load admittance to 1 / 50. According to formulas (16) and (17), solve the simultaneous admittance equations to make the network input impedance satisfy formula (18) at the center frequency:

[0046] (18);

[0047] Taking advantage of the fact that the degrees of freedom provided by paths 1 and 2 are greater than the constraints, the integrated design of matched filters is completed by independently adjusting the parameters of each microstrip line and introducing auxiliary tuning microstrip lines 29 and 35 for orthogonal tuning.

[0048] Optionally, the harmonic control network includes microstrip line 17, microstrip line 18, and microstrip line 28; one end of microstrip line 17 is connected to the drain of the power amplifier transistor, and the other end is connected to microstrip line 18, microstrip line 28, and the integrated filter matching network, respectively, and the other end of microstrip line 17 remains open; microstrip line 18 is used to suppress the selected second harmonic frequency.

[0049] Optionally, the gate bias network includes a gate resistor, decoupling capacitor one, decoupling capacitor two, decoupling capacitor three, and microstrip line five, microstrip line six, microstrip line seven, microstrip line eight, microstrip line nine, microstrip line ten, microstrip line eleven, microstrip line twelve, microstrip line thirteen, and microstrip line fourteen.

[0050] One end of microstrip line 5 is connected to the input matching network, and the other end of microstrip line 5 is connected to the gate resistor. The other end of the gate resistor is connected to microstrip line 6, and the other end of microstrip line 6 is connected to microstrip lines 8 and 9. The other end of microstrip line 8 is connected to decoupling capacitor 1, and the other end of decoupling capacitor 1 is connected to microstrip line 7. The other end of microstrip line 7 is grounded. The other end of microstrip line 9 is connected to microstrip lines 11, 12, and 14. The other end of microstrip line 11 is connected to decoupling capacitor 2, and the other end of decoupling capacitor 2 is connected to microstrip line 10. The other end of microstrip line 10 is grounded. The other end of microstrip line 12 is connected to decoupling capacitor 3, and decoupling capacitor 3 is connected to microstrip line 13. The other end of microstrip line 13 is grounded. The other end of microstrip line 14 is connected to the gate bias voltage.

[0051] Optionally, the drain bias network comprises microstrip line 19, microstrip line 20, microstrip line 21, microstrip line 22, microstrip line 23, microstrip line 24, microstrip line 25, microstrip line 26, and microstrip line 27, along with decoupling capacitors 4, 5, and 6. One end of microstrip line 19 is connected to the output matching network, and the other end of microstrip line 19 is connected to microstrip lines 20 and 22. The other end of microstrip line 20 is connected to decoupling capacitor 6, and the other end of decoupling capacitor 1 is connected to the microstrip line... Microstrip line 21 is connected to the ground at the other end; the other end of microstrip line 22 is connected to microstrip lines 24, 25, and 27; the other end of microstrip line 24 is connected to decoupling capacitor 4; the other end of decoupling capacitor 4 is connected to microstrip line 23; the other end of microstrip line 23 is grounded; the other end of microstrip line 25 is connected to decoupling capacitor 5; decoupling capacitor 5 is connected to microstrip line 26; the other end of microstrip line 26 is grounded; the other end of microstrip line 27 is connected to the drain bias voltage.

[0052] Optionally, the power amplifier transistor is a GaN HEMT CGH40010F transistor.

[0053] Second aspect: A radio frequency front-end module including the integrated power amplifier described in the second aspect.

[0054] Third aspect: A communication device comprising the radio frequency front-end module described in the first aspect.

[0055] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0056] This invention further reduces the overall area of ​​the power amplifier by integrating harmonic control and matched filtering into a single network. It also cross-integrates the harmonic network, matching network, and filter, introducing an integrated harmonic control and matched filtering network. The invention exhibits excellent performance indicators, with an operating bandwidth of 1.7-3.9 GHz, drain efficiency of 59-75%, saturated output power greater than 40 dBm, and gain of 11-13.9 dBm, while simultaneously reducing the power amplifier area. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of the topology of the integrated power amplifier in this invention;

[0059] Figure 2 This is a schematic diagram of the gate bias and input matching network topology in this invention;

[0060] Figure 3 This is a schematic diagram of the drain bias and output matching network topology in this invention;

[0061] Figure 4 This is a schematic diagram of harmonic control impedance calculation in this invention;

[0062] Figure 5 This is the impedance design space in an embodiment of the present invention;

[0063] Figure 6 The output power, drain efficiency, and gain simulation results are shown in the figure for an embodiment of the present invention. Detailed Implementation

[0064] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0065] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0066] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0067] Example 1

[0068] See Figure 1 An integrated power amplifier is disclosed, comprising a gate bias network 10, an input matching network 20, a power amplifier transistor 30, a drain bias network 40, and an output matching network 50. The gate bias network provides the gate bias voltage required by the power amplifier transistor 30. Similarly, the drain bias network 40 provides the drain bias voltage required by the power amplifier transistor 30. The input matching network 20 includes a microstrip line, a DC blocking capacitor, and an RC parallel bias network. The output matching network 50 is composed of a harmonic network 51, a harmonic control network, and an integrated impedance matching filter network 52. The harmonic network 51 and the integrated harmonic control and impedance matching filter network 52 simultaneously control two second harmonics outside the passband. The integrated harmonic control and impedance matching filter network 52 is an improvement on a fourth-order bandpass filter, capable of performing impedance matching while providing filtering, further reducing the area occupied by the output matching network.

[0069] See Figure 2The diagram shows the topology of the gate bias network 10 and the input matching network 20 in this invention. The gate bias network 10 includes microstrip line TL5, microstrip line TL6, microstrip line TL7, microstrip line TL9, microstrip line TL10, microstrip line TL11, microstrip line TL12, microstrip line TL13, microstrip line TL14, and decoupling capacitors BYPASS1, BYPASS2, and BYPASS3, as well as a gate resistor R1. One end of microstrip line TL5 is connected to the input impedance matching network, and the other end of microstrip line TL5 is connected to the gate resistor R1. The other end of the gate resistor R1 is connected to microstrip line TL6, and the other end of microstrip line TL6 is connected to microstrip lines TL8 and TL9. The other end of microstrip line TL8 is connected to decoupling capacitor BYPASS1, and the other end of decoupling capacitor BYPASS1 is connected to microstrip line TL7. The other end of microstrip line TL7 is grounded. The other end of microstrip line TL9 is connected to microstrip lines TL11, TL12, and TL14. The other end of microstrip line TL11 is connected to decoupling capacitor BYPASS2, and the other end of decoupling capacitor BYPASS2 is connected to microstrip line TL10. The other end of microstrip line TL10 is grounded. The other end of microstrip line TL12 is connected to decoupling capacitor BYPASS3, which is connected to microstrip line TL13. The other end of microstrip line TL13 is grounded. The other end of microstrip line TL14 is connected to the gate bias voltage.

[0070] The input signal enters the gate of the power amplifier transistor 30 through the input matching network 20. The 50-ohm input impedance at the input port is matched to the optimal source impedance of the power amplifier transistor 30 through the input impedance matching network 20. The left end of microstrip line TL1 is the signal input terminal, and the other end is connected to the DC blocking capacitor C1. The other end of the DC blocking capacitor C1 is connected to microstrip line TL2. The other end of microstrip line TL2 is connected to microstrip line TL3. The other end of microstrip line TL3 is connected to microstrip line TL4. The other end of microstrip line TL4 is connected to microstrip line TL15. Microstrip line TL15 is connected to one end of a parallel RC network. The other end of the parallel RC network is connected to microstrip line TL16. The other end of microstrip line TL16 is connected to the gate of the power amplifier transistor. The input signal enters the gate of the power amplifier transistor through the above-mentioned input impedance matching network and is matched to the optimal source impedance, further improving the overall circuit performance.

[0071] See Figure 3The diagram shows the topology of the drain bias network 40 and the output matching network 50 in this invention. The drain bias network includes microstrip line 19 TL19, microstrip line 20 TL20, microstrip line 21 TL21, microstrip line 22 TL22, microstrip line 23 TL23, microstrip line 24 TL24, microstrip line 25 TL25, microstrip line 26 TL26, and microstrip line 27 TL27, along with decoupling capacitors 4, 5, and 6. One end of microstrip line 19 TL19 is connected to the output impedance matching network, and the other end is connected to microstrip lines 20 TL20 and 22 TL22. The other end of microstrip line 20 TL20 is connected to decoupling capacitor 6, and the other end of decoupling capacitor 1 is connected to microstrip line 21 TL21. The other end of microstrip line 21 TL21 is grounded. The other end of microstrip line TL22 is connected to microstrip lines TL24, TL25, and TL27. The other end of microstrip line TL24 is connected to decoupling capacitor BYPASS4, which in turn is connected to microstrip line TL23. The other end of microstrip line TL23 is grounded. The other end of microstrip line TL25 is connected to BYPASS5, and decoupling capacitor BYPASS5 is connected to microstrip line TL26. The other end of microstrip line TL26 is grounded. The other end of microstrip line TL27 is connected to the drain bias voltage.

[0072] The harmonic control network 51 comprises microstrip line 17 TL17, microstrip line 18 TL18, and microstrip line 28 TL28. One end of microstrip line 17 TL17 serves as the input terminal of the output impedance matching network and is connected to the drain of the power amplifier transistor. The other end is connected to one end of microstrip line 17 TL17 and microstrip line 28 TL28. The other end of microstrip line 17 TL17 remains open, thereby controlling the second harmonic.

[0073] The integrated harmonic control and filtering matching network 52 comprises microstrip line 28 TL28, microstrip line 29 TL29, microstrip line 30 TL30, microstrip line 31 TL31, microstrip line 32 TL32, microstrip line 33 TL33, microstrip line 34 TL34, microstrip line 35 TL35, and coupling microstrip line 1 CL1. This integrated harmonic control and filtering matching network, while providing filtering, also achieves a certain matching effect, further reducing the overall power amplifier area. Simultaneously, the short-circuit coupling microstrip line 1 CL1 transmits the second harmonic short-circuiting effect through microstrip line 30 TL30, microstrip line 29 TL29, and DC blocking capacitor, and microstrip line 28 TL28 to the connection point between microstrip line 17 TL17 and microstrip line 28 TL28, simultaneously serving as a second harmonic short-circuit at microstrip line 18 TL18. For radio frequency signals, the DC blocking capacitor is approximately a short circuit. Therefore, in order to ensure that the second harmonic short-circuit signal of the coupled microstrip line is better conducted to the connection between microstrip line 17 TL17 and microstrip line 28 TL28, we set the total electrical length of microstrip line 28 TL28 and microstrip line 29 TL29 at half the wavelength of the fundamental wave.

[0074] See Figure 4 The diagram shows a schematic of the output matching network 50 in this invention, which consists of a harmonic control network 51, a harmonic control network, and an integrated impedance matching filter network 52. The harmonic control network 51 includes microstrip line 17 TL17, microstrip line 18 TL18, and microstrip line 28 TL28. One end of microstrip line 17 TL17 serves as the input terminal of the output impedance matching network and is connected to the drain of the power amplifier transistor. The other end is connected to one end of microstrip line 17 TL17 and microstrip line 28 TL28. The other end of microstrip line 17 TL17 remains open, thereby controlling the second harmonic. The electrical length of microstrip line 18 TL18 is... The microstrip line TL18 will suppress the selected second harmonic. The input impedance of the impedance-matched filter integrated network 52 is Zfilter, and point A is the connection point of the harmonic control network (see [link]). Figure 4 The input impedance Z of the output matching network can be calculated. A for:

[0075] (1)

[0076] in, and These are the characteristic impedance and electrical length of microstrip line 18 (TL18), respectively. This is the input impedance of the impedance matching filter integrated network 52.

[0077] The design steps of the impedance matching filter integrated network 52 are as follows: First, the filter structure consists of microstrip line TL30, microstrip line TL31, microstrip line TL32, microstrip line TL33, microstrip line TL34, and coupling microstrip line CTL1. To further adjust the influence of the parasitic parameters of the T-junction, microstrip lines TL30 and TL34 are added to adjust the zero point and the parasitic parameters generated by the T-junction. Path 1 is formed by cascading microstrip lines TL31, TL32, and TL33. Assume the characteristic impedance of the i-th microstrip line is Z. i The electric length is Then the overall transition matrix of this path. The product of the matrices of each series of microstrip lines:

[0078] (2)

[0079] Based on two-port network theory, the ABCD matrix is ​​transformed into an admittance parameter matrix, and the forward transfer admittance is then used. With port admittance It can be represented as: (3); (4); (5); = (6);

[0080] Path 2 includes the series-compensated microstrip line TL30 and TL34, as well as the short-circuited cross-coupled microstrip line CTL1. Assume the odd-even mode characteristic admittances of the coupled lines are respectively... The electric length is Due to the cross-grounding of the ports, the equivalent intrinsic admittance matrix... The formula is: (7); (8); = (9);

[0081] Will Transform into a transition matrix Simultaneously, by cascading it with the compensation microstrip lines TL30 and TL34 on both sides, the overall transfer matrix of path 2 can be obtained. , (10);

[0082] From equations (3), (4), and (5) above, we obtain the overall admittance matrix for path 2: (11);

[0083] Similarly, the positive transfer admittance for path 2 is: (12);

[0084] To demonstrate that the network achieves highly selective out-of-band filtering of two-path transverse signal interferometry, for the parallel topology, the total admittance matrix is... The sum of the admittance matrices of the two paths: (13);

[0085] Therefore, the total forward transfer admittance of the system It is a linear superposition of the transfer admittances of two parallel branches: (14);

[0086] The electric lengths mentioned above are all expressed as the electric length at the center frequency. Since changes in frequency will cause changes in electric length, therefore, we introduce... The change in electrical length with frequency is represented by the following formula:

[0087]

[0088] in It is electrical length. It is the phase constant. Where c is the physical length of the transmission line and c is the speed of light. It is the effective dielectric constant (assuming it does not change drastically with frequency). Therefore, it is evident that the electric length changes with frequency. To address this, we introduce... To describe this change, we use the coefficients representing the electrical length at a specific frequency and the electrical length at the center frequency, assuming the specific frequency is f. 1, With a center frequency of f0, we have:

[0089]

[0090] The change in electric length is proportional to Center frequency electrical length Specific frequency electrical length have:

[0091]

[0092] Therefore, use The change in electrical length represents the ratio between the center frequency and a specific frequency. By adjusting the physical lengths of the fourth microstrip line 30TL30 and the fifth microstrip line 34TL34, the ratio at a specific frequency can be achieved. At that point, that is, the electric length is transformed into When the filtering equation (13) is satisfied: This generates transmission zeros, enabling highly selective out-of-band filtering;

[0093] To enable filtering functionality in this passive network, it is necessary to use it at a specific frequency. This produces an extremely deep transmission attenuation pole, i.e., the forward transmission coefficient. From the formula, we can obtain the equivalent mathematical necessary and sufficient condition as follows: .

[0094] (15);

[0095] Combining equation (13), we can obtain the filtering equation: (16);

[0096] Therefore, this structure provides an inherent phase reversal characteristic of 180° over a wide frequency band. Nonlinear reconstruction is possible by independently introducing the physical lengths of microstrip line TL30 and microstrip line TL34. The phase dispersion slope. When the two paths are at... When the amplitudes are equal and the phases are strictly opposite, a completely destructive interference will occur, resulting in a transmission null.

[0097] Based on this filtering, the network can be obtained through Equation 13: (17);

[0098] in The load equivalent admittance is equal to 1 / 50. Since the network is a passive reciprocal network, combining equations 13 and 17 yields:

[0099] (18);

[0100] This article proposes to transform a 50-ohm load to a target impedance of 30 ohms, requiring that at the center frequency... The following conditions must be met:

[0101] (19);

[0102] Right now The real part is The imaginary part is 0, requiring only two constraints, while the core network has more than two degrees of freedom. With more degrees of freedom than constraints, there are inevitably countless solutions. Therefore, the structure of this invention possesses independent impedance transformation capability. However, in practical broadband integration, concentrating all tasks in the core parallel region would severely compress the feasible solution space of the equations. This leads to the introduction of microstrip lines TL29 and TL35, whose physical significance lies in providing an orthogonal tuning effect through a simple phase rotation and real part boosting effect of the two transmission lines, anchoring the output at 50 ohms.

[0103] See Figure 5 The figure shows the simulation results of the impedance trajectory of the output current source plane of the present invention. As can be seen from the figure, the obtained output matching network matches the impedance theoretical design control.

[0104] See Figure 6 The figure shows the simulation results of the drain efficiency, output power, and gain of the broadband high-efficiency Class F power amplifier based on the integrated harmonic control and filter matching network of this invention. It can be seen that the designed power amplifier has an operating bandwidth of 1.7-3.9 GHz, a drain efficiency of 59-75.1%, a saturated output power of 40-42.5 dBm, and a gain of 11.3-14 dBm, demonstrating excellent performance.

[0105] Example 2

[0106] A radio frequency front-end module includes the integrated power amplifier described in Example 1.

[0107] Example 3

[0108] A communication device includes the radio frequency front-end module described in Embodiment 2.

[0109] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An integrated power amplifier, characterized in that, It includes an input matching network, a power amplifier transistor, an output matching network connected in sequence, and a gate bias network and a drain bias network that provide bias voltages for the power amplifier transistor, respectively. The output terminal of the input matching network is connected to the gate of the power amplifier transistor, and the drain of the power amplifier transistor is connected to the input terminal of the output matching network. The output matching network includes a cascaded harmonic control network and an integrated filtering and matching network; The harmonic control network is used to control the second harmonic outside the passband; The integrated filtering and matching network is configured as a dual-path parallel structure based on an improved fourth-order bandpass filter, which is used to achieve harmonic suppression by generating transmission zeros while realizing broadband impedance matching.

2. The integrated power amplifier according to claim 1, characterized in that, The integrated filtering and matching network includes a first signal transmission path and a second signal transmission path connected in parallel; The first signal transmission path includes microstrip line 31 (TL31), microstrip line 32 (TL32), and microstrip line 33 (TL33) cascaded in sequence. The input terminal of microstrip line 31 (TL31) serves as the input terminal of the first signal transmission path, and the output terminal of microstrip line 33 (TL33) serves as the output terminal of the first signal transmission path. The overall transfer matrix of the first signal transmission path is the product of the matrices of each cascaded microstrip line and is converted into an admittance parameter matrix. The second signal transmission path includes a series compensation line and a short-circuit cross-coupled microstrip line 1 (CTL1) in the middle. The series compensation line includes microstrip line 30 (TL30) and microstrip line 34 (TL34). The input terminal of microstrip line 30 (TL30) serves as the input terminal of the second signal transmission path and is connected to microstrip line 29 (TL29). The output terminal of microstrip line 29 (TL29) is connected to microstrip line 31 (TL31) and microstrip line 30 (TL30). The output terminal of microstrip line 34 (TL34) serves as the output terminal of the second signal transmission path. The output terminal of microstrip line 30 (TL30) is connected to one end of the short-circuit cross-coupled microstrip line 1 (CTL1). The other end of the short-circuit cross-coupled microstrip line 1 (CTL1) is connected to the input terminal of microstrip line 34 (TL34). Microstrip line 34 (TL34) and microstrip line 33 (TL33) are connected to microstrip line 35 (TL35). The integrated filtering and matching network compensates for the parasitic parameters of the T-junction by adjusting the physical lengths of microstrip line 30 (TL30) and microstrip line 34 (TL34), and makes the amplitudes of the two paths equal and the phases opposite at a specific frequency, resulting in completely destructive interference and thus generating a transmission zero.

3. The integrated power amplifier according to claim 1, characterized in that, The input impedance Z of the integrated filtering and matching network A The following relationship must be satisfied: （1）； in, and These are the characteristic impedance and electrical length of the microstrip line 18 (TL18), respectively. The input impedance of the impedance-matched filter integrated network. Let j be the admittance at point A, and j be an imaginary number satisfying j 2 =-1.

4. The integrated power amplifier according to claim 2, characterized in that, The design steps of the integrated filtering and matching network include: The integrated filtering and matching network is composed of path 1 and path 2 connected in parallel. Path 1 is composed of microstrip line 31 (TL31), microstrip line 32 (TL32), and microstrip line 33 (TL33) cascaded together. Path 2 is composed of a series compensation line and a short-circuited cross-coupled microstrip line 1 (CTL1) in the middle. The series compensation line includes microstrip line 30 (TL30) and microstrip line 34 (TL34). Let the characteristic impedance of the i-th microstrip line be Z. i Admittance is ,and The electrical lengths of microstrip lines 31 (TL31), 32 (TL32), and 33 (TL33) along the uplink path are: Then the overall transition matrix of this path The product of the matrices of each series of microstrip lines: （2）； According to the two-port network theory, using formulas (2) to (4), the transfer matrix is ​​transformed into an admittance parameter matrix to obtain the positive transfer admittance of path 1. With port admittance Represented as: （3）； （4）； （5）； = （6）； Assume the odd and even mode characteristic admittances of coupling line one (CTL1) are respectively The electrical length of coupling line 1 (CTL1) in the downlink path is Due to the cross-grounding of the ports, the equivalent intrinsic admittance matrix is... The formula is, where , Each is a matrix The elements in the formula are shown in equation (9): （7）； （8）； = （9）； Will Transform into a transition matrix Simultaneously, it is cascaded with the two side compensation microstrip lines 30 (TL30) and 34 (TL34) to obtain the overall transfer matrix of path 2. ; （10）； The global admittance matrix of path 2 is obtained from equations (3), (4), and (5) above. （11） Therefore, the positive transfer admittance of path 2 is obtained as follows: （12）； According to formulas (10) and (11), the admittance matrices of path 1 and path 2 are added together to obtain the total system admittance matrix, and the total forward transfer admittance matrix is ​​obtained. The sum of the admittance matrices of the two paths: （13）； Therefore, the total forward transfer admittance It is a linear superposition of the transfer admittances of two parallel branches: （14）； The change in electrical length represents the ratio between the center frequency and a specific frequency. By adjusting the physical lengths of the fourth microstrip line 30 (TL30) and the fifth microstrip line 34 (TL34), the ratio at a specific frequency can be achieved. At that point, that is, the electric length is transformed into When the filtering equation (13) is satisfied: This generates transmission zeros, enabling highly selective out-of-band filtering; （15）； Combining equation (13), we can obtain the filtering equation: （16）； Based on this filtering, the network is obtained through formula (13): （17）； Set the equivalent load admittance to 1 / 50. According to formulas (16) and (17), solve the simultaneous admittance equations to make the network input impedance satisfy formula (18) at the center frequency: （18）； Taking advantage of the fact that the degrees of freedom provided by path 1 and path 2 are greater than the constraints, the integrated design of matched filtering is completed by independently adjusting the parameters of each microstrip line and introducing auxiliary tuning microstrip lines 29 (TL29) and 35 (TL35) for orthogonal tuning.

5. The integrated power amplifier according to claim 1, characterized in that, The harmonic control network includes microstrip line 17 (TL17), microstrip line 18 (TL18), and microstrip line 28 (TL28). One end of microstrip line 17 (TL17) is connected to the drain of the power amplifier transistor, and the other end is connected to microstrip line 18 (TL18), microstrip line 28 (TL28), and the integrated filter matching network, respectively, and the other end of microstrip line 17 (TL17) remains open. Microstrip line 18 (TL18) is used to suppress the second harmonic frequency at a selected frequency.

6. The integrated power amplifier according to claim 1, characterized in that, The gate bias network includes a gate resistor (R1), decoupling capacitor one (BYPASS1), decoupling capacitor two (BYPASS2), decoupling capacitor three (BYPASS3), and microstrip line five (TL5), microstrip line six (TL6), microstrip line seven (TL7), microstrip line eight (TL8), microstrip line nine (TL8), microstrip line ten (TL10), microstrip line eleven (TL11), microstrip line twelve (TL12), microstrip line thirteen (TL13), and microstrip line fourteen (TL14). One end of microstrip line 5 (TL5) is connected to the input matching network, and the other end of microstrip line 5 (TL5) is connected to the gate resistor (R1). The other end of the gate resistor (R1) is connected to microstrip line 6 (TL6), and the other end of microstrip line 6 (TL6) is connected to microstrip line 8 (TL8) and microstrip line 9 (TL9). The other end of microstrip line 8 (TL8) is connected to decoupling capacitor 1 (BYPASS1), and the other end of decoupling capacitor 1 (BYPASS1) is connected to microstrip line 7 (TL7). The other end of microstrip line 7 (TL7) is grounded, and the other end of microstrip line 9 (TL9) is connected to microstrip line 11 (TL11). Microstrip line 12 (TL12) and microstrip line 14 (TL14) are connected. The other end of microstrip line 11 (TL11) is connected to decoupling capacitor 2 (BYPASS2). The other end of decoupling capacitor 2 (BYPASS2) is connected to microstrip line 10 (TL10). The other end of microstrip line 10 (TL10) is grounded. The other end of microstrip line 12 (TL12) is connected to decoupling capacitor 3 (BYPASS3). Decoupling capacitor 3 (BYPASS3) is connected to microstrip line 13 (TL13). The other end of microstrip line 13 (TL13) is grounded. The other end of microstrip line 14 (TL14) is connected to the gate bias voltage.

7. The integrated power amplifier according to claim 1, characterized in that, The drain bias network comprises microstrip line 19 (TL19), microstrip line 20 (TL20), microstrip line 21 (TL21), microstrip line 22 (TL22), microstrip line 23 (TL23), microstrip line 24 (TL24), microstrip line 25 (TL25), microstrip line 26 (TL26), and microstrip line 27 (TL27), along with decoupling capacitors 4 (BYPASS4), 5 (BYPASS5), and 6 (BYPASS6). One end of microstrip line 19 (TL19) is connected to the output matching network, and the other end of microstrip line 19 (TL19) is connected to microstrip lines 20 (TL20) and 22 (TL22). The other end of microstrip line 20 (TL20) is connected to decoupling capacitor 6 (BYPASS6), and the other end of decoupling capacitor 1 (BYPASS1) is connected to the output matching network. One end of microstrip line 21 (TL21) is connected to microstrip line 22 (TL22), and the other end of microstrip line 22 (TL22) is connected to microstrip line 24 (TL24), microstrip line 25 (TL25), and microstrip line 27 (TL27). The other end of microstrip line 24 (TL24) is connected to decoupling capacitor 4 (BYPASS4), and the other end of decoupling capacitor 4 (BYPASS4) is connected to microstrip line 23 (TL23). The other end of microstrip line 23 (TL23) is grounded. The other end of microstrip line 25 (TL25) is connected to decoupling capacitor 5 (BYPASS5), and decoupling capacitor 5 (BYPASS5) is connected to microstrip line 26 (TL26). The other end of microstrip line 26 (TL26) is grounded. The other end of microstrip line 27 (TL27) is connected to the drain bias voltage.

8. The integrated power amplifier according to claim 1, characterized in that, The power amplifier transistor is a GaN HEMT CGH40010F transistor.

9. A radio frequency front-end module, characterized in that, The integrated power amplifier includes any one of claims 1-8.

10. A communication device, characterized in that, Includes the radio frequency front-end module as described in claim 9.

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