A dark current compensation readout circuit, method and photodetection system

Abstract

The application discloses a kind of dark current compensation readout circuit, method and photoelectric detection system.The circuit includes public readout node, dark current compensation branch and transimpedance amplifier stage.Photoelectric detector is electrically connected between first and second bias voltage source with dark current compensation branch, and the electrical connection intersection point of both constitutes public readout node, which is electrically connected with the input end of transimpedance amplifier stage simultaneously.Dark current compensation branch generates compensation current opposite to the direction of dark current, and the dark current component in total current is cancelled at public readout node, to form net input current and send into transimpedance amplifier stage.The application realizes the overall design of front-end compensation of dark current in current domain first, and then completing step-by-step amplification and output shaping in voltage domain.The scheme can effectively reduce the problems of DC offset, operating point shift and dynamic range compression caused by dark current, and significantly improve the readout and resolution capability of weak light signal of the system.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detection technology, specifically relating to a dark current compensation readout circuit, method, and photoelectric detection system. Background Technology

[0002] Photoelectric detection technology, as a core means of modern information sensing and perception, is widely used in many technical fields such as ambient light detection, low-light sensing, biological detection, imaging readout, and optical communication reception. Its basic working principle mainly involves using a photodetector to receive the incident light signal from the target, converting it into a corresponding current signal, and then amplifying, converting, and finally outputting the signal through a subsequent readout circuit. With the development of portable electronic devices, intelligent sensing systems, and low-light detection applications, photoelectric detection circuits increasingly need to achieve stable readout under relatively small light signal conditions. Therefore, minimizing the impact of dark current, DC offset, and ambient temperature changes on the detection results during the readout process has become crucial for improving system performance.

[0003] As a core component of the detection front-end, CMOS photodetectors can output a light intensity-dependent current under incident light and are widely integrated into photoelectric detection systems. However, in actual operation, the output current of the photodetector not only includes the photocurrent caused by the incident light but also inevitably includes dark current that still exists under no-light conditions. If this total current is directly fed into the subsequent high-gain transimpedance amplifier, the dark current will form a large DC component during amplification, which can easily cause amplifier operating point offset, reduced effective dynamic range, and significantly reduced system resolution for weak light signals. Especially in applications with weak light detection or large ambient temperature variations, the DC offset, operating point offset, and dynamic range compression caused by dark current will be more pronounced, thus requiring the design of a dedicated dark current compensation readout circuit.

[0004] To mitigate the adverse effects of dark current in photodetectors on subsequent readout circuits, various solutions have been proposed in existing technologies. One common approach involves setting up a reference branch structure at the front end of the detector. The main detection branch receives the actual incident light and outputs a total current containing both photocurrent and dark current. The reference branch, however, is shielded from light by methods such as light blocking, metal covering, or other physical barriers, thus outputting only dark current. The two signals are then subtracted using differential readout. While this reference branch compensation scheme can obtain dark current samples, it has limitations regarding device matching and layout between the main detection branch and the reference branch. Figure 1The requirements for consistency and differential readout accuracy are extremely high. When there are device process deviations between the two branches due to fluctuations in semiconductor manufacturing processes, or when the actual operating conditions of the two branches are inconsistent, the compensation effect is easily affected, and this solution usually requires the addition of additional detection paths, thereby increasing the structural complexity of the front-end circuit.

[0005] The second approach employs a DC offset cancellation loop. This typically detects the DC offset component at the output of the subsequent amplifier and feeds the detected offset information back to the front-end bias branch, compensation branch, or balance control branch via a low-frequency negative feedback loop to gradually reduce the DC offset at the output. However, this closed-loop cancellation scheme usually relies on a complex closed-loop feedback chain. In practical circuit design, significant effort is required to balance loop stability, response speed, and the complexity of additional circuitry, which significantly increases the difficulty of circuit implementation and layout debugging.

[0006] The third approach involves setting different current mirror branches on the readout circuit and configuring impedance networks or frequency selection networks in each branch. This allows the dark current component and the useful optical signal component to have different transmission characteristics in each branch. The influence of dark current is then suppressed through differential output or current subtraction. This type of current mirror differential compensation scheme also leads to a bulky and complex front-end circuit structure and places extremely high demands on the matching accuracy of the current mirror, parasitic parameter control, and frequency response design. This makes the theoretical analysis, parameter optimization, and tape-out process of the entire circuit relatively cumbersome.

[0007] Besides the aforementioned solutions involving adjustments at the readout circuit level, existing technologies also attempt to reduce dark current at the device structure and process level. For example, this can be achieved by optimizing the doping structure of semiconductor devices, improving surface passivation conditions, setting physical guard ring structures, adjusting device biasing methods, or employing specific device geometries to reduce the dark current of the optoelectronic device itself at its source. These methods typically rely heavily on specific process conditions or customized modifications to the device structure. Because it is difficult to directly improve the circuit state of the readout link, they cannot directly solve the problems of DC offset, operating point shift, and dynamic range compression caused by dark current entering the subsequent amplifier in existing readout links.

[0008] In summary, existing dark current processing solutions generally suffer from technical challenges such as high requirements for device matching, complex front-end circuit structures, difficulty in closed-loop feedback design, stringent control of parasitic parameters, or difficulty in directly improving the operating state of the subsequent readout link. How to effectively compensate for the dark current component in the photodetector output without relying on additional reference photosensitive devices or introducing complex closed-loop cancellation circuits, thereby reducing the adverse effects of dark current on the operating point, output baseline, and dynamic range of the subsequent transimpedance amplifier and improving signal resolution and readout stability under low-light conditions, remains a technical problem that needs to be solved in this field. Summary of the Invention

[0009] To address the technical problems of DC offset, operating point shift, and dynamic range compression caused by dark current entering the subsequent amplifier in the existing technical solutions, this invention provides a dark current compensation readout circuit, method, and photoelectric detection system. This invention changes the traditional compensation mode that relies on redundant light-shielding devices or complex closed-loop feedback links. Instead, it directly sets up a dark current compensation branch at the output of the photodetector, thereby performing front-end cancellation and pre-compensation of the dark current component in the photodetector output during the front-end readout stage. Through this current superposition and cancellation mechanism at the most recent common readout node, the absolute component of dark current directly entering the subsequent high-gain amplifier can be minimized. This fundamentally improves the input operating conditions of the subsequent transimpedance amplifier, reduces DC offset, operating point shift, and dynamic range compression caused by dark current amplification in the subsequent stage, and ensures that the operating point of the subsequent amplifier can be more easily kept within the linear range. Therefore, with a relatively simple structure, this significantly improves the system's readout and resolution capabilities for weak light signals in low-light detection scenarios.

[0010] In the overall design of the cascaded architecture and signal flow, this invention constructs a cascaded readout structure consisting of front-end dark current compensation, transimpedance amplification, inverting amplification, and differential amplification. This achieves a complete technical solution: first, front-end compensation of the dark current in the current domain, and then staged amplification and output shaping in the voltage domain. The circuit consists of a photodetector connected in series at a common readout node and a dark current compensation branch, forming a current-counting front-end. This common readout node is directly connected to the input of the first-stage transimpedance amplifier. This allows the total current generated by the photodetector, including both photocurrent and dark current, to be superimposed with the compensation current provided by the compensation branch at the common readout node, forming a net input current after dark current compensation, which is then fed into the transimpedance amplification stage. Based on this, the system converts the counteracted net input current signal into a corresponding voltage signal through the transimpedance amplification stage. Subsequently, the inverting voltage amplification stage reverses the polarity and adjusts the amplitude of this voltage signal. Finally, it is fed into the differential amplification stage for comparison and amplification with an externally set reference voltage, thus completing the front-end compensation, transimpedance conversion, polarity adjustment, and final output of the photodetector output signal.

[0011] Specifically, the first aspect of the present invention provides a dark current compensation readout circuit for a photodetector. The circuit includes a common readout node, a dark current compensation branch, and a transimpedance amplifier stage. The photodetector and the dark current compensation branch are electrically connected between a first bias voltage source and a second bias voltage source, and the point where their electrical connections intersect constitutes the common readout node. The common readout node is also electrically connected to the input terminal of the transimpedance amplifier stage. The dark current compensation branch generates a compensation current opposite to the direction of the dark current in the photodetector, thereby offsetting the dark current component in the total output current of the photodetector at the common readout node, forming a net input current that is fed into the transimpedance amplifier stage. This technical solution can directly achieve front-end cancellation and pre-compensation of the current domain at the most front-end common readout node of the readout circuit, minimizing the absolute component of dark current directly entering the subsequent high-gain amplifier, thus significantly improving the system's readout and resolution capability for weak light signals while maintaining a relatively simple structure.

[0012] Furthermore, this invention provides a dark current compensation readout circuit, wherein the dark current compensation branch includes a resistor connected in series between the common readout node and the corresponding bias voltage source; the potential of the common readout node is maintained as a constant using the virtual short clamping condition at the input of the transimpedance amplifier stage. This technical solution can utilize the virtual short condition formed by the negative feedback of the subsequent transimpedance amplifier stage to keep the potential of the common readout node approximately constant during circuit operation, thereby locking the voltage difference across the resistor and forming an extremely stable constant compensation current in the dark current compensation branch, ensuring the reliable operation of the front-end current domain offsetting mechanism.

[0013] Furthermore, the readout circuit also includes an inverting voltage amplifier stage and a differential amplifier stage cascaded after the transimpedance amplifier stage; the transimpedance amplifier stage is used to perform transimpedance conversion on the net input current to output a primary voltage signal; the inverting voltage amplifier stage is used to perform polarity reversal and amplitude adjustment on the primary voltage signal to output a secondary voltage signal; the differential amplifier stage is used to perform differential amplification operation on the secondary voltage signal and an externally set reference voltage to output a final voltage signal. This technical solution constructs a complete voltage domain cascaded processing architecture of front-end dark current compensation, transimpedance amplification, inverting amplification, and differential amplification, realizing front-end compensation, transimpedance conversion, polarity adjustment, and final output of the signal, which helps to complete the step-by-step smooth amplification and shaping of the signal in the voltage domain.

[0014] Furthermore, the transimpedance amplification stage consists of a first operational amplifier, and a feedback resistor and a feedback capacitor connected in parallel between the inverting input and output of the first operational amplifier; the inverting voltage amplification stage consists of a second operational amplifier, an input resistor connected between the output of the preceding stage and the inverting input of the second operational amplifier, and a feedback resistor connected between the inverting input and output of the second operational amplifier. This allows for high-frequency filtering using the parallel feedback capacitor, effectively suppressing high-frequency noise in the system and eliminating self-oscillations that may be caused by parasitic parameters, ensuring the stability of the primary and secondary amplification conversion of the entire readout link.

[0015] Furthermore, the differential amplifier stage consists of a third operational amplifier and resistors R1, R2, R3, and R4; the non-inverting input of the third operational amplifier is connected to the output of the previous stage through resistor R2 and grounded through resistor R3; its inverting input is connected to an external adjustable reference voltage V through resistor R1. ref This is connected to the final voltage output terminal via a feedback resistor R4; the resistance values ​​of each resistor are matched to satisfy the proportional relationship: R4 / R1 = R3 / R2. This resistor subtraction network architecture enables precise differential amplification of the final output voltage, which can be achieved by adjusting the external reference voltage V. ref The size is used to shift the output baseline, thereby providing a reliable reference for the final output signal.

[0016] This invention also provides a dark current compensation readout method, comprising the following steps: under the action of a bias voltage, a photodetector is excited by incident light to generate a total current containing a photogenerated current component and a dark current component, and the total current is output to a common readout node; a compensation current opposite in direction to the dark current component is introduced at the common readout node, and the dark current component in the total current is physically canceled in the current domain by the superposition and offset of the compensation current and the total current at the common readout node, thereby obtaining a net input current characterizing an effective photogenerated signal; the net input current is converted into a primary voltage signal to complete the current-voltage conversion; the primary voltage signal is subjected to polarity reversal and amplitude amplification processing to obtain a positively changing secondary voltage signal; the secondary voltage signal is differentially subtracted from an externally provided adjustable reference voltage to output a final voltage signal after static zeroing at the output terminal. This method enables a complete process of first performing front-end offset compensation for dark current in the current domain, and then completing step-by-step amplification and output shaping in the voltage domain. This allows the signal entering the subsequent circuit to reflect more of the components related to effective photogenerated charge, effectively reducing the ineffective occupation of the amplifier output swing by dark current, and significantly improving the system's signal-to-noise ratio and effective dynamic range.

[0017] Furthermore, a compensation current opposite to the direction of the dark current component is introduced at the common readout node. Specifically, this includes: utilizing the virtual short condition formed by negative feedback to approximately maintain the potential of the common readout node as constant, thereby locking the voltage difference across the dark current compensation branch that generates the compensation current; and adjusting the resistance value of the adjustable resistor in the dark current compensation branch to make the magnitude of the compensation current as close as possible to the dark current component. This method can ensure that the front-end compensation current does not jump with changes in light intensity and node current through virtual short clamping, and in actual operation, it can achieve active offsetting and optimal cancellation of the dark current component by adjusting the resistance value of the adjustable resistor.

[0018] Furthermore, the differential subtraction operation specifically includes: adjusting the magnitude of the externally set reference voltage to arbitrarily shift the output zero point and baseline within the linear range. This enables the complete removal of residual DC offset at the output end, achieving precise static output zeroing, thus ensuring that the final output voltage signal can perfectly adapt to subsequent acquisition and processing stages such as analog-to-digital conversion or threshold judgment.

[0019] Finally, this invention also provides a photoelectric detection system, including the aforementioned dark current compensation readout circuit, and a subsequent processing circuit electrically connected to the output terminal of the dark current compensation readout circuit. This system solution electrically couples the readout circuit, which has dark current front-end offsetting and step-by-step amplification and shaping functions, to the subsequent processing circuit at the system level. This enables the transmission of a high-quality voltage signal to the back end, reducing DC offset, operating point shift, and dynamic range compression caused by dark current to extremely low levels. This significantly improves the measurement accuracy of the entire system in practical application scenarios such as low-light detection.

[0020] Furthermore, at least one of a buffer stage and a filter stage is cascaded between each amplification stage in the dark current compensation readout circuit, or between the dark current compensation readout circuit and the subsequent processing circuit. By introducing a buffer stage or a filter stage, better resistance matching and signal isolation can be provided between the preceding and following hardware stages, and the signal during transmission can be further purified and smoothed, thereby improving the long-term working stability and anti-interference performance of the entire photoelectric detection system.

[0021] Compared with the prior art, one or more technical solutions provided by the present invention have at least the following technical effects or advantages: 1. High Signal-to-Noise Ratio. This invention incorporates a dark current compensation branch at the output of the photodetector, ensuring that the dark current component is compensated before entering the transimpedance amplifier, thereby significantly reducing the interference of dark current on the readout signal of subsequent stages. Especially under weak light detection conditions, where the photogenerated current is relatively weak, dark current is more likely to interfere with the resolution of useful signals. This invention performs current domain compensation at the most recent common readout node, ensuring that the net input signal sent to the subsequent transimpedance amplifier stage reflects more of the effective photogenerated charge component related to changes in incident light, thus significantly improving the signal-to-noise ratio of the readout circuit.

[0022] 2. The circuit structure is relatively simple. Compared with existing processing schemes that require additional reference photosensitive devices, complex closed-loop DC offset cancellation loops, multi-current mirror branch networks, or complex timing control, this invention does not rely on additional reference photosensitive devices, nor does it need to introduce complex closed-loop negative feedback links. The front-end structure is relatively simple, the overall system complexity is low, and it is easier to implement in actual hardware fabrication and layout debugging.

[0023] 3. Improved effective dynamic range and output stability. Since the dark current component is offset and compensated at the common node at the front end, the subsequent high-gain transimpedance amplifier does not need to simultaneously amplify the large DC component of the dark current. This effectively reduces the ineffective occupation of the amplifier's output swing by the dark current, preventing premature amplifier saturation and improving the system's effective dynamic range. Furthermore, by combining this with the subsequent cascaded inverting voltage amplification stage and differential amplification stage, the voltage polarity of the front-end compensated signal can be further adjusted and the reference standard normalized, thereby improving the long-term stability of the final output signal and making it more suitable for subsequent acquisition and processing stages such as analog-to-digital conversion and threshold judgment. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0025] Figure 1 This is a schematic diagram of a dark current compensation readout circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of an alternative circuit structure for a dark current compensation readout circuit provided in an embodiment of the present invention; Figure 3 The output result diagram of a dark current compensation readout circuit provided in an embodiment of the present invention in the dark state is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0027] This invention provides a dark current compensation readout circuit and method for front-end compensation of the dark current component in the photodetector output during photoelectric detection, reducing DC offset, operating point shift, and dynamic range compression caused by the dark current after subsequent transimpedance amplification. Figure 1 As shown, the overall circuit provided in this embodiment mainly consists of a CMOS photodetector, a dark current compensation branch, a transimpedance amplifier stage, an inverting voltage amplifier stage, and a differential amplifier stage. In the electrical connection relationship of the overall circuit, the output terminal of the CMOS photodetector is connected to a common readout node, which is simultaneously connected to the input terminal of the dark current compensation branch and the input terminal of the first-stage transimpedance amplifier. The total output current generated by the photodetector and the compensation current provided by the compensation branch are superimposed and canceled at the common readout node to form a net input current after dark current compensation. This net input current is then sent to the first-stage transimpedance amplifier for current-to-voltage conversion and subsequent signal processing. Through this cascaded readout structure of the front-end circuit, the present invention realizes the overall circuit design concept of first compensating for dark current in the current domain and then performing step-by-step amplification and output shaping in the voltage domain. This can minimize the DC offset, operating point offset, and dynamic range compression problems caused by the dark current directly entering the subsequent high-gain amplifier, thereby improving the system's readout capability for weak light signals.

[0028] Based on the overall electrical architecture described above, the CMOS photodetector in this embodiment of the invention is mainly used to receive incident light and output a current signal related to the light intensity. This signal, in actual operation, manifests as containing a photocurrent I0. Light and dark current I Dark The total current in the two parts is denoted as I in the circuit. DSTo broaden the technical applicability of this readout circuit, although the CMOS photodetector in this embodiment uses a photodiode as the preferred implementation, it can also be extended to other optoelectronic devices with similar photocurrent output characteristics. In specific implementations, the CMOS photodetector can also be equivalently replaced by a phototransistor, a CMOS photosensitive device, a photosensitive field-effect transistor, or other photodetectors. Through this equivalent extension at the device level, the dark current compensation readout circuit disclosed in this embodiment can achieve stable front-end current offsetting with a wide range of front-end device selections, providing a fundamental guarantee for the linear operation of subsequent circuit stages.

[0029] The following combination Figure 1 and Figure 2 The dark current physical cancellation mechanism of the present invention will be described in detail. For example... Figure 1 As shown, in the front-end electrical topology of the basic embodiment, the dark current compensation branch is specifically connected to the output node of the CMOS photodetector to generate a compensation current in the opposite direction to the dark current. Specifically, this dark current compensation branch is connected to a resistor and a negative bias voltage -V. b The configuration includes an input terminal of the dark current compensation branch electrically connected to the common readout node, and an output terminal electrically connected to the negative bias voltage -V. b An adjustable resistor is connected in series in the middle of this branch. At this time, the common readout node is also connected to the inverting input of the subsequent transimpedance amplifier. Under the action of the negative feedback network, the inverting and non-inverting inputs of this transimpedance amplifier satisfy the virtual short condition, therefore the potential of the common readout node is approximately and firmly maintained at the potential of the non-inverting input. Since the non-inverting input is usually connected to a fixed potential, such as ground, the potential of the common readout node remains approximately constant during circuit operation, not changing with the incident light and current. In this state, the voltage difference across the dark current compensation branch is entirely determined by the negative bias voltage -V. b Together with the fixed clamping potential of this node, it can form an extremely stable compensation current I in the branch. comp Its magnitude is mainly determined by the negative bias voltage -V b The value of the adjustable resistor is determined together with its resistance.

[0030] The common readout node forms a point of current superposition and physical cancellation. Under bias and illumination conditions, the CMOS photodetector outputs a total current I to this node. DS The dark current compensation branch draws a compensation current I in the opposite direction from this node. comp After the two signals undergo current superposition and cancellation at the common node at the front end, the net input current finally fed into the transimpedance amplifier can be expressed as I. out = IDS - I comp Ideally, by adjusting the resistance value of the adjustable resistor, a stable compensation current I is generated. comp By approximating the dark current component of the photodetector itself as closely as possible, the total current I can be reduced. DS The dark current component in the circuit is physically offset and pre-cancelled at the front end, resulting in a net input current I that ultimately enters the subsequent stage. out The main signal retained is the effective signal related to the change of incident light, thus completing the active compensation of dark current in the front-end current domain.

[0031] The present invention also provides an alternative embodiment, such as Figure 2 As shown, in this alternative circuit structure, the photodetector and the dark current compensation structure can be interchanged. Specifically, the dark current compensation branch is replaced by a pull-up connection to the bias voltage source V. DD Between the common readout node and the common readout node, the circuit evolves into a topology where a stable compensation current is injected into the common readout node through a resistor. The corresponding photodetector is then replaced with a pull-down connection between the common readout node and the negative bias voltage source -V. b The current superposition and cancellation at the common readout node in this alternative circuit is essentially dual to the basic embodiment. Although the node potential configuration and current flow direction are reversed due to the positional interchange, it still utilizes the virtual short condition of the subsequent transimpedance amplifier to form a stable countercurrent at the front end, achieving pre-cancellation of the dark current component before it enters the amplification stage.

[0032] Furthermore, in this embodiment, the internal hardware structure of the dark current compensation branch, in addition to employing the aforementioned adjustable resistor and negative bias voltage -V, b Besides the series structure, this dark current compensation branch can also be implemented using other circuit structures with constant current extraction or injection characteristics. Specifically, the dark current compensation branch can also be equivalent to a constant current source structure, a current mirror structure, or a compensation structure composed of a resistor network and an adjustable reference voltage. These circuit structures can achieve the same current domain physical offsetting effect at the common readout node at the front end.

[0033] After the front-end common readout node completes the current domain physical offset of the dark current, this embodiment of the invention sets up a three-stage cascaded voltage domain processing architecture in the back stage.

[0034] The first-stage transimpedance amplifier stage is used to convert the net input current signal, after offset compensation at the front-end common readout node, into a corresponding voltage signal, thus achieving primary current-to-voltage conversion. For example... Figure 1 As shown, in the specific circuit connection, this transimpedance amplifier stage mainly consists of a first operational amplifier and a feedback resistor R.f and feedback capacitor C f The configuration is as follows: The inverting input of the first operational amplifier is electrically connected to the front-end common readout node, and its non-inverting input is connected to a fixed potential, such as ground. The feedback resistor R... f and feedback capacitor C f These capacitors are connected in parallel between the inverting input and output of the first operational amplifier, forming a high-gain negative feedback transimpedance amplifier network. Since the dark current component is largely physically canceled at the common readout node at the front end, the DC component at the input of this stage is smaller. This makes it easier to keep the DC operating point of the first operational amplifier within the linear range, reducing the occupation of the output swing by the dark current and avoiding premature saturation under high-gain amplification. Simultaneously, the parallel feedback capacitor C... f It can effectively suppress high-frequency noise and eliminate self-excited oscillations that may be caused by parasitic parameters, thus ensuring the stability of the primary conversion of the entire readout link.

[0035] For the second-stage inverting voltage amplifier, since the voltage signal output from the transimpedance amplifier stage usually exhibits a negative voltage change, polarity reversal and amplitude amplification are required in the second stage to facilitate subsequent system processing. For example... Figure 1 As shown, in the specific circuit connection, this inverting voltage amplifier stage consists of a second operational amplifier and corresponding input and feedback resistors, adopting a conventional inverting proportional amplifier structure. Specifically, the output of the first operational amplifier is connected to the inverting input of the second operational amplifier through an input resistor. The non-inverting input of the second operational amplifier is also connected to a fixed potential, such as ground. The output of the second operational amplifier is then connected back to its own inverting input through its corresponding feedback resistor. This stage, through a conventional inverting proportional amplifier topology, smoothly flips the negative voltage change of the output of the first stage into a positive voltage change, realizing the reversal of signal polarity. Furthermore, by adjusting the ratio of the feedback resistor to the input resistor in this stage, precise adjustment of the signal amplitude and secondary gain enhancement are achieved, making the signal more resistant to interference.

[0036] The third differential amplifier stage, located at the end of the entire readout chain, compares and amplifies the voltage signal processed by the previous stage with an externally set reference voltage, and introduces an adjustable reference at the output to facilitate adjustment of the output zero point and baseline. Figure 1As shown, in the specific circuit connection, this differential amplifier stage consists of a third operational amplifier and four resistors R1, R2, R3, and R4 forming a differential subtraction network. Specifically, the output voltage V1 of the preceding second operational amplifier is connected to the non-inverting input of the third operational amplifier through resistor R2. This non-inverting input is also connected to a fixed potential, such as ground, through resistor R3. An externally adjustable reference voltage V0 is also provided. ref Then, it is connected to the inverting input terminal of the third operational amplifier through resistor R1, and the output terminal V of the third operational amplifier is... out The feedback resistor R4 is connected back to its inverting input. This differential amplifier stage enables precise zero-adjustment of the output. In practice, the external resistor network is matched to ensure the ratio of R4 / R1 = R3 / R2, so that the final output voltage satisfies the mathematical expression V. out =R4 / R1·(V1-V ref Through this differential network, the reference voltage V can be adjusted. ref The size of the output zero and baseline can be arbitrarily shifted to remove any residual DC offset in the system, thereby improving the final output signal V. out It is more suitable for subsequent analog-to-digital conversion, threshold judgment or other signal processing stages.

[0037] To meet the customized application needs of different application scenarios, the subsequent signal processing link composed of the above three cascaded amplification stages in this embodiment also has extremely high flexibility and scalability. In specific implementations, the specific number of stages, arrangement, or partial merging of the transimpedance amplification stage, inverting voltage amplification stage, and differential amplification stage can all be adjusted according to actual needs. For example, without departing from the core concept of this invention, additional processing circuits can be added after the transimpedance amplification stage or between each amplifier stage, such as a buffer stage for interface isolation or a filtering stage for further signal purification. These local cascaded changes and equivalent configuration schemes for the signal processing link all fall within the protection scope of this invention.

[0038] The following describes the specific logic and overall workflow of the circuit in its powered-on operating state. After the system is powered on and enters the operating state, the overall workflow of the circuit is executed sequentially and cyclically according to the following specific operations.

[0039] First, by configuring external bias conditions, the CMOS photodetector is placed under a preset bias voltage. When incident light shines on the CMOS photodetector, it is stimulated to generate a current signal related to the incident light intensity and outputs it to the front-end common readout node. During this process, due to the non-ideal physical characteristics of semiconductor devices, the current signal actually manifests as a total current including both photocurrent and dark current that still exists under no-light conditions, denoted as I in circuit logic. DS .

[0040] After system startup, the first-stage transimpedance amplifier automatically establishes a closed-loop stable state under the action of the negative feedback network, forcing a virtual short condition between the inverting and non-inverting inputs of its internal first operational amplifier. At this time, the potential of the front-end common readout node connected at the inverting input is approximately clamped to the fixed ground potential connected to the non-inverting input. Because the potential of this front-end common readout node is locked to a constant value by the virtual short characteristic of the operational amplifier, a constant voltage difference is generated across the dark current compensation branch that does not change with light intensity. Consequently, a voltage completely induced by the negative bias voltage -V is generated in the adjustable resistor connected in series in the middle of this branch. b The compensation current I, which is determined together with the fixed clamping potential of the node, has extremely high constant stability. comp .

[0041] The total current I output by the CMOS photodetector DS The compensation current I generated by the dark current compensation branch comp Simultaneously, they converge at the aforementioned front-end common readout node for physical algebraic superposition. At this node, the compensation current I... comp The total current I DS The dark current component contained within is front-end offset and pre-cancelled, thereby completing the physical compensation of the dark current in the current domain before entering the subsequent amplification stage. After superposition and offsetting, the net input current I is formed. out = I DS - I comp And it is fed into the input terminal of the first-stage transimpedance amplifier. In a specific implementation, by adjusting the resistance value of the adjustable resistor at the front end, I... comp The magnitude of the current should be as close as possible to the dark current component, so that the net input current I entering the subsequent stage is... out The main components retained are the effective signal components related to changes in incident light.

[0042] Next, the net input current I out After entering the transimpedance amplification stage, the current flows through the first operational amplifier and the feedback resistor R. f and feedback capacitor C fThe negative feedback transimpedance amplifier network is constructed, and the net input current I... out It is converted into the corresponding output voltage signal. Since the dark current component has been largely canceled out at the common readout node at the front end, the DC component entering the input of the first operational amplifier in this step is extremely small, so that its DC operating point is always stably kept within the linear range, reducing the occupation of the output swing by the dark current.

[0043] Since the voltage signal output from the preamplifier stage typically exhibits a negative voltage change, this signal then enters the second-stage inverting voltage amplification stage. It flows through a conventional inverting proportional amplification structure comprised of a second operational amplifier and corresponding input and feedback resistors, completing the polarity reversal and amplitude adjustment of the voltage signal. This step reverses the negative voltage change to a positive voltage change through inverting amplification, and then performs secondary voltage amplification of the signal using the resistor ratio of this stage, outputting a positive secondary voltage signal V1.

[0044] The secondary voltage signal V1 output from the preamplifier then enters the differential amplifier stage, the last stage in the entire readout chain. It flows through the third operational amplifier and a differential subtraction network consisting of four resistors: R1, R2, R3, and R4. By ensuring the external resistor values ​​satisfy the ratio R4 / R1 = R3 / R2, the third operational amplifier subtracts the secondary voltage signal V1 from an externally set adjustable reference voltage V. ref Perform the difference subtraction operation, and finally output the expression V at the output terminal. out =R4 / R1·(V1-V ref The final voltage result. In this step, the operator fine-tunes the external reference voltage V within the linear range. ref The magnitude of the DC level allows for arbitrary shifting of the output zero and baseline, thereby eliminating any residual DC offset and achieving static output zeroing, ensuring the final output voltage signal V... out It can perfectly adapt to the full-scale input requirements of subsequent analog-to-digital conversion, threshold judgment or other subsequent signal processing stages.

[0045] To verify the actual working effect and technical feasibility of the above-mentioned dark current compensation readout circuit and method, the output of the overall circuit was simulated and verified in this embodiment of the invention. For example... Figure 3 As shown in the simulation graph, the final output voltage V generated at the output terminal of the circuit under completely dark conditions is visually displayed. out The fluctuations over time are shown. The horizontal axis of the simulation curve represents time, presented scientifically using a logarithmic coordinate system, with the time scale smoothly extending from 10 nanoseconds to over 10 microseconds. The corresponding vertical axis represents the final output voltage V. outIt also uses a logarithmic coordinate axis to expand the fine measurement, with the level amplitude ranging from 1 microvolt to 1 volt.

[0046] Through the Figure 3 Quantitative analysis of the data waveforms reveals that when the system is powered on and in continuous operation, even over time, the output voltage V of the circuit in the dark state remains constant. out It has also remained extremely stable at a very low level of around 1 millivolt.

[0047] Because a dark current compensation branch is set at the most front-end common readout node, the negative feedback virtual short condition of the first-stage operational amplifier is used to make the generated stable compensation current I, which is close to the dark current component, so that the magnitude is close to the stable compensation current I. comp The total current I output by the photodetector DS A front-end physical offset was performed, thereby reducing the net input current I entering the subsequent transimpedance amplifier. out The dark current component in the signal is almost completely canceled out. The extremely low voltage baseline feedback from the simulation results shows that the high-gain transimpedance amplifier stage in the later stage successfully avoids the ineffective amplification of the large DC dark current component. The DC operating point of the first-stage operational amplifier is stably protected within the linear range, eliminating the DC offset problem. This greatly reduces the space occupied by the non-useful signal on the amplifier output swing, fundamentally releasing and expanding the effective dynamic range of the readout circuit.

[0048] Meanwhile, the flatness and stability of the simulation curves throughout the entire time period quantitatively confirm the technical advantages of the cascaded structure of the subsequent inverting voltage amplifier stage and the differential amplifier stage. By introducing a differential amplifier network in the last stage and ensuring that the external resistance values ​​satisfy the proportional relationship R4 / R1 = R3 / R2, even if there is an extremely weak DC drift remaining at the front end, it can be mitigated by adjusting the external adjustable reference voltage V. ref The DC level completely eliminates it, thus achieving precise static zeroing at the output.

[0049] Furthermore, embodiments of the present invention also provide a photoelectric detection system including the above-described dark current compensation readout circuit. For example... Figure 1 or Figure 2 As shown, the photoelectric detection system includes the dark current compensation readout circuit described in the foregoing embodiment, and the final voltage output terminal V of the dark current compensation readout circuit. out A subsequent processing circuit for the electrical connection. This subsequent processing circuit includes at least one component for receiving the final voltage signal V. out And convert it into a digital signal using an analog-to-digital converter circuit, or use it to convert the final voltage signal V outA threshold judgment circuit compares the signal with a set threshold to output a high or low level determination result. By electrically coupling the readout circuit with dark current front-end offsetting and step-by-step amplification and shaping functions to the subsequent processing circuit, a stable, high-quality voltage signal in the dark state can be transmitted to the back end. This avoids errors caused by DC offset and operating point deviation in subsequent quantization or judgment, significantly improving the measurement accuracy of the entire system in practical applications such as low-light detection.

[0050] Building upon this foundation, to optimize the transmission quality of signals within the system, the photoelectric detection system described in this embodiment also possesses high link scalability. Specifically, at least one of a buffer stage and a filter stage can be cascaded between the transimpedance amplification stage, the inverting voltage amplification stage, and the differential amplification stage in the dark current compensation readout circuit, or between the final output of the dark current compensation readout circuit and the input of the subsequent processing circuit. The buffer stage provides impedance matching and signal isolation between the preceding and following hardware stages, while the filter stage further purifies and smooths the voltage signal during transmission, filtering out residual weak high-frequency ripples. The introduction of these functional units provides a more robust system-level hardware guarantee for the long-term stable operation and anti-interference performance of the entire photoelectric detection system in complex electromagnetic environments.

[0051] In summary, combining Figure 3 The verification results show that the electrical structure with front-end current domain compensation and voltage domain step-by-step amplification and shaping provided in this embodiment of the invention has a consistently low output level in the dark state. This effectively reduces the interference of dark current on the readout signal of the subsequent stage, reduces DC offset, operating point offset and dynamic range compression caused by dark current, and significantly improves the signal resolution and output stability of the system under low illumination and weak light conditions.

[0052] While preferred embodiments of the present invention have been described above, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0053] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dark current compensation readout circuit for a photodetector, characterized in that, include: Common readout node, dark current compensation branch, and transimpedance amplifier stage; The photodetector and the dark current compensation branch are electrically connected between the first bias voltage source and the second bias voltage source, and the intersection of their electrical connections constitutes the common readout node. The common readout node is also electrically connected to the input terminal of the transimpedance amplifier stage; The dark current compensation branch is used to generate a compensation current in the opposite direction to the dark current of the photodetector, so as to offset the dark current component in the total output current of the photodetector at the common readout node, forming a net input current and sending it to the transimpedance amplifier stage.

2. The dark current compensation readout circuit according to claim 1, characterized in that: The dark current compensation branch includes a resistor connected in series between the common readout node and the corresponding bias voltage source; The potential of the common readout node is kept constant using the virtual short clamping condition at the input of the transimpedance amplifier stage.

3. The dark current compensation readout circuit according to claim 1, characterized in that, The readout circuit also includes an inverting voltage amplifier stage and a differential amplifier stage cascaded after the transimpedance amplifier stage; The transimpedance amplifier stage is used to perform transimpedance conversion on the net input current to output a primary voltage signal; The inverting voltage amplifier stage is used to reverse the polarity and adjust the amplitude of the primary voltage signal to output a secondary voltage signal; The differential amplifier stage is used to perform differential amplification operations on the secondary voltage signal and an externally set reference voltage to output the final voltage signal.

4. The dark current compensation readout circuit according to claim 3, characterized in that: The transimpedance amplifier stage consists of a first operational amplifier, and a feedback resistor and a feedback capacitor connected in parallel between the inverting input terminal and the output terminal of the first operational amplifier. The inverting voltage amplifier stage consists of a second operational amplifier, an input resistor connected between the output terminal of the preamplifier and the inverting input terminal of the second operational amplifier, and a feedback resistor connected between the inverting input terminal and the output terminal of the second operational amplifier.

5. The dark current compensation readout circuit according to claim 3, characterized in that: The differential amplifier stage consists of a third operational amplifier and resistors R1, R2, R3, and R4. The non-inverting input of the third operational amplifier is connected to the output of the preceding stage via resistor R2 and grounded via resistor R3; its inverting input is connected to an external adjustable reference voltage V via resistor R1. ref And it is connected to the final voltage output terminal through the feedback resistor R4; The resistance values ​​of each resistor are matched to satisfy the proportional relationship: R4 / R1 = R3 / R2.

6. A dark current compensation readout method, characterized in that, Includes the following steps: Under the action of bias voltage, the photodetector is excited by incident light to generate a total current containing photocurrent and dark current components, and the total current is output to the common readout node. A compensation current opposite to the direction of the dark current component is introduced at the common readout node. Through the superposition and offset of the compensation current and the total current at the common readout node, the dark current component in the total current is physically canceled in the current domain, thereby obtaining the net input current characterizing the effective photogenerated signal. The net input current is converted into a primary voltage signal to complete the current-to-voltage conversion; The primary voltage signal is subjected to polarity reversal and amplitude amplification to obtain a positively changing secondary voltage signal; The secondary voltage signal is differentially subtracted from the externally provided adjustable reference voltage to output the final voltage signal after static zeroing at the output terminal.

7. The dark current compensation readout method according to claim 6, characterized in that, The introduction of a compensation current at the common readout node that is opposite in direction to the dark current component specifically includes: By utilizing the virtual short condition formed by negative feedback, the potential of the common readout node is approximately kept constant to lock the voltage difference across the dark current compensation branch that generates the compensation current. By adjusting the resistance value of the adjustable resistor in the dark current compensation branch, the magnitude of the compensation current can be made as close as possible to the dark current component.

8. The dark current compensation readout method according to claim 6, characterized in that, The difference subtraction operation steps specifically include: By adjusting the magnitude of the externally set reference voltage, the output zero and baseline can be shifted arbitrarily within the linear range.

9. A photoelectric detection system, characterized in that, include: Dark current compensation readout circuit as described in any one of claims 1 to 5; It also includes a subsequent processing circuit that is electrically connected to the output of the dark current compensation readout circuit.

10. The photoelectric detection system according to claim 9, characterized in that: At least one of a buffer stage and a filter stage is cascaded between each amplification stage in the dark current compensation readout circuit, or between the dark current compensation readout circuit and the subsequent processing circuit.

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