Pvt-insensitive ring amplifier based pga for silicon microphones

Abstract

The present disclosure relates to a PVT-insensitive ring amplifier based PGA for a silicon microphone. A ring amplifier comprising: a plurality of series coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series coupled inverters comprises a bias node; a dead zone generator coupled to the plurality of series coupled inverters; and a bias generator coupled to the bias node of the first inverter, the bias generator controlling a current through the first inverter.

Description

Technical Field

[0001] This invention generally relates to a programmable gain amplifier (PGA) for a process, voltage, and temperature (PVT) ring amplifier for silicon microphones, as well as corresponding systems and methods. Background Technology

[0002] Ring amplifiers are widely used in modern integrated circuits due to their high gain, low power consumption, and small area. However, their performance can be significantly affected by variations in process, voltage, and temperature (PVT). Variations in PVT can cause changes in the current consumption, gain, bandwidth, and stability of the ring amplifier, thus degrading performance and reliability. Various compensation techniques are known in the prior art, but they primarily focus on improving the stability of the ring amplifier by addressing "dead-time" bias, establishing the response, and improving overall ring amplifier stability. However, existing solutions do not address the issue of controlling amplifier current consumption, and inherent variations in the inverter-based structure can lead to significant variations in current consumption. In applications where noise and power consumption are primary design constraints, stable amplifier current across PVT conditions is crucial. Summary of the Invention

[0003] According to an embodiment, a ring amplifier includes: a plurality of series-coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series-coupled inverters includes a bias node; a dead-time generator coupled to the plurality of series-coupled inverters; and a bias generator coupled to the bias node of the first inverter, the bias generator being configured to control the current through the first inverter.

[0004] According to an embodiment, a method of operating a ring amplifier includes a plurality of series-coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series-coupled inverters includes a bias node, the method comprising: generating a reference voltage; and applying the reference voltage to the bias node to provide a controlled current through the first inverter.

[0005] According to an embodiment, a system includes: a first ring amplifier including a first bias node; and a reference current source coupled to the first bias node to provide a controlled current through a first inverter of the first ring amplifier. Attached Figure Description

[0006] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0007] Figure 1 This is a schematic diagram of a self-biased ring amplifier based on existing technology;

[0008] Figure 2AThis is a schematic diagram of a controlled current biased ring amplifier according to an embodiment;

[0009] Figure 2B This is a schematic diagram of a bandgap core circuit for generating a reference voltage according to an embodiment;

[0010] Figure 2C This is a schematic diagram of a PVT current source, including a bandgap core circuit and a voltage-to-current converter, used for... Figure 2A In a controlled current-biased ring amplifier; and

[0011] Figure 3 This is according to the usage of the embodiments. Figure 2A A schematic diagram of a silicon microphone system with two controlled current biased ring amplifiers. Detailed Implementation

[0012] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific environments. The specific embodiments discussed are merely illustrative of specific ways of manufacturing and using the invention and do not limit the scope of the invention.

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and which illustrate specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the invention. For example, features illustrated or described for one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another embodiment. The invention is intended to include these modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, identical or similar elements are designated by corresponding reference numerals in different drawings.

[0014] According to an embodiment, the ring amplifier uses a current source from a voltage reference generator to stabilize the current of the first-stage inverter (which typically accounts for the majority of the total current consumption due to noise constraints). Specifically, the ring amplifier includes a high-impedance bias network acting on the gates of the PMOS or NMOS transistors in the first inverter. The PMOS or NMOS gate voltage sets the desired bias current through the first inverter and tracks PVT changes, thereby maintaining stable power and performance of the ring amplifier. This ring amplifier, the corresponding method, and the silicon microphone system will be explained in further detail below.

[0015] Figure 1This is a schematic diagram of a self-biased ring amplifier 100 according to the prior art. The self-biased ring amplifier includes a chain of three inverters P2 / N2, P3 / N3, and P4 / N4, where P2, P3, and P4 are PMOS transistors, and where N2, N3, and N4 are NMOS transistors. These inverters are coupled between a first power supply voltage rail 102 and a second power supply voltage rail 104. Figure 1 In this circuit, the body contacts of PMOS transistors P2, P3, and P4 are coupled to the first power supply voltage rail 102. The input of inverter P2 / N2 is coupled to the Vin input node, and the output of inverter P2 / N2 is coupled to node 106. The input of inverter P3 / N3 is coupled to node 106. The drain of transistor P3 is coupled to node 108, and the drain of transistor N3 is coupled to node 110. The gate of transistor P4 is coupled to node 108, and the gate of transistor N4 is coupled to node 110. The output of inverter P4 / N4 is coupled to the Vout output node. A "dead zone" is achieved by a resistor Rmid coupled between nodes 108 and 110. The "dead zone" effectively generates the voltage required to achieve a small quiescent current at the output stage. This, in turn, effectively creates the dominant pole at the output, thereby dynamically stabilizing the negative feedback loop. Figure 1 (Not shown in the image). However, in this implementation, the current consumption of the self-biased ring amplifier 100 is not well controlled.

[0016] Figure 2A This is a schematic diagram of a controlled current biased ring amplifier 200 according to an embodiment. The controlled current biased ring amplifier 200 includes a ring amplifier comprising inverters P2 / N2, P3 / N3, P4 / N4 and resistor Rmid as previously described, a stable reference current source 202, and a PMOS transistor P1 configured with a diode. The stable reference current source 202 is used to generate a desired gate voltage Vbp that satisfies the current / noise tradeoff (primarily determined by the first inverter stage P2 / N2). The voltage Vbp is applied to the gate of transistor P2 via a high-ohm resistor 204 (Vpb_filt). The input (Vin) of the controlled current biased ring amplifier 200 is decoupled from Vpb_filt via capacitor Cfilt. The stable bandgap generated current and the matching between PMOS transistor P2 and the reference diode (PMOS transistor P1) ensure that Vbp_filt tracks any process, voltage, or temperature (PVT) changes, thereby maintaining current stability in the inverters (P2 / N2). In other words, PMOS transistors P1 and PMOS transistor P2 are in a current mirror configuration, and because the gate current is very low, the high-ohm resistor 204 does not significantly affect this configuration.

[0017] Figure 2BThis is a schematic diagram of a bandgap core circuit 210 used to generate a reference voltage. The bandgap core circuit 210 includes PMOS transistors P5 and PMOS transistor P6, whose sources are coupled together and connected to VDD, and whose gates are also coupled together. The bandgap core circuit 210 also includes a resistor divider located in the current path of PMOS transistor P5, consisting of resistors 212 and 214. The output of this resistor divider is coupled to the first input of amplifier 218. Resistor 216, located in the current path of PMOS transistor P6, is coupled to the second input of amplifier 218. The output of amplifier 218 is coupled to the gates of PMOS transistors P5 and PMOS transistor P6. The bandgap core circuit 210 also includes PNP bipolar transistors Q1 and Q2 in a coupling diode configuration. PNP bipolar transistor Q1 is coupled between resistor 214 and ground, and PNP bipolar transistor Q2 is coupled between resistor 216 and ground. A stable reference voltage VDD is generated. REF It is generated at the junction of the drain of PMOS transistor P6 and resistor 216.

[0018] Figure 2C This is a schematic diagram of a reference current source including a bandgap core circuit 210 and a voltage-current (V2I) generator 226, used for Figure 2A The controlled current biased ring amplifier 200 is described above. The bandgap core circuit 210 is as described above. In this embodiment, the V2I generator 226 includes an operational amplifier 224, PMOS transistors P7 and PMOS transistors P8, and a trimming resistor R. TRIM The positive input of operational amplifier 224 receives V. REF Voltage, and provides the output reference current I at the drain of PMOS transistor P8. REF The formula for the output reference current is I. REF =V REF / R TRIM The gates of PMOS transistors P7 and P8 are coupled together, and their sources are coupled to VDD. The drain of PMOS transistor P7 is coupled to resistor R. TRIM And the negative input of operational amplifier 224. PMOS transistor P7 typically corresponds to Figure 2A PMOS transistor P1, while PMOS transistor P8 typically corresponds to Figure 2A The PMOS transistor P2 in the middle.

[0019] Figure 3 This is according to the usage of the embodiments. Figure 2A A schematic diagram of a silicon microphone system 300 with two controlled current biased ring amplifiers. Figure 3The complete PGA structure for a microphone readout system is also shown, from the microelectromechanical system (MEMS) bias and source follower buffer to the implemented pseudo-differential ring amplifier-based PGA, which includes a first ring amplifier 312A and a second ring amplifier 312B.

[0020] The first ring amplifier 312A includes series-coupled inverters P2A / N2A, P3A / N3A, P4A / N4A and resistor RmidA, and a feedback path including a high-impedance resistor 310A and an adjustable capacitor C2A. The first ring amplifier 312A also includes an input capacitor C1A. The output of the first ring amplifier 312A is coupled to a first analog-to-digital converter (ADC), wherein... Figure 3 Only the adjustable input capacitor C3A for the first ADC is shown. In some embodiments, a single differential input ADC may be used instead of separate first and second ADCs.

[0021] Similarly, the second ring amplifier 312B includes series-coupled inverters P2B / N2B, P3B / N3B, and P4B / N4B, a resistor RmidB, and a feedback path including a high-impedance resistor 310B and an adjustable capacitor C2B. The second ring amplifier 312B also includes an input capacitor C1B. The output of the second ring amplifier 312B is coupled to a second analog-to-digital converter (ADC), wherein... Figure 3 Only the adjustable input capacitor C3B for the second ADC is shown. As mentioned above, a single differential ADC can also be used instead of the independent first and second ADCs.

[0022] The silicon microphone system 300 also includes a stable current source 202 as described above, which is coupled at node Vbp to a diode-configured PMOS transistor P1. The Vbp node is coupled to the Vbp_p bias node of the first ring amplifier 312A via a high-impedance resistor 204A. The Vbp bias node is coupled to the input of the first ring amplifier 312A via a capacitor CfiltA. The Vbp node is also coupled to the Vbp_n bias node of the second ring amplifier 312B via a high-impedance resistor 204B. The Vbp bias node is also coupled to the input of the second ring amplifier 312B via a capacitor CfiltB.

[0023] The silicon microphone system 300 includes a differential MEMS device 302, whose first output is coupled to the inputs of a first bias resistor 304A and a first source follower 306A, and whose second output is coupled to the inputs of a second bias resistor 304B and a second source follower 306B. A chopper 308 has its first input coupled to the first output (Out_p) of the first source follower 306A, and its second input coupled to the second output (Out_n) of the second source follower 306B. The first output of the chopper 308 is coupled to a capacitor C1A, and the second output of the chopper 308 is coupled to a capacitor C1B.

[0024] In short, such as Figure 2A The illustrated ring amplifier 200 includes: a plurality of series-coupled inverters P2 / N2, P3 / N3, and P4 / N4 coupled between an input node Vin and an output node Vout, wherein a first inverter P2 / N2 of the plurality of series-coupled inverters includes a bias node Vbp_filt; a dead-time generator Rmid coupled to the plurality of series-coupled inverters; and a bias generator including a current source 202 and a PMOS transistor P1, the bias generator being coupled to the bias node of the first inverter and configured to control the current through the first inverter. The ring amplifier 200 also includes: a resistor 204 inserted between the bias generator and the bias node of the first inverter; and a capacitor Cfilt coupled between the bias node of the first inverter and the input node. In an embodiment, the bias generator includes a bandgap circuit 210. In an embodiment, the resistor 204 includes at least one transistor biased in a cutoff region. In some embodiments, the dead-time generator Rmid is coupled to an inverter different from the first inverter in a plurality of series-coupled inverters, and may include resistor or diode circuitry. In Figure 2, the plurality of series-coupled inverters includes a total of three series-coupled inverters, but a different number of inverters may be used in other embodiments.

[0025] In summary, a method of operating a ring amplifier 200 includes a plurality of series-coupled inverters P2 / N2, P3 / N3, and P4 / N4 coupled between an input node Vin and an output node Vout, wherein a first inverter P2 / N2 of the plurality of series-coupled inverters includes a bias node Vbp_filt. The method includes: generating a reference voltage Vbp; and applying the reference voltage Vbp to the bias node Vbp_filt to provide a controlled current through the first inverter. In an embodiment, applying the reference voltage includes: applying the reference voltage Vbp via a resistor 204 coupled to the bias node Vpb_filt, and coupling a voltage at the input node Vin to the bias node Vpb_filt via a capacitor Cfilt. In an embodiment, generating the reference voltage Vbp includes: generating the reference voltage using a bandgap circuit 210. In some embodiments, the resistor 204 includes at least one transistor biased in a cutoff region. In some embodiments, the method includes: using a resistor Rmid, a transistor, or a diode circuit coupled to an intermediate inverter in the plurality of series-coupled inverters to generate a dead zone region in the DC transfer characteristics of the plurality of series-coupled inverters.

[0026] In summary, according to the embodiments, Figure 3The system 300 shown includes: a first ring amplifier 312A, which includes a first bias node Vbp_p; and a reference current source 202 coupled to the first bias node Vbp_p to provide a controlled current through a first inverter P2A / N2A of the first ring amplifier 312A. The system 300 also includes: a first resistor 204A inserted between the reference current source 202 and the first bias node Vbp_p; and a first filter capacitor CfiltA coupled between the first bias node Vbp_p and the first input node of the first ring amplifier 312A. The system also includes: a first input capacitor C1A coupled to the first input node, and a first adjustable feedback capacitor C2A coupled between the first input node and the output node of the first ring amplifier. The system 300 also includes a first adjustable analog-to-digital converter (ADC) input capacitor C3A coupled to the output node of the first ring amplifier 312A. System 300 also includes a second ring amplifier 312B, which includes a second bias node Vbp_n coupled to a reference current source 202 to provide a stable current through the first inverter P2B / N2B of the second ring amplifier 312B. System 300 also includes: a chopper 308 coupled to a first input node of the first ring amplifier 312A and a second input node of the second ring amplifier 312B; a first source follower circuit 306A and a second source follower circuit 306B coupled to the chopper 308; and a microelectromechanical system (MEMS) device 302 coupled to the first source follower circuit 306A and the second source follower circuit 306B. In some embodiments, capacitors C3A and C3B may also be coupled to the differential input of a single differential ADC.

[0027] In some embodiments, the gate of the PMOS or NMOS transistor in the first inverter can be used as a bias node. It is also possible to use both the gates of the PMOS and NMOS transistors simultaneously. However, when using both transistor gates simultaneously, a DC output voltage regulation loop is required to set the operating point. In some embodiments, the gate of the PMOS or NMOS transistor in a subsequent inverter can also be used as a bias node.

[0028] In some embodiments that do not require extremely low supply voltages, a cascode PMOS transistor configuration or a cascode NMOS transistor configuration can be implemented to separate the bias node and the input node. Other circuit variations can also be used to control the current through the first inverter at the core of the ring amplifier.

[0029] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0030] Example 1. According to an embodiment, a ring amplifier includes: a plurality of series-coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series-coupled inverters includes a bias node; a dead-time generator coupled to the plurality of series-coupled inverters; and a bias generator coupled to the bias node of the first inverter, the bias generator being configured to control the current through the first inverter.

[0031] Example 2. The ring amplifier according to Example 1 further includes: a resistor inserted between the bias generator and the bias node of the first inverter; and a capacitor coupled between the bias node of the first inverter and the input node.

[0032] Example 3. A ring amplifier according to any of the above examples, wherein the bias generator includes a bandgap circuit.

[0033] Example 4. A ring amplifier according to any of the above examples, wherein the resistor includes at least one transistor biased in the cutoff region.

[0034] Example 5. A ring amplifier according to any of the above examples, wherein a dead-time generator is coupled to an inverter different from the first inverter among a plurality of series-coupled inverters.

[0035] Example 6. A ring amplifier according to any of the above examples, wherein the dead-time generator comprises a resistor or diode circuit.

[0036] Example 7. A ring amplifier according to any of the above examples, wherein the plurality of series-coupled inverters comprise a total of three series-coupled inverters.

[0037] Example 8. According to an embodiment, a method of operating a ring amplifier including a plurality of series-coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series-coupled inverters includes a bias node, the method comprising: generating a reference voltage; and applying the reference voltage to the bias node to provide a controlled current through the first inverter.

[0038] Example 9. According to the method of Example 8, applying the reference voltage includes: applying the reference voltage via a resistor coupled to the bias node, and coupling the voltage at the input node to the bias node via a capacitor.

[0039] Example 10. The method according to any of the above examples, wherein generating the reference voltage includes generating the reference voltage using a bandgap circuit.

[0040] Example 11. The method according to any of the above examples, wherein the resistor includes at least one transistor biased in the cutoff region.

[0041] Example 12. The method according to any of the above examples further includes: using a resistor, transistor, or diode circuit coupled to an intermediate inverter in a plurality of series-coupled inverters to generate a dead zone region in the DC transfer characteristics of the plurality of series-coupled inverters.

[0042] Example 13. According to an embodiment, a system includes: a first ring amplifier including a first bias node; and a reference current source coupled to the first bias node to provide a controlled current through a first inverter of the first ring amplifier.

[0043] Example 14. The system according to Example 13 further includes: a first resistor inserted between a reference current source and a first bias node; and a first filter capacitor coupled between the first bias node and a first input node.

[0044] Example 15. The system according to any of the above examples further includes a first input capacitor and a first adjustable feedback capacitor, the first input capacitor being coupled to a first input node and the first adjustable feedback capacitor being coupled between the first input node and the output node of the first ring amplifier.

[0045] Example 16. The system according to any of the above examples further includes a first adjustable analog-to-digital converter (ADC) input capacitor coupled to the output node of the first ring amplifier.

[0046] Example 17. The system according to any of the above examples further includes a second ring amplifier, which includes a second bias node coupled to a reference current source to provide a stable current through the first inverter of the second ring amplifier.

[0047] Example 18. The system according to any of the preceding examples further includes a chopper coupled to a first input node of the first ring amplifier and a second input node of the second ring amplifier.

[0048] Example 19. The system according to any of the preceding examples further includes a first source follower circuit and a second source follower circuit coupled to the chopper.

[0049] Example 20. The system according to any of the preceding examples further includes a microelectromechanical system (MEMS) device coupled to a first source follower circuit and a second source follower circuit.

[0050] While the present invention has been described with reference to exemplary embodiments, this description should not be construed as limiting. Those skilled in the art will clearly understand, upon referring to this description, various modifications and combinations of exemplary embodiments, as well as other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A ring amplifier, comprising: Multiple series-coupled inverters are coupled between an input node and an output node, wherein the first inverter of the multiple series-coupled inverters includes a bias node; Dead-time generator, coupled to the plurality of series-coupled inverters; as well as A bias generator, coupled to the bias node of the first inverter, is configured to control the current through the first inverter.

2. The ring amplifier according to claim 1, further comprising: A resistor is inserted between the bias generator and the bias node of the first inverter; as well as A capacitor is coupled between the bias node and the input node of the first inverter.

3. The ring amplifier according to claim 1, wherein the bias generator includes a bandgap circuit.

4. The ring amplifier of claim 2, wherein the resistor comprises at least one transistor biased in a cutoff region.

5. The ring amplifier of claim 1, wherein the dead-time generator is coupled to an inverter of the plurality of series-coupled inverters that is different from the first inverter.

6. The ring amplifier of claim 5, wherein the dead zone generator comprises a resistor or diode circuit.

7. The ring amplifier of claim 1, wherein the plurality of series-coupled inverters comprises a total of three series-coupled inverters.

8. A method of operating a ring amplifier, the ring amplifier including a plurality of series-coupled inverters coupled between an input node and an output node, wherein a first inverter of the plurality of series-coupled inverters includes a bias node, the method comprising: Generate a reference voltage; as well as The reference voltage is applied to the bias node to provide a controlled current through the first inverter.

9. The method of claim 8, wherein applying the reference voltage comprises: The reference voltage is applied via a resistor coupled to the bias node, and the voltage at the input node is coupled to the bias node via a capacitor.

10. The method of claim 8, wherein generating the reference voltage comprises: The reference voltage is generated using a bandgap circuit.

11. The method of claim 9, wherein the resistor comprises at least one transistor biased in a cutoff region.

12. The method according to claim 8, further comprising: A dead zone region is generated in the DC transfer characteristics of the plurality of series-coupled inverters by using a resistor, transistor, or diode circuit coupled to an intermediate inverter in the plurality of series-coupled inverters.

13. A system comprising: The first ring amplifier includes a first bias node; as well as A reference current source is coupled to the first bias node to provide a controlled current through the first inverter of the first ring amplifier.

14. The system of claim 13, further comprising: A first resistor is inserted between the reference current source and the first bias node; as well as The first filter capacitor is coupled between the first bias node and the first input node.

15. The system of claim 14, further comprising a first input capacitor and a first adjustable feedback capacitor, the first input capacitor being coupled to the first input node, and the first adjustable feedback capacitor being coupled between the first input node and the output node of the first ring amplifier.

16. The system of claim 15, further comprising a first adjustable analog-to-digital converter (ADC) input capacitor coupled to the output node of the first ring amplifier.

17. The system of claim 13, further comprising a second ring amplifier, the second ring amplifier including a second bias node coupled to the reference current source to provide a stable current through the first inverter of the second ring amplifier.

18. The system of claim 17 further includes a chopper coupled to a first input node of the first ring amplifier and a second input node of the second ring amplifier.

19. The system of claim 18 further includes a first source follower circuit and a second source follower circuit coupled to the chopper.

20. The system of claim 19 further includes a microelectromechanical system (MEMS) device coupled to the first source follower circuit and the second source follower circuit.

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