Power amplifier circuit, communication device

Abstract

The embodiment of the application provides a power amplifier circuit and a communication device, relates to the technical field of communication, and comprises a main amplification module and a peak amplification module, the main amplification module comprises M circuit units, the first ends of the M circuit units are connected together, and the second ends of the M circuit units are connected through a transmission line; the peak amplification module comprises N circuit units, the first ends of the N circuit units are connected together, and the second ends of the N circuit units are connected through a transmission line; and the output end of the main amplification module and the output end of the peak amplification module are connected with a common load through an output combining network. By taking the circuit unit as a subcircuit of the main amplification module, the circuit unit has a backoff efficiency adjusting function, can offset impedance changes of an external port, can maintain the load of an internal main transistor in an original modulation depth range, and cannot be enlarged with an increase in the total number of paths. The coupling relationship between multi-path expansion and bandwidth is decoupled, and multi-path backoff high efficiency and wideband working performance are considered.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more specifically, to a power amplifier circuit and a communication device. Background Technology

[0002] With the widespread promotion of green environmental protection and low-carbon economy concepts, people have increasingly higher requirements for reducing the power consumption of wireless communication systems. In wireless communication systems, the radio frequency power amplifier in the base station equipment is one of the core modules of the system and accounts for a relatively high proportion of the power consumption in the base station. Therefore, in order to reduce the power consumption of base station equipment, it is necessary to improve the efficiency of the power amplifier.

[0003] In related technologies, a Doherty power amplifier is used, in which the main amplifier and the peak amplifier respectively handle different input signal power, so that both power amplifiers operate in their respective saturation regions as much as possible, thereby ensuring that the entire power amplifier maintains high efficiency over the widest possible range of input signal power.

[0004] However, power amplifiers in related technologies cannot simultaneously achieve high efficiency with multiple back-off and wideband performance. Summary of the Invention

[0005] This invention provides a power amplifier circuit and a communication device to at least solve the problem in the related art that power amplifiers cannot simultaneously achieve high efficiency with multiple back-off and wideband performance.

[0006] According to an embodiment of the present invention, a power amplifier circuit is provided, comprising: a main amplification module and a peak amplification module, wherein:

[0007] The main amplification module includes M circuit units, the first ends of the M circuit units are connected together, and the second ends of the M circuit units are connected through transmission lines;

[0008] The peak amplification module includes N circuit units, the first ends of the N circuit units are connected together, and the second ends of the N circuit units are connected through a transmission line.

[0009] The output terminals of the main amplification module and the peak amplification module are connected to a common load through an output combining network.

[0010] Each of the circuit units includes a main transistor and at least one peak transistor. The first terminal of the main transistor and the first terminal of the at least one peak transistor are connected together as the first terminal of the circuit unit. The second terminal of the main transistor and the second terminal of the at least one peak transistor are connected through a transmission line and serve as the second terminal of the circuit unit. The main transistor of at least one of the M circuit units is in a conducting state when no signal is connected to the input terminal of the main amplification module. Each transistor in the N circuit units is in a non-conducting state when no signal is connected to the input terminal of the peak amplification module. M and N are both positive integers, and N is greater than or equal to M.

[0011] In an exemplary embodiment, at least one of the M circuit units and / or the N circuit units includes: a main transistor, a first peak transistor, and a second peak transistor. The main transistor, the first peak transistor, and the second peak transistor are connected according to a first connection method, which includes: the second terminal of the main transistor is connected to the second terminal of the first peak transistor via a transmission line; the second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via a transmission line; and the second terminal of the second peak transistor serves as the second terminal of the circuit unit.

[0012] In one exemplary embodiment, at least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method; and at least one circuit unit of the second module includes: a main transistor and a first peak transistor, the main transistor and the first peak transistor being connected by a second connection method, the second connection method including: the second terminal of the main transistor being connected to the second terminal of the first peak transistor via a transmission line; the second terminal of the first peak transistor serving as the second terminal of the circuit unit; the first module being one of the main amplification module and the peak amplification module; and the second module being the other of the main amplification module and the peak amplification module.

[0013] In one exemplary embodiment, at least one circuit unit in the main amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method; at least one circuit unit in the peak amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method.

[0014] In an exemplary embodiment, at least one of the M circuit units and / or the N circuit units includes: a main transistor, a first peak transistor, and a second peak transistor. The main transistor, the first peak transistor, and the second peak transistor are connected in a third connection manner, which includes: the second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via a first transmission line; the second terminal of the second peak transistor is connected to the first terminal of the second transmission line; the second terminal of the main transistor is connected to the first terminal of the third transmission line; and the second terminal of the third transmission line is connected to the second terminal of the second transmission line as the second terminal of the circuit unit.

[0015] In one exemplary embodiment, at least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; and at least one circuit unit of the second module includes: a main transistor and a first peak transistor, the main transistor and the first peak transistor being connected by a second connection method, the second connection method including: the second terminal of the main transistor being connected to the second terminal of the first peak transistor via a transmission line; the second terminal of the first peak transistor serving as the second terminal of the circuit unit; wherein, the first module is one of the main amplification module and the peak amplification module, and the second module is the other of the main amplification module and the peak amplification module.

[0016] In one exemplary embodiment, at least one circuit unit in the main amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; at least one circuit unit in the peak amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method.

[0017] In one exemplary embodiment, at least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; and at least one circuit unit of the second module includes: a main transistor, a first peak transistor, and a second peak transistor, wherein the main transistor, the first peak transistor, and the second peak transistor are connected by a first connection method, the first connection method including: the second terminal of the main transistor is connected to the second terminal of the first peak transistor via a transmission line; the second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via a transmission line; and the second terminal of the second peak transistor serves as the second terminal of the circuit unit; wherein the first module is one of the main amplification module and the peak amplification module, and the second module is the other of the main amplification module and the peak amplification module.

[0018] In one exemplary embodiment, the power amplifier circuit includes: a first power divider, the input terminal of which is used to receive an input signal; a second power divider, the input terminal of which is connected to one output terminal of the first power divider, and the output terminal of the second power divider is connected to the control terminals of the main transistors and at least one peak transistor of the M circuit units respectively; and a third power divider, the input terminal of which is connected to one output terminal of the first power divider, and the output terminal of the third power divider is connected to the control terminals of the main transistors and at least one peak transistor of the N circuit units respectively.

[0019] In one exemplary embodiment, the power amplifier circuit includes: a first power divider, the input terminal of which is used to receive an input signal, and the output terminal of which is connected to the control terminals of the main transistors and at least one peak transistor of the M circuit units respectively; and a second power divider, the input terminal of which is used to receive an input signal, and the output terminal of which is connected to the control terminals of the main transistors and at least one peak transistor of the N circuit units respectively.

[0020] In one exemplary embodiment, the electrical phase of the impedance of the transmission line satisfies (2A+1). 90°, where A is an integer greater than or equal to 0.

[0021] In one exemplary embodiment, the characteristic impedance of the transmission line is determined based on the normalized power of the transistor of the corresponding connected circuit unit, the intrinsic power impedance of the transistor of the corresponding connected circuit unit, and the apparent impedance of the corresponding connected circuit unit to the outside.

[0022] According to another embodiment of the present invention, a communication device is provided, the communication device including the power amplifier circuit as described above.

[0023] In the above embodiments of the present invention, by using circuit units with a Doherty circuit architecture as sub-circuits of the main amplification module, first-order modulation of the circuit unit and second-order modulation at the module level are achieved. The peak amplification module does not directly modulate the bottom-level main transistor, but first modulates the overall port impedance of the main amplification module. The main amplification module itself includes a complete Doherty circuit unit, which has independent active load modulation capability and can buffer external impedance changes through the synchronous turn-on of the internal peak transistor. The main transistor is located inside the circuit unit of the main amplification module, and the impedance change directly faced by the main transistor is determined only by the peak-to-main power ratio inside the circuit unit. The active modulation of the circuit unit itself controls the load impedance of the main transistor within a fixed high-efficiency range. This modulation depth is determined during the circuit unit design and does not change with the expansion of the external module level. Even if the number of peak amplification modules is increased, the total power is expanded, and the back-off depth is increased, the newly added peak current will only act on the combining point of the module, changing only the overall apparent impedance of the main amplification module. The circuit units in the main amplification module, acting as active Doherty circuits, synchronously activate their internal peak transistors and inject internal current to offset impedance changes at external ports. This ensures that the load on the internal main transistors remains within the original modulation depth range, without proportionally increasing with the total number of paths. This decouples the multi-path expansion from the bandwidth, thus achieving a balance between high efficiency with multi-path backoff and wideband performance. Attached Figure Description

[0024] Figure 1 This is a structural diagram of a power amplifier circuit according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a two-way partial structure of a circuit unit according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a three-way partial structure of a circuit unit according to an embodiment of the present invention;

[0027] Figure 4 This is a structural diagram of a dual-module power amplifier circuit according to an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the dual-module circuit structure of a power amplifier circuit according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the two-way and three-way combined circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the dual three-channel circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0031] Figure 8 This is a partial structural diagram of the adjustment of the three output terminals of the circuit unit according to an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of another circuit structure for a two-way and three-way power amplifier circuit according to an embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of another dual-three-channel circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0034] Figure 11 This is a schematic diagram of another dual-three-channel circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0035] Figure 12 This is a schematic diagram of the dual two-channel circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0036] Figure 13 This is a schematic diagram of another dual-channel circuit structure of the power amplifier circuit according to an embodiment of the present invention;

[0037] Figure 14 This is a schematic diagram of the structure of a microstrip transmission line according to an embodiment of the present invention;

[0038] Figure 15 This is a schematic diagram of the structure of a semi-lumped transmission line according to an embodiment of the present invention;

[0039] Figure 16 This is a schematic diagram of another structure of a semi-lumped transmission line according to an embodiment of the present invention;

[0040] Figure 17 This is a schematic diagram of the structure of a lumped transmission line according to an embodiment of the present invention;

[0041] Figure 18 This is a schematic diagram of another structure of a lumped transmission line according to an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached diagram: 10-Main amplification module, 20-Peak amplification module, 30-Circuit unit, RL-Common load, Q1-Main transistor, Q2-Peak transistor, Q3-Second peak transistor, 40-First module, 50-Second module, K1-First power divider, K2-Second power divider, K3-Third power divider. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, power amplifiers in related technologies cannot simultaneously achieve high efficiency with multiple back-off and wide bandwidth performance. This is because in the multi-channel Doherty power amplifier architecture of related technologies, the impedance modulation depth of the main amplifier is strongly coupled with the number of parallel transistors. The more transistors connected, the larger the modulation ratio, leading to bandwidth contraction, thus making it impossible to achieve both high efficiency with multiple back-off and wide bandwidth performance. Specifically, multi-channel Doherty technology in related technologies typically employs a structure where multiple peak amplifiers are directly connected in parallel to impedance modulate the main amplifier. In this architecture, to achieve high-efficiency back-off performance, the number of parallel peak transistors needs to be increased. According to Doherty theory, as the number of parallel transistors increases, the required impedance transformation ratio (i.e., modulation depth) of the main amplifier also increases linearly or non-linearly. For example, in the classic four-channel Doherty architecture, the modulation depth of the main amplifier typically needs to reach four times or even higher. According to the Bode-Fano constraint theory, the matchable bandwidth of a power amplifier is inversely proportional to the impedance transformation ratio (modulation depth). When the impedance modulation depth of the main amplifier increases, its effective operating bandwidth contracts sharply. This means that while increasing the number of transistors improves efficiency under light load, it sacrifices bandwidth performance, causing the amplifier to lose its ability to maintain good impedance matching and efficiency characteristics across a wide bandwidth. Conversely, if the modulation depth is limited to ensure bandwidth performance, the efficiency advantage of multi-channel Doherty technology in light load scenarios cannot be fully utilized.

[0046] Therefore, to address the strong coupling between the impedance modulation depth and the number of transistors in the main amplifier, and to maintain a low impedance modulation ratio to ensure broadband performance while increasing the number of transistor channels to improve back-off efficiency, this application provides a novel power amplifier circuit architecture. By using circuit units employing a Doherty circuit architecture as sub-circuits of the main amplifier module, second-order modulation (first-order modulation of the circuit unit plus second-order modulation of the module) is achieved. The peak amplifier module does not directly modulate the bottom-level main transistor; instead, it first modulates the overall port impedance of the main amplifier module. The main amplifier module itself is a complete Doherty circuit with independent active load modulation capability, which can buffer external impedance changes through the synchronous turn-on of internal peak transistors. The main transistor is located inside the circuit unit of the main amplifier module, and the impedance change directly faced by the main transistor is determined only by the peak-to-main power ratio within the circuit unit. The active modulation of the circuit unit itself controls the load impedance of the main transistor within a fixed high-efficiency range. This modulation depth is determined during the circuit unit design and does not change with external module-level expansion. Even with increased peak amplifier modules, expanded total power, and increased back-off depth, the added peak current only affects the module's combining point, altering the overall apparent impedance of the main amplifier module. The circuit units within the main amplifier module, acting as active Doherty circuits, simultaneously activate their internal peak transistors and inject internal current to offset impedance changes at external ports. This ensures the load on the internal main transistors remains within the original modulation depth range, without proportionally increasing with the total number of paths. This decouples the multi-path expansion from bandwidth, thus achieving a balance between high efficiency with multi-path back-off and wideband performance.

[0047] Embodiments of this application provide a power amplifier circuit, such as Figure 1 As shown, it includes: a main amplification module 10 and a peak amplification module 20, wherein:

[0048] The main amplification module 10 includes M circuit units 30, the first ends of the M circuit units 30 are connected together, and the second ends of the M circuit units 30 are connected through transmission lines.

[0049] The peak amplification module 20 includes N circuit units 30, the first ends of the N circuit units 30 are connected together, and the second ends of the N circuit units 30 are connected through transmission lines.

[0050] Specifically, the power amplifier circuit employs a two-layer architecture of modular modulation modules. The circuit is divided into two high-level modules: a main amplification module 10 responsible for providing basic power and back-off efficiency, and a peak amplification module 20 responsible for providing additional power gain under large signal input conditions. The main amplification module 10 contains M independent circuit units 30, each of which is itself a complete and independent Doherty circuit. The peak amplification module 20 contains N independent circuit units 30, each of which is itself a complete and independent Doherty circuit.

[0051] The output terminals of the main amplification module 10 and the peak amplification module 20 are connected to the common load RL through an output combining network.

[0052] Specifically, the signal synthesized by the main amplification module 10 and the peak amplification module 20 through a combining network drives a common load RL (such as an antenna or a next-stage circuit).

[0053] Among them, such as Figure 2 As shown, any circuit unit 30 includes: a main transistor Q1 and at least one peak transistor Q2. The first terminal of the main transistor Q1 and the first terminal of the at least one peak transistor Q2 are connected together as the first terminal of the circuit unit 30. The second terminal of the main transistor Q1 and the second terminal of the at least one peak transistor Q2 are connected through a transmission line and serve as the second terminal of the circuit unit 30. The main transistor Q1 of at least one of the M circuit units 30 is in a conducting state when no signal is applied to the input terminal of the main amplification module 10, i.e., Class AB bias. Each transistor in the N circuit units 30 is in a non-conducting state when no signal is applied to the input terminal of the peak amplification module 20, i.e., not higher than Class B bias. M and N are both positive integers, and N is greater than or equal to M.

[0054] Specifically, the main transistor Q1 of circuit unit 30 in the main amplification module 10 is Class AB (or Class A) biased, meaning it is in the on state when there is no signal input. This ensures that the main amplification module 10 can operate independently and provide high efficiency in deep back-off (light load) scenarios, which is a prerequisite for the Doherty amplifier to improve back-off efficiency. The transistors in the peak amplification module 20 are Class B or Class C biased (i.e., no quiescent current or extremely low quiescent current), meaning they are in the off state when there is no signal input. This ensures that the peak module does not consume power under light load and does not interfere with the operation of the main module when the signal amplitude is small. The number N of circuit units 30 in the peak amplification module 20 is not less than the number M of circuit units 30 in the main amplification module 10. This ratio is a necessary condition to ensure that the peak amplification module 20 has sufficient current drive capability to complete the load modulation of the main amplification module 10, and also provides a basis for the scalability of the architecture.

[0055] Among them, such as Figure 2 The diagram shows the basic structure of circuit unit 30, including a main transistor Q1 and a peak transistor Q2. A transmission line connects the two transistors at their second terminals. This transmission line is not only a physical connection but also the impedance transformation element that realizes the core of the Doherty effect. Zsub is the characteristic impedance of the transmission line. The value of the characteristic impedance is related to the load impedance. It is calculated based on the intrinsic impedance of the transistor and the required power combining ratio to ensure correct impedance modulation at a specific power level. θsub is the phase of the transmission line, which needs to satisfy (2A+1). 90°, where A is an integer greater than or equal to 0. The phase of the transmission line must be chosen to satisfy (2A+1). The 90° angle is due to the impedance reversal of the quarter-wavelength line, which is the basis of Doherty circuit modulation. The core mechanism for Doherty circuits to achieve high back-off efficiency is active load modulation. At low power, only the main amplifier module operates, resulting in a high load impedance and the main transistor operating in its high-efficiency voltage region. As power increases, the peak amplifier module turns on, injecting current into the output node and actively changing the load impedance of the main amplifier module, ensuring the main transistor remains at its high-efficiency operating point. The physical carrier for this impedance modulation is a transmission line with an odd-order multiple of 90° electrical phase, which ensures that the input impedance is inversely proportional to the load impedance, exhibiting impedance reversal characteristics. The current injected by the peak amplifier module increases the load impedance; after reversal via the 90° phase of the transmission line, the impedance of the main amplifier module decreases synchronously, thus completing active load modulation. Therefore, the phase of the transmission line needs to satisfy (2A+1). 90°.

[0056] Among them, such as Figure 3The diagram shows a simplified structure of a power amplifier circuit, including a main amplification module 10 and a peak amplification module 20. The main amplification module 10 is not a single transistor, but a module composed of at least one circuit unit 30, responsible for providing basic output power and back-off efficiency during light load and low-to-medium power stages. The peak amplification module 20 is also a module composed of at least one circuit unit 30, which turns on during high power input. By injecting current into the synthesis point, it modulates the output of the main amplification module 10, thereby improving efficiency under large signal conditions.

[0057] like Figure 4 The diagram shows the simplified structure of the power amplifier circuit. The main amplification module 10 contains a 2-way circuit unit 30, namely a main transistor Q1 and a peak transistor Q2. The peak amplification module 20 also contains a 2-way circuit unit 30, namely a main transistor Q1 and a peak transistor Q2.

[0058] In this embodiment, by using the Doherty circuit architecture-based circuit unit 30 as a sub-circuit of the main amplification module 10, first-order modulation of the circuit unit 30 and second-order modulation at the module level are achieved. The peak amplification module 20 does not directly modulate the bottom-level main transistor Q1, but first modulates the overall port impedance of the main amplification module 10. The main amplification module 10 itself includes a complete Doherty circuit unit 30, which has independent active load modulation capability and can buffer external impedance changes through the synchronous turn-on of the internal peak transistor. The main transistor Q1 is located inside the circuit unit 30 of the main amplification module 10, and the impedance change directly faced by the main transistor Q1 is determined only by the peak-to-main power ratio inside the circuit unit 30. The active modulation of the circuit unit 30 itself controls the load impedance of the main transistor Q1 within a fixed high-efficiency range. This modulation depth is determined during the design of the circuit unit 30 and does not change with the expansion of the external module level. Even if the number of peak amplification modules 20 is increased, the total power is expanded, and the back-off depth is increased, the newly added peak current will only act on the combining point of the module, changing only the overall apparent impedance of the main amplification module 10. The circuit unit 30 in the main amplification module 10, as an active Doherty circuit, synchronously turns on the internal peak transistor and injects internal current to offset the impedance changes at the external ports. This ensures that the load of the internal main transistor Q1 remains within the original modulation depth range and does not increase proportionally with the increase in the total number of paths. This decouples the coupling relationship between multiplex expansion and bandwidth, thus achieving both high efficiency of multiple back-off and wideband operating performance.

[0059] In one embodiment, such as Figure 5As shown, at least one of the M circuit units 30 and / or N circuit units 30 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3. The main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 are connected according to a first connection method, which includes:

[0060] The second terminal of the main transistor Q1 is connected to the second terminal of the first peak transistor Q2 via a transmission line.

[0061] The second terminal of the first peak transistor Q2 is connected to the second terminal of the second peak transistor Q3 via a transmission line.

[0062] The second terminal of the second peak transistor Q3 serves as the second terminal of circuit unit 30.

[0063] Specifically, the circuit unit 30 can be a 3-way structure including a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3. The output terminal of the radio frequency signal of the circuit unit 30 is defined at the output terminal of the second peak transistor Q3, thereby realizing a cascaded Doherty circuit.

[0064] In this embodiment, circuit unit 30 can adopt a 3-way structure, thereby achieving higher saturation power compared to a 2-way structure, making it suitable for scenarios with high requirements for large signal driving capability. By implementing two-stage active load modulation through the graded turn-on of the two peak transistors, a deeper back-off efficiency range can be achieved compared to the 2-way structure. The graded modulation allows the main transistor Q1 to maintain its optimal impedance range over a wider back-off power range.

[0065] In one embodiment, such as Figure 6 As shown, at least one circuit unit 30 of the first module 40 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a first connection manner.

[0066] Furthermore, at least one circuit unit 30 of the second module 50 includes a main transistor Q1 and a first peak transistor Q2, which are connected according to a second connection method. This second connection method includes connecting the second terminal of the main transistor Q1 to the second terminal of the first peak transistor Q2 via a transmission line. The second terminal of the first peak transistor Q2 serves as the second terminal of the circuit unit 30. The first module 40 is one of the main amplification module 10 and the peak amplification module 20, and the second module 50 is the other of the main amplification module 10 and the peak amplification module 20.

[0067] In this embodiment, the first module 40 adopts a 3-way circuit structure containing three transistors. Compared to a two-way structure, the three-way structure can provide greater current combining capability and higher saturation power output. This improves the driving capability and output power limit of the power amplifier in high-signal (high-power) scenarios, making it suitable for base station applications with high peak power requirements. The second module 50 adopts a 2-way circuit containing two transistors. 2-way circuits generally have better bandwidth characteristics than 3-way circuits. Designing the main amplification module 10 as a 2-way structure helps maintain a wider impedance matching bandwidth within the main amplification module 10. The combination of one module using a 2-way structure and the other using a 3-way structure utilizes both the main bandwidth advantage of the 2-way structure and the peak power advantage of the 3-way structure, achieving a good balance between broadband performance and high power output.

[0068] In one embodiment, such as Figure 7 As shown, at least one circuit unit 30 in the main amplification module 10 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a first connection manner.

[0069] At least one circuit unit 30 in the peak amplification module 20 includes a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a first connection manner.

[0070] In this embodiment, both the main amplification module 10 and the peak amplification module 20 adopt a 3-way circuit structure, enabling each circuit unit 30 to provide greater current combining capability and improve power output. Secondly, since the main amplification module 10 and the peak amplification module 20 use identical circuit structures, this means that the transistors constituting these two modules can be consistent in model, specifications, and even packaging. This structural symmetry allows designers to use a unified bill of materials in the procurement and production stages, eliminating the need to prepare transistors of different specifications for different modules. This significantly reduces material management costs, simplifies supply chain complexity, and improves production yield and consistency.

[0071] In one embodiment, such as Figure 8 As shown, at least one of the M circuit units 30 and / or N circuit units 30 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3. The main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 are connected according to a third connection method, which includes:

[0072] The second terminal of the first peak transistor Q2 is connected to the second terminal of the second peak transistor Q3 via the first transmission line.

[0073] The second terminal of the second peak transistor Q3 is connected to the first terminal of the second transmission line.

[0074] The second terminal of the main transistor Q1 is connected to the first terminal of the third transmission line, and the second terminal of the third transmission line is connected to the second terminal of the second transmission line as the second terminal of the circuit unit 30.

[0075] In this embodiment, a 3-way circuit unit 30 structure is provided, and the output terminal of the circuit unit 30 is designed to be located inside the circuit unit 30, while the first peak transistor Q2 is located on the periphery of the circuit unit 30. By moving the output port inward, the transmission line path from the main amplification branch to the output terminal is shortened, reducing the trace loss and parasitic radiation at high frequencies; at the same time, the cascaded structure of the peak branch is more compact, and the phase deviation caused by transmission line dispersion is smaller.

[0076] In one embodiment, such as Figure 9 As shown, at least one circuit unit 30 of the first module 40 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a third connection manner.

[0077] Furthermore, at least one circuit unit 30 of the second module 50 includes: a main transistor Q1 and a first peak transistor Q2, wherein the main transistor Q1 and the first peak transistor Q2 are connected according to a second connection method, the second connection method including: the second terminal of the main transistor Q1 is connected to the second terminal of the first peak transistor Q2 through a transmission line. The second terminal of the first peak transistor Q2 serves as the second terminal of the circuit unit 30.

[0078] The first module 40 is one of the main amplification module 10 and the peak amplification module 20, and the second module 50 is the other of the main amplification module 10 and the peak amplification module 20.

[0079] In this embodiment, the first module 40 adopts a 3-way circuit structure containing three transistors. Compared to a two-way structure, the three-way structure can provide greater current combining capability and higher saturation power output. This improves the driving capability and output power limit of the power amplifier in high-signal (high-power) scenarios, making it suitable for base station applications with high peak power requirements. The second module 50 adopts a 2-way circuit containing two transistors. 2-way circuits generally have better bandwidth characteristics than 3-way circuits. Designing the main amplification module 10 as a 2-way structure helps maintain a wider impedance matching bandwidth within the main amplification module 10. The combination of one module using a 2-way structure and the other using a 3-way structure utilizes both the main bandwidth advantage of the 2-way structure and the peak power advantage of the 3-way structure, achieving a good balance between broadband performance and high power output.

[0080] In one embodiment, such as Figure 10 As shown, at least one circuit unit 30 in the main amplification module 10 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a third connection manner.

[0081] At least one circuit unit 30 in the peak amplification module 20 includes a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a third connection manner.

[0082] In this embodiment, both the main amplification module 10 and the peak amplification module 20 adopt a 3-way circuit structure, enabling each circuit unit 30 to provide greater current combining capability and improve power output. Secondly, since the main amplification module 10 and the peak amplification module 20 use identical circuit structures, this means that the transistors constituting these two modules can be consistent in model, specifications, and even packaging. This structural symmetry allows designers to use a unified bill of materials in the procurement and production stages, eliminating the need to prepare transistors of different specifications for different modules. This significantly reduces material management costs, simplifies supply chain complexity, and improves production yield and consistency.

[0083] In one embodiment, such as Figure 11 As shown, at least one circuit unit 30 of the first module 40 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3 connected in a third connection manner.

[0084] Furthermore, at least one circuit unit 30 of the second module 50 includes: a main transistor Q1, a first peak transistor Q2, and a second peak transistor Q3, wherein the main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 are connected according to a first connection method, the first connection method including:

[0085] The second terminal of the main transistor Q1 is connected to the second terminal of the first peak transistor Q2 via a transmission line.

[0086] The second terminal of the first peak transistor Q2 is connected to the second terminal of the second peak transistor Q3 via a transmission line.

[0087] The second terminal of the second peak transistor Q3 serves as the second terminal of circuit unit 30.

[0088] The first module 40 is one of the main amplification module 10 and the peak amplification module 20, and the second module 50 is the other of the main amplification module 10 and the peak amplification module 20.

[0089] In this embodiment, both the main amplification module 10 and the peak amplification module 20 adopt a 3-way circuit structure, thereby enabling each circuit unit 30 to provide greater current combining capability and improve power output. The first module 40 adopts a 3-way circuit structure with a first connection method, in which the main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 are cascaded sequentially. This makes the physical path of the two-stage modulation clear, the impedance calculation and phase compensation logic intuitive, and the difficulty of circuit debugging and mass production verification lower, making it suitable for rapid iterative engineering development. In the mid-to-low frequency bands below 3GHz, the RF wavelength is longer and the physical size of the transmission line is larger. This single-sided linear routing method is smoother, parasitic parameters are easier to control, the space utilization of the circuit board level wiring is higher, and the engineering implementation cost is lower. The second module 50 adopts a 3-way circuit structure with a third connection method. The transmission line path from the main transistor Q1 to the output port is significantly shortened, and the routing loss, phase dispersion deviation, and parasitic radiation at high frequencies are significantly reduced. It can maintain better bandwidth and efficiency performance in the 3GHz and above frequency bands, meeting the application requirements of the upper 3GHz frequency band.

[0090] In one embodiment, such as Figure 12 As shown, the power amplifier circuit includes: a first power divider K1, a second power divider K2, and a third power divider K3, wherein:

[0091] The input terminal of the first power divider K1 is used to receive the input signal RFin.

[0092] The first power divider K1 splits the input signal into two paths: one path goes to the main amplification module 10, and the other path goes to the peak amplification module 20. This achieves the initial power distribution of the input signal.

[0093] The input terminal of the second power divider K2 is connected to one output terminal of the first power divider K1, and the output terminal of the second power divider K2 is connected to the control terminal of the main transistor Q1 of the M circuit units 30 and at least one peak transistor.

[0094] The output of the second power divider K2 is connected to the control terminals (such as gates or bases) of the transistors in all circuit units 30 of the main amplification module 10. Each circuit unit 30 requires an input signal to drive it. The function of the second power divider K2 is to further distribute the signal of the main amplification signal branch to the main transistor Q1 and peak transistor of each circuit unit 30 in the main amplification module 10, ensuring that they receive in-phase drive signals to achieve correct modulation within the module.

[0095] The input terminal of the third power divider K3 is connected to one output terminal of the first power divider K1, and the output terminal of the third power divider K3 is connected to the control terminals of the main transistor Q1 of the N circuit units 30 and at least one peak transistor.

[0096] The output of the third power divider K3 is connected to the control terminals of the transistors in all circuit units 30 of the peak amplification module 20. The function of the third power divider K3 is to distribute the signal of the peak amplification signal branch to each circuit unit 30 within the peak amplification module 20.

[0097] A phase compensation line (Offsetθ) is set between the power divider and the peak transistor. Through phase compensation, it is ensured that when the peak transistor is turned on at a specific power level (such as the 6dB back-off point), its current injection is phase-matched with the current of the main transistor Q1.

[0098] In this embodiment, by setting a first power divider K1, a second power divider K2, and a third power divider K3, the input signal is distributed to all transistors, forming a hierarchical signal distribution network. This ensures that all transistors in the main amplification module 10 and the peak amplification module 20 can receive RF drive signals from the same source. Since the signal source is the same input port and is distributed through the power dividers, the signals received by each transistor have high phase consistency and amplitude correlation.

[0099] In one embodiment, such as Figure 13 As shown, the power amplifier circuit includes: a first power divider K1 and a second power divider K2, wherein:

[0100] The input terminal of the first power divider K1 is used to receive the input signal RFin1, and the output terminal of the first power divider K1 is connected to the control terminal of the main transistor Q1 of the M circuit units 30 and at least one peak transistor.

[0101] The first power divider K1 directly receives external radio frequency input signals at its input terminal. Its output terminal is directly connected to the control terminals (gate or base) of the main transistor Q1 and peak transistor of the M sub-circuit units 30 of the main amplifier module 10. The input signal is directly distributed by the first power divider K1 to all transistors inside the main amplifier module 10, simplifying the input matching network of the main amplifier module 10.

[0102] The input terminal of the second power divider K2 is used to receive the input signal RFin2, and the output terminal of the second power divider K2 is connected to the control terminal of the main transistor Q1 of N circuit units 30 and at least one peak transistor.

[0103] The input of the second power divider K2 directly receives the external radio frequency input signal. Its output is directly connected to the main transistor Q1 and the control terminal (gate or base) of the peak transistor in the N sub-circuit units 30 of the peak amplifier module 20. The input signal is directly distributed by the second power divider K2 to all transistors inside the peak amplifier module 20, simplifying the input matching network of the peak amplifier module 20.

[0104] In this embodiment, by setting a first power divider K1 and a second power divider K2, the main amplification module 10 and the peak amplification module 20 each have independent input ports, allowing independent control of the amplitude, phase, and frequency of the RF signals input to the main amplification module 10 and the peak amplification module 20. Thus, the system can control the input power and frequency response of the peak amplification module 20 as required to achieve performance optimization for different power application scenarios. The efficiency, linearity, or bandwidth of the amplifier at specific operating points (such as the back-off point or saturation point) can be precisely optimized by adjusting the independent input signal of the peak amplification module 20.

[0105] In one embodiment, the characteristic impedance of the transmission line is determined based on the normalized power of the transistor in the corresponding connected circuit unit, the intrinsic power impedance of the transistor in the corresponding connected circuit unit, and the apparent impedance of the corresponding connected circuit unit to the outside.

[0106] In one or more alternative embodiments, please continue to refer to Figure 12 The main amplification module 10 includes a main transistor Q1 and a first peak transistor Q2. The peak amplification module 20 also includes a main transistor Q1 and a first peak transistor Q2. Normalizing the intrinsic power of the main transistor Q1 in the main amplification module 10, we obtain the normalized power ratio of the main transistor Q1 and the first peak transistor Q2 in the main amplification module 10 as 1:P1:P2:P3. The intrinsic power impedance of the main transistor Q1 in the main amplifier module 10 is... The intrinsic power impedance is the modulation power impedance of the main transistor Q1 in the main amplifier module 10. The intrinsic power impedance is the optimal load impedance of the transistor, i.e., the optimal load value for achieving maximum power and highest efficiency when the transistor is saturated. It is determined by the device process and gate size, and is a fixed value after the transistor model is selected. Based on the intrinsic power impedance of the transistor, the module-level combining transmission line impedance of the peak amplifier module 20 is determined by the following formula. and the module-level transmission line impedance of the main amplification module 10 :

[0107]

[0108]

[0109] In this context, the normalized power ratio of the main transistor Q1 and the first peak transistor Q2 in the main amplification module 10, and the main transistor Q1 and the first peak transistor Q2 in the peak amplification module 20, is 1:P1:P2:P3. The intrinsic power impedance of the main transistor Q1 of the main amplifier module 10.

[0110]

[0111] in, The impedance of the transmission line in the circuit unit of the peak amplifier module 20. The modulation power impedance of the main transistor Q1 in the main amplification module 10 is the load impedance of the main transistor Q1 after the peak amplification module is fully turned on and modulated at full power. This is the common load impedance.

[0112] The modulation depth is MR, which is defined as the ratio of the modulation impedance to the intrinsic power impedance. By squaring equation (3) and dividing it by equation (1), the modulation depth MR of the main transistor Q1 of the main amplifier module 10 can be calculated:

[0113]

[0114] When the main transistor Q1 and the first peak transistor Q2 of the main amplification module 10 have the same power, equation (4) can be simplified to:

[0115] As can be seen from the above formula, the modulation depth of the main amplifier module 10 is only related to the following factors: the normalized intrinsic power impedance (P1) of the peak transistor inside the main amplifier module 10, and the impedance of the transmission line in the circuit unit of the peak amplifier module 20. Module-level combiner transmission line impedance And the common load RL. The total number of transistors is not a direct determinant of the modulation depth, thus achieving decoupling between the expansion of the number of transistors and the modulation depth. For example, based on formula (4), if we want the bandwidth and efficiency to be optimal when the number of circuit units in the main amplifier module 10 is 2, then the impedance design of the transmission line only needs to meet the following conditions: ,in, It is the characteristic impedance of the module-level combining transmission line, which is the quarter-wavelength transmission line impedance between the output of the main amplifier module and the system combining point. It is responsible for realizing the second-order impedance modulation at the module level. It is the transmission line characteristic impedance of the sub-Doherty circuit unit inside the main amplifier module, responsible for realizing the first-order impedance modulation inside the sub-circuit. RL is the final load impedance of the system, which is usually a standard 50Ω in RF base station systems.

[0116] The bandwidth of an amplifier is typically characterized using the Bode-Fano constraint:

[0117]

[0118] in, It is the magnitude of the port reflection coefficient, a function of frequency, and characterizes the degree of impedance matching. The smaller the value, the better the matching and the lower the reflected power. The intrinsic optimal power impedance of the transistor corresponds to the resistive component of the load. In a power amplifier scenario, this corresponds to the intrinsic optimal power impedance of the transistor. It is the parasitic capacitance component of the load, corresponding to the parasitic capacitance at the transistor output, and is an inherent reactance parameter of the device.

[0119] by Figure 12 For example, assuming that the main transistor and the peak transistor are both the same type of transistor with the same parasitic parameters, C is the intrinsic power impedance of the transistor. 寄生 If the capacitance is a transistor parasitic capacitance, then the Bode-Fano boundary is:

[0120]

[0121] It can be seen that the larger the modulation depth MR, the wider the impedance variation range of the main amplifier, the more severe the equivalent reactance mismatch, and the narrower the achievable bandwidth under the Bode-Fano constraint. Conversely, the smaller the modulation depth MR, the smaller the impedance variation range, the easier it is to achieve matching, and the wider the achievable operating bandwidth. The modulation depth MR of the 4-channel Doherty in related technologies is 4, while the second-order architecture of this application has MR=2 for the same 4-channel scale, with an impedance variation range only half that of the related technologies. Based on the Bode-Fano constraint derivation, under the same transistor conditions, the theoretical bandwidth limit of this architecture is approximately twice that of the 4-channel Doherty in related technologies.

[0122] In one or more alternative embodiments, please continue to refer to Figure 3 , Figure 4 The diagram shows three apparent impedances that significantly affect the main amplifier module: ZMD1, ZMD2, and ZMD3. ZMD1 is the apparent impedance of the main amplifier module at the load end, and ZMD2 is the apparent impedance of the main amplifier module. The impedance values ​​of ZMD2 and ZMD1 satisfy a quarter-wavelength transformation relationship, meaning ZMD1 and ZMD2 are inversely proportional. The power amplifier circuit includes the following typical operating conditions:

[0123]

[0124] Operating Condition 1: Deep Backoff Condition: Extremely low input power, corresponding to light load and high power backoff scenarios for base stations. The peak amplifier module is completely shut down; the peak amplifier module does not modulate the main amplifier module, and the peak amplifier of the main amplifier module is also turned off. Only the main transistor Q1 of the main amplifier module operates independently. After the peak module is turned off, it is equivalent to a high-impedance open circuit state. The apparent impedance ZMD1 of the main amplifier module at the load end is equal to the system load RL; the impedance is reversed through the quarter-wavelength transmission line between modules, and the apparent impedance ZMD2 at the main module port is a fixed value; the load impedance directly seen by the main transistor DM is the designed optimal power impedance ZMD3, operating in a high-efficiency state with optimal voltage and current matching. The main transistor DM has significant energy efficiency advantages under light load, and the low modulation depth and better matching bandwidth of the main transistor DM make it the main operating range for base stations in daily low-traffic scenarios, meeting the requirements of green energy saving.

[0125] Operating Condition 2: Low to Medium Power Operation. The input power increases to the first turn-on point, corresponding to a low to medium load flow scenario. The peak transistor DP of the main amplifier module turns on, and the first-stage peak transistor PM of the peak amplifier module turns on simultaneously, while the main transistor PP (second-stage peak transistor) of the peak amplifier module remains off. After the first-stage peak transistor PM of the peak amplifier module turns on, it injects current into the system load. The load RL is constant, so the apparent impedance ZMD1 of the main amplifier module at the load end increases. Due to the impedance reversal characteristic of the quarter-wavelength line, the apparent impedance ZMD2 at the port of the main amplifier module will decrease inversely. At the same time, the peak transistor DP inside the main amplifier module also turns on simultaneously, injecting current into the output end of the main amplifier module, which exactly offsets the decrease in ZMD2, so that the load impedance seen by the main transistor DM of the main amplifier module is always maintained in the optimal high-efficiency range, and is not directly modulated by changes at the external module level. All three transistors, DM, DP, and PM, operate in the high-efficiency region, and the overall circuit efficiency remains high, widening the high-efficiency power range.

[0126] Operating Condition 3: Medium to High Power Operation. The input power continues to increase to the second turn-on point, with all transistors turned on, but not yet reaching saturation output. Transistors DM and DP in the main amplifier module are all operational; transistors PM and PP in the peak amplifier module are also all turned on. Transistor DM maintains a high-efficiency state, while the peak amplifier module enters a high-power output state. After transistor PP turns on, active load modulation is first completed within the peak amplifier module, pulling transistor PM from a high-efficiency load state back to a high-power load state, enhancing the overall current output capability of the peak amplifier module. The total current injected into the load by the peak amplifier module further increases, with ZMD1 continuously rising and ZMD2 continuously decreasing. The output current of transistor DP in the main amplifier module also increases synchronously, continuing to maintain dynamic impedance balance, ensuring that the load impedance of transistor DM remains locked within the high-efficiency range. The main transistor DM continues to operate at high efficiency, with only the peak amplifier module entering a high-power state. Although the overall efficiency is slightly lower than in Operating Conditions 1 and 2, it is still far superior to multi-channel Doherty transistors of similar scale; achieving the effect of increasing output power without the main transistor leaving the high-efficiency region.

[0127] Operating Condition 4: Full Power Saturation Condition. The input power reaches its rated maximum value, and the circuit outputs full power, corresponding to a base station full-load traffic scenario. All transistors (DM, DP, PM, PP) in the main and peak amplifier modules are fully powered on, entering a saturated output state. The current output of the peak amplifier module reaches its upper limit, and the current of transistor DP in the main amplifier module is insufficient to offset the impedance drop at the module level, breaking the dynamic balance. Transistors DM and DP are pulled back to a high-power load state, and all transistors operate in a saturated high-power state, jointly completing full-power synthesis. All transistors can be fully modulated to a high-power saturation state, resulting in high power synthesis efficiency and no power loss. There is no oversaturation problem of the main amplifier common in multi-channel Doherty circuits in related technologies, avoiding the risk of burnout caused by the main voltage / current exceeding the safe operating area, resulting in better long-term reliability.

[0128] In one or more alternative embodiments, please continue to refer to Figure 2 The normalized power ratio of the main transistor Q1 and the peak transistor Q2 is 1:P (for ease of understanding, for example, if the power of the main transistor Q1 is 10W and the power of the peak transistor Q2 is 20W, then the normalized power ratio is 1:2). The impedance design requirements are as follows:

[0129]

[0130] in, The intrinsic power impedance of the main transistor Q1 is determined once both the main transistor Q1 and the peak transistor Q2 are selected. ZDload is the external apparent impedance of this sub-circuit.

[0131] In one or more alternative embodiments, please continue to refer to Figure 5 The normalized power of the main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 is 1:P1:P2, and the impedance relationship is as follows:

[0132]

[0133]

[0134] Where ZDload is the external apparent impedance of this circuit unit. The characteristic impedance of the first-stage transmission line, located near the output, connects the output ports of the first peak transistor Q2 and the second peak transistor Q3, serving as the impedance transformation carrier for the outer layer modulation of the circuit unit. It is the characteristic impedance of the second-stage transmission line close to the main transistor Q1, connecting the node of the main transistor Q1 and the first peak transistor Q2, and is the impedance transformation carrier of the inner layer modulation of the sub-circuit.

[0135] In one or more alternative embodiments, please continue to see Figure 8 The normalized power of the main transistor Q1, the first peak transistor Q2, and the second peak transistor Q3 is 1:P1:P2, and the impedance relationship is as follows:

[0136]

[0137]

[0138]

[0139] Where ZDload is the external apparent impedance of the circuit unit, and N is the external apparent impedance scaling factor, which can be used to correct the problem of excessive or insufficient impedance during the design and implementation process. The characteristic impedance of the transmission line between the first peak transistor Q2 and the second peak transistor Q3 is located outside the output port, in the peak branch responsible for load modulation within the peak branch. The characteristic impedance of the transmission line between the first peak transistor Q2 and the output port is used to connect the first-stage peak branch to the output combiner point. It is the characteristic impedance of the transmission line between the main transistor Q1 and the output port, connecting the main amplification branch to the output combining point.

[0140] In one or more alternative embodiments, such as Figure 1 As shown, when the main amplifier module has only one circuit unit, the impedance transmission line requirement is as follows:

[0141]

[0142] in, This value can be determined by selecting the transistor model based on the intrinsic power impedance of the main transistor corresponding to the main amplifier module.

[0143] When the number of circuit units in the peak amplifier module is 1, its external apparent impedance is:

[0144]

[0145] in, This is the intrinsic power impedance of the main transistor in the corresponding peak amplification module.

[0146] When the number of circuit units in the main amplifier module is greater than 1 and is even (M=2.4...), its external apparent impedance is:

[0147]

[0148] in, Let be the external apparent impedance of the Mth circuit unit.

[0149] When the number of main amplifier modules is greater than 1 and is odd (M=1.3...), the external apparent impedance of the modules is:

[0150]

[0151] in, Let be the external apparent impedance of the Mth circuit unit.

[0152] The impedance requirement for the peak amplifier module is as follows:

[0153]

[0154] in, The intrinsic power impedance of the main transistor in the corresponding peak amplifier module is determined once the transistor is selected. Q is the normalized ratio of the power of the peak transistor in the peak amplifier module to the power of the main transistor in the peak amplifier module.

[0155] When the peak amplifier module has only one circuit unit (N=1), its external apparent impedance is:

[0156]

[0157] When the number of amplification modules is greater than 1 and is even (N=2.4...), the apparent impedance of the modules is:

[0158]

[0159] in, Let be the external apparent impedance of the Nth circuit unit.

[0160] When the number of amplification modules is greater than 1 and is odd (N=1.3...), the apparent impedance of the modules is:

[0161]

[0162] For the main transistor in the circuit unit of a main amplification module, its modulation depth is as follows:

[0163] When the number of circuit units in the main amplifier module is greater than 1 and is even (M=2.4...), the modulation depth (MR) of the main transistor in the circuit unit of the main amplifier module is:

[0164]

[0165] When the number of circuit units in the main amplifier module is greater than 1 and is odd (M=1.3...), the modulation depth (MR) of the main amplifier in the sub-circuits of the main amplifier module is:

[0166]

[0167] in, This value represents the intrinsic power impedance of the main transistor in the corresponding circuit unit. Once the transistor is selected, this value can be determined. It can be seen that the modulation depth (MR) is strongly correlated with the characteristic impedance ratio of the quarter-wavelength line of the module combiner. By setting the impedance ratio, the amplifier bandwidth can be maintained without reduction even when multiple paths are extended.

[0168] In one or more alternative embodiments, the type of transmission line includes at least one of the following: pure microstrip transmission lines, such as... Figure 14 As shown, a semi-lumped transmission line, such as Figure 15 , Figure 16 As shown, a lumped transmission line, such as Figure 17 , Figure 18 As shown.

[0169] In one or more alternative embodiments, the material of the microstrip transmission line includes at least one of the following: PCB board material, silicon substrate material, ceramic substrate material, gallium arsenide substrate material, and gallium nitride substrate material.

[0170] In one or more alternative embodiments, the lumped capacitance includes at least one of the following: SMD surface-mount capacitors and inductors, ceramic monolithic capacitors, ceramic multilayer capacitors, silicon MOS capacitors, gallium arsenide MIM capacitors, and gallium nitride MIM capacitors.

[0171] In one or more alternative embodiments, the lumped inductor includes at least one of the following: a gallium arsenide on-chip spiral inductor, a gallium nitride on-chip spiral inductor, and a glass-based inductor.

[0172] In one embodiment, a communication device is provided, which includes a power amplifier circuit as described in any of the above embodiments.

[0173] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0174] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power amplifier circuit, characterized in that, include: Main amplification module and peak amplification module, wherein: The main amplification module includes M circuit units, the first ends of the M circuit units are connected together, and the second ends of the M circuit units are connected through transmission lines; The peak amplification module includes N circuit units, the first ends of the N circuit units are connected together, and the second ends of the N circuit units are connected through a transmission line; The output terminals of the main amplification module and the peak amplification module are connected to a common load through an output combining network. Each of the circuit units includes a main transistor and at least one peak transistor. The first terminal of the main transistor and the first terminal of the at least one peak transistor are connected together as the first terminal of the circuit unit. The second terminal of the main transistor and the second terminal of the at least one peak transistor are connected through a transmission line and serve as the second terminal of the circuit unit. The main transistor of at least one of the M circuit units is in a conducting state when no signal is connected to the input terminal of the main amplification module. Each transistor in the N circuit units is in a non-conducting state when no signal is connected to the input terminal of the peak amplification module. M and N are both positive integers, and N is greater than or equal to M.

2. The power amplifier circuit according to claim 1, characterized in that, At least one of the M circuit units and / or the N circuit units includes: a main transistor, a first peak transistor, and a second peak transistor, wherein the main transistor, the first peak transistor, and the second peak transistor are connected according to a first connection method, the first connection method including: The second terminal of the main transistor is connected to the second terminal of the first peak transistor via a transmission line; The second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via a transmission line; The second terminal of the second peak transistor serves as the second terminal of the circuit unit.

3. The power amplifier circuit according to claim 2, characterized in that, At least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method; Furthermore, at least one circuit unit of the second module includes: a main transistor and a first peak transistor, wherein the main transistor and the first peak transistor are connected in a second connection manner, wherein the second connection manner includes: the second terminal of the main transistor is connected to the second terminal of the first peak transistor through a transmission line; the second terminal of the first peak transistor serves as the second terminal of the circuit unit; the first module is one of the main amplification module and the peak amplification module; and the second module is the other of the main amplification module and the peak amplification module.

4. The power amplifier circuit according to claim 2, characterized in that, At least one circuit unit in the main amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method; At least one circuit unit in the peak amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the first connection method.

5. The power amplifier circuit according to any one of claims 1-4, characterized in that, At least one of the M circuit units and / or the N circuit units includes: a main transistor, a first peak transistor, and a second peak transistor, wherein the main transistor, the first peak transistor, and the second peak transistor are connected according to a third connection method, the third connection method including: The second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via the first transmission line; The second terminal of the second peak transistor is connected to the first terminal of the second transmission line; The second end of the main transistor is connected to the first end of the third transmission line, and the second end of the third transmission line is connected to the second end of the second transmission line as the second end of the circuit unit.

6. The power amplifier circuit according to claim 5, characterized in that, At least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; Furthermore, at least one circuit unit of the second module includes: a main transistor and a first peak transistor, wherein the main transistor and the first peak transistor are connected according to a second connection method, the second connection method including: the second terminal of the main transistor is connected to the second terminal of the first peak transistor through a transmission line; the second terminal of the first peak transistor serves as the second terminal of the circuit unit; The first module is one of the main amplification module and the peak amplification module, and the second module is the other of the main amplification module and the peak amplification module.

7. The power amplifier circuit according to claim 5, characterized in that, At least one circuit unit in the main amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; At least one circuit unit in the peak amplification module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method.

8. The power amplifier circuit according to claim 5, characterized in that, At least one circuit unit of the first module includes: a main transistor, a first peak transistor, and a second peak transistor connected by the third connection method; Furthermore, at least one circuit unit of the second module includes: a main transistor, a first peak transistor, and a second peak transistor, wherein the main transistor, the first peak transistor, and the second peak transistor are connected according to a first connection method, the first connection method including: The second terminal of the main transistor is connected to the second terminal of the first peak transistor via a transmission line; The second terminal of the first peak transistor is connected to the second terminal of the second peak transistor via a transmission line; The second terminal of the second peak transistor serves as the second terminal of the circuit unit; The first module is one of the main amplification module and the peak amplification module, and the second module is the other of the main amplification module and the peak amplification module.

9. The power amplifier circuit according to any one of claims 1-4, characterized in that, include: The first power divider, the input terminal of the first power divider is used to receive the input signal; The second power divider has its input terminal connected to one output terminal of the first power divider, and its output terminal is connected to the control terminals of the main transistors and at least one peak transistor of the M circuit units respectively. The third power divider has its input terminal connected to one output terminal of the first power divider, and its output terminal connected to the control terminals of the main transistors and at least one peak transistor of the N circuit units.

10. The power amplifier circuit according to any one of claims 1-4, characterized in that, include: The first power divider has an input terminal for receiving input signals and an output terminal connected to the control terminals of the main transistors and at least one peak transistor of the M circuit units, respectively. The second power divider has an input terminal for receiving input signals and an output terminal connected to the control terminals of the main transistors and at least one peak transistor of the N circuit units.

11. The power amplifier circuit according to any one of claims 1-4, characterized in that, The electrical phase of the impedance of the transmission line satisfies (2A+1). 90°, where A is an integer greater than or equal to 0.

12. The power amplifier circuit according to any one of claims 1-4, characterized in that, The characteristic impedance of the transmission line is determined based on the normalized power of the transistor in the corresponding connected circuit unit, the intrinsic power impedance of the transistor in the corresponding connected circuit unit, and the apparent impedance of the corresponding connected circuit unit to the outside.

13. A communication device, characterized in that, The communication device includes a power amplifier circuit as described in any one of claims 1-12.

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