A feed-forward transient enhanced buffer circuit for high precision digital-to-analog converters

Abstract

The application belongs to the technical field of high-precision digital-to-analog conversion, and particularly relates to a feedforward transient enhancement type buffer circuit for a high-precision digital-to-analog converter. The feedforward transient enhancement type buffer circuit is mainly composed of a transient enhancement circuit, a folded cascode amplifier and a Class A output stage. The transient enhancement circuit is composed of an improved differential amplifier and a pull-down tube. A full-parallel input and nonlinear feedforward cooperative circuit architecture is adopted, a parallel transient enhancement circuit is connected to the input end of the folded cascode amplifier, the transient enhancement feedforward path and the main gain path work independently and in parallel, and strong acceleration is realized through a nonlinear load network, so that the output signal is quickly established from high to low. The solution provided by the application can effectively improve the negative transient response speed of the high-precision digital-to-analog converter and improve the dynamic performance of the circuit without sacrificing the signal bandwidth through the micro-power feedforward transient enhancement circuit.

Description

Technical Field

[0001] This invention relates to the field of CMOS analog integrated circuits, and more specifically to an output buffer amplifier circuit for a high-precision digital-to-analog converter, particularly a circuit architecture employing fully parallel input and nonlinear feedforward coordination. Background Technology

[0002] The dynamic characteristics of high-performance DACs (such as spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are severely limited by the settling time and slew rate of their output buffer amplifiers. Traditional Class A or Class AB output stages become bottlenecks when dealing with large-signal transients due to their limited slew rate. Some improvements use larger bias currents to increase the slew rate, but this leads to a linear increase in quiescent power dissipation. Existing transient enhancement techniques (such as feedforward capacitors and switching current boosting) often introduce additional issues related to loop stability, noise, or design complexity. Summary of the Invention

[0003] The purpose of this invention is to propose an output buffer circuit that effectively enhances the negative transient response speed of large signals and improves the negative setup characteristics without significantly increasing the static power consumption of the circuit.

[0004] The technical solution adopted by this invention to achieve the above objectives is: a feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter, comprising: a transient enhancement circuit, a folded cascode amplifier, and a Class A output stage, wherein:

[0005] The transient enhancement circuit input and the folded cascode amplifier input are both differential input signals. The output of the folded cascode amplifier is connected to the Class A output stage, and the transient enhancement circuit output is connected to the Class A output stage output terminal VOUT.

[0006] The transient enhancement circuit includes: an improved differential amplifier and a pull-down transistor, wherein:

[0007] The non-inverting input of the improved differential amplifier is connected to the non-inverting input of the folded cascode amplifier, the inverting input of the improved differential amplifier is connected to the inverting input of the folded cascode amplifier, the output of the improved differential amplifier is connected to the gate of the pull-down transistor, the drain of the pull-down transistor is connected as the output to the output VOUT of the Class A output stage, and the source of the pull-down transistor is grounded.

[0008] The improved differential amplifier is specifically:

[0009] MOSFETs MP1 and MP2 are connected, with the source of MP1 and the source of MP2 connected to the drain of MP3. The gate of MP1 serves as the non-inverting input of the differential amplifier, and the gate of MP2 serves as the inverting input of the differential amplifier.

[0010] MOSFETs MN1 and MN2 are connected as loads in a diode configuration. The gate and drain of MN1 are shorted to form terminal A, which is connected to the drain of MP1. The gate and drain of MN2 are shorted to form terminal B, which is connected to the drain of MP2. The sources of MN1 and MN2 are grounded. Terminal A serves as the output terminal of the improved differential amplifier and is connected to the gate of the pull-down transistor.

[0011] MOSFETs MN3 and MN4, with the gates of MN3 and MN4 connected to an external bias voltage V. BN1 The drain of MN3 is connected to the drain of MP1, the drain of MN4 is connected to the drain of MP2, and the sources of MN3 and MN4 are grounded.

[0012] The MOSFET MP3 has its source connected to the power supply and its gate connected to an external bias voltage V. BP1 The drain is connected to the source of MP1 and MP2.

[0013] The pull-down transistor is a MOSFET MN12, specifically:

[0014] The gate of MN12 is connected to the drain of MP1, the drain of MN1, and the drain of MN3, serving as the input of the pull-down transistor. The drain of MN12 is connected to the drain of MP15 and the drain of MN11 in the class A output stage, and the source of MN12 is grounded.

[0015] The Class A output stage includes MOSFETs MP11, MP12, MP13, MP14, MP15, MN9, MN10, and MN11, specifically:

[0016] The source of MOSFET MP11 is connected to the power supply. The gate of MP11 is connected to the output of the folded cascode amplifier and the gate of MP15. The drain of MP11 is connected to the source of MP12. The source of MP13 is connected to the power supply. The drain of MP13 is connected to the source of MP14. The gates of MP12 and MP14 are connected to an external reference voltage V. BP2 The drain of MP12 is connected to the drain of MN9. The gate of MN9 is connected to the gate and drain of MN10. The sources of MN9 and MN10 are grounded. The gate of MP15 is connected to the drain of MP15 after capacitor C1 and resistor R1 in sequence. MP14 is connected to the gate and drain of MN10, and is also connected to the gate of MN11. It is connected to the drain of MN11 after capacitor C2 and resistor R2 in sequence. The drain of MP15 is connected to the drain of MN11 and the drain of pull-down transistor MN12, serving as the output terminal VOUT of the class A output stage.

[0017] A feedforward transient enhancement buffer method for high-precision digital-to-analog converters includes the following steps:

[0018] The differential signals are input to the transient enhancement circuit and the folded cascode amplifier, respectively. The folded cascode amplifier amplifies the differential signals and drives the class A output stage. The improved differential amplifier in the transient enhancement circuit works independently and in parallel with the folded cascode amplifier. The transient enhancement circuit accelerates the settling time when the output signal transitions from high to low. Finally, the pull-down transistor detects the transition of the DAC output signal from high to low, thus achieving the establishment of the output signal from high to low.

[0019] The transient enhancement circuit operates as follows:

[0020] When the input differential signal transitions from high to low, the output VOUT level of the class A output stage is high, the external negative feedback circuit, and the inverting input of the feedforward transient enhancement buffer circuit are also high. The drain and gate of MP2 in the improved differential amplifier are out of phase, node B is pulled low, and node A is pulled high. The voltage change at point A is applied to the gate of the pull-down transistor MN12, turning it on. MN12 provides a milliampere-level pull-down current, which discharges the load capacitor connected to the VOUT terminal, pulling the output VOUT terminal voltage low to improve the response speed of the output signal transitioning from high to low.

[0021] The present invention has the following beneficial effects and advantages:

[0022] 1. Effectively enhances the negative transient response speed of large signals: Through a specially optimized feedforward path and output pull-down diode, the output is rapidly established from high to low, effectively shortening the establishment time.

[0023] 2. Overall performance improvement: The large signal slew rate is increased by more than 2 times without significantly increasing the static power consumption of the circuit.

[0024] 3. High precision maintenance: The main gain path operates independently, ensuring excellent DC accuracy, linearity and low noise characteristics.

[0025] 4. Good stability: The overall stability is guaranteed by the loop negative feedback and compensation network, and it is not sensitive to process changes. Attached Figure Description

[0026] Figure 1 This invention provides a framework diagram of a feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter.

[0027] Figure 2 Schematic diagram of an improved differential amplifier circuit;

[0028] Figure 3 This invention discloses a schematic diagram of a feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter;

[0029] Figure 4 The output waveform of the circuit without the addition of a transient enhancement circuit;

[0030] Figure 5 The output waveform after adding a transient enhancement circuit to the circuit. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0032] This invention mainly consists of a transient enhancement circuit, a folded cascode amplifier, and a Class A output stage. The transient enhancement circuit comprises an improved differential amplifier and pull-down transistors. It employs a fully parallel input and nonlinear feedforward coordinated circuit architecture, connecting a parallel transient enhancement circuit at the input of the folded cascode amplifier. This transient enhancement feedforward path operates independently and in parallel with the main gain path, and achieves strong acceleration through a nonlinear load network, enabling rapid establishment of the output signal from high to low. The solution proposed in this invention, through a low-power feedforward transient enhancement circuit, can effectively improve the negative transient response speed of a high-precision digital-to-analog converter and enhance the circuit's dynamic performance without sacrificing signal bandwidth.

[0033] The specific technical solution of this invention is as follows: A feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter, comprising: a transient enhancement circuit, a folded cascode amplifier, and a Class A output stage, wherein:

[0034] The transient enhancement circuit and the folded cascode amplifier both have differential input signals (VIN, VIP), and the output of the transient enhancement circuit is connected to the output terminal VOUT of the folded cascode amplifier.

[0035] The transient enhancement circuit includes an improved differential amplifier and a pull-down transistor, wherein: the non-inverting input of the improved differential amplifier is connected to the non-inverting input of the folded cascode amplifier, the inverting input of the improved differential amplifier is connected to the inverting input of the folded cascode amplifier, the output of the differential amplifier is connected to the gate of the pull-down transistor, the output of the pull-down transistor is connected to the output of the folded cascode amplifier, and the source is grounded.

[0036] The improved differential amplifier is specifically as follows:

[0037] The sources of MOSFETs MP1 and MP2 are connected to the drain of MP3. The gate of MP1 serves as the non-inverting input of the differential amplifier, and the gate of MP2 serves as the inverting input of the differential amplifier.

[0038] MOSFETs MN1 and MN2 are connected as loads in a diode configuration. The gate and drain of MN1 are shorted to form terminal A, which is connected to the drain of MP1. The gate and drain of MN2 are shorted to form terminal B, which is connected to the drain of MP2. The sources of MN1 and MN2 are grounded.

[0039] MOSFETs MN3 and MN4 have their gates connected to an external bias voltage V. BN1 The drain of MN3 is connected to the drain of MP1, the drain of MN4 is connected to the drain of MP2, and the sources of MN3 and MN4 are grounded;

[0040] The MOSFET MP3 has its source connected to the power supply and its gate connected to an external bias voltage V. BP1 The drain is connected to the source of MP1 and MP2.

[0041] Specifically, the pull-down transistors are configured such that the gate of MN12 is connected to the drain of MP1, the drain of MN1, and the drain of MN3, serving as the input of the pull-down transistor. The drain of MN12 is connected to the drain of MP15 and the drain of MN11, and the source is grounded.

[0042] The Class A output stage is specifically configured as follows: the source of MOSFET MP11 is connected to the power supply; the gate of MP11 is connected to the output of the folded cascode amplifier and the gate of MP15; the drain of MP11 is connected to the source of MP12; the source of MP13 is connected to the power supply; the drain of MP13 is connected to the source of MP14; and the gates of MP12 and MP14 are connected to the external reference voltage V. BP2 The drain of MP12 is connected to the drain of MN9. The gate of MN9 is connected to the gate and drain of MN10. The sources of MN9 and MN10 are grounded. The gate of MP15 is connected to the drain of MP15 after capacitor C1 and resistor R1 in sequence. MP14 is connected to the gate and drain of MN10, and is also connected to the gate of MN11. It is connected to the drain of MN11 after capacitor C2 and resistor R2 in sequence. The drain of MP15 is connected to R1, R2, the drain of MN11, and the drain of MN12, serving as the output terminal.

[0043] The main gain stage circuit consists of a folded cascode amplifier and a CLASS output stage, while the transient enhancement circuit consists of a modified differential amplifier and a pull-down transistor MN12. Differential signals are input from VIN and VIP, respectively, pass through the folded cascode amplifier, and reach the output. The output is biased against the gate of MP15. MP11, MP12, MP13, and MP14 form a cascode structure. MP9 and MP10 are current source loads. VBP1, VBP2, VBN1, and VBN2 are external bias voltages used to bias the operating points of the PMOS and NMOS transistors. The folded cascode amplifier provides high open-loop gain and power supply rejection ratio, amplifies the differential signal, and drives the output stage. To optimize the transient response speed from high to low for large signals, a parallel transient enhancement circuit is connected at the input of the folded cascode amplifier. This transient enhancement feedforward path works independently and in parallel with the main gain path, and achieves strong acceleration through a nonlinear load network. Finally, it detects the large jump in the DAC output signal from high to low through the pull-down diode, thereby achieving rapid establishment of the output signal from high to low and optimizing large signals.

[0044] This circuit is implemented by connecting a parallel transient enhancement circuit to the input of the folded cascode amplifier. The transient enhancement feedforward path works independently and in parallel with the main gain path, and strong acceleration is achieved through a nonlinear load network. Finally, the output signal is quickly established from high to low after the pull-down diode detects the large jump from high to low of the DAC output signal, thereby optimizing the transient response speed of large signals from high to low.

[0045] Example:

[0046] A feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter includes a fully parallel transient enhancement circuit, a folded cascode amplifier, and a class A output stage, such as... Figure 1 As shown.

[0047] The transient enhancement circuit consists of an improved differential amplifier and a pull-down transistor. For example... Figure 2 The diagram shows an improved differential amplifier. MP1 and MP2 form the differential amplifier transistors, and MN1 and MN2 serve as active loads. MN3 and MN4 are connected in parallel with MN1 and MN2 respectively to increase the current passing through MP1 and MP2.

[0048] The circuit gain can be expressed as:

[0049]

[0050]

[0051] in, , These represent the process transconductance parameters of PMOS and NMOS transistors, respectively. , These represent the channel width and channel length of the PMOS transistor MP1, respectively. , These represent the channel width and channel length of the NMOS transistor MN3, respectively. , These represent the currents flowing through NMOS transistors MN3 and MN1, respectively.

[0052] Given the W / L values ​​of MP1 and MN3, the gain A V and Proportional. Because the gate-source capacitance of ordinary differential pair transistors increases the input signal delay and feedthrough effect, affecting system performance and speed. The structure used in this invention can reduce the W / L values ​​of MP1 and MP2 while achieving the same gain, thereby reducing their gate-source capacitance and improving the feedthrough effect.

[0053] like Figure 3 The diagram shows the specific circuit implementation of this invention. Due to the high gain and large output swing characteristics of the folded cascode structure, the main gain stage uses a folded cascode amplifier. To reduce circuit power consumption and achieve higher efficiency, the output stage adopts a Class A structure. Miller compensation is used at the output to ensure good frequency characteristics of the circuit. MN12 is the key actuator for achieving fast pull-down of the output signal.

[0054] When the input signal undergoes a rapid transition from high to low (an instantaneous change in code value, corresponding to a significant decrease in the DAC input code value), the transient enhancement mechanism is activated. Since VOUT is high, the external circuit is a negative feedback circuit, and the inverting input of the output buffer is also high, the drain and gate of MP2 are out of phase, node B is rapidly pulled low, and simultaneously node A is rapidly pulled high. The voltage change at point A is applied to the gate of the pull-down transistor MN12, causing it to turn on rapidly. MN12 (nanosecond level) instantaneously provides a milliampere-level pull-down current, rapidly discharging the load capacitor connected to VOUT, quickly pulling the output voltage VOUT low, thus completing the rapid response to a large signal transition from high to low. To reduce circuit power consumption, the output stage adopts a Class A output stage structure. The transient enhancement circuit used in this invention improves upon the structural defect of the Class A structure's slow response to rapid transitions of large signals from high to low, effectively enhancing transient response performance.

[0055] like Figure 4 To achieve the output waveform at VOUT without adding a transient enhancement circuit, such as Figure 5 To enhance the output waveform at the VOUT terminal during transient enhancement circuitry. (This is achieved through...) Figure 4 , Figure 5It can be seen that after applying the transient enhancement circuit, the negative transient response speed of the output signal is significantly improved, the slew rate is significantly improved, and the settling time is greatly shortened.

Claims

1. A feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter, characterized in that, include: A transient enhancement circuit, a folded cascode amplifier, and a Class A output stage, wherein: The transient enhancement circuit input and the folded cascode amplifier input are both differential input signals. The output of the folded cascode amplifier is connected to the Class A output stage, and the transient enhancement circuit output is connected to the Class A output stage output terminal VOUT.

2. The feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter according to claim 1, characterized in that, The transient enhancement circuit includes: an improved differential amplifier and a pull-down transistor, wherein: The non-inverting input of the improved differential amplifier is connected to the non-inverting input of the folded cascode amplifier, the inverting input of the improved differential amplifier is connected to the inverting input of the folded cascode amplifier, the output of the improved differential amplifier is connected to the gate of the pull-down transistor, the drain of the pull-down transistor is connected as the output to the output VOUT of the Class A output stage, and the source of the pull-down transistor is grounded.

3. The feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter according to claim 2, characterized in that, The improved differential amplifier is specifically: MOSFETs MP1 and MP2 are connected, with the source of MP1 and the source of MP2 connected to the drain of MP3. The gate of MP1 serves as the non-inverting input of the differential amplifier, and the gate of MP2 serves as the inverting input of the differential amplifier. MOSFETs MN1 and MN2 are connected as loads in a diode configuration. The gate and drain of MN1 are shorted to form terminal A, which is connected to the drain of MP1. The gate and drain of MN2 are shorted to form terminal B, which is connected to the drain of MP2. The sources of MN1 and MN2 are grounded. Terminal A serves as the output terminal of the improved differential amplifier and is connected to the gate of the pull-down transistor. MOSFETs MN3 and MN4, with the gates of MN3 and MN4 connected to an external bias voltage V. BN1 The drain of MN3 is connected to the drain of MP1, the drain of MN4 is connected to the drain of MP2, and the sources of MN3 and MN4 are grounded. The MOSFET MP3 has its source connected to the power supply and its gate connected to an external bias voltage V. BP1 The drain is connected to the source of MP1 and MP2.

4. A feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter according to claim 2, characterized in that, The pull-down transistor is a MOSFET MN12, specifically: The gate of MN12 is connected to the drain of MP1, the drain of MN1, and the drain of MN3, serving as the input of the pull-down transistor. The drain of MN12 is connected to the drain of MP15 and the drain of MN11 in the class A output stage, and the source of MN12 is grounded.

5. A feedforward transient enhancement buffer circuit for a high-precision digital-to-analog converter according to claim 1, characterized in that, The Class A output stage includes MOSFETs MP11, MP12, MP13, MP14, MP15, MN9, MN10, and MN11, specifically: The source of MOSFET MP11 is connected to the power supply. The gate of MP11 is connected to the output of the folded cascode amplifier and the gate of MP15. The drain of MP11 is connected to the source of MP12. The source of MP13 is connected to the power supply. The drain of MP13 is connected to the source of MP14. The gates of MP12 and MP14 are connected to an external reference voltage V. BP2 The drain of MP12 is connected to the drain of MN9. The gate of MN9 is connected to the gate and drain of MN10. The sources of MN9 and MN10 are grounded. The gate of MP15 is connected to the drain of MP15 after capacitor C1 and resistor R1 in sequence. MP14 is connected to the gate and drain of MN10, and is also connected to the gate of MN11. It is connected to the drain of MN11 after capacitor C2 and resistor R2 in sequence. The drain of MP15 is connected to the drain of MN11 and the drain of pull-down transistor MN12, serving as the output terminal VOUT of the class A output stage.

6. A feedforward transient enhancement buffering method for high-precision digital-to-analog converters, characterized in that, Includes the following steps: The differential signals are input to the transient enhancement circuit and the folded cascode amplifier, respectively. The folded cascode amplifier amplifies the differential signals and drives the class A output stage. The improved differential amplifier in the transient enhancement circuit works independently and in parallel with the folded cascode amplifier. The transient enhancement circuit accelerates the settling time when the output signal transitions from high to low. Finally, the pull-down transistor detects the transition of the DAC output signal from high to low, thus achieving the establishment of the output signal from high to low.

7. A feedforward transient enhancement buffering method for a high-precision digital-to-analog converter according to claim 6, characterized in that, The transient enhancement circuit operates as follows: When the input differential signal transitions from high to low, the output VOUT level of the class A output stage is high, the external negative feedback circuit, and the inverting input of the feedforward transient enhancement buffer circuit are also high. The drain and gate of MP2 in the improved differential amplifier are out of phase, node B is pulled low, and node A is pulled high. The voltage change at point A is applied to the gate of the pull-down transistor MN12, turning it on. MN12 provides a milliampere-level pull-down current, which discharges the load capacitor connected to the VOUT terminal, pulling the output VOUT terminal voltage low to improve the response speed of the output signal transitioning from high to low.

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