Variable gain amplifier, signal processing chip and electronic device
Patent Information
- Application Number
- CN202611168925.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-03
- Publication Date
- 2026-10-27
AI Technical Summary
[0004]当VGA工作于高增益档位时，主极点与次极点的频率间距大幅缩小，次极点向主极点靠近会导致环路相位裕度显著降低，负反馈环路易出现自激振荡，造成输出信号失真、增益精度劣化，严重时电路无法正常工作，直接限制了VGA的增益调节上限与高速场景适配能力
[0044]本公开实施例通过在差分输入模块和差分放大模块之间设置电压跟随模块，能够降低差分放大模块输入端的电阻，将环路的次极点推远，从而增加可变增益放大器的带宽，从而避免在运行中次极点与主极点接近导致环路发生振荡，因此，本公开实施例的可变增益放大器具有较高的环路稳定性。
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Figure CN122993645A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a variable gain amplifier, a signal processing chip, and an electronic device. Background Technology
[0002] Variable gain amplifiers (VGAs) are core functional modules in wireless communication transceiver links, high-speed signal processing systems, and analog front-ends. They are used to dynamically adjust signal gain so that subsequent circuits can obtain a stable input signal amplitude. They have wide applications in communication, radar, sensing and other fields.
[0003] Current-mode negative feedback VGAs with constant bandwidth achieve continuously adjustable gain by adjusting the tail currents of the amplification and feedback stages in tandem. Simultaneously, the synchronous inverse change of the dominant pole and loop gain maintains a constant gain-bandwidth product, ensuring the closed-loop bandwidth remains essentially unchanged during gain adjustment. However, this architecture's negative feedback loop has two critical poles: the dominant pole is located at the output of the preamplifier module, and its frequency shifts to higher frequencies as the gain level increases; the secondary pole is located at the output node (input summation node) of the feedback transconductance stage, and its frequency is determined by the fixed input resistance and node parasitic capacitance, remaining unchanged with gain adjustment.
[0004] When a VGA operates at a high gain setting, the frequency gap between the dominant and secondary poles is significantly reduced. The secondary pole moving closer to the dominant pole will cause a significant reduction in the loop phase margin. The negative feedback loop is prone to self-oscillation, resulting in output signal distortion and deterioration of gain accuracy. In severe cases, the circuit cannot work properly, directly limiting the upper limit of VGA gain adjustment and its adaptability to high-speed scenarios. Summary of the Invention
[0005] In view of this, this disclosure proposes a variable gain amplifier, which includes a differential input module, a voltage follower module, a differential amplification module, and an output module, wherein...
[0006] The differential input module is used to receive the differential input signal and the differential amplified signal output by the differential amplification module, and to output a differential control signal based on the differential input signal and the differential amplified signal.
[0007] The voltage follower module, connected to the differential input module and the differential amplifier module, is used to receive the differential control signal and output a follower voltage signal to the differential amplifier module according to the differential control signal.
[0008] The differential amplifier module is used to differentially amplify the following voltage signal and output a differential amplified signal.
[0009] The output module is connected to the differential amplifier module and is used to generate an output voltage based on the differential amplified signal.
[0010] In one possible implementation, the differential input module includes a first input resistor, a second input resistor, a first input transistor, a second input transistor, and a second tail current source, wherein,
[0011] The first terminal of the first input resistor and the first terminal of the second input resistor are used to connect to the differential input signal.
[0012] The common node between the second terminal of the first input resistor and the first terminal of the first input transistor, and the common node between the second terminal of the second input resistor and the first terminal of the second input transistor, are used to output the differential control signal.
[0013] The second terminal of the first input transistor and the second terminal of the second input transistor are grounded through the second tail current source.
[0014] The control terminals of the first input transistor and the second input transistor are used to receive the differential amplified signal.
[0015] In one possible implementation, the voltage follower module includes a first voltage follower and a second voltage follower, wherein both the first voltage follower and the second voltage follower include a first voltage follower transistor, a second voltage follower transistor, a first voltage follower current source, and a second voltage follower current source, wherein...
[0016] The control terminal of the first voltage follower transistor is used to receive the differential control signal.
[0017] The first terminal of the first voltage follower transistor and the positive terminal of the second voltage follower current source are used to receive the power supply voltage.
[0018] The second terminal of the first voltage follower transistor is connected to the positive terminal of the first voltage follower current source and the control terminal of the second voltage follower transistor.
[0019] The negative terminal of the first voltage follower current source and the second terminal of the second voltage follower transistor are grounded.
[0020] The common node of the first terminal of the second voltage follower transistor and the negative terminal of the second voltage follower current source is used to output the following voltage signal.
[0021] In one possible implementation, the differential amplifier module includes a first amplification unit and a second amplification unit. The first amplification unit includes a first amplification transistor, a second amplification transistor, a third amplification transistor, a fourth amplification transistor, and a first tail current source.
[0022] The control terminals of the first and second amplifying transistors are used to receive the following voltage signal.
[0023] The first terminal of both the third and fourth amplifying transistors is used to receive the power supply voltage.
[0024] The control terminals of the third and fourth amplifying transistors are both used to receive a preset bias voltage.
[0025] The common node of the second terminal of the third amplifying transistor, the first terminal of the first amplifying transistor, the second terminal of the fourth amplifying transistor, and the first terminal of the second amplifying transistor is used to output the first-stage amplified signal.
[0026] The second terminal of the first amplifying transistor and the second terminal of the second amplifying transistor are grounded through the first tail current source.
[0027] The first input terminal and the second input terminal of the second amplification unit are used to receive the first-stage amplified signal, and the second amplification unit is used to amplify the first-stage amplified signal and output the differential amplified signal.
[0028] In one possible implementation, the first amplification unit further includes a first common-mode feedback circuit, and a second common-mode feedback circuit is provided between the two differential output terminals of the second amplification unit. The first common-mode feedback circuit and the second common-mode feedback circuit are used to stabilize the common-mode voltage.
[0029] In one possible implementation, the differential amplifier module further includes a first differential capacitor, a second differential capacitor, and a first switch, wherein...
[0030] The first terminal of the first differential capacitor and the first terminal of the second differential capacitor are both connected to the first input terminal of the second amplification unit.
[0031] The second terminal of the second differential capacitor is connected to the first terminal of the first switch.
[0032] The second terminal of the first differential capacitor and the second terminal of the first switch are both connected to the second input terminal of the second amplifier unit.
[0033] The control terminal of the first switch is used to receive switch control signals.
[0034] In one possible implementation, the switch control signal is related to a gain control voltage, wherein the gain control voltage is used to adjust the current of the first tail current source and the second tail current source, thereby adjusting the gain of the variable gain amplifier.
[0035] In one possible implementation, the output module includes a first output transistor, a second output transistor, a first current source, a second current source, a first operational amplifier, a second operational amplifier, a first output resistor, a second output resistor, and a third tail current source, wherein...
[0036] The control terminals of the first and second output transistors are used to receive the differential amplified signal.
[0037] The first terminal of the first output transistor is connected to the negative terminal of the first current source, the first terminal of the first output resistor, and the input terminal of the first operational amplifier.
[0038] The first terminal of the second output transistor is connected to the negative terminal of the second current source, the first terminal of the second output resistor, and the input terminal of the second operational amplifier.
[0039] The positive terminals of the first current source and the second current source are used to receive the power supply voltage.
[0040] The second terminal of the first output resistor, the common node of the output terminal of the first operational amplifier, the second terminal of the second output resistor, and the common node of the output terminal of the second operational amplifier are used to generate the output voltage.
[0041] The second terminal of the first output transistor and the second terminal of the second output transistor are both grounded through the third tail current source.
[0042] According to one aspect of this disclosure, a signal processing chip is provided, the signal processing chip including the aforementioned variable gain amplifier.
[0043] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned signal processing chip.
[0044] This embodiment of the present disclosure reduces the resistance at the input terminal of the differential amplifier module by setting a voltage follower module between the differential input module and the differential amplifier module, thereby pushing the secondary pole of the loop further away and increasing the bandwidth of the variable gain amplifier. This avoids loop oscillation caused by the secondary pole approaching the primary pole during operation. Therefore, the variable gain amplifier of this embodiment of the present disclosure has high loop stability.
[0045] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0046] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0047] Figure 1 A schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.
[0048] Figure 2 Another schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.
[0049] Figure 3 A simulation diagram of a variable gain amplifier from related technologies and a variable gain amplifier according to an embodiment of this disclosure is shown. Detailed Implementation
[0050] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0051] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0052] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0053] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0054] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0055] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0056] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.
[0057] Please see Figure 1 , Figure 1 A schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.
[0058] like Figure 1 As shown, the variable gain amplifier includes a differential input module 10, a voltage follower module 20, a differential amplification module 30, and an output module 40, wherein...
[0059] The differential input module 10 is used to receive differential input signals (Vin, Vip) and differential amplified signals output by the differential amplification module 30, and output differential control signals according to the differential input signals and differential amplified signals.
[0060] The voltage follower module 20 is connected to the differential input module 10 and the differential amplifier module 30, and is used to receive the differential control signal and output a follower voltage signal to the differential amplifier module 30 according to the differential control signal.
[0061] The differential amplifier module 30 is used to differentially amplify the following voltage signal and output a differential amplified signal.
[0062] The output module 40 is connected to the differential amplifier module 30 and is used to generate an output voltage (Von, Vop) based on the differential amplification signal.
[0063] This embodiment of the present disclosure reduces the resistance at the input terminal of the differential amplifier module 30 by setting a voltage follower module 20 between the differential input module 10 and the differential amplifier module 30, thereby pushing the secondary pole of the loop further away and increasing the bandwidth of the variable gain amplifier. This avoids loop oscillation caused by the secondary pole approaching the primary pole during operation. Therefore, the variable gain amplifier of this embodiment of the present disclosure has high loop stability.
[0064] Those skilled in the art should understand that all types of amplifiers generally have poles. The essence of a pole is the RC low-pass effect of the amplifier's signal nodes: the equivalent resistance R and equivalent capacitance C of each signal node form a time constant τ = R × C, corresponding to a pole in the transfer function, with a pole frequency of fp = 1 / (2πRC). Multi-stage negative feedback amplifiers have multiple signal nodes, thus generating multiple poles. Sorted from low to high pole frequency, they are divided into primary poles, secondary poles (secondary poles), and higher-order poles. The definitions, characteristics, and impacts on loop stability of these two types are clearly distinguished.
[0065] The dominant pole is the lowest frequency pole in the open-loop transfer function of the negative feedback loop, and it is the first inflection point where the amplifier gain begins to roll off from the DC gain. The second non-dominant pole is the second lowest frequency pole in the open-loop transfer function of the negative feedback loop, and its frequency is always higher than that of the dominant pole.
[0066] For VGA, when the gain is adjusted, the gap between the dominant pole and the secondary pole may be greatly reduced, which may lead to insufficient phase margin and loop self-oscillation, resulting in loop instability. In this embodiment, the voltage follower module 20 can push the secondary pole further away, thereby improving the loop stability of VGA.
[0067] The present invention does not limit the specific implementation of the differential input module 10, voltage follower module 20, differential amplifier module 30, and output module 40. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies, as long as the corresponding functions can be achieved.
[0068] The embodiments disclosed herein do not limit the specific method of adjusting the gain of the variable gain amplifier. Those skilled in the art can implement it according to the actual situation and needs, referring to relevant technologies. For example, the gain can be adjusted by controlling the current of the adjustable current source in the gain control circuit through the gain control voltage.
[0069] Please see Figure 2 , Figure 2 A schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.
[0070] In one possible implementation, such as Figure 2 As shown, the differential input module 10 may include a first input resistor Rin1, a second input resistor Rin2, a first input transistor Q11, a second input transistor Q12, and a second tail current source I2, wherein,
[0071] The first terminal of the first input resistor Rin1 and the first terminal of the second input resistor Rin2 are used to connect the differential input signals (Vin, Vip).
[0072] The common node between the second terminal of the first input resistor Rin1 and the first terminal (collector) of the first input transistor Q11, and the common node between the second terminal of the second input resistor Rin2 and the first terminal (collector) of the second input transistor Q12, are used to output the differential control signal.
[0073] The second terminal (emitter) of the first input transistor Q11 and the second terminal (emitter) of the second input transistor Q12 are grounded through the second tail current source I2.
[0074] The control terminal (base) of the first input transistor Q11 and the control terminal (base) of the second input transistor Q12 are used to receive the differential amplified signal.
[0075] In this embodiment, the differential amplification signal fed back from the differential amplification module 30 is received by the first input transistor Q11 and the second input transistor Q12. The differential amplification signal is applied to the base of the differential pair formed by the first input transistor Q11 and the second input transistor Q12, so that the first input transistor Q11 and the second input transistor Q12 convert the loop output differential voltage into differential feedback current. The feedback current flows through the differential first input resistor Rin1 and the second input resistor Rin2 to generate a differential feedback voltage, which is sent to the voltage follower module 20.
[0076] It should be noted that in various embodiments of this disclosure, the prefixes of devices such as transistors, current sources, capacitors, and operational amplifiers (such as input transistors, amplifying transistors, amplifying resistors, voltage follower transistors, voltage follower current sources, etc.) are only used to distinguish names. In other embodiments, the naming methods such as first, second, and third can also be used for distinction. This disclosure does not limit this.
[0077] The second tail current source I2 in this embodiment can be an adjustable current source. For example, the current of the second tail current source I2 can be adjusted by the gain control voltage, thereby adjusting the feedback transconductance and thus changing the gain of the amplifier.
[0078] This disclosure does not limit the transistor types of the first input transistor Q11 and the second input transistor Q12. Those skilled in the art can select appropriate transistors according to actual conditions and needs, for example, Figure 2 As shown, both the first input transistor Q11 and the second input transistor Q12 can be transistors, and both the first input transistor Q11 and the second input transistor Q12 can be NPN transistors.
[0079] In one possible implementation, such as Figure 2 As shown, the voltage follower module 20 includes a first voltage follower 210 and a second voltage follower 220. This embodiment does not limit the specific implementation of the first voltage follower 210 and the second voltage follower 220. Those skilled in the art can implement them according to actual conditions and needs, referring to relevant technologies. For example, the first voltage follower 210 and the second voltage follower 220 can both be source followers. This embodiment implements the voltage follower module 20 through source followers, which can reduce the resistance seen in the subsequent circuit and maintain the original input common mode of the circuit unchanged, so it will not change the input range of the original circuit.
[0080] For example, such as Figure 2 As shown, both the first voltage follower 210 and the second voltage follower 220 may include a first voltage follower transistor Q21, a second voltage follower transistor Q22, a first voltage follower current source I21, and a second voltage follower current source I22, wherein,
[0081] The control terminal (base) of the first voltage follower transistor Q21 is used to receive the differential control signal.
[0082] The first terminal (collector) of the first voltage follower transistor Q21 and the positive terminal of the second voltage follower current source I22 are used to receive the power supply voltage (Vdd).
[0083] The second terminal (emitter) of the first voltage follower transistor Q21 is connected to the positive terminal of the first voltage follower current source I21 and the control terminal (base) of the second voltage follower transistor Q22.
[0084] The negative terminal of the first voltage follower current source I21 and the second terminal (collector) of the second voltage follower transistor Q22 are grounded.
[0085] The common node of the first terminal (emitter) of the second voltage follower transistor Q22 and the negative terminal of the second voltage follower current source I22 is used to output the following voltage signal.
[0086] This disclosure does not limit the specific transistor types of the first voltage follower transistor Q21 and the second voltage follower transistor Q22. Those skilled in the art can select appropriate transistors according to actual conditions and needs, for example, Figure 2 As shown, the first voltage follower transistor Q21 and the second voltage follower transistor Q22 can be an NPN transistor and a PNP transistor, respectively.
[0087] It should be understood that although the above example of implementing the first voltage follower 210 and the second voltage follower 220 with a source follower is a preferred example, the embodiments of this disclosure are not limited thereto. The first voltage follower 210 and the second voltage follower 220 may also be emitter followers, operational amplifier voltage followers, etc.
[0088] In one possible implementation, such as Figure 2 As shown, the differential amplifier module 30 may include a first amplification unit 310 and a second amplification unit 320. The first amplification unit 310 includes a first amplification transistor Q31, a second amplification transistor Q32, a third amplification transistor Q33, a fourth amplification transistor Q34, and a first tail current source I1.
[0089] The control terminal (base) of the first amplifying transistor Q31 and the control terminal (base) of the second amplifying transistor Q32 are used to receive the following voltage signal.
[0090] The first terminal (emitter) of the third amplifying transistor Q33 and the first terminal (emitter) of the fourth amplifying transistor Q33 are both used to receive the power supply voltage (Vdd).
[0091] The control terminal (base) of the third amplifying transistor Q33 and the control terminal (base) of the fourth amplifying transistor Q34 are both used to receive a preset bias voltage (VBias).
[0092] The common node of the second terminal (collector) of the third amplifying transistor Q33, the first terminal (collector) of the first amplifying transistor Q31, the second terminal (collector) of the fourth amplifying transistor Q33, and the first terminal (collector) of the second amplifying transistor Q32 is used to output the first-stage amplified signal (to the input terminal of the second-stage amplifying unit 320).
[0093] The second terminal (emitter) of the first amplifying transistor Q31 and the second terminal (emitter) of the second amplifying transistor Q32 are grounded through the first tail current source I1.
[0094] The first input terminal and the second input terminal of the second amplification unit 320 are used to receive the first-stage amplified signal, and the second amplification unit 320 is used to amplify the first-stage amplified signal and output the differential amplified signal.
[0095] For example, such as Figure 2As shown, the first amplifying transistor Q31 has a parasitic capacitance Cu1 between its base and collector, and the second amplifying transistor Q32 has a parasitic capacitance Cu2 between its base and collector. Due to the presence of parasitic capacitances Cu1 and Cu2, the Miller effect is amplified, causing the secondary point to shift to lower frequencies. In this embodiment, the voltage follower module 20 reduces the resistance (resistance at the input of the differential amplifier module 30) seen forward from the bases of the first amplifying transistor Q31 and the second amplifying transistor Q32, pushing the secondary pole of the loop further away, thereby increasing the bandwidth of the variable gain amplifier and preventing the loop from oscillating when the secondary pole approaches the primary pole during operation.
[0096] This disclosure does not limit the transistor types of the first amplifying transistor Q31, the second amplifying transistor Q32, the third amplifying transistor Q33, and the fourth amplifying transistor Q34. Those skilled in the art can select appropriate transistors based on actual circumstances and needs. For example, ... Figure 2 As shown, the first amplifying transistor Q31, the second amplifying transistor Q32, the third amplifying transistor Q33, and the fourth amplifying transistor Q34 can all be transistors. Among them, the first amplifying transistor Q31 and the second amplifying transistor Q32 can both be NPN transistors, and the third amplifying transistor Q33 and the fourth amplifying transistor Q34 can both be PNP transistors.
[0097] For example, in the embodiments of this disclosure, the first input transistor Q11, the second input transistor Q12, the first amplifying transistor Q31, and the second amplifying transistor Q32 can all be configured to include multiple BJT transistors connected in parallel. In operation, the number of BJT transistors connected in parallel can be controlled by the gain control voltage. For example, if the gain control voltage increases, the number of BJT transistors connected in parallel in the first input transistor Q11, the second input transistor Q12, the first amplifying transistor Q31, and the second amplifying transistor Q32 can be increased or decreased accordingly.
[0098] For example, the second amplification unit 320 may include at least one differential amplifier. The gain of each differential amplifier in the second amplification unit 320 may be fixed or adjustable as needed. For example, it may include two differential amplifiers with gains of A2 and A3, which amplify the first-stage amplified signal output by the first amplification unit 310 respectively. The specific values of A2 and A3 are not limited in this embodiment of the present disclosure. Those skilled in the art can set them according to actual conditions and needs.
[0099] In one possible implementation, the first amplification unit 310 may further include a first common-mode feedback circuit CMFB1, and a second common-mode feedback circuit CMFB2 is provided between the two differential output terminals of the second amplification unit 320. The first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2 are used to stabilize the common-mode voltage.
[0100] The embodiments disclosed herein do not limit the specific implementation of the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2. Those skilled in the art can refer to the common-mode feedback circuits in related technologies to implement them according to actual conditions and needs.
[0101] In one possible implementation, such as Figure 2 As shown, the differential amplifier module 30 may further include a first differential capacitor C2, a second differential capacitor C3, and a first switch K1, wherein...
[0102] The first terminal of the first differential capacitor C2 and the first terminal of the second differential capacitor C3 are both connected to the first input terminal of the second amplification unit 320.
[0103] The second terminal of the second differential capacitor C3 is connected to the first terminal of the first switch K1.
[0104] The second terminal of the first differential capacitor C2 and the second terminal of the first switch K1 are both connected to the second input terminal of the second amplifier unit 320.
[0105] The control terminal of the first switch K1 is used to receive switch control signals.
[0106] This embodiment of the present disclosure sets up a first differential capacitor C2, a second differential capacitor C3, and a first switch K1. The conduction state of the first switch K1 is controlled by a switch control signal. The second differential capacitor C3 can be connected to the circuit or not connected to the circuit as needed, thereby adjusting the input capacitance at the input terminal of the second amplification unit 320.
[0107] This disclosure does not limit the setting method of the switch control signal. Those skilled in the art can set it according to actual conditions and needs. For example, in one possible implementation, the switch control signal is related to the gain control voltage, wherein the gain control voltage can be used to adjust the current of the first tail current source I1 and the second tail current source I2, thereby adjusting the gain of the variable gain amplifier. Exemplarily, the gain control voltage can be set to be inversely correlated with the loop gain. When it is necessary to increase the gain, the gain control voltage can be decreased; when it is necessary to decrease the gain, the gain control voltage can be increased.
[0108] This disclosure does not limit the specific type of the first switch K1. Those skilled in the art can select appropriate devices as needed. For example, the first switch K1 may include any one of the following: a relay, a reed switch, a silicon controlled rectifier, a switching diode, a switching transistor, an electronic bidirectional switch, an optocoupler, a transistor, etc. The transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The transistor may be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.
[0109] For example, in this embodiment of the present disclosure, when the gain control voltage is lower than or equal to a preset voltage, the first switch K1 can be turned on by a switch control signal; conversely, when the gain control voltage is higher than the preset voltage, the first switch K1 can be turned off by a switch control signal. The specific value of the preset voltage can be set according to actual conditions and needs, and this embodiment of the present disclosure does not limit it.
[0110] This disclosure embodiment addresses the gain control voltage (such as...) Figure 2 As shown, the specific size of (denoted as VGAIN) is not limited. Those skilled in the art can set it according to actual conditions and needs. Accordingly, the embodiments of this disclosure can set a preset voltage according to the magnitude of the gain control voltage. The following is an exemplary description.
[0111] For example, the adjustable range of the gain control voltage can be 0.1~1.1V, and correspondingly, the preset voltage can be set to 0.4~0.8V. Taking the preset voltage set to 0.6V as an example, when VGAIN<0.6V, the number of npn transistors in the first amplifying transistor Q31 and the second amplifying transistor Q32 is only 1. At this time, the secondary pole is far away, and the primary pole does not need to be pushed away. Therefore, in this case, the second differential capacitor C3 can be connected to the circuit in this embodiment. When VGAIN>0.6V, the number of npn transistors in parallel in the first amplifying transistor Q31 and the second amplifying transistor Q32 increases. At this time, the secondary pole moves to a lower frequency, and the primary pole needs to be pushed away to maintain the bandwidth. Therefore, the second differential capacitor C3 is disconnected from the circuit in this embodiment.
[0112] This disclosure does not limit the specific generation method of the switch control signal for the first switch K1. Those skilled in the art can implement it according to actual conditions and needs by referring to relevant technologies. For example, this disclosure can set the conduction threshold voltage of the first switch K1 according to the magnitude range of the gain control voltage. In this way, this disclosure can use the gain control voltage directly as a switch control signal to control the conduction or de-conduction of the first switch K1. Of course, this disclosure can also generate a corresponding switch control signal according to the magnitude of the gain control voltage. For example, when the gain control voltage is less than 0.6V, a high-level switch control signal is generated to turn on the first switch K1 so as to connect the second differential capacitor C3 in parallel with the first differential capacitor C2; conversely, when the gain control voltage is above 0.6V, a low-level switch control signal is generated to turn off the first switch K1. In this way, the capacitor at the input terminal of the second amplification unit 320 only has the first differential capacitor C2, thereby pushing the major pole of the VGA away to offset the proximity effect of the secondary pole, thereby maintaining a wide bandwidth level.
[0113] In one example, the processing component includes, but is not limited to, a standalone processor, discrete components, or a combination of processors and discrete components. The processor may include a controller in an electronic device capable of executing instructions. The processor may be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions may be executed via hardware circuitry such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.
[0114] In one possible implementation, such as Figure 2 As shown, the output module 40 may include a first output transistor Q41, a second output transistor Q42, a first current source I41, a second current source I42, a first operational amplifier A41, a second operational amplifier A42, a first output resistor R41, a second output resistor R42, and a third tail current source I3, wherein,
[0115] The control terminal (base) of the first output transistor Q41 and the control terminal (base) of the second output transistor Q42 are used to receive the differential amplified signal.
[0116] The first terminal (collector) of the first output transistor Q41 is connected to the negative terminal of the first current source I41, the first terminal of the first output resistor R41, and the input terminal of the first operational amplifier A41.
[0117] The first terminal (collector) of the second output transistor Q42 is connected to the negative terminal of the second current source I42, the first terminal of the second output resistor R42, and the input terminal of the second operational amplifier A42.
[0118] The positive terminals of the first current source I41 and the second current source I42 are used to receive the power supply voltage (Vdd).
[0119] The second terminal of the first output resistor R41, the common node of the output terminal of the first operational amplifier A41, the second terminal of the second output resistor R42, and the common node of the output terminal of the second operational amplifier A42 are used to generate the output voltage (Von, Vop).
[0120] The second terminal (emitter) of the first output transistor Q41 and the second terminal (emitter) of the second output transistor Q42 are both grounded through the third tail current source I3.
[0121] This disclosure does not limit the transistor types of the first output transistor Q41 and the second output transistor Q42. Those skilled in the art can select appropriate transistors according to actual conditions and needs, for example, Figure 2 As shown, the first output transistor Q41 and the second output transistor Q42 can both be NPN transistors.
[0122] Please see, Figure 3 A simulation diagram of a variable gain amplifier from related technologies and a variable gain amplifier according to an embodiment of this disclosure is shown.
[0123] like Figure 3 As shown, the variable gain amplifier of this embodiment exhibits a significant jump in bandwidth near the preset voltage (0.6V) compared to the variable gain amplifiers of related technologies, indicating that the dominant pole is pushed further away. Simultaneously, this design significantly improves bandwidth; at VGAIN=1.1V, the bandwidth of related technologies is only 1.8MHz, while the bandwidth of this embodiment doubles to 3.5MHz without sacrificing much phase margin.
[0124] Figure 3The curves can be divided into four groups from top to bottom. The horizontal axis represents the control voltage VGAIN, ranging from 0.1 to 1.1V. The vertical axis represents the results of some typical corners. The four groups of curves from top to bottom are: phase margin without major and minor pole adjustment techniques, phase margin with major and minor pole adjustment techniques, loop bandwidth without major and minor pole adjustment techniques, and loop bandwidth with major and minor pole adjustment techniques. In each group of curves, different colors represent different corners. For example, the red and yellow curves can represent the high and low temperature results of the ff corner, respectively, and the blue and green curves can represent the high and low temperature results of the ss corner, respectively.
[0125] Please see Figure 2 Assuming that the variable gain amplifier does not have a voltage follower module 20 between the differential input module 10 and the differential amplification module 30, and the differential control signal is directly input to the input terminal of the differential amplification module 30, and the second differential capacitor C3 and the first switch K1 are removed, that is, only one first differential capacitor C2 is set at the input terminal of the second amplification unit 320, then for this architecture:
[0126] The voltage gain of the variable gain amplifier is Rout / Rin·I3 / I2, where Rout is the resistance value of the first output resistor R41 and the second output resistor R42 (R41, R42), Rin is the resistance value of the first input resistor Rin1 and the second input resistor Rin2 (Rin1, Rin2), I3 is the current of the third tail current source I3, and I2 is the current of the second tail current source I2. The base voltages of the first input transistor Q11, the second input transistor Q12, the first output transistor Q41, and the second output transistor Q42 are provided by a negative feedback loop composed of the differential input module 10 and the differential amplifier module 30. There are two important poles in this loop: one is the primary pole, located at the output terminal of the first amplification unit 310, generated by the amplification resistors (Ro1, Ro2) and the first differential capacitor C2; the other is the secondary pole, located at the output terminal of the differential input module 10, generated by Rin and the parasitic capacitances (Cu1, Cu2) between the base and collector of the amplification transistor.
[0127] In this circuit, the current magnitudes of the first tail current source I1 and the second tail current source I2 are adjusted according to the gain control voltage VGAIN. For example, they can be adjusted proportionally in opposite directions. Ideally, I1·I2 are fixed values. This design ensures that the transconductance product of the first amplifying transistor Q31, the second amplifying transistor Q32, the first input transistor Q11, and the second input transistor Q12 remains consistent. Since Ro1 and Ro2 are typically inversely proportional to the current, if we assume that I1 increases as VGAIN increases, the gain of the loop formed by the differential input module 10 and the differential amplifying module 30 will be inversely proportional to VGAIN; that is, as VGAIN increases, the loop gain decreases. Simultaneously, the dominant pole is provided by the amplifying resistors (Ro1, Ro2) and the first differential capacitor C2. The first differential capacitor C2 does not change with the gain control voltage VGAIN, therefore the dominant pole increases with increasing VGAIN.
[0128] It can be observed that the rate at which the loop gain decreases is consistent with the rate at which the dominant pole increases, both determined by the amplification resistors (Ro1, Ro2). Therefore, the loop gain-bandwidth product remains unchanged, and VGA can thus achieve a fixed bandwidth.
[0129] Furthermore, the above description is only for an ideal situation and does not take into account the location of the secondary pole.
[0130] For example, in circuit implementation, it is often necessary to use switching technology to control the number of parallel npn transistors in the input transistor and amplifying transistor, thereby adjusting the current density. However, the number of npn transistors changes drastically before and after the switch is switched, which leads to a change in the total base capacitance of the npn transistors, causing the secondary pole to shift.
[0131] For example, such as Figure 2 As shown, the first amplifying transistor Q31, the second amplifying transistor Q32, the first input transistor Q11, and the second input transistor Q12 all require switching technology to control current density. Therefore, the output terminals of the differential input module 10, i.e., the bases of the first amplifying transistor Q31 and the second amplifying transistor Q32, will have a large capacitance introduced due to the switching technology. If Rin is chosen to be large, it will cause the secondary pole to fall into the in-band, affecting the bandwidth of the VGA. More seriously, when the gain of the first amplification unit 310 is large, the parasitic capacitance Cu of the first amplifying transistor Q31 and the second amplifying transistor Q32 will be amplified due to the Miller effect, causing the size of the secondary pole to be close to that of the primary pole, and the loop is prone to oscillation.
[0132] In this embodiment of the disclosure, the current density of npn can be controlled by the above-mentioned switching control method (using gain control voltage to control the number of transistors of the first amplifying transistor Q31, the second amplifying transistor Q32, the first input transistor Q11, and the second input transistor Q12). Furthermore, in this embodiment of the disclosure, the effective Rin is reduced by setting the voltage follower module 20 to push the secondary pole further away, thereby reducing the impact of parasitic capacitance and Miller capacitance on the stability and bandwidth of the circuit.
[0133] Furthermore, since the positional relationship between the dominant and secondary poles varies in different designs, to adapt to more situations, the dominant pole is pushed away while the secondary pole is also pushed away. In this embodiment, a first differential capacitor C2, a second differential capacitor C3, and a first switch K1 are set at the input terminal of the second amplification unit 320. The second differential capacitor C3 is connected to the circuit by selecting whether to connect it through the gain control voltage and a preset voltage, thereby adjusting the dominant pole. If pushing away the secondary pole is sufficient in a low-bandwidth system, the dominant pole can remain stationary. However, if in a high-bandwidth system the secondary pole remains within the band after being pushed away, the dominant pole can be pushed away, sacrificing some phase margin to gain bandwidth.
[0134] According to one aspect of this disclosure, a signal processing chip is provided, the signal processing chip including the aforementioned variable gain amplifier.
[0135] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned signal processing chip.
[0136] This disclosure does not limit the specific type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include a terminal device or a server. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.
[0137] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A variable gain amplifier, characterized in that, The variable gain amplifier includes a differential input module, a voltage follower module, a differential amplification module, and an output module, wherein... The differential input module is used to receive the differential input signal and the differential amplified signal output by the differential amplification module, and to output a differential control signal based on the differential input signal and the differential amplified signal. The voltage follower module, connected to the differential input module and the differential amplifier module, is used to receive the differential control signal and output a follower voltage signal to the differential amplifier module according to the differential control signal. The differential amplifier module is used to differentially amplify the following voltage signal and output a differential amplified signal. The output module is connected to the differential amplifier module and is used to generate an output voltage based on the differential amplified signal.
2. The variable gain amplifier according to claim 1, characterized in that, The differential input module includes a first input resistor, a second input resistor, a first input transistor, a second input transistor, and a second tail current source, wherein... The first terminal of the first input resistor and the first terminal of the second input resistor are used to connect to the differential input signal. The common node between the second terminal of the first input resistor and the first terminal of the first input transistor, and the common node between the second terminal of the second input resistor and the first terminal of the second input transistor, are used to output the differential control signal. The second terminal of the first input transistor and the second terminal of the second input transistor are grounded through the second tail current source. The control terminals of the first input transistor and the second input transistor are used to receive the differential amplified signal.
3. The variable gain amplifier according to claim 1, characterized in that, The voltage follower module includes a first voltage follower and a second voltage follower. Both the first and second voltage followers include a first voltage follower transistor, a second voltage follower transistor, a first voltage follower current source, and a second voltage follower current source. The control terminal of the first voltage follower transistor is used to receive the differential control signal. The first terminal of the first voltage follower transistor and the positive terminal of the second voltage follower current source are used to receive the power supply voltage. The second terminal of the first voltage follower transistor is connected to the positive terminal of the first voltage follower current source and the control terminal of the second voltage follower transistor. The negative terminal of the first voltage follower current source and the second terminal of the second voltage follower transistor are grounded. The common node of the first terminal of the second voltage follower transistor and the negative terminal of the second voltage follower current source is used to output the following voltage signal.
4. The variable gain amplifier according to claim 2, characterized in that, The differential amplifier module includes a first amplification unit and a second amplification unit. The first amplification unit includes a first amplification transistor, a second amplification transistor, a third amplification transistor, a fourth amplification transistor, and a first tail current source. The control terminals of the first and second amplifying transistors are used to receive the following voltage signal. The first terminal of both the third and fourth amplifying transistors is used to receive the power supply voltage. The control terminals of the third and fourth amplifying transistors are both used to receive a preset bias voltage. The common node between the second terminal of the third amplifying transistor and the first terminal of the first amplifying transistor, and the common node between the second terminal of the fourth amplifying transistor and the first terminal of the second amplifying transistor, are used to output the first-stage amplified signal. The second terminal of the first amplifying transistor and the second terminal of the second amplifying transistor are grounded through the first tail current source. The first input terminal and the second input terminal of the second amplification unit are used to receive the first-stage amplified signal, and the second amplification unit is used to amplify the first-stage amplified signal and output the differential amplified signal.
5. The variable gain amplifier according to claim 4, characterized in that, The first amplification unit further includes a first common-mode feedback circuit, and a second common-mode feedback circuit is provided between the two differential output terminals of the second amplification unit. The first common-mode feedback circuit and the second common-mode feedback circuit are used to stabilize the common-mode voltage.
6. The variable gain amplifier according to claim 4, characterized in that, The differential amplifier module further includes a first differential capacitor, a second differential capacitor, and a first switch, wherein... The first terminal of the first differential capacitor and the first terminal of the second differential capacitor are both connected to the first input terminal of the second amplification unit. The second terminal of the second differential capacitor is connected to the first terminal of the first switch. The second terminal of the first differential capacitor and the second terminal of the first switch are both connected to the second input terminal of the second amplifier unit. The control terminal of the first switch is used to receive switch control signals.
7. The variable gain amplifier according to claim 6, characterized in that, The switch control signal is related to the gain control voltage, wherein the gain control voltage is used to adjust the current of the first tail current source and the second tail current source, thereby adjusting the gain of the variable gain amplifier.
8. The variable gain amplifier according to claim 1, characterized in that, The output module includes a first output transistor, a second output transistor, a first current source, a second current source, a first operational amplifier, a second operational amplifier, a first output resistor, a second output resistor, and a third tail current source, wherein... The control terminals of the first and second output transistors are used to receive the differential amplified signal. The first terminal of the first output transistor is connected to the negative terminal of the first current source, the first terminal of the first output resistor, and the input terminal of the first operational amplifier. The first terminal of the second output transistor is connected to the negative terminal of the second current source, the first terminal of the second output resistor, and the input terminal of the second operational amplifier. The positive terminals of the first current source and the second current source are used to receive the power supply voltage. The second terminal of the first output resistor, the common node of the output terminal of the first operational amplifier, the second terminal of the second output resistor, and the common node of the output terminal of the second operational amplifier are used to generate the output voltage. The second terminal of the first output transistor and the second terminal of the second output transistor are both grounded through the third tail current source.
9. A signal processing chip, characterized in that, The signal processing chip includes a variable gain amplifier as described in any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the signal processing chip as described in claim 9.