Variable gain amplifier, signal processing circuit and chip, electronic device

Abstract

The present disclosure relates to the technical field of integrated circuits, and particularly relates to a variable gain amplifier, a signal processing circuit and a chip, and an electronic device, the variable gain amplifier comprising a first input transistor, a second input transistor, a first input resistor, a second input resistor, a first tail current source, a differential amplifier, an output module and an adjusting module, wherein the output module is configured to generate a target amplified signal according to a differential amplified signal output by the differential amplifier, the adjusting module is connected to the first input transistor and the second input transistor, and the adjusting module is configured to adjust current density of the first input transistor and the second input transistor according to a received gain control signal. Embodiments of the present disclosure can adaptively adjust the current density of the input transistor according to the size of the gain control signal, can avoid the influence of large injection effect while obtaining a larger amplification coefficient, and thus can ensure the precision of the circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a variable gain amplifier, signal processing circuit and chip, and electronic device. Background Technology

[0002] Variable gain amplifiers (VGAs) are core functional modules in wireless communication transceiver links, high-speed signal processing systems, and analog front-ends. They are used to dynamically adjust signal gain so that subsequent circuits can obtain a stable input signal amplitude. They have wide applications in communication, radar, sensing and other fields.

[0003] However, the current density of the input transistors in current variable gain amplifiers is usually not adjustable, which cannot meet the amplification accuracy requirements of applications. Summary of the Invention

[0004] In view of this, this disclosure proposes a variable gain amplifier, which includes a first input transistor, a second input transistor, a first input resistor, a second input resistor, a first tail current source, a differential amplifier, an output module, and an adjustment module, wherein...

[0005] Both the first terminal of the first input resistor and the first terminal of the second input resistor are used to receive the input voltage.

[0006] The second end of the first input resistor is connected to the first end of the first input transistor and the first input end of the differential amplifier.

[0007] The second terminal of the second input resistor is connected to the first terminal of the second input transistor and the second input terminal of the differential amplifier.

[0008] The first output terminal of the differential amplifier is connected to the control terminal of the first input transistor and the first input terminal of the output module.

[0009] The second output terminal of the differential amplifier is connected to the control terminal of the second input transistor and the second input terminal of the output module.

[0010] The second terminal of the first input transistor and the second terminal of the second input transistor are grounded through the first tail current source.

[0011] The output module is used to generate a target amplified signal based on the differential amplified signal output by the differential amplifier.

[0012] The adjustment module is connected to the first input transistor and the second input transistor, and is used to adjust the current density of the first input transistor and the second input transistor according to the received gain control signal.

[0013] The gain control signal is used to control the gain of the variable gain amplifier.

[0014] In one possible implementation, the adjustment module includes at least one first adjustment transistor, at least one second adjustment transistor, and a switch control circuit, wherein,

[0015] The first terminal of each first adjustment transistor is connected to the first terminal of the first input transistor, and the second terminal of each first adjustment transistor is connected to the second terminal of the first input transistor.

[0016] The first terminal of each second adjustment transistor is connected to the first terminal of the second input transistor, and the second terminal of each second adjustment transistor is connected to the second terminal of the second input transistor.

[0017] The control terminals of each first adjustment transistor and each second adjustment transistor are respectively connected to the control terminals of the first input transistor and the second input transistor through the switch control circuit.

[0018] The switch control circuit is used to: establish a connection relationship between the control terminal of at least one first adjustment transistor and the control terminal of the first input transistor, and a connection relationship between the control terminal of at least one second adjustment transistor and the control terminal of the second input transistor, based on the voltage amplitude of the gain control signal and the magnitude relationship of at least one preset voltage.

[0019] In one possible implementation, the switch control circuit includes at least one first switch, at least one second switch, and at least one voltage comparator, wherein,

[0020] Each first adjusting transistor corresponds one-to-one with each first switch. For any given first adjusting transistor, its control terminal is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the control terminal of the first input transistor.

[0021] Each second adjustment transistor corresponds one-to-one with each second switch. For any given second adjustment transistor, its control terminal is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the control terminal of the second input transistor.

[0022] Each voltage comparator is configured with a different preset voltage to compare the voltage amplitude of the gain control signal with the corresponding preset voltage and output the corresponding comparison result signal.

[0023] The output of each voltage comparator is connected to the control terminal of the corresponding first switch and the control terminal of the second switch. For any voltage comparator, the comparison result signal output by the voltage comparator is used to control the conduction state of at least one first switch and at least one second switch.

[0024] In one possible implementation, the preset voltages of each voltage comparator increase sequentially.

[0025] The number of first adjustment transistors connected to the first input transistor and the number of second adjustment transistors connected to the second input transistor are both related to the voltage amplitude of the gain control signal.

[0026] In one possible implementation, the first input transistor, the second input transistor, the first adjustment transistor, and the second adjustment transistor are all NPN transistors.

[0027] In one possible implementation, the output module includes a first output transistor, a second output transistor, a first current source, a second current source, a first operational amplifier, a second operational amplifier, a first output resistor, a second output resistor, and a second tail current source, wherein...

[0028] The control terminals of the first and second output transistors are used to receive the differential amplified signal.

[0029] The first terminal of the first output transistor is connected to the negative terminal of the first current source, the first terminal of the first output resistor, and the input terminal of the first operational amplifier.

[0030] The first terminal of the second output transistor is connected to the negative terminal of the second current source, the first terminal of the second output resistor, and the input terminal of the second operational amplifier.

[0031] The positive terminals of the first current source and the second current source are used to receive the power supply voltage.

[0032] The second terminal of the first output resistor, the common node of the output terminal of the first operational amplifier, the second terminal of the second output resistor, and the common node of the output terminal of the second operational amplifier are used to generate the target amplified signal.

[0033] The second terminal of the first output transistor and the second terminal of the second output transistor are both grounded through the second tail current source.

[0034] According to one aspect of this disclosure, a signal processing circuit is provided, the signal processing circuit including the aforementioned variable gain amplifier.

[0035] According to one aspect of this disclosure, a signal processing chip is provided, the signal processing chip including the aforementioned signal processing circuit.

[0036] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned signal processing chip.

[0037] In this embodiment, an adjustment module is connected to the first input transistor and the second input transistor. The adjustment module is used to adjust the current density of the first input transistor and the second input transistor according to the received gain control signal. It can adaptively adjust the current density of the input transistor according to the magnitude of the gain control signal, thereby obtaining a large amplification factor and avoiding the influence of large injection effect, thus ensuring the accuracy of the circuit.

[0038] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0040] Figure 1 A schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0041] Figure 2 A schematic diagram of one possible implementation of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0042] Figure 3 A schematic diagram of one embodiment of the adjustment module of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0043] Figure 4 A schematic diagram of a switch control assembly according to an embodiment of the present disclosure is shown.

[0044] Figure 5 The simulation diagram of the amplification factor and characteristic frequency of VGA in related technologies is shown. Detailed Implementation

[0045] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0046] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0047] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0048] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0049] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0050] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0051] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0052] Please see Figure 1 , Figure 1 A schematic diagram of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0053] like Figure 1 As shown, the variable gain amplifier may include a first input transistor Q1, a second input transistor Q2, a first input resistor Rin1, a second input resistor Rin2, a first tail current source I1, a differential amplifier Loop_amp, an output module 10, and an adjustment module 20, wherein...

[0054] The first terminal of the first input resistor Rin1 and the first terminal of the second input resistor Rin2 are both used to receive the input voltage (VIN).

[0055] The second terminal of the first input resistor Rin1 is connected to the first terminal of the first input transistor Q1 and the first input terminal of the differential amplifier Loop_amp.

[0056] The second terminal of the second input resistor Rin2 is connected to the first terminal of the second input transistor Q2 and the second input terminal of the differential amplifier Loop_amp.

[0057] The first output terminal of the differential amplifier Loop_amp is connected to the control terminal of the first input transistor Q1 and the first input terminal of the output module 10.

[0058] The second output terminal of the differential amplifier Loop_amp is connected to the control terminal of the second input transistor Q2 and the second input terminal of the output module 10.

[0059] The second terminals of the first input transistor Q1 and the second input transistor Q2 are grounded through the first tail current source I1.

[0060] The output module 10 is used to generate a target amplified signal (VOUT) based on the differential amplified signal output by the differential amplifier Loop_amp.

[0061] The adjustment module 20 is connected to the first input transistor Q1 and the second input transistor Q2. The adjustment module 20 is used to adjust the current density of the first input transistor Q1 and the second input transistor Q2 according to the received gain control signal.

[0062] The gain control signal is used to control the gain of the variable gain amplifier.

[0063] In this embodiment, an adjustment module 20 is connected to the first input transistor Q1 and the second input transistor Q2. The adjustment module 20 is used to adjust the current density of the first input transistor Q1 and the second input transistor Q2 according to the received gain control signal. It can adaptively adjust the current density of the input transistors according to the magnitude of the gain control signal, thereby obtaining a large amplification factor and avoiding the influence of large injection effect, thus ensuring the accuracy of the circuit.

[0064] For example, the adjustment module 20 can be connected to the first terminal, the second terminal, and the control terminal of the first input transistor Q1, and the first terminal, the second terminal, and the control terminal of the second input transistor Q2. This embodiment does not limit the specific method by which the adjustment module adjusts the current density of the first input transistor Q1 and the second input transistor Q2. Those skilled in the art can implement this method according to actual conditions and needs, referring to relevant technologies. For instance, this embodiment can determine whether to shunt the current flowing through the first input transistor Q1 and the second input transistor Q2 through the adjustment module 20 based on the voltage magnitude of the gain control signal, thereby adjusting the current density of the first input transistor Q1 and the second input transistor Q2. Furthermore, the adjustment module 20 itself can be configured to have one or more shunt branches to select the number of branches connected in parallel with the first input transistor Q1 and the second input transistor Q2 based on the voltage magnitude of the gain control signal, thereby improving the flexibility and efficiency of current density adjustment.

[0065] The present invention does not limit the specific implementation of the output module 10 and the adjustment module 20. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies, as long as the corresponding functions can be achieved.

[0066] This disclosure does not limit the transistor types of the first input transistor Q1 and the second input transistor Q2. Those skilled in the art can select appropriate transistors according to actual conditions and needs, for example, Figure 1 As shown, both the first input transistor Q1 and the second input transistor Q2 can be transistors, specifically NPN transistors. The first terminal of the first input transistor Q1 and the first terminal of the second input transistor Q2 are both collectors, and the second terminals of the first input transistor Q1 and the second input transistor Q2 are both emitters. The control terminals of the first input transistor Q1 and the second input transistor Q2 are both bases.

[0067] This disclosure does not limit the specific method for controlling the gain of a variable gain amplifier using a gain control signal. Those skilled in the art can set the method according to actual conditions and needs. For example, the gain control signal can be used to adjust the current of the first tail current source I1, thereby adjusting the gain of the variable gain amplifier. Exemplarily, the voltage corresponding to the gain control signal can be set to be positively correlated with the loop gain. When gain needs to be increased, the gain control voltage can be increased; when gain needs to be decreased, the gain control voltage can be decreased. For example, if the voltage of the gain control signal (denoted as VGAIN) is between 0.1 and 1.1V, and the preset voltage is set to 0.6V, controlling the gain from 0dB to 80dB corresponds to a change in the I1 current from 10mA to 1uA (the larger the gain, the smaller I1). It can be calculated that for every 0.1V increase in VGAIN, the gain increases by 8dB, and I1 shrinks to 1 / 2.5 of its original value.

[0068] Please see Figure 2 , Figure 2 A schematic diagram of one possible implementation of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0069] In one possible implementation, such as Figure 2 As shown, the adjustment module 20 may include at least one first adjustment transistor Qd (e.g., Qd1~Qdn, where n is a positive integer greater than 1), at least one second adjustment transistor Qe (e.g., Qe1~Qen, where n is a positive integer greater than 1), and a switch control circuit 210, wherein,

[0070] The first terminal (collector) of each first adjustment transistor Qd is connected to the first terminal (collector) of the first input transistor Q1, and the second terminal (emitter) of each first adjustment transistor Qd is connected to the second terminal (emitter) of the first input transistor Q1.

[0071] The first terminal (collector) of each second adjustment transistor Qe is connected to the first terminal (collector) of the second input transistor Q2, and the second terminal (emitter) of each second adjustment transistor Qe is connected to the second terminal (emitter) of the second input transistor Q2.

[0072] The control terminals (bases) of each first adjustment transistor Qd and each second adjustment transistor Qe are respectively connected to the control terminals (bases) of the first input transistor Q1 and the second input transistor Q2 through the switch control circuit 210.

[0073] The switch control circuit 210 is used to: establish the connection relationship between the control terminal of at least one first adjustment transistor Qd and the control terminal of the first input transistor Q1, and the connection relationship between the control terminal of at least one second adjustment transistor Qe and the control terminal of the second input transistor Q2, based on the voltage amplitude of the gain control signal and the magnitude relationship of at least one preset voltage.

[0074] The embodiments disclosed herein do not limit the specific transistor types of the first adjustment transistor Qd and the second adjustment transistor Qe. Those skilled in the art can set them according to actual conditions and needs. The transistor types of the first adjustment transistor Qd and the second adjustment transistor Qe can be the same as those of the first input transistor Q1 and the second input transistor Q2. For example, the first adjustment transistor Qd and the second adjustment transistor Qe are also NPN transistors.

[0075] The present invention does not limit the number of NPN transistors in the first adjustment transistor Qd and the second adjustment transistor Qe. Those skilled in the art can set the number of NPN transistors according to actual conditions and needs. For example, each adjustment transistor may include several or dozens (e.g., 24) NPN transistors. That is, the present invention can set the ratio of the number of NPN transistors in the adjustment transistor to the number of NPN transistors in the input transistor to be N:1, where N is a positive integer greater than 1.

[0076] For example, in this embodiment of the present disclosure, if the switch control circuit 210 connects the control terminal of at least one first adjusting transistor Qd to the control terminal of the first input transistor Q1, and connects the control terminal of at least one second adjusting transistor Qe to the control terminal of the second input transistor Q2, the control voltage of the control terminal of each first adjusting transistor Qd is the same as that of the control terminal of the first input transistor Q1, and the control voltage of the control terminal of each second adjusting transistor Qe is the same as that of the control terminal of the second input transistor Q2. Since the controlled voltage of the adjusting transistors and the input transistors is the same, this embodiment of the present disclosure can shunt the current flowing through the first input transistor Q1 and the second input transistor Q2 through the first adjusting transistor Qd and the second adjusting transistor Qe, thereby reducing the current density.

[0077] Of course, the number of the first adjustment transistor Qd and the second adjustment transistor Qe can be multiple. In the embodiments of this disclosure, the number of adjustment transistors connected to the first input transistor Q1 and the second input transistor Q2 can be selected according to the voltage range of the voltage amplitude of the gain control signal, thereby improving the flexibility of current density adjustment.

[0078] The present disclosure does not limit the specific implementation of the switch control circuit 210. Those skilled in the art can implement it according to the actual situation and needs, referring to relevant technologies, as long as it can achieve its function. The following is an exemplary description.

[0079] In one possible implementation, such as Figure 2 As shown, the switch control circuit 210 may include at least one first switch Kd (e.g., Kd1~Kdn, where n is a positive integer greater than 1), at least one second switch Ke (e.g., Ke1~Ken, where n is a positive integer greater than 1), and at least one voltage comparator COMP (e.g., n comparators), wherein,

[0080] Each first adjustment transistor Qd corresponds one-to-one with each first switch Kd. For any one first adjustment transistor Qd, the control terminal of the first adjustment transistor Qd is connected to the first terminal of the first switch Kd, and the second terminal of the first switch Kd is connected to the control terminal of the first input transistor Q1.

[0081] Each second adjustment transistor Qe corresponds one-to-one with each second switch Ke. For any given second adjustment transistor Qe, the control terminal of Qe is connected to the first terminal of the second switch Ke, and the second terminal of the second switch Ke is connected to the control terminal of the second input transistor Q2.

[0082] Each voltage comparator COMP is configured with a different preset voltage to compare the voltage amplitude of the gain control signal with the corresponding preset voltage and output the corresponding comparison result signal.

[0083] The output of each voltage comparator COMP is connected to the control terminal of the corresponding first switch Kd and the control terminal of the second switch Ke. For any voltage comparator COMP, the comparison result signal output by the voltage comparator COMP is used to control the conduction state of at least one first switch Kd and at least one second switch Ke.

[0084] For example, the number of voltage comparator COMP, first adjustment transistor, and second adjustment transistor can be the same.

[0085] For example, such as Figure 2As shown, if the voltage VGAIN of the gain control signal is between 0.1 and 1.1V, and the preset voltage is set to 0.6V, when VGAIN is between 0.1 and 0.6V, the voltage comparator COMP does not flip, and the comparison result (Ctr signal) output by the voltage comparator COMP is low. The first adjustment transistor Qd and the second adjustment transistor Qe are not connected to the circuit, and the current of the first tail current source I1 is evenly distributed between the first input transistor Q1 and the second input transistor Q2. At this time, the corresponding range of I1 is 1uA to 98uA, and the current density of Q1 and Q2 is in the range of 0.5 to 50uA / unit, which can meet the requirements of characteristic frequency ft and amplification factor β. When VGAIN is between 0 and 1.1V, the voltage comparator COMP does not flip, and the comparison result (Ctr signal) output by the voltage comparator COMP is low. The first adjustment transistor Qd and the second adjustment transistor Qe are not connected to the circuit, and the current of the first tail current source I1 is evenly distributed between the first input transistor Q1 and the second input transistor Q2. At this time, the current of I1 is between 1uA and 98uA, and the current density of Q1 and Q2 is in the range of 0.5 to 50uA / unit, which can meet the requirements of characteristic frequency ft and amplification factor β. When the voltage is between 0.7 and 1.1V, the comparator flips, the Ctr signal is high, and the first adjustment transistor Qd and the second adjustment transistor Qe are connected to the circuit. The current of I1 is distributed among the first input transistor Q1, the second input transistor Q2, the first adjustment transistor Qd, and the second adjustment transistor Qe (if distributed according to a preset ratio, the preset ratio can be the ratio of the number of transistors connected in parallel in each transistor). At this time, the total number of npn is 50, and the range of I1 is 240uA to 10mA. Therefore, the current density of the first input transistor Q1, the second input transistor Q2, the first adjustment transistor Qd, and the second adjustment transistor Qe is 4.8 to 200uA / unit, which can also meet the requirements.

[0086] As can be seen, by adding the adjustment module 20, the current density per unit npn can be controlled within a suitable range, while satisfying the requirements of β and ft, and leaving a certain margin to reduce the impact of resistance ratio, I1 current, temperature and process changes.

[0087] It should be noted that, Figure 2 The illustration shows a case with a first adjusting transistor Qd and a second adjusting transistor Qe, but the embodiments of this disclosure are not limited thereto. The number of the first adjusting transistor Qd and the second adjusting transistor Qe can be set as needed. Correspondingly, the number of the first switch Kd, the second switch Ke, and the voltage comparator COMP can also be adaptively set according to the number of the first adjusting transistor Qd and the second adjusting transistor Qe.

[0088] For example, taking a first adjustment transistor Qd comprising four transistors, correspondingly, there are four first switches Kd, denoted as Kd1~Kd4. Each first switch Kd receives the comparison result of each voltage comparator COMP. The outputs of the four voltage comparators COMP are Ctr_1, Ctr_2, Ctr_3, and Ctr_4, respectively. The first adjustment transistors are denoted as Qd1~Qd4, respectively, and the reference voltages of the voltage comparators COMP from low to high are Vref1~Vref4.

[0089] For example, when VGAIN<Vref1, the outputs of the four comparators are all 0 (low level), at this time all the switches (Kd1 to Kd4) are turned off, and none of Qd1 to Qd4 are connected into the circuit;

[0090] For example, when Vref1<VGAIN<Vref2, Ctr_1 is at a high level at this time, and Ctr_2 to Ctr_4 output by the other three comparators are at a low level, therefore, Kd1 is turned on, Qd1 is connected into the circuit, Qd2 to Qd4 are turned off, and Qd2 to Qd4 are not connected into the circuit;

[0091] For example, when Vref1<Vref2<VGAIN<Vref3, Ctr_1 and Ctr_2 are at a high level, Qd1 to Qd2 are turned on, and Qd1 to Qd2 are connected into the circuit; Ctr_3 to Ctr_4 are at a low level, Qd3 to Qd4 are turned off, and Qd3 to Qd4 are not connected into the circuit;

[0092] By analogy, when VGAIN>Vref4, the comparator outputs Ctr_1 to Ctr_4 are all at a high level, Kd1 to Kd4 are all turned on, and Qd1 to Qd4 are all connected into the circuit.

[0093] It can be seen that the number of the first adjustment transistors Qd and the second adjustment transistors Qe in the embodiments of the present disclosure can be set to multiple, so that a corresponding number of adjustment transistors are selected to be connected to the input transistor according to the range where the voltage VGAIN of the gain control signal is located. In this case, the switch control circuit 210 includes a plurality of first switches Kd, a plurality of second switches Ke, and a plurality of voltage comparators COMP, and the preset voltage of each voltage comparator COMP is set as required. For example, in a possible implementation, the preset voltages of the respective voltage comparators COMP increase sequentially,

[0094] The number of the first adjustment transistors Qd connected to the first input transistor Q1 and the number of the second adjustment transistors Qe connected to the second input transistor Q2 are both related to the voltage amplitude of the gain control signal.

[0095] It should be noted that the embodiments of the present disclosure are not limited to the manner in which the adjustment transistors and the switches are in one-to-one correspondence (each first adjustment transistor Qd is in one-to-one correspondence with each first switch Kd, and each second adjustment transistor Qe is in one-to-one correspondence with each second switch Ke), but the embodiments of the present disclosure are not limited thereto. In other implementations, each adjustment transistor Qd can also be controlled to be turned on or off by a switch control component, and the switch control component is not limited to a single switch form, and may also be a combination of multiple switches, which will be described below by way of example.

[0096] Please refer to Figure 3 , Figure 3A schematic diagram of one embodiment of the adjustment module of a variable gain amplifier according to an embodiment of the present disclosure is shown.

[0097] Please see Figure 4 , Figure 4 A schematic diagram of a switch control assembly according to an embodiment of the present disclosure is shown.

[0098] For example, such as Figure 3 As shown in the embodiments of this disclosure, the first input transistor Q1 and the second input transistor Q2 are respectively provided with a plurality of adjustment transistors, such as... Figure 4 As shown, each adjustment transistor is equipped with a corresponding switch control component Ctr_logic, and each switch control component Ctr_logic is controlled by the comparison result of the corresponding voltage comparator COMP.

[0099] For example, the number of switch control components Ctr_logic, voltage comparator COMP, first adjustment transistor, and second adjustment transistor can be the same.

[0100] For example, each switch control component Ctr_logic may include multiple cascaded switches, and each switch in the switch control component Ctr_logic is controlled by the output signal of the corresponding voltage comparator COMP to turn on or off.

[0101] For example, for the first input transistor Q1, the i-th switch control component Ctr_logic may include i cascaded first switches Kd, where i ≤ n and i is a positive integer. Exemplarily, the first switch control component Ctr_logic corresponds to the first first adjustment transistor Qd and includes one first switch Kd; the second switch control component Ctr_logic corresponds to the second first adjustment transistor Qd and includes two cascaded first switches Kd; the third switch control component Ctr_logic corresponds to the third first adjustment transistor Qd and includes three cascaded first switches Kd, ..., the n-th switch control component Ctr_logic corresponds to the n-th first adjustment transistor Qd and includes n cascaded first switches Kd.

[0102] For example, for the second input transistor Q2, the i-th switch control component Ctr_logic may include i cascaded second switches Ke, where i ≤ n and i is a positive integer. Exemplarily, the first switch control component Ctr_logic corresponds to the first second adjustment transistor Qe and includes one second switch Ke; the second switch control component Ctr_logic corresponds to the second second adjustment transistor Qe and includes two cascaded second switches Ke; the third switch control component Ctr_logic corresponds to the third second adjustment transistor Qe and includes three cascaded second switches Ke, ..., the n-th switch control component Ctr_logic corresponds to the n-th second adjustment transistor Qe and includes n cascaded second switches Ke.

[0103] The following example illustrates the implementation of the switching control component Ctr_logic, using the first adjustment transistor Qd, which comprises four first adjustment transistors Qd.

[0104] like Figure 4 As shown in the example, this example illustrates a possible implementation of the switch control component Ctr_logic when the number of the first adjustment transistors Qd is 4.

[0105] It should be understood that in this example, the second input transistor Q2 is also equipped with four second adjustment transistors Qe, and a corresponding switching control component Ctr_logic is provided.

[0106] For example, such as Figure 3 and Figure 4 As shown, when the number of adjusting transistors is 4, there are corresponding 4 switch control components Ctr_logic and 4 voltage comparators COMP. Each adjusting transistor is equipped with one switch control component Ctr_logic, and each switch control component Ctr_logic includes at least one switch (such as...). Figure 4 As shown, the first input transistor Q1 corresponds to four switch control components Ctr_logic. Each switch control component Ctr_logic includes at least one first switch Kd (denoted as Kd1~Kd4). Each first switch Kd receives the comparison result of each voltage comparator COMP. The outputs of the four voltage comparators COMP are Ctr_1, Ctr_2, Ctr_3, and Ctr_4, respectively. The first adjustment transistors are denoted as Qd1~Qd4, respectively. The reference voltages of the voltage comparators COMP from low to high are Vref1~Vref4.

[0107] For example, such as Figure 4 as shown, when VGAIN<Vref1, the outputs of all four comparators are 0, all switches are disconnected at this time, and none of Qd1 to Qd4 are connected into the circuit;

[0108] For example, as shown in Figure 4 as shown, when Vref1<VGAIN<Vref2, Ctr_1 is at a high level at this time, and Ctr_2 to Ctr_4 output by the other three comparators are at a low level, therefore, Qd1 is connected into the circuit, and Qd2 to Qd4 are not connected into the circuit;

[0109] For example, as shown in Figure 4 as shown, when Vref2<VGAIN<Vref3, Ctr_1 and Ctr_2 are at a high level, and Qd1 to Qd2 are connected into the circuit; Ctr_3 to Ctr_4 are at a low level, and Qd3 to Qd4 are not connected into the circuit;

[0110] By analogy, when VGAIN>Vref4, all the comparator outputs Ctr_1 to Ctr_4 are at a high level, and all of Qd1 to Qd4 are connected into the circuit.

[0111] It should be noted that in the embodiments of the present disclosure, the specific number of NPN transistors in Qd1 to Qd4 can be allocated according to the actual current situation. In addition, the above implementation of the control logic is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure. In other embodiments, those skilled in the art can also implement the same or similar functions by any other means.

[0112] In the embodiments of the present disclosure, the greater the number of the first adjustment transistors Qd and the second adjustment transistors Qe, the further the average current can be reduced. Performing segmented selection and control on the adjustment transistors connected in parallel to the input transistor according to the voltage magnitude of the gain control signal can improve the flexibility and adaptability of adjustment.

[0113] In a possible implementation, as shown in Figure 2 as shown, the output module 10 may include a first output transistor Q3, a second output transistor Q4, a first current source I11, a second current source I12, a first operational amplifier A1, a second operational amplifier A2, a first output resistor Rout1, a second output resistor Rout2, and a second tail current source I2, wherein

[0114] The control terminal (base) of the first output transistor Q3 and the control terminal (base) of the second output transistor Q4 are configured to receive the differential amplified signal,

[0115] The first terminal (collector) of the first output transistor Q3 is connected to the negative electrode of the first current source I11, the first terminal of the first output resistor Rout1, and the input terminal of the first operational amplifier A1,

[0116] The first terminal (collector) of the second output transistor Q4 is connected to the negative terminal of the second current source I12, the first terminal of the second output resistor Rout2, and the input terminal of the second operational amplifier A2.

[0117] The positive terminals of the first current source I11 and the second current source I12 are used to receive the power supply voltage (Vdd).

[0118] The second terminal of the first output resistor Rout1, the common node of the output terminal of the first operational amplifier A1, the second terminal of the second output resistor Rout2, and the common node of the output terminal of the second operational amplifier A2 are used to generate the target amplified signal (Von, Vop).

[0119] The second terminal (emitter) of the first output transistor Q3 and the second terminal (emitter) of the second output transistor Q4 are both grounded through the second tail current source I2.

[0120] This disclosure does not limit the transistor types of the first output transistor Q3 and the second output transistor Q4. Those skilled in the art can select appropriate transistors according to actual conditions and needs, for example, Figure 2 As shown, the first output transistor Q3 and the second output transistor Q4 can both be NPN transistors.

[0121] In this embodiment of the present disclosure, the gain control signal can also control the current magnitude of the second tail current source I2, thereby achieving gain adjustment (of course, the current of the second tail current source I2 can also be fixed). Thus, in this embodiment of the present disclosure, the gain control signal can act on the first tail current source I1 and / or the second tail current source I2, thereby achieving effective control of the gain. This embodiment of the present disclosure does not limit this aspect.

[0122] In one possible implementation, both the first output transistor Q3 and the second output transistor Q4 are NPN transistors.

[0123] For example, such as Figure 2 As shown in the embodiment of this disclosure, the input voltage generates an input current across the first input resistor Rin1 and the second input resistor Rin2, where Iout / Iin = I2 / I1. Then, Iout passes through Rout to generate an output voltage Vout. Therefore, Gain = Vout / Vin = (I2 × Rout) / (I1 × Rin). Generally, the resistance values ​​of Rin and Rout are fixed. If I1 and I2 are designed to be adjustable, the gain can be adjusted by adjusting the ratio of I1 and I2. If I2 is fixed, the gain can be adjusted by adjusting the value of I1 in this embodiment of the disclosure.

[0124] If Rout / Rin=10, i.e. 20dB, and I2 is fixed at 1mA, in order to achieve a voltage gain range of 0~80dB, I1 needs to be able to cover 1uA~10mA, which will cause the current density of the first input transistor Q1 and the second input transistor Q2 to change accordingly.

[0125] In the TSMC 180nm BCD process, in order for the NPN transistor to have a certain ft and β, the current density of the NPN transistor needs to be strictly controlled.

[0126] Please see Figure 5 , Figure 5 The simulation diagram of the amplification factor and characteristic frequency of VGA in related technologies is shown.

[0127] For example, such as Figure 5 As shown, in order to obtain a high β, ensure a certain level of circuit accuracy, and avoid the influence of large injection effects, the current density needs to be controlled below 500uA / unit. For broadband VGA, if a bandwidth of 10MHz is required, the minimum current density required is 30MHz, which corresponds to a current density greater than 600nA / unit. Therefore, under this process, the operating current density of npn can be determined to be 0.6~500uA / unit.

[0128] To achieve an 80dB gain range, I1 needs to cover a current range of 1uA to 10mA. After distributing this current evenly to the first input transistor Q1 and the second input transistor Q2, the current density of the nPN transistor is 500nA to 5mA / unit. If only one nPN transistor is used, it's difficult to meet the required current density of 0.6 to 500uA / unit. Furthermore, if the above conditions change—for example, if the resistance ratio changes, or I1 changes, or even if the temperature and process angle change—the current density of the first input transistor Q1 and the second input transistor Q2 may further exceed the range. Once this range is exceeded, especially in the high-current region, the amplification accuracy of the circuit cannot be guaranteed.

[0129] The variable gain amplifier of this embodiment can ensure that the current density of npn can be kept within a relatively stable range, so that npn can obtain better ft and β at the same time, enabling broadband VGA to work with high performance.

[0130] The variable gain amplifier of this embodiment, by providing the adjustment module 20, has the following beneficial technical effects:

[0131] ① Throughout the entire voltage gain range, i.e. the entire current range of I1, the ft and β of npn can meet the specifications, without the need to compromise between accuracy and speed, thus ensuring both high accuracy and high speed for VGA.

[0132] ② By compressing the current density while leaving a margin, the robustness under different environments can be improved, and the circuit can be expanded according to the magnitude of the I1 current to adapt to different gains.

[0133] According to one aspect of this disclosure, a signal processing circuit is provided, the signal processing circuit including the aforementioned variable gain amplifier.

[0134] According to one aspect of this disclosure, a signal processing chip is provided, the signal processing chip including the aforementioned signal processing circuit.

[0135] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned signal processing chip.

[0136] This disclosure does not limit the specific type of electronic device. For example, an electronic device may include a terminal device, which can be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, self-driving, remote medical surgery, smart grids, transportation safety, smart cities, smart homes, and vehicle-to-everything (V2X) networks. For example, a server can be a local server or a cloud server.

[0137] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A variable gain amplifier, characterized in that, The variable gain amplifier includes a first input transistor, a second input transistor, a first input resistor, a second input resistor, a first tail current source, a differential amplifier, an output module, and an adjustment module, wherein... Both the first terminal of the first input resistor and the first terminal of the second input resistor are used to receive the input voltage. The second end of the first input resistor is connected to the first end of the first input transistor and the first input end of the differential amplifier. The second terminal of the second input resistor is connected to the first terminal of the second input transistor and the second input terminal of the differential amplifier. The first output terminal of the differential amplifier is connected to the control terminal of the first input transistor and the first input terminal of the output module. The second output terminal of the differential amplifier is connected to the control terminal of the second input transistor and the second input terminal of the output module. The second terminal of the first input transistor and the second terminal of the second input transistor are grounded through the first tail current source. The output module is used to generate a target amplified signal based on the differential amplified signal output by the differential amplifier. The adjustment module is connected to the first input transistor and the second input transistor, and is used to adjust the current density of the first input transistor and the second input transistor according to the received gain control signal. The gain control signal is used to control the gain of the variable gain amplifier.

2. The variable gain amplifier according to claim 1, characterized in that, The adjustment module includes at least one first adjustment transistor, at least one second adjustment transistor, and a switch control circuit, wherein... The first terminal of each first adjustment transistor is connected to the first terminal of the first input transistor, and the second terminal of each first adjustment transistor is connected to the second terminal of the first input transistor. The first terminal of each second adjustment transistor is connected to the first terminal of the second input transistor, and the second terminal of each second adjustment transistor is connected to the second terminal of the second input transistor. The control terminals of each first adjustment transistor and each second adjustment transistor are respectively connected to the control terminals of the first input transistor and the second input transistor through the switch control circuit. The switch control circuit is used to: establish a connection relationship between the control terminal of at least one first adjustment transistor and the control terminal of the first input transistor, and a connection relationship between the control terminal of at least one second adjustment transistor and the control terminal of the second input transistor, based on the voltage amplitude of the gain control signal and the magnitude relationship of at least one preset voltage.

3. The variable gain amplifier according to claim 2, characterized in that, The switch control circuit includes at least one first switch, at least one second switch, and at least one voltage comparator, wherein, Each first adjusting transistor corresponds one-to-one with each first switch. For any given first adjusting transistor, its control terminal is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the control terminal of the first input transistor. Each second adjustment transistor corresponds one-to-one with each second switch. For any given second adjustment transistor, its control terminal is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the control terminal of the second input transistor. Each voltage comparator is configured with a different preset voltage to compare the voltage amplitude of the gain control signal with the corresponding preset voltage and output the corresponding comparison result signal. The output of each voltage comparator is connected to the control terminal of the corresponding first switch and the control terminal of the second switch. For any voltage comparator, the comparison result signal output by the voltage comparator is used to control the conduction state of at least one first switch and at least one second switch.

4. The variable gain amplifier according to claim 3, characterized in that, The preset voltages of each voltage comparator increase sequentially. The number of first adjustment transistors connected to the first input transistor and the number of second adjustment transistors connected to the second input transistor are both related to the voltage amplitude of the gain control signal.

5. The variable gain amplifier according to claim 2, characterized in that, The first input transistor, the second input transistor, the first adjustment transistor, and the second adjustment transistor are all NPN transistors.

6. The variable gain amplifier according to claim 1, characterized in that, The output module includes a first output transistor, a second output transistor, a first current source, a second current source, a first operational amplifier, a second operational amplifier, a first output resistor, a second output resistor, and a second tail current source, wherein... The control terminals of the first and second output transistors are used to receive the differential amplified signal. The first terminal of the first output transistor is connected to the negative terminal of the first current source, the first terminal of the first output resistor, and the input terminal of the first operational amplifier. The first terminal of the second output transistor is connected to the negative terminal of the second current source, the first terminal of the second output resistor, and the input terminal of the second operational amplifier. The positive terminals of the first current source and the second current source are used to receive the power supply voltage. The second terminal of the first output resistor, the common node of the output terminal of the first operational amplifier, the second terminal of the second output resistor, and the common node of the output terminal of the second operational amplifier are used to generate the target amplified signal. The second terminal of the first output transistor and the second terminal of the second output transistor are both grounded through the second tail current source.

7. A signal processing circuit, characterized in that, The signal processing circuit includes a variable gain amplifier as described in any one of claims 1-6.

8. A signal processing chip, characterized in that, The signal processing chip includes the signal processing circuit as described in claim 8.

9. An electronic device, characterized in that, The electronic device includes the signal processing chip as described in claim 8.

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