A gain slope conversion circuit for a dB linear variable gain amplifier

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a gain slope conversion circuit suitable for a dB linear variable gain amplifier, which comprises a V MODE signal input stage circuit, a setting node V O1 ~V O4 ; the V MODE signal input stage circuit is used for switching the output state of the node V O1 ~V O4 according to the level state of a conversion control signal, so as to determine the direction of a gain slope; the V GPOS -V GNEG signal input stage circuit is used for converting a differential gain control voltage V GPOS − V GNEG into current signals I S1 and I S2 according to the determined direction of the gain slope; a finger stage circuit is used for receiving the current signals I S1 and I S2 and outputting currents I SINK1 ~I SINK8 ; and a transconductance gating stage circuit is used for changing the gain value of the amplifier according to the distribution of the currents I SINK1 ~I SINK8 ; the application can meet the demand of a complex system for positive and negative conversion of a gain slope.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a gain slope conversion circuit suitable for dB linear variable gain amplifiers. Background Technology

[0002] A dB linear variable gain amplifier is an amplifier whose gain (in dB) is linearly related to the gain control voltage (V). Its core function is to adjust the gain in real time by regulating the gain control voltage, thereby ensuring the amplitude stability of the signal under different operating conditions. These amplifiers are widely used in automatic gain control (AGC) loops, test and measurement equipment, and sensor signal conditioning. However, some dB linear variable gain amplifiers only exhibit a monotonic relationship between gain and gain control voltage, which is insufficient to meet the requirements of flexible adjustment of this correlation in complex system designs. Summary of the Invention

[0003] To address the above problems, this invention provides a gain slope conversion circuit suitable for dB linear variable gain amplifiers, comprising:

[0004] V MODE The signal input stage circuit has internal nodes O1 to O4, and the voltage of each node is denoted as V. O1 ~V O4 The V MODE The signal input stage circuit is used to convert the control signal V. MODE Level state switching V O1 ~V O4 The output state is used to determine the direction of the gain slope; where:

[0005] When the conversion control signal V MODE When it is high, V O1 and V O2 It exhibits low impedance to the outside, V O3 and V O4 Output a high level;

[0006] When the conversion control signal V MODE When it is low, V O3 and V O4 It exhibits low impedance to the outside, V O1 and V O2 Output a high level;

[0007] V GPOS -V GNEG The signal input stage circuit is connected to the non-inverting input of the gain control voltage V. GPOS and the gain control voltage inverting terminal V GNEG It is also connected to V MODENodes O1~O4 of the signal input stage circuit; the V GPOS -V GNEG The signal input stage circuit is used to determine the signal input based on V. MODE The gain slope direction determined by the signal input stage circuit will affect the differential gain control voltage V. GPOS -V GNEG Converted to current signal I S1 and I S2 Output;

[0008] Interpolation stage circuit, used to receive V GPOS -V GNEG The current signal I output by the signal input stage circuit S1 and I S2 Output current I SINK1 ~I SINK8 ;

[0009] Transconductance gating stage circuit, used to select based on current I SINK1 ~I SINK8 The distribution of the transconductance stage is used to select the corresponding transconductance stage, thereby changing the gain value of the amplifier.

[0010] The beneficial effects of this invention are:

[0011] The gain slope conversion circuit of the dB linear variable gain amplifier involved in this invention can meet the requirements of positive and negative conversion of gain slope in complex system design.

[0012] This circuit is highly versatile and is applicable not only to the aforementioned differential gain control voltage but also to single-ended gain control voltage.

[0013] This invention employs a bipolar process, which can verify and promote the further development of advanced processes. Attached Figure Description

[0014] Figure 1 This is a diagram of a VGA architecture based on gain interpolation according to an embodiment of the present invention;

[0015] Figure 2 This is a structural diagram of a conventional dB linear variable gain amplifier according to an embodiment of the present invention;

[0016] Figure 3 This is a conventional GM cell bias circuit diagram according to an embodiment of the present invention;

[0017] Figure 4 This is a conventional GM unit circuit diagram according to an embodiment of the present invention;

[0018] Figure 5 V in the gain slope conversion circuit of this embodiment of the invention MODE Signal input stage circuit diagram;

[0019] Figure 6 V in the gain slope conversion circuit of this embodiment of the invention GPOS -V GNEG Signal input stage circuit diagram;

[0020] Figure 7 This is a circuit diagram of the interpolation stage in the gain slope conversion circuit of this invention embodiment;

[0021] Figure 8 This is a circuit diagram of the transconductance gating stage in the gain slope conversion circuit of this invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] In analog circuits, dB linear variable gain amplifiers typically employ a VGA architecture based on gain interpolation, such as... Figure 1 As shown. This structure utilizes a passive resistor network composed of resistors R and 2R as a multi-stage attenuator, inputting signals with different attenuation factors into multiple transconductance stages (g). m1 ~g mn The current is converted from the input to the current-to-voltage converter and then converges to the input of the fixed-gain amplifier. After current-to-voltage conversion, the final output is a voltage VOUT. Continuous gain adjustment can be achieved by controlling the conduction state of a specific transconductance stage and its adjacent stages, and by increasing or decreasing the number of stages accordingly. The final gain is determined by the feedback resistor R. F1 R F2 It is determined by both the effective attenuation factor and the equivalent attenuation factor.

[0024] Based on this, an existing dB linear variable gain amplifier structure is as follows: Figure 2 As shown, it introduces a GM cell bias circuit driven by a gain control voltage into the aforementioned gain interpolation architecture to control the GM cell circuit composed of multiple transconductance stages, thereby achieving continuous and controllable gain.

[0025] The specific GM unit bias circuit is as follows: Figure 3 As shown. Gain control voltage V GPOS and V GNEG It first undergoes two stages of buffering and one stage of amplification, and is then amplified to V. A1 ~V A8 The voltage amplification factor is A. V A1 ~V A8The values ​​are respectively:

[0026] ,

[0027] ,

[0028] ,

[0029] ,

[0030] ,

[0031] ,

[0032] ,

[0033] ,

[0034] Therefore, the voltage V A1 To V A8 With gain control voltage V GPOS and V GNEG There is a correlation between them. These voltages, serving as analog switch control voltages for each transconductance stage in the GM unit circuit, regulate the signal attenuation by controlling the on / off state of transistors Q4 to Q11, such as... Figure 4 As shown.

[0035] Assuming the fixed gain determined by R1 and R2 is 36 dB, then under different gain control voltages V GPOS With V GNEG Under this effect, the specific gain adjustment process is as follows:

[0036] when At that time, V A1 At maximum, Q4 is on, input signal attenuation is -3dB to 0dB, and total amplification is 33dB to 36dB;

[0037] when At that time, V A2 At its maximum, Q5 is turned on, the input signal attenuates by -9dB to -3dB, and the total amplification factor is 27dB to 33dB.

[0038] when At that time, V A3 At its maximum, Q6 is turned on, the input signal attenuation is -15dB to -9dB, and the total amplification factor is 21dB to 27dB.

[0039] when At that time, V A4 At its maximum, Q7 is turned on, the input signal attenuation is -21dB to -15dB, and the total amplification factor is 15dB to 21dB.

[0040] when At that time, V A5 At its maximum, Q8 is turned on, the input signal attenuation is -27dB to -21dB, and the total amplification factor is 9dB to 15dB.

[0041] when At that time, V A6 At its maximum, Q9 is turned on, the input signal attenuation is -33dB to -27dB, and the total amplification factor is 3dB to 9dB.

[0042] when At that time, V A7 At its maximum, Q10 is turned on, the input signal attenuation is -39dB to -33dB, and the total amplification factor is -3dB to 3dB.

[0043] when At that time, V A8 At its maximum, Q11 is turned on, the input signal attenuation is -42dB to -39dB, and the total amplification factor is -6dB to -3dB.

[0044] The above analysis shows that the gain of the existing dB linear variable gain amplifier varies with the gain control voltage V. GPOS -V GNEG The gain increases with the gain control voltage, and the two are positively correlated. However, in some applications, the gain and the gain control voltage need to be negatively correlated, or even switch between positive and negative correlation. Under such requirements, simply soldering other components around the variable gain amplifier often makes it difficult to keep the input and output ranges constant at the same time, thus failing to meet the design requirements of complex systems.

[0045] To overcome the problem that the correlation between gain and gain control voltage in the aforementioned dB linear variable gain amplifier cannot meet the design requirements of complex systems, i.e., it cannot switch between positive and negative correlation, this invention proposes a gain slope conversion circuit suitable for dB linear variable gain amplifiers. This circuit switches the control signal V... MODE The high and low levels enable the variable gain amplifier to switch between positive and negative gain slopes while keeping the input and output ranges essentially unchanged.

[0046] In some embodiments, the circuit provided by the present invention includes:

[0047] V MODE The signal input stage circuit has internal nodes O1 to O4, and the voltage of each node is denoted as V. O1 ~V O4 The V MODE The signal input stage circuit is used to convert the control signal V. MODE Level state switching VO1 ~V O4 The output state is used to determine the direction of the gain slope; where:

[0048] When the conversion control signal V MODE When it is high, V O1 and V O2 It exhibits low impedance to the outside, V O3 and V O4 Output a high level;

[0049] When the conversion control signal V MODE When it is low, V O3 and V O4 It exhibits low impedance to the outside, V O1 and V O2 Output a high level;

[0050] V GPOS -V GNEG The signal input stage circuit is connected to the non-inverting input of the gain control voltage V. GPOS and the gain control voltage inverting terminal V GNEG It is also connected to V MODE Nodes O1~O4 of the signal input stage circuit; the V GPOS -V GNEG The signal input stage circuit is used to determine the signal input based on V. MODE The gain slope direction determined by the signal input stage circuit will affect the differential gain control voltage V. GPOS -V GNEG Converted to current signal I S1 and I S2 Output;

[0051] Interpolation stage circuit, used to receive V GPOS -V GNEG The current signal I output by the signal input stage circuit S1 and I S2 Output current I SINK1 ~I SINK8 ;

[0052] Transconductance gating stage circuit, used to select based on current I SINK1 ~I SINK8 The distribution of the transconductance stage is used to select the corresponding transconductance stage, thereby changing the gain value of the amplifier.

[0053] Preferably, such as Figure 5 As shown, the V MODE The signal input stage circuit includes resistors R1~R15, NPN transistors Q1~Q3, PNP transistors Q4, NPN transistors Q5~Q7, PNP transistors Q8~Q11, NPN transistors Q12~Q15, and diodes D1~D3, wherein:

[0054] One end of resistor R1 is connected to the reference voltage V. BIAS1 Its other end is connected to the collector of NPN transistor Q1, one end of resistor R2, and the bases of NPN transistors Q12~Q15; the base of NPN transistor Q1 is connected to the other end of resistor R2, and the emitter of NPN transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 is grounded; one end of resistor R4 is connected to the conversion control signal V. MODE The other end of resistor R4 is connected to the anode of diode D1 and the base of NPN transistors Q2-Q3; the cathode of diode D1 is connected to the base of NPN transistor Q5; the collector of NPN transistor Q5 is connected to one end of resistor R8, the anode of diode D2, and the base of NPN transistors Q6-Q7; the emitter of NPN transistor Q5 is grounded; the cathode of diode D2 is connected to the anode of diode D3; the cathode of diode D3 is grounded; the collectors of NPN transistors Q2-Q3 are connected to one end of resistor R7 and the base of PNP transistors Q8-Q9; the emitter of NPN transistor Q2 is connected to one end of resistor R5; the emitter of NPN transistor Q3 is connected to one end of resistor R6; the other end of resistor R5 is connected to one end of resistor R12 and the emitter of NPN transistor Q12; the other end of resistor R6 is connected to one end of resistor R13 and the emitter of NPN transistor Q12. The emitter of transistor Q13 is connected to the collector of NPN transistors Q6-Q7, which is connected to one end of resistor R9 and the base of PNP transistors Q10-Q11. The emitter of PNP transistor Q4 is connected to power supply VCC, and the base of PNP transistor Q4 is connected to the collector of NPN transistor Q4, the other end of resistor R7, the other end of resistor R8, the other end of resistor R9, and the emitters of PNP transistors Q8-Q11. The emitter of NPN transistor Q6 is connected to one end of resistor R10, and the emitter of NPN transistor Q7 is connected to one end of resistor R11. The other end of resistor R10 is connected to one end of resistor R14 and the emitter of NPN transistor Q14, and the other end of resistor R11 is connected to one end of resistor R15 and the emitter of NPN transistor Q15. The collector of PNP transistor Q8 is connected to the collector of NPN transistor Q12. This connection point is denoted as node O4, and its voltage is V. O4 The collector of PNP transistor Q9 is connected to the collector of NPN transistor Q13. This connection point is denoted as node O3, and its voltage is V. O3 The collector of PNP transistor Q10 is connected to the collector of NPN transistor Q14. This connection point is denoted as node O2, and its voltage is V. O2 The collector of PNP transistor Q11 is connected to the collector of NPN transistor Q15. This connection point is denoted as node O1, and its voltage is V. O1 The other end of resistors R12~R15 is grounded.

[0055] Preferably, such as Figure 6 As shown, the V GPOS -V GNEGThe signal input stage circuit includes PNP transistors Q16-Q17, NPN transistors Q18, PNP transistors Q19-Q20, NPN transistors Q21-Q25, PNP transistors Q26-Q27, resistors R16-R21, and current source I. total1 ~I total2 Subtractor, where:

[0056] Gain control voltage non-inverting input V GPOS Connect the base of PNP transistor Q16, and the inverting input of the gain control voltage V. GNEG Connect the base of PNP transistor Q17; connect the emitter of PNP transistor Q16 to current source I. total1 The output terminal and the inverting terminal of the subtractor are connected, and the emitter of the PNP transistor Q17 is connected to the current source I. total1 The output terminal of the subtractor is connected to the non-inverting terminal of the subtractor, and the output signal V of the subtractor is... GPOS -V GNEG Connect one end of resistor R16 to the emitter of NPN transistor Q18, with reference voltage V. BIAS2 Connect the base of NPN transistor Q18, the base of NPN transistor Q21, and the base of NPN transistor Q23; connect the collector of NPN transistor Q18 to the collectors of PNP transistors Q19~Q20, and connect the base of PNP transistor Q19 to V. O4 The base of the PNP transistor Q20 is connected to V. O1 The emitter of NPN transistor Q21 is connected to one end of resistor R17, the emitter of NPN transistor Q22 is connected to one end of resistor R18, the emitter of NPN transistor Q23 is connected to one end of resistor R20, and the emitter of NPN transistor Q25 is connected to one end of resistor R21. The collector of NPN transistor Q21 is connected to the collector of NPN transistor Q22, the base of NPN transistor Q24, and current source I. total2 The output terminal; the collector of NPN transistor Q23 is connected to the base of NPN transistor Q22, the base of NPN transistor Q25, and one end of resistor R19. The other end of resistor R19 is connected to the emitter of NPN transistor Q24. The collector of NPN transistor Q25 is connected to the collectors of PNP transistors Q26~Q27. The base of PNP transistor Q26 is connected to V... O2 The base of PNP transistor Q27 is connected to V. O3 The emitters of PNP transistor Q19 and PNP transistor Q26 are connected, and this connection point serves as the first current output terminal, used to output current I. S1 The emitters of PNP transistor Q20 and PNP transistor Q27 are connected, and this connection point serves as the second current output terminal for outputting current I. S2 Power supply VCC connected to current source I total1 Input terminal, current source I total2The input terminal, the collector of NPN transistor Q24, the collector of PNP transistor Q16, the collector of PNP transistor Q17, the other ends of resistors R16~R18, and the other ends of resistors R20~R21 are all grounded.

[0057] Preferably, such as Figure 7 As shown, the interpolation stage circuit includes PNP transistors Q28~Q36, NPN transistors Q37~Q44, resistors R22~R31, and current source I. total3 ,in:

[0058] The emitter of PNP transistor Q28 is connected to one end of resistor R23; the emitter of PNP transistor Q29 is connected to one end of resistor R24; the emitter of PNP transistor Q30 is connected to one end of resistor R25; the emitter of PNP transistor Q31 is connected to one end of resistor R26; the emitter of PNP transistor Q32 is connected to one end of resistor R27; the emitter of PNP transistor Q33 is connected to one end of resistor R28; the emitter of PNP transistor Q34 is connected to one end of resistor R29; the emitter of PNP transistor Q35 is connected to one end of resistor R30; the emitter of PNP transistor Q36 is connected to one end of resistor R31; and the collector of PNP transistor Q28 is connected to the base of PNP transistors Q28~Q36 and one end of resistor R22.

[0059] The collector of PNP transistor Q29 is connected to the base of NPN transistor Q37 and the current I. S1 Let this connection point be designated as the first intermediate point, with a voltage of V1; the collector of PNP transistor Q30 is connected to the base of NPN transistor Q38, and this connection point is designated as the second intermediate point, with a voltage of V2; the collector of PNP transistor Q31 is connected to the base of NPN transistor Q39, and this connection point is designated as the third intermediate point, with a voltage of V3; the collector of PNP transistor Q32 is connected to the base of NPN transistor Q40, and this connection point is designated as the fourth intermediate point, with a voltage of V4; PNP The collector of transistor Q33 is connected to the base of NPN transistor Q41. This connection point is designated as the fifth intermediate point, and its voltage is V5. The collector of PNP transistor Q34 is connected to the base of NPN transistor Q42. This connection point is designated as the sixth intermediate point, and its voltage is V6. The collector of PNP transistor Q35 is connected to the base of NPN transistor Q43. This connection point is designated as the seventh intermediate point, and its voltage is V7. The collector of PNP transistor Q36 is connected to the base of NPN transistor Q44 and the current I. S2 This connection point is designated as the eighth intermediate point, and its voltage is V8; current source I total3 The input terminal is connected to the other end of resistor R22 and the emitter of NPN transistors Q37~Q44. This connection point is designated as the midpoint, and its voltage is V0. The collectors of NPN transistors Q37~Q44 serve as current output terminals, sequentially outputting current I. SINK1 ~I SINK8A resistor of the same value is connected between each of the following intermediate points: the first intermediate point and the second intermediate point, the second intermediate point and the third intermediate point, the third intermediate point and the fourth intermediate point, the fourth intermediate point and the fifth intermediate point, the fifth intermediate point and the sixth intermediate point, the sixth intermediate point and the seventh intermediate point, and the seventh intermediate point and the eighth intermediate point.

[0060] Furthermore, the resistance values ​​of resistors R25 to R30 are kept consistent, and the resistance values ​​of resistors R24 and R31 are kept consistent.

[0061] Preferably, such as Figure 8 As shown, the transconductance gating stage circuit includes eight units, each consisting of a resistor and a transistor; in the q-th unit, q = 1, 2, ..., 8, one end of the resistor is connected to a voltage V. REF The other end of the resistor is connected to the current I. SINKq The base of the transistor; the emitter of the transistor is connected to the current source I. total4 The output terminal of the transistor is the collector, which is used to output current I. q .

[0062] In the q-th unit, the voltage between the other end of the resistor and the base of the transistor is denoted as V. Aq .

[0063] Furthermore, the transistors in the first to eighth units are all PNP transistors, and are designated as Q45 to Q52 respectively.

[0064] Furthermore, the eight units of the transconductance gating stage circuit use resistors with the same resistance value.

[0065] The working principle of the circuit proposed in this embodiment of the invention is as follows:

[0066] First, assume the power supply VCC = 5V. For Figure 5 The V shown MODE The signal input stage circuit, when the conversion control signal V MODE When the voltage level is high, a current is generated across resistor R4, most of which flows into the base of Q5, causing a large transient current at the collector of Q5. Because the resistance of R8 is relatively large, the collector voltage of Q5 is very low, causing Q5 to enter deep saturation, i.e., Q5 acts as a switch. At this time, the forward voltage drop V of diode D1... D With the base-emitter voltage V of Q5 BEQ5 The sum of these voltages causes Q2 and Q3 to conduct, generating currents in R5 and R6 respectively. These currents flow through R12 and R13, increasing the emitter voltages of Q12 and Q13. The base voltages of Q12 and Q13 are determined by the reference voltage V. BIAS1 Decision, V BIAS1The current generated across R3 determines the collector voltage of Q1. This voltage is relatively small, causing Q12 and Q13 to fail to conduct because their base-emitter voltage is lower than the turn-on voltage. On the other hand, the larger resistor R7 only requires a current of a few tens of microamps to turn on Q8 and Q9, but most of the collector current of Q2 and Q3 needs to be pulled from the bases of Q8 and Q9, approaching hundreds of microamps. Theoretically, the current flowing into node V... O3 and V O4 The currents originate from Q8 and Q9 respectively, but at V GPOS -V GNEG In the signal input stage circuit, node V O3 and V O4 Since there is no path for current to reach ground, the collector current I of Q8... CQ8 and the collector current I of Q9 CQ9 Approaching 0, Q8 and Q9 are in deep saturation. At this time, the collector-emitter voltage V of Q8... CEQ8 With the collector-emitter voltage V of Q9 CEQ9 Satisfy | V CEQ8 | = |V CEQ9 | ≈10 mV, therefore V O3 = V O4 ≈ 4.1 V. Because the collector voltage of Q5 is extremely low, Q6 and Q7 are not working, and no current flows through R9, preventing Q10 and Q11 from conducting. Simultaneously, there is no current through R10 and R11, resulting in low emitter voltages for Q14 and Q15. At this point, the collector voltage of Q1 is sufficient to turn on Q14 and Q15, so the current flowing from nodes O1 and O2 flows through Q14 and Q15.

[0067] When the conversion control signal V MODE When the voltage is low, Q2, Q3, D1, Q5, Q8, and Q9 are not conducting. The current flowing from nodes O3 and O4 flows through Q12 and Q13, respectively. The presence of D2 and D3 turns on Q6, Q7, Q10, and Q11, while Q14 and Q15 are not conducting. Q10 and Q11 are in deep saturation. At this time, the collector-emitter voltage V of Q13 is... CEQ13 With the collector-emitter voltage V of Q14 CEQ14 Satisfy | V CEQ13 | = |V CEQ14 | ≈ 10 mV, therefore V O1 = V O2 ≈ 4.1 V.

[0068] for Figure 6 The V shown GPOS -V GNEG Signal input stage circuit, gain control voltage non-inverting input V GPOSand the gain control voltage inverting terminal V GNEG Converted to difference V by subtraction GPOS - V GNEG This difference controls the collector current I of Q18 through resistor R16. CQ18 The collector current I of Q21 CQ21 For I CQ18 1 / K times, the collector current I of Q22 CQ22 With the collector current I of Q21 CQ21 From current source I total2 Provide the collector current I of Q25 CQ25 For I CQ22 K times.

[0069] for Figure 7 The interpolation stage circuit shown is connected to V. GPOS -V GNEG I of the signal input stage circuit S1 and I S2 Since the collector currents of Q28~Q36 are all stable current sources, meaning Q28~Q36 are all in the amplification region, the CB junction is reverse biased, and the values ​​of V1~V8 are all less than approximately 4.3 V. Therefore, regardless of V... MODE Whether it is at a high or low level, or V O1 and V O2 Approximately 4.1 V makes Q20 and Q26 non-conducting, or V O3 and V O4 A voltage of approximately 4.1 V prevents Q19 and Q27 from conducting; they cannot occur simultaneously. Therefore, I... S1 + I S2 = I CQ18 + I CQ25 = K·I total2 , that is I S1 with I S2 The sum is a constant. In the design, the collector currents of Q30~Q35 are assumed to be the same, denoted as I; the collector currents of Q29 and Q36 are the same, denoted as aI; and it is assumed that β of Q28~Q36 is much greater than 1. Analyzing the circuit according to Kirchhoff's Current Law (KCL), we can obtain:

[0070] (1)

[0071] (2)

[0072] (3)

[0073] (4)

[0074] (5)

[0075] (6)

[0076] (7)

[0077] (8)

[0078] Adding (1) to (8), we get:

[0079] (9)

[0080] Right now:

[0081] (10)

[0082] Using (4)-(5), (3)-(6), (2)-(7), we can obtain:

[0083] (11)

[0084] (12)

[0085] (13)

[0086] Using (1)-(8), we can obtain:

[0087] (14)

[0088] It is now known that I S1 with I S2 The sum is a constant. Under the condition that the resistance R is constant, the gain controls the voltage V. GPOS -V GNEG The controlled difference I S2 -I S1 This determines the difference between V1 and V8. Since the collector current of Q28 is bI, then:

[0089] (15)

[0090] During the design, when parameter a, determined by the ratio of R24 to R25, is a constant, I S1 with I S2 The sum of these factors determines the magnitude of the current I. IR determines the voltage relationship between three adjacent points, such as the difference between (V2-V3) and (V2-V1), but it cannot determine the voltage difference between any two adjacent points individually. However, by adding the sum of (I...)... S2 -I S1The difference between V1 and V8, determined by R, determines the voltage difference between two adjacent points. The ratio of R23 to R25 determines the parameter b, while R22 and R23 together determine the value of V0. Since I... total3 It is a constant, i.e., I SINK1 to I SINK8 The sum remains constant, therefore V1~V8, which have a certain difference distribution, determine I. SINK1 ~I SINK8 The distribution of values ​​was determined, which ultimately led to the determination of the specific values ​​of V1 to V8.

[0091] for Figure 8 The transconductance gating stage circuit shown, I SINK1 ~I SINK8 The distributed current flows through the same resistor R32, generating a voltage V with a certain voltage difference distribution across Q45~Q52. A1 ~V A8 ,and Figure 4 V in A1 ~V A8 These voltages select the corresponding transconductance stages by controlling the magnitude of the transconductance stage tail currents I1~I8, thereby controlling the amplitude of the input signal entering the fixed gain amplifier, and thus adjusting the gain of the entire amplifier.

[0092] In summary, when V MODE When it is high, V O3 = V O4 ≈ 4.1 V. Since V1~V8 are all less than 4.3 V, Q19 and Q27 are not conducting, while Q20 and Q26 are conducting. When V GPOS - V GNEG As I continuously increases from 0, CQ18 Gradually increasing from 0 to K·I total2 I CQ25 Then correspondingly from K·I total2 Decrease to 0. During this process, I S2 From small to large, I S1 From large to small. Among them, when I S2 =0、I S1 = K·I total2 When V8 > V1, then I SINK8 The current is at its maximum, decreasing sequentially to the left to I. SINK1 The current is at its minimum, and therefore V A8 > V A1 The current is highest at I8, decreasing sequentially to the left until the current is lowest at I1, where the attenuation factor reaches its maximum and the overall gain is minimum. When I... S2 =I S1 = K·I total2 When V8 = V1 and V4 = V5, then ISINK4 and I SINK5 The current is at its maximum at I4 and decreases sequentially to both sides. Consequently, I4 and I5 have the highest currents, decreasing sequentially to both sides. The attenuation factor is in the middle, and the overall gain is in the middle. When I... S2 =K·I total2 I S1 When V = 0, V8 < V1, at this time I SINK1 The current is at its maximum, decreasing sequentially to the right. Consequently, I1 current is at its maximum, decreasing sequentially to the right, with the attenuation factor at its minimum and the overall gain at its maximum. Therefore, the overall gain increases with the increase of the gain control voltage.

[0093] When V MODE When it is low, V O1 = V O2 ≈ 4.1 V. Since V1~V8 are all less than 4.3 V, Q20 and Q26 are not conducting, while Q19 and Q27 are conducting. When V GPOS - V GNEG As I continuously increases from 0, CQ18 Gradually increasing from 0 to K·I total2 I CQ25 Then correspondingly from K·I total2 Decrease to 0. During this process, I S2 From large to small, I S1 From small to large. Among them, when I S2 = K·I total2 I S1 When V = 0, V8 < V1, at this time I SINK1 The current is at its maximum, decreasing sequentially to the right, thus I1 is at its maximum, decreasing sequentially to the right, with the smallest attenuation factor and the largest overall gain. When I... S2 = I S1 = K·I total2 When V8 = V1 and V4 = V5, then I SINK4 and I SINK5 The current is at its maximum at I4 and decreases sequentially to both sides. Consequently, I4 and I5 have the highest currents, decreasing sequentially to both sides. The attenuation factor is in the middle, and the overall gain is in the middle. When I... S2 = 0、I S1 = K·I total2 When V8 > V1, then I SINK8 The current is at its maximum, decreasing sequentially to the left to I. SINK1 The current is at its minimum, and therefore V A8 > V A1 The current is highest at I8, decreasing sequentially to the left until I1 has the lowest current, the largest attenuation factor, and the lowest overall gain. Therefore, the overall gain decreases as the gain control voltage increases.

[0094] It is important to note that if V is required... GPOS -V GNEG If it varies within a certain range, simply include V in the design. GPOS -V GNEG Set it to the midpoint of this interval, and adjust R16, R24, and R25 so that I at this point... SINK4 and I SINK5 The maximum current is sufficient.

[0095] The above design and simulation results show that the gain slope conversion circuit of the dB linear variable gain amplifier involved in this invention can realize that the gain changes in a positive or negative proportion with the gain control voltage, while ensuring that the gain range and input / output range remain unchanged, thus meeting the requirement of variable correlation between gain and control voltage in complex system design.

[0096] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A gain slope conversion circuit suitable for dB linear variable gain amplifiers, characterized in that, include: V MODE The signal input stage circuit has internal nodes O1 to O4, and the voltage of each node is denoted as V. O1 ~V O4 The V MODE The signal input stage circuit is used to convert the control signal V. MODE Level state switching V O1 ~V O4 The output state is used to determine the direction of the gain slope; where: When the conversion control signal V MODE When it is high, V O1 and V O2 It exhibits low impedance to the outside, V O3 and V O4 Output a high level; When the conversion control signal V MODE When it is low, V O3 and V O4 It exhibits low impedance to the outside, V O1 and V O2 Output a high level; V GPOS -V GNEG The signal input stage circuit is connected to the non-inverting input of the gain control voltage V. GPOS and the gain control voltage inverting terminal V GNEG It is also connected to V MODE Nodes O1~O4 of the signal input stage circuit; the V GPOS -V GNEG The signal input stage circuit is used to determine the signal input based on V. MODE The gain slope direction determined by the signal input stage circuit will affect the differential gain control voltage V. GPOS -V GNEG Converted to current signal I S1 and I S2 Output; Interpolation stage circuit, used to receive V GPOS -V GNEG The current signal I output by the signal input stage circuit S1 and I S2 Output current I SINK1 ~I SINK8 ; Transconductance gating stage circuit, used to select based on current I SINK1 ~I SINK8 The distribution of the transconductance stage is used to select the corresponding transconductance stage, thereby changing the gain value of the amplifier.

2. The gain slope conversion circuit for a dB linear variable gain amplifier according to claim 1, characterized in that, The V MODE The signal input stage circuit includes resistors R1~R15, NPN transistors Q1~Q3, PNP transistors Q4, NPN transistors Q5~Q7, PNP transistors Q8~Q11, NPN transistors Q12~Q15, and diodes D1~D3, wherein: One end of resistor R1 is connected to the reference voltage V. BIAS1 Its other end is connected to the collector of NPN transistor Q1, one end of resistor R2, and the bases of NPN transistors Q12~Q15; the base of NPN transistor Q1 is connected to the other end of resistor R2, and the emitter of NPN transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 is grounded; one end of resistor R4 is connected to the conversion control signal V. MODE The other end of resistor R4 is connected to the anode of diode D1 and the base of NPN transistors Q2-Q3; the cathode of diode D1 is connected to the base of NPN transistor Q5; the collector of NPN transistor Q5 is connected to one end of resistor R8, the anode of diode D2, and the base of NPN transistors Q6-Q7; the emitter of NPN transistor Q5 is grounded; the cathode of diode D2 is connected to the anode of diode D3; the cathode of diode D3 is grounded; the collectors of NPN transistors Q2-Q3 are connected to one end of resistor R7 and the base of PNP transistors Q8-Q9; the emitter of NPN transistor Q2 is connected to one end of resistor R5; the emitter of NPN transistor Q3 is connected to one end of resistor R6; the other end of resistor R5 is connected to one end of resistor R12 and the emitter of NPN transistor Q12; the other end of resistor R6 is connected to one end of resistor R13 and the emitter of NPN transistor Q12. The emitter of transistor Q13 is connected to the collector of NPN transistors Q6-Q7, which is connected to one end of resistor R9 and the base of PNP transistors Q10-Q11. The emitter of PNP transistor Q4 is connected to power supply VCC, and the base of PNP transistor Q4 is connected to the collector of NPN transistor Q4, the other end of resistor R7, the other end of resistor R8, the other end of resistor R9, and the emitters of PNP transistors Q8-Q11. The emitter of NPN transistor Q6 is connected to one end of resistor R10, and the emitter of NPN transistor Q7 is connected to one end of resistor R11. The other end of resistor R10 is connected to one end of resistor R14 and the emitter of NPN transistor Q14, and the other end of resistor R11 is connected to one end of resistor R15 and the emitter of NPN transistor Q15. The collector of PNP transistor Q8 is connected to the collector of NPN transistor Q12. This connection point is denoted as node O4, and its voltage is V. O4 The collector of PNP transistor Q9 is connected to the collector of NPN transistor Q13. This connection point is denoted as node O3, and its voltage is V. O3 The collector of PNP transistor Q10 is connected to the collector of NPN transistor Q14. This connection point is denoted as node O2, and its voltage is V. O2 The collector of PNP transistor Q11 is connected to the collector of NPN transistor Q15. This connection point is denoted as node O1, and its voltage is V. O1 The other end of resistors R12~R15 is grounded.

3. The gain slope conversion circuit for a dB linear variable gain amplifier according to claim 1, characterized in that, The V GPOS -V GNEG The signal input stage circuit includes PNP transistors Q16-Q17, NPN transistors Q18, PNP transistors Q19-Q20, NPN transistors Q21-Q25, PNP transistors Q26-Q27, resistors R16-R21, and current source I. total1 ~I total2 Subtractor, where: Gain control voltage non-inverting input V GPOS Connect the base of PNP transistor Q16, and the inverting input of the gain control voltage V. GNEG Connect the base of PNP transistor Q17; connect the emitter of PNP transistor Q16 to current source I. total1 The output terminal and the inverting terminal of the subtractor are connected, and the emitter of the PNP transistor Q17 is connected to the current source I. total1 The output terminal of the subtractor is connected to the non-inverting terminal of the subtractor, and the output signal V of the subtractor is... GPOS -V GNEG Connect one end of resistor R16 to the emitter of NPN transistor Q18, with reference voltage V. BIAS2 Connect the base of NPN transistor Q18, the base of NPN transistor Q21, and the base of NPN transistor Q23; connect the collector of NPN transistor Q18 to the collectors of PNP transistors Q19~Q20, and connect the base of PNP transistor Q19 to V. O4 The base of the PNP transistor Q20 is connected to V. O1 The emitter of NPN transistor Q21 is connected to one end of resistor R17, the emitter of NPN transistor Q22 is connected to one end of resistor R18, the emitter of NPN transistor Q23 is connected to one end of resistor R20, and the emitter of NPN transistor Q25 is connected to one end of resistor R21. The collector of NPN transistor Q21 is connected to the collector of NPN transistor Q22, the base of NPN transistor Q24, and current source I. total2 The output terminal; the collector of NPN transistor Q23 is connected to the base of NPN transistor Q22, the base of NPN transistor Q25, and one end of resistor R19. The other end of resistor R19 is connected to the emitter of NPN transistor Q24. The collector of NPN transistor Q25 is connected to the collectors of PNP transistors Q26~Q27. The base of PNP transistor Q26 is connected to V... O2 The base of PNP transistor Q27 is connected to V. O3 The emitters of PNP transistor Q19 and PNP transistor Q26 are connected, and this connection point serves as the first current output terminal, used to output current I. S1 The emitters of PNP transistor Q20 and PNP transistor Q27 are connected, and this connection point serves as the second current output terminal for outputting current I. S2 Power supply VCC connected to current source I total1 Input terminal, current source I total2 The input terminal, the collector of NPN transistor Q24, the collector of PNP transistor Q16, the collector of PNP transistor Q17, the other ends of resistors R16~R18, and the other ends of resistors R20~R21 are all grounded.

4. The gain slope conversion circuit for a dB linear variable gain amplifier according to claim 1, characterized in that, Let the collector current of NPN transistor Q18 be I. CQ18 The collector current of NPN transistor Q25 is I. CQ25 The following relationship exists: I CQ18 +I CQ25 =I S1 +I S2 = K·I total2 K is a coefficient.

5. The gain slope conversion circuit for a dB linear variable gain amplifier according to claim 1, characterized in that, The interpolation stage circuit includes PNP transistors Q28~Q36, NPN transistors Q37~Q44, resistors R22~R31, and current source I. total3 ,in: The emitter of PNP transistor Q28 is connected to one end of resistor R23; the emitter of PNP transistor Q29 is connected to one end of resistor R24; the emitter of PNP transistor Q30 is connected to one end of resistor R25; the emitter of PNP transistor Q31 is connected to one end of resistor R26; the emitter of PNP transistor Q32 is connected to one end of resistor R27; the emitter of PNP transistor Q33 is connected to one end of resistor R28; the emitter of PNP transistor Q34 is connected to one end of resistor R29; the emitter of PNP transistor Q35 is connected to one end of resistor R30; the emitter of PNP transistor Q36 is connected to one end of resistor R31; and the collector of PNP transistor Q28 is connected to the base of PNP transistors Q28~Q36 and one end of resistor R22. The collector of PNP transistor Q29 is connected to the base of NPN transistor Q37 and the current I. S1 Let this connection point be designated as the first intermediate point, with a voltage of V1; the collector of PNP transistor Q30 is connected to the base of NPN transistor Q38, and this connection point is designated as the second intermediate point, with a voltage of V2; the collector of PNP transistor Q31 is connected to the base of NPN transistor Q39, and this connection point is designated as the third intermediate point, with a voltage of V3; the collector of PNP transistor Q32 is connected to the base of NPN transistor Q40, and this connection point is designated as the fourth intermediate point, with a voltage of V4; PNP The collector of transistor Q33 is connected to the base of NPN transistor Q41. This connection point is designated as the fifth intermediate point, and its voltage is V5. The collector of PNP transistor Q34 is connected to the base of NPN transistor Q42. This connection point is designated as the sixth intermediate point, and its voltage is V6. The collector of PNP transistor Q35 is connected to the base of NPN transistor Q43. This connection point is designated as the seventh intermediate point, and its voltage is V7. The collector of PNP transistor Q36 is connected to the base of NPN transistor Q44 and the current I. S2 This connection point is designated as the eighth intermediate point, and its voltage is V8; current source I total3 The input terminal is connected to the other end of resistor R22 and the emitter of NPN transistors Q37~Q44. This connection point is designated as the midpoint, and its voltage is V0. The collectors of NPN transistors Q37~Q44 serve as current output terminals, sequentially outputting current I. SINK1 ~I SINK8 A resistor of the same value is connected between each of the following intermediate points: the first intermediate point and the second intermediate point, the second intermediate point and the third intermediate point, the third intermediate point and the fourth intermediate point, the fourth intermediate point and the fifth intermediate point, the fifth intermediate point and the sixth intermediate point, the sixth intermediate point and the seventh intermediate point, and the seventh intermediate point and the eighth intermediate point.

6. A gain slope conversion circuit for a dB linear variable gain amplifier according to claim 5, characterized in that, Resistors R25 to R30 have the same resistance value, and resistors R24 and R31 have the same resistance value.

7. A gain slope conversion circuit suitable for a dB linear variable gain amplifier according to claim 1, characterized in that, The transconductance gating stage circuit comprises eight units, each consisting of a resistor and a transistor; in the q-th unit, q = 1, 2, ..., 8, one end of the resistor is connected to a voltage V. REF The other end of the resistor is connected to the current I. SINKq The base of the transistor; the emitter of the transistor is connected to the current source I. total4 The output terminal of the transistor is the collector, which is used to output current I. q .

8. A gain slope conversion circuit suitable for a dB linear variable gain amplifier according to claim 7, characterized in that, The eight units of the transconductance gating stage circuit use resistors with the same resistance value.

9. A gain slope conversion circuit suitable for a dB linear variable gain amplifier according to claim 7, characterized in that, All eight transistors in the transconductance gating stage circuit are PNP transistors.

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