Multi-stage ping-pong serial multiplexing hardware implementation method for two-channel lattice filter bank

Abstract

The application discloses a multi-stage ping-pong serial multiplexing hardware implementation method of a two-channel lattice filter bank, which comprises the following steps: firstly, fixed-point quantization is performed on lattice coefficients, normalization coefficients and output compensation coefficients, and a relationship between positive-order coefficient taking at an analysis end and reverse-order coefficient taking at a synthesis end is established; secondly, state holding type hierarchical serial calculation is completed to obtain input data pairs, analysis result data pairs and synthesis result data pairs, ping-pong buffering and atomic reading and writing are respectively performed, and reading effective and writing permission states are generated; then, analysis calculation, synthesis calculation and phase recombination are scheduled to be executed in a staggered manner for different data pairs, and the states of the ping-pong buffers are updated; finally, the synthesis result data pairs are read according to the scheduling results, phase recombination is completed, and filter output is formed by using compensation quantization coefficients at the synthesis end. According to the application, analysis calculation, synthesis calculation and phase recombination are executed in a staggered manner for different data pairs, so that the occupation of hardware resources is reduced and the continuous sampling throughput capacity is improved.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and digital hardware implementation technology, specifically relating to a hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank. Background Technology

[0002] Dual-channel lattice filter banks are commonly used structures in multi-rate digital signal processing. They decompose the input signal into two sub-band signals through analysis, and then the synthesized filter bank reconstructs the signal. They are widely used in communication, audio processing, sub-band coding, and wavelet transform. Lattice filter structures are characterized by clear cascading relationships, high modularity, and suitability for fixed-point hardware implementation. Existing hardware implementations typically deploy the lattice stages in parallel at both the analysis and synthesis ends, configuring multipliers, addition / subtraction units, and registers for each stage. While this structure can achieve high data throughput, the problem of redundant resource allocation at each stage becomes more pronounced as the number of lattice stages increases. Simultaneous deployment at both the analysis and synthesis ends further increases the occupancy of multipliers, combinational logic, and registers, making implementation on resource-constrained platforms less feasible.

[0003] Using shared computing resources to process different lattice levels sequentially can reduce the resource overhead of parallel expansion structures, but several issues still need to be addressed when converting lattice filter banks to serial multiplexing structures. Lattice levels not only transmit current computation results but also historical states corresponding to inter-level delays. If historical states are not saved and retrieved separately for each lattice level during serial scheduling, current data may be combined with incorrect historical data, causing the serial computation results to lose their original lattice concatenation relationship. Ordinary serial structures typically process the same data pair sequentially in the order of analysis, synthesis, and phase reassembly. Waiting exists between different processing stages, resulting in a long processing cycle for a single data pair and limiting continuous sampling throughput. Furthermore, the two phase data obtained from synthesis need to be reassembled and scaled in the same order as the input two-phase decomposition. Under continuous sampling conditions, the lack of input enable, output valid, and overflow indication controls can lead to problems such as the previous data not being processed before the input data arrives, incorrect phase reconstruction order, or difficulty in determining stable input sampling intervals. Therefore, a hardware implementation method for a dual-channel lattice filter bank is needed that can take into account lattice-level serial multiplexing, preservation of historical states at each level, multi-stage data overlap processing, and phase recombination and continuous sampling control. Summary of the Invention

[0004] To address the issues of redundant multipliers, addition / subtraction units, and registers in dual-channel lattice analysis-synthesis filter banks employing multi-stage parallel expansion structures, and the difficulty in correctly maintaining the historical states of each lattice level, sequential waiting between different processing stages, and coordination difficulties between phase reassembly and continuous sampling processes when using ordinary serial multiplexing structures, this invention provides a hardware implementation method for dual-channel lattice filter banks based on multi-stage ping-pong serial processing. This method, based on hierarchical serial multiplexing of lattice computing resources, utilizes state maintenance at each level and multi-stage data pair ping-pong buffering to enable analysis calculations, synthesis calculations, and phase reassembly to be performed on overlapping data pairs, thereby reducing hardware resource consumption and improving continuous sampling throughput.

[0005] The method includes the following steps: Step 1: Perform fixed-point quantization on the lattice coefficients, normalized coefficients, and output compensation coefficients, and establish a relationship between the forward-order coefficient selection at the analysis end and the reverse-order coefficient selection at the synthesis end based on the level index. Assume the lattice filter bank has a total of... Level lattice unit, level lattice coefficient is The normalization coefficient at the analysis end is The integrated output compensation coefficient is The aforementioned Determined by the lattice coefficients at each level, it is used to normalize the input signal. The calculation formula is: To accommodate fixed-point hardware implementation, the number of decimal places for coefficient quantization is set to 1. Then the first The level-type coefficient, the analysis-side normalization coefficient, and the synthesis-side output compensation coefficient can be quantified as follows: in, This indicates the rounding operation. To normalize the quantization coefficients at the analysis end, The quantization coefficient is used to compensate for the overall result; the quantized grid coefficient is used for the result. Write the coefficients to the coefficient storage module in hierarchical order. On the analysis side, the level index control module determines the level index based on the level index. Read in ascending order At the integration end, the level index control module, according to... Read in reverse order .

[0006] In the original parallel expansion structure, each level of analytical lattice unit and each level of synthetic lattice unit has independent multiplication and addition / subtraction operation resources. This invention maps the independent analytical lattice units and synthetic lattice units in the parallel structure to shared analytical lattice computation modules and shared synthetic lattice computation modules. Each shared lattice computation module, during the processing of a data pair, according to... The lattice operations at each level are performed sequentially, thereby converting the spatially parallel multi-level computational relationship into a time-reused hierarchical computational relationship.

[0007] Step 2: Using the parameters obtained in Step 1, complete input normalization, two-phase decomposition, and state-preserving hierarchical serial calculations at the analysis and synthesis ends, sequentially obtaining input data pairs, analysis result data pairs, and synthesis result data pairs. Original input sequence After normalization at the analysis end, the input data pairs are obtained: In fixed-point hardware implementations, the above operations can be achieved through multiplication, rounding, and right shift: in, This indicates a fixed-point rounding shift operator. The two-phase decomposition module decomposes the normalized input sequence into two correlated phase data streams, resulting in input data pairs: For the i-th level lattice computation at the analysis end, define the fixed-point multiplication operator: The lattice operation relation of the i-th level of the analysis end is: in, and Indicates the analysis end Level output data, and Indicates the analysis end The input data for each level. Additionally, the analysis terminal status register is used to store the historical results of branches under each lattice level. Let the first... The status register of the analysis terminal is After the current level calculation is completed, the following can be written: The input to the next lattice level consists of the calculation results of the branches above the current level and the historical state of the corresponding level. Therefore, the same input data pair will not be incorrectly combined and run through all lattice levels within a single clock cycle, but will instead proceed level by level according to the delay relationships in the original lattice structure. After completing the calculation of level N-1, the analysis result data pair is obtained: in, , These are the outputs of the upper and lower branches of the analysis terminal, respectively.

[0008] The synthesis end uses the reverse order coefficient reading relationship corresponding to the analysis end. Let the current level of the synthesis end be... Its reading coefficient is: Comprehensive Terminal The calculation relationship for the tiered grid type is as follows: in, and Indicates the integrated end Level output data, and Indicates the integrated end Level input data. The synthesis terminal status register is used to store the historical results of the branches at each lattice level. Let the first level be... The status register of the synthesis stage is After the current level calculation is completed, the following can be written: The next integrated grid level is driven by both the corresponding historical state and the calculation results of the current level's lower branches. After completing the N-1 level integrated calculation, the integrated result data pair is obtained: These are the outputs of the upper and lower branches of the integrated terminal, respectively.

[0009] By employing state-preservation mechanisms at both the analysis and synthesis ends, the hierarchical serial multiplexing structure maintains the cascaded state relationship of the dual-channel lattice analysis-synthesis filter bank while reducing multi-level independent computing resources.

[0010] Step 3: Perform ping-pong caching and atomic read / write operations on the three types of associated data pairs formed in Step 2, and generate read-valid and write-allowed states through read pointers, write pointers, and occupancy counts. To reduce sequential waiting between analysis calculations, synthesis calculations, and phase reassembly in the hierarchical serial multiplexing structure, this invention sets up three-level data pair ping-pong caching units at the processing stage boundaries: input data pair ping-pong caching unit, analysis result data pair ping-pong caching unit, and synthesis result data pair ping-pong caching unit.

[0011] The three ping-pong cache units are used to cache the following associated data pairs: Each ping-pong buffer unit includes a first data pair storage location, a second data pair storage location, and a read pointer. Write pointer and occupancy count The two components of the data pair are written, read, and released as a whole to avoid... and , and ,as well as and They were split into different processing batches.

[0012] For any ping-pong buffer unit, the read validity condition is... and valid readout conditions They are respectively: in, This represents the logical AND operation. This indicates a read read read read signal, allowing the writing of new data pairs when the current cache count is less than two data pairs, or when a valid read operation exists within the current clock cycle. in, This indicates a logical OR operation, and the corresponding valid write operation. for: when When valid, both components of the data pair to be written are written simultaneously. Point to the storage location and flip it. ;when When valid, downstream modules read simultaneously. The two components of the data pair are pointed to and flipped. Only when a write operation occurs, Increment by 1; only when a read operation occurs. Decrement by 1; when write and read operations occur simultaneously within the same clock cycle, It remains unchanged.

[0013] when Effective When invalid, it indicates that both data pairs are occupied and the existing data pairs have not been released in the current cycle. In this case, the full load signal of the corresponding ping-pong cache unit is set. Through the aforementioned atomic data pair read / write and same-cycle read / write mechanisms, the two storage locations can be used alternately, providing data caching for pipeline overlap between different processing stages while maintaining the integrity of associated data pairs.

[0014] Step 4: Based on the cache status generated in Step 3 and the busy / idle status of each processing module, schedule the analysis calculation, synthesis calculation, and phase reorganization to be executed overlappingly for different data pairs, and update the status of each ping-pong cache according to the task completion status. The analysis task is started when there are valid data pairs in the input data pair ping-pong cache, the shared analysis lattice calculation module is idle, and there is a writable location in the analysis result data pair ping-pong cache. The combined startup conditions are as follows: Represented as: in, This indicates that the input data is not empty in the ping-pong buffer. This indicates that the shared analysis lattice calculation module is idle. This indicates that the analysis results data is writable in the PingPong cache.

[0015] The conditions for starting the synthesis task are: the analysis results data contains valid data pairs in the ping-pong cache, the shared comprehensive lattice calculation module is idle, and the synthesis results data has a writable location in the ping-pong cache. for: The phase reassembly task is initiated when there are valid data pairs in the ping-pong buffer and the phase reassembly module is in an acceptable state. for: in, and These indicate that the analysis result data in the ping-pong cache and the comprehensive result data in the ping-pong cache are not empty, respectively. and This indicates that the integrated lattice calculation module and the phase reassembly module are idle, respectively. This indicates that the overall result data is writable in the PingPong cache.

[0016] During steady-state processing, the shared analysis lattice calculation module can handle the first... The input data pairs are processed simultaneously by the shared comprehensive grid calculation module. The phase reconstruction module simultaneously processes the data pairs from the group analysis results. The combined results data pairs are used to achieve overlapping execution.

[0017] When the analysis results cache is temporarily full If the input becomes invalid, the analysis end will not read new input data pairs; when the synthesis result cache is temporarily full... If the data becomes invalid, the integrated terminal will not read new analysis result data pairs. This backpressure relationship prevents upstream data from being released prematurely when downstream is blocked, thus maintaining the order of data pairs and the correspondence between stages.

[0018] Step 5: Based on the scheduling results from Step 4, read the integrated result data pairs, perform phase reassembly according to the same phase convention as in Step 2, and use the integrated end compensation quantization coefficients obtained in Step 1 to form the final filtered output. Simultaneously, complete the effective, busy / idle, and overflow control under continuous sampling conditions. The phase reassembly module restores the integrated output data pairs into a single-channel sequence according to the phase convention consistent with the input two-phase decomposition. The output compensation module is based on the output compensation coefficient. Scale recovery of the reconstructed sequence: In the fixed-point implementation, the final filtered output can be expressed as: System Settings , , , and .in, Indicates the input sampling time; The writable state of the ping-pong buffer is determined by the input data; This indicates that there are pairs of data to be processed in the shared analysis lattice calculation module, the shared comprehensive lattice calculation module, the phase reassembly module, or any ping-pong buffer; This indicates that the final filtered output is valid.

[0019] When the input data to the ping-pong cache, the analysis result data to the ping-pong cache, or the comprehensive result data to the ping-pong cache cannot write new associated data pairs, or the phase reassembly module cannot receive comprehensive result data pairs, the overflow indicator is set. .

[0020] The present invention has the following beneficial effects: This invention maps multi-level parallel lattice computation into a serial multiplexed computation process through hierarchical indexing, coefficient storage, and a shared lattice computation module, reducing redundant configuration of multipliers and addition / subtraction logic.

[0021] This invention saves the historical state of each stage through the status register group of the analysis end and the synthesis end, so that the serial calculation results remain consistent with the original lattice cascade structure.

[0022] This invention improves the continuous sampling throughput of ordinary serial multiplexing structures by using a multi-stage ping-pong buffer for input, analysis results, and synthesis results, enabling analysis, synthesis, and phase reassembly to be performed on different data pairs overlappingly.

[0023] Through phase recombining, output compensation and Throughput control ensures the correct reconstructed output sequence and provides a basis for determining the stable input sampling interval of the serial multiplexing structure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the principle structure of a dual-channel lattice analysis-synthesis filter bank. Figure 2 A schematic diagram illustrating the mapping from parallel expansion to hierarchical serial multiplexing in multi-level lattice computing; Figure 3 This is a diagram of the overall hardware structure for multi-stage ping-pong serial multiplexing. Figure 4 A structural diagram of the ping-pong cache unit for associated data; Figure 5 Here is a flowchart illustrating the state-preserving hierarchical serial multiplexing structure and control process at the analysis end; Figure 6 The integrated terminal state-preserving hierarchical serial multiplexing structure and control flowchart are shown below. Figure 7 This is a schematic diagram of two-phase decomposition, phase recombination, and output compensation. Figure 8 This is a timing diagram for hierarchical serial multiplexing and multi-stage ping-pong collaborative scheduling. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. These embodiments are used to illustrate the technical solutions of the present invention and do not limit the scope of protection of the present invention.

[0026] The specific steps are as follows: Step 1: Perform fixed-point quantization on the grid coefficients, normalization coefficients, and output compensation coefficients, and establish the relationship between the forward order coefficients of the analysis end and the reverse order coefficients of the synthesis end based on the level index.

[0027] This embodiment employs a twelve-level dual-channel lattice analysis-synthesis filter bank. For example... Figure 1 As shown, the normalization coefficient is set at the input end to adjust the amplitude range of the input data before two-phase decomposition; the output compensation coefficient at the synthesis end is set after phase reassembly to restore the amplitude scale of the reconstructed data. Setting these two coefficients allows the internal lattice calculation to be performed within the specified data bit width and reduces the possibility of overflow in intermediate calculation results.

[0028] To adapt to fixed-point digital hardware implementation, before hardware configuration, the twelve lattice coefficients, normalization coefficients, and output compensation coefficients are proportionally amplified according to a preset number of decimal places, and the amplified values ​​are rounded to the nearest integer. The quantized coefficients are represented using 16-bit signed fixed-point numbers, with the sign remaining consistent with that before quantization. This processing method converts the original floating-point coefficients into integer constants that the multiplier can directly use, simplifying hardware multiplication and data bit width control while maintaining the required calculation accuracy. The decimal fixed-point values ​​corresponding to the twelve lattice coefficients are shown in Table 1, and the normalization coefficients and output compensation coefficients can be stored in their respective constant registers.

[0029] Table 1

[0030] like Figure 2 As shown, the twelve quantized lattice coefficients are written into the coefficient storage module in lattice-level order. When the analysis end begins processing an input data pair, it will use the level index. Set it to 0, and then read the coefficients in order from level 0 to level 11; when the integrated terminal starts processing the analysis result data pairs, it also starts from... Scheduling starts at 0, but coefficients are read in the order from level 11 to level 0. The analysis end uses forward order to retrieve coefficients in order to maintain the forward cascading relationship of the analysis lattice level; the synthesis end uses reverse order to correspond to the reverse cascading order of the synthesis lattice level, avoiding deviations in reconstruction results due to incorrect coefficient order.

[0031] With the above parameter configuration, each lattice level does not need to set independent coefficient connections and computational resources; instead, these are handled by... Select the coefficients required for the current lattice level at different processing times. The quantized lattice coefficients and normalized coefficients are used for input normalization and analysis in step 2, and for comprehensive serial lattice calculation. The output compensation coefficients are used for reconstruction amplitude recovery in step 5, thus providing a unified fixed-point parameter basis for subsequent steps.

[0032] Step 2: Using the parameters obtained in Step 1, complete the input normalization, two-phase decomposition, and state-preserving hierarchical serial calculations at the analysis and synthesis ends, and sequentially obtain the input data pairs, analysis result data pairs, and synthesis result data pairs, and send them to the ping-pong buffer unit corresponding to Step 3.

[0033] like Figure 3 and Figure 7 As shown, this embodiment first uses the normalized quantization coefficients from step 1. Its value is 2266. Fixed-point multiplication and bit-width adjustment are performed on the 16-bit input sample to obtain 28-bit internal data. The two-phase decomposition module saves the previous odd-phase sample according to a preset phase convention, and when the current even-phase sample arrives, it combines the two to form a data structure containing... and The input data pairs are fed into the ping-pong buffer of the input data pairs in step 3. Using a paired output method maintains the correspondence between the two phase data streams in subsequent processing.

[0034] like Figure 5 As shown, after the shared analysis lattice calculation module reads an input data pair, it will... Set to 0 and read the twelve-level lattice coefficients in ascending order. Before each level calculation, read the historical state of the corresponding analysis terminal's lower branch. After the first-level pipeline multiplication and addition / subtraction results are valid, write the new lower branch result back to the current level's status register and send the inter-level data to the next lattice level. After completing the 11th level calculation, obtain... and And send it as the analysis result data into the analysis result ping-pong cache.

[0035] like Figure 6 As shown, the shared integrated grid calculation module reads... and Afterwards, The values ​​are reset to 0, and the twelve-level lattice coefficients are read in reverse order. The synthesis end calculates level by level according to the addition and subtraction relationships corresponding to the analysis end, and uses the upper branch status register group to save the historical results of each level. After completing the twelve-level calculation, the following is obtained: and And it is used as the comprehensive result data and sent to the comprehensive result ping-pong cache.

[0036] The analysis and synthesis ends each have their own set of status registers to preserve the inter-level delay relationships in the original lattice structure and prevent current data from being combined with erroneous historical states. Therefore, the shared computing module only reuses multiplication and addition / subtraction operation resources, while the historical states of each lattice level are still saved separately, ensuring that the serial computation results remain consistent with the original lattice cascade structure.

[0037] Step 3: Perform ping-pong caching and atomic read / write on the three types of associated data pairs formed in Step 2, and generate read valid and write allowed states through read pointer, write pointer and occupancy count, for task scheduling in Step 4.

[0038] like Figure 3 and Figure 4 As shown, this embodiment sets up ping-pong caches for input data pairs, analysis result data pairs, and comprehensive result data pairs. The three types of caches are stored sequentially. and , and as well as and Each cache is set and Two storage locations, as shown in the diagram and This represents the addresses of the two components of a data pair. By using paired storage and overall read / write methods, misalignment of two phase data or sub-band data within the same data pair can be avoided during scheduling.

[0039] In this embodiment, each component is represented by a 28-bit signed number. Using two storage locations allows for the reception of one data pair while another awaits processing at the next stage, thus isolating speed differences between adjacent processing stages. Each ping-pong buffer has a read pointer, a write pointer, and an occupancy count. Upon reset, both pointers and the occupancy count are cleared to zero. When a write operation is valid and the buffer allows writing, both data components are simultaneously written to the location pointed to by the write pointer, after which the write pointer switches. When a read operation is valid and the next stage allows reading, both data components are simultaneously output, after which the read pointer switches. When only reading or only writing occurs, the occupancy count decreases or increases accordingly; when reading and writing occur simultaneously within the same clock cycle, the occupancy count remains unchanged.

[0040] A read-enabled state is generated when the cache is not empty, and a write-enabled state is generated when it is not full. Even if the cache is full but older data is read within the same clock cycle, new data can still be written to the recently released location. If the cache is full and cannot be released, and the previous level still requests writes, an overflow indication is generated. These cache states are used for task startup and backpressure control in step 4, allowing adjacent processing stages to overlap while maintaining data order and correspondence.

[0041] Step 4: Based on the cache status generated in Step 3 and the busy / idle status of each processing module, schedule the analysis calculation, comprehensive calculation, and phase reorganization to be executed for overlapping data pairs, and update the status of each ping-pong cache according to the task completion status. For example... Figure 3 As shown, the pipeline control module controls the startup of the shared analysis lattice calculation module, the shared comprehensive lattice calculation module, and the phase reassembly module. Before each processing task starts, it is necessary to simultaneously determine whether there is valid data in the previous-level ping-pong cache, whether the current processing module is idle, and whether the next-level ping-pong cache allows writing. Setting these startup conditions ensures that computing resources and result storage space are available before reading data, preventing the loss of processing results due to the next-level cache being full.

[0042] When valid input data exists in the ping-pong buffer, the analysis module is idle, and write access to the analysis result data is permitted in the ping-pong buffer, the control module reads an input data pair and starts the analysis calculation. After the analysis end completes the twelve-level serial lattice calculation, it will... and As a complete data pair, write the analysis result data pair to the ping-pong cache. The control module reads the data when the analysis result data pair is valid, the synthesis module is idle, and the synthesis result data pair ping-pong cache allows writing. and And start the integrated calculation; after the integrated calculation is completed, and The overall result data is written to the Ping Pong cache.

[0043] When the integrated result data contains valid data in the ping-pong cache and the phase reconstruction module is idle, the control module reads... and Then, the phase reorganization in step 5 is initiated. Each time a task starts, the corresponding storage location is released from the previous level cache; each time a task completes, the next level cache occupies a new storage location, and the read pointer, write pointer, and occupancy count described in step 3 are updated synchronously. When the next level cache cannot receive new data, the corresponding previous level task is paused, allowing the waiting state to be passed along each level cache to the input, preventing unprocessed data from being overwritten.

[0044] like Figure 8 As shown, after the system enters a stable working state, the analysis module processes the current input data pair, the synthesis module simultaneously processes the analysis results corresponding to the previous data pair, and the phase reconstruction module simultaneously processes the synthesis results corresponding to an earlier data pair. The three stages process different data objects and can overlap in execution; the analysis and synthesis ends are still internally handled by a shared lattice calculation module. The computation is completed step by step. Therefore, this scheduling method maintains the advantages of hierarchical serial multiplexing of resources while reducing sequential waiting between analysis, synthesis, and phase reassembly, thus improving continuous sampling throughput.

[0045] Step 5: Based on the scheduling results of Step 4, read the integrated result data pair, complete phase reassembly according to the phase convention consistent with Step 2, and use the integrated end compensation quantization coefficients obtained in Step 1 to form the final reconstructed output. Simultaneously, complete the effective, busy / idle, and overflow control under continuous sampling conditions. For example... Figure 7 As shown, when the integrated result data has valid data in the ping-pong buffer and the phase reassembly module is in an idle state, the scheduling control in step 4 reads the data. and Both phases are simultaneously latched into the phase reassembly module. This module has three operating states: idle, transmit u-phase, and transmit v-phase. It outputs the phase reassembly phase first at the enable time of two consecutive output sampling events. Then output By adopting the phase convention corresponding to the two-phase decomposition in step 2, phase reversal or output order misalignment of the two reconstructed data can be avoided.

[0046] The 28-bit data after phase reconstruction is sent to the output compensation module. This module calls the synthesis-end compensation quantization coefficients obtained in step 1, and restores the amplitude scale of the reconstructed data through fixed-point multiplication and bit width adjustment. When the compensation result exceeds the range of a 16-bit signed number, it is saturated and limited to keep the final output within the specified data range, avoiding sign flipping or large-amplitude distortion caused by direct truncation.

[0047] System Settings , , , and Signal. Used to indicate the input sampling and phase output times; The writable state of the input data pairs in the ping-pong buffer is determined to indicate whether the system can accept new samples; this is used when the analysis, synthesis, or phase reconstruction module is processing data, or when there are pending data pairs in any ping-pong buffer. Remain valid; when each compensated reconstructed sample is valid, Set the bit for one clock cycle, and the subsequent module reads the final output accordingly.

[0048] When any ping-pong buffer is full but a new data pair is still received, or when the phase reassembly module has not yet completed the output of the current data pair but a new synthesized result data pair is received, Position. By gradually shortening... Sampling interval and observation Whether it occurs can determine the minimum input sampling interval that the current hardware configuration can stably support.

[0049] To verify the above implementation method, synthesis and timing analysis were performed on a Cyclone IV EP4CE115F29C7 device. Quartus II 13.1 was used as the development tool, and the timing model used was Slow 1200mV 85℃. Parallel, ordinary serial, and three-stage ping-pong serial structures all employed a single-stage multiplier pipeline. The corresponding results are shown in Table 2.

[0050] Table 2

[0051] All structures were reconfigured under a 50MHz clock constraint without timing violations. Modelsim continuous sampling scan results demonstrate that the minimum time required for a typical serial structure to avoid overflow is [not specified]. The minimum time interval for a ping-pong serial structure to prevent overflow is 56 clock cycles. The interval is 13 clock cycles. This means that under the same operating clock conditions, the data throughput of the multi-stage ping-pong serial multiplexing structure is about 4.31 times higher than that of the ordinary serial structure, at the cost of a small increase in logic units and registers. However, it still maintains a significant advantage in multiplier and logic resources compared to the parallel structure.

Claims

1. A hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank, characterized in that, Includes the following steps: Step 1: Perform fixed-point quantization on the grid coefficients, normalization coefficients, and output compensation coefficients, and establish the relationship between the forward order coefficients of the analysis end and the reverse order coefficients of the synthesis end based on the level index; Step 2: Use the parameters obtained in Step 1 to complete the state-preserving hierarchical serial calculation, and obtain the input data pairs, analysis result data pairs, and comprehensive result data pairs in sequence; Step 3: Perform ping-pong caching and atomic read / write on the three types of data pairs formed in Step 2, and generate read-valid and write-allowed states through read pointers, write pointers, and occupancy counts; Step 4: Based on the cache status generated in Step 3, schedule analysis calculation, comprehensive calculation and phase reorganization to be performed on overlapping data pairs, and update the status of each ping-pong cache according to the task completion status; Step 5: Read the integrated result data pair according to the scheduling result of Step 4, complete the phase reorganization according to the phase agreement, and use the integrated end to compensate the quantization coefficient to form the final filter output.

2. The hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank according to claim 1, characterized in that, The specific implementation process of step 1 is as follows: Let the lattice filter bank have a total of Level lattice unit, level lattice coefficient is The normalization coefficient at the analysis end is The integrated output compensation coefficient is The Determined by the lattice coefficients at each level, it is used to normalize the input signal; Let the number of decimal places for the coefficient quantization be . Quantize them separately to obtain the first Classification coefficient Normalized coefficients at the analysis end and integrated output compensation coefficient Quantized lattice coefficients Write the coefficients to the coefficient storage module in hierarchical order. ; On the analysis side, the level index control module determines the level index based on the level index. Read in ascending order At the integration end, the level index control module, according to... Read in reverse order .

3. The hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank according to claim 2, characterized in that, The specific implementation process of step 2 is as follows: Original input sequence After normalization of the analysis end, the following is obtained In fixed-point hardware implementations, normalization operations are achieved through multiplication, rounding, and right shift: ,in, This indicates a fixed-point rounding shift operator; the two-phase decomposition module decomposes the normalized input sequence into two correlated phase data streams, resulting in input data pairs: For the i-th level lattice computation at the analysis end, define the fixed-point multiplication operator: The lattice operation relation of the i-th level of the analysis end is: in, and Indicates the current analysis terminal number Level output data, and Indicates the current analysis terminal number The input data for each level; the analysis terminal status register is used to store the historical results of each branch under each lattice level; let the first level be... The status register of the analysis terminal is Then, after the current level calculation is completed, write... ; The input for the next grid level consists of the calculation results of the branches above the current level and the historical state of the corresponding level; after completing the calculation of level N-1, the analysis result data is obtained. ,in, These are the outputs of the upper and lower branches of the analysis terminal, respectively. The synthesis end uses the reverse order coefficient reading relationship corresponding to the analysis end. Let the current level of the synthesis end be j, and its reading coefficient be... ; Comprehensive Terminal The calculation relationship for the tiered grid type is as follows: in, and Indicates the current integrated terminal number Level output data, and Indicates the current integrated terminal number The input data for level j is stored in the synthesis terminal status register, which is used to save the historical results of the branches at each lattice level. Let the status register of the j-th synthesis terminal be... Then, after the current level calculation is completed, write... ; The next integrated grid level is driven by the corresponding historical state and the calculation results of the current level's lower branches. After completing the N-1 level integrated calculation, the integrated result data pair is obtained. ,in These are the outputs of the upper and lower branches of the integrated terminal, respectively.

4. The hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank according to claim 3, characterized in that, The specific implementation process of step 3 is as follows: Three levels of data pair ping-pong caching units are set at the boundary of the processing stage: input data pair ping-pong caching unit, analysis result data pair ping-pong caching unit, and comprehensive result data pair ping-pong caching unit. The three ping-pong cache units are used to cache the following related data pairs: Each ping-pong buffer unit includes a first data pair storage location, a second data pair storage location, and a read pointer. Write pointer and occupancy count The two components of the data pair are written, read, and released as a whole. For any ping-pong buffer unit, the read validity condition is... for Valid readout conditions for ,in, This represents the logical AND operation. Ready signal for reading; ready to write. To allow new data pairs to be written when the current cache cell occupancy count is less than two data pairs, or when there is a valid read operation within the current clock cycle; the corresponding valid write... Operation is ; when When valid, both components of the data pair to be written are written simultaneously. Point to the storage location and flip it. ;when When valid, downstream modules read simultaneously. The two components of the data pair are pointed to and flipped. Only when a write operation occurs Increment by 1; only when a read operation occurs. Decrement by 1; when write and read operations occur simultaneously within the same clock cycle, Remain unchanged; when Effective When invalid, it indicates that both data pairs are occupied and the existing data pairs have not been released in the current cycle. In this case, the full load signal of the corresponding ping-pong cache unit is set. .

5. The hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank according to claim 4, characterized in that, The specific implementation process of step 4 is as follows: The analysis task is started when there are valid data pairs in the input data ping-pong cache, the shared analysis lattice calculation module is idle, and the analysis result data has a writable location in the ping-pong cache; combined startup conditions. Represented as: in, This indicates that the input data is not empty in the ping-pong buffer. This indicates that the shared analysis lattice calculation module is idle. This indicates that the analysis results data is writable in the Ping-Pong cache; The synthesis task is initiated when: there are valid data pairs in the ping-pong cache unit, the shared comprehensive lattice calculation module is idle, and the synthesis result data has a writable location in the ping-pong cache. for: The phase reassembly task is initiated when there are valid data pairs in the ping-pong buffer and the phase reassembly module is in an acceptable state. for: in, and These indicate that the analysis result data in the ping-pong cache and the comprehensive result cache in the ping-pong cache are not empty, respectively. and This indicates that the integrated lattice calculation module and the phase reassembly module are idle, respectively. This indicates that the composite result data is writable in the Ping-Pong cache; During steady-state processing, the shared analysis lattice calculation module processes the first... The input data pairs are processed simultaneously by the shared comprehensive grid calculation module. The phase reconstruction module simultaneously processes the data pairs from the group analysis results. The combined results data pairs are used to achieve overlapping execution.

6. The hardware implementation method for multi-stage ping-pong serial multiplexing of a dual-channel lattice filter bank according to claim 5, characterized in that, The specific implementation process of step 5 is as follows: The phase reconstruction module restores the synthesized result data pairs into a single-path sequence according to the phase convention consistent with the input two-phase decomposition: The output compensation module is based on the output compensation coefficient. Scale recovery of the reconstructed sequence: In the fixed-point implementation, the final filtered output is represented as: When the input data to the ping-pong buffer, the analysis result data to the ping-pong buffer, or the comprehensive result data to the ping-pong buffer cannot write new associated data pairs, or the phase reassembly module cannot receive comprehensive result data pairs, the overflow indicator signal is set. .

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