Triangular wave generating circuit and signal generator

Abstract

The application discloses a kind of triangular wave generating circuit and signal generator.Circuit includes: reference voltage generating circuit, oscillator circuit, frequency divider, comparison voltage signal generating circuit, charge pump circuit and integrator;Reference voltage generating circuit connects reference band gap generating circuit and oscillator circuit, oscillator circuit is also connected frequency divider and generates comparison voltage signal circuit, charge pump circuit connects frequency divider and integrator, generates comparison voltage signal circuit and connects oscillator circuit.The reference voltage generating circuit generates two input voltages, and the oscillator circuit compares the comparison voltage signal with them, outputs first latching signal, and the output of the comparison voltage signal generating circuit is sent to the oscillator circuit to generate second latching signal, and the frequency divider outputs the on-off signal with duty cycle of 50% to the charge pump circuit according to first latching signal or second latching signal, and the charge pump circuit generates two voltages with duty cycle of 50%, and the integrator outputs the triangular wave with duty cycle of 50%.

Description

Technical Field

[0001] This invention relates to the field of signal generation technology, and in particular to a triangular wave generating circuit and a signal generator. Background Technology

[0002] The comparator in the existing triangular wave generation circuit is in a completely ideal state, and the duty cycle of the output triangular wave will achieve an ideal 50%. In reality, the offset voltage of the comparator and the switching threshold of the logic device will affect the duty cycle. The duty cycle after passing through the RS latch in the triangular wave generation circuit will deviate from 50%, resulting in the actual output triangular wave duty cycle not being 50% and deviating from the common-mode voltage, which affects the operating point of the subsequent ADC circuit. Summary of the Invention

[0003] This invention proposes a triangular wave generating circuit and a signal generator, which aims to output a triangular wave signal with a duty cycle of 50% and without deviating from the common-mode voltage.

[0004] To achieve the above objectives, the triangular wave generation circuit proposed in this invention includes: a reference voltage generation circuit, an oscillator circuit, a frequency divider, a comparison voltage signal generation circuit, a charge pump circuit, and an integrator; The reference voltage generation circuit is connected to the reference bandgap generation circuit and the oscillator circuit. The oscillator circuit is also connected to the frequency divider and the comparison voltage signal generation circuit. The charge pump circuit is connected to the frequency divider and the integrator. The output of the comparison voltage signal generation circuit is connected to the oscillator circuit. The reference voltage generating circuit is used to generate a first input voltage and a second input voltage and output them to the oscillator circuit. The oscillator circuit is used to compare the first input voltage and the second input voltage with the voltage of the comparison voltage signal, respectively, and output a first latch signal to the frequency divider and the comparison voltage signal generation circuit according to the comparison result; The comparison voltage signal generation circuit is used to adjust the comparison voltage signal according to the first latch signal, and output the adjusted comparison voltage signal to the oscillator circuit, so that the oscillator circuit outputs the second latch signal; The frequency divider is used to divide the first latch signal or the second latch signal into an on / off signal with a duty cycle of 50%, and output the on / off signal to the charge pump circuit. The charge pump circuit is used to adjust the first voltage and the second voltage output to the integrator according to the received on / off signal; The integrator is used to generate and output a triangular wave based on the first voltage and the second voltage; The oscillator circuit includes: a first comparator, a second comparator, and an RS latch; The integrator includes: a second capacitor, a third capacitor, and a third amplifier; The comparison voltage signal generation circuit includes: a third switch, a fourth switch, and a first capacitor; One end of the third switch is connected to the positive terminal of the third current source, and the other end of the third switch is connected to the negative terminal of the fourth current source, one end of the first capacitor, the positive input terminal of the first comparator, and the negative input terminal of the second comparator. The control terminal of the third switch is connected to the output terminal of the RS latch. One end of the fourth switch is connected to the positive terminal of the fourth current source, and the other end of the fourth switch is grounded. The control terminal of the fourth switch is connected to the inverting output terminal of the RS latch. The other end of the first capacitor is connected to the common-mode voltage output terminal of the amplifier in the integrator, so as to maintain the linearity of the first capacitor consistent with that of the second and third capacitors.

[0005] In one embodiment, the frequency divider is a divide-by-two frequency divider; The input terminal of the frequency divider is connected to the output terminal of the oscillator circuit, the output terminal of the frequency divider is connected to the charge pump circuit, and the inverted output terminal of the frequency divider is connected to the charge pump circuit.

[0006] In one embodiment, the reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first resistor is connected to the power supply, the other end of the first resistor is connected to the second resistor and the oscillator circuit and one end of the second resistor, the other end of the second resistor is connected to the reference bandgap generating circuit and one end of the third resistor, the other end of the third resistor is connected to the fourth resistor and the oscillator circuit, and the other end of the fourth resistor is grounded.

[0007] In one embodiment, the oscillator circuit further includes: a first buffer and a second buffer; The positive input of the first comparator is connected to the comparison voltage signal generation circuit, the negative input of the first comparator is connected to the other end of the first resistor and one end of the second resistor, the output of the first comparator is connected to the input of the first buffer, the output of the first buffer is connected to the reset terminal of the RS latch, the negative input of the second comparator is connected to the comparison voltage signal generation circuit, the positive input of the second comparator is connected to the other end of the third resistor and one end of the fourth resistor, the output of the second comparator is connected to the input of the second buffer, the output of the second buffer is connected to the set terminal of the RS latch, and the output of the RS latch is connected to the frequency divider.

[0008] In one embodiment, the integrator further includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The positive input terminal of the third amplifier is connected to one end of the second capacitor, one end of the fifth resistor, and the first output terminal of the charge pump circuit. The negative input terminal of the third amplifier is connected to one end of the third capacitor, one end of the sixth resistor, and the second output terminal of the charge pump circuit. The negative output terminal of the third amplifier is connected to one end of the seventh resistor. The positive output terminal of the third amplifier is connected to one end of the eighth resistor. The other end of the seventh resistor is connected to the other end of the second capacitor, the other end of the fifth resistor, and the other end of the first capacitor. The other end of the eighth resistor is connected to the other end of the third capacitor and the other end of the sixth resistor.

[0009] In one embodiment, the charge pump circuit includes: a first current circuit and a second current circuit; The first current circuit connects the frequency divider and the integrator, and the second current circuit connects the frequency divider and the integrator. The first current circuit is used to adjust the duty cycle of the first voltage according to the on / off signal, and output the second voltage to the integrator; The second current circuit is used to adjust the duty cycle of the second voltage according to the on / off signal and output the second voltage to the integrator; wherein the current of the first current circuit is equal to the current of the second current circuit, and the output current of the comparison voltage signal generation circuit is twice the current of the first current circuit.

[0010] In one embodiment, the first current circuit includes: a first switch and a second switch; One end of the first switch is connected to the positive terminal of the first current source, and the other end of the first switch is connected to the negative terminal of the second current source and the first input terminal of the integrator. The control terminal of the first switch is connected to the output terminal of the frequency divider. One end of the second switch is connected to the positive terminal of the second current source, and the other end of the second switch is grounded. The control terminal of the second switch is connected to the inverted output terminal of the frequency divider.

[0011] In one embodiment, the second current circuit includes a fifth switch and a sixth switch; One end of the fifth switch is connected to the positive terminal of the fifth current source, and the other end of the fifth switch is connected to the negative terminal of the sixth current source and the second input terminal of the integrator. The control terminal of the fifth switch is connected to the inverting output terminal of the frequency divider. One end of the sixth switch is connected to the positive terminal of the sixth current source, and the other end of the sixth switch is grounded. The control terminal of the sixth switch is connected to the output terminal of the frequency divider.

[0012] The present invention also proposes a signal generator, which includes the triangular wave generating circuit described in any of the above embodiments.

[0013] This invention discloses a triangular wave generation circuit and a signal generator. The triangular wave generation circuit includes: a reference voltage generation circuit, an oscillator circuit, a frequency divider, a comparison voltage signal generation circuit, a charge pump circuit, and an integrator; the reference voltage generation circuit is connected to a reference bandgap generation circuit and the oscillator circuit, the oscillator circuit is also connected to the frequency divider and the comparison voltage signal generation circuit, the charge pump circuit is connected to the frequency divider and the integrator, and the output of the comparison voltage signal generation circuit is connected to the oscillator circuit; the reference voltage generation circuit is used to generate a first input voltage and a second input voltage and output them to the oscillator circuit; the oscillator circuit is used to compare the first input voltage and the second input voltage with the voltage of the comparison voltage signal, respectively, and according to the comparison... The comparison result outputs a first latch signal to the frequency divider and the comparison voltage signal generation circuit; the comparison voltage signal generation circuit is used to adjust the comparison voltage according to the first latch signal and output the adjusted comparison voltage signal to the oscillator circuit, so that the oscillator circuit outputs a second latch signal; the frequency divider is used to divide the first latch signal or the second latch signal into an on / off signal and output the on / off signal with a duty cycle of 50% to the charge pump circuit; the charge pump circuit is used to adjust the first voltage and the second voltage output to the integrator according to the received on / off signal; the integrator is used to generate and output a triangular wave according to the first voltage and the second voltage. The reference voltage generation circuit generates a first input voltage and a second input voltage. The oscillator circuit compares the comparison voltage signal with these voltages and outputs a first latch signal to the frequency divider and the comparison voltage signal generation circuit based on the comparison result. The comparison voltage signal generation circuit adjusts the comparison voltage signal according to the first latch signal to make the oscillator circuit output a second latch signal, so that the latch signal output by the oscillator circuit is a square wave signal with alternating first and second latch signals. The frequency divider outputs an on / off signal to the charge pump circuit according to the first or second latch signal. The charge pump circuit generates a first voltage and a second voltage with a duty cycle of 50%. The integrator outputs a triangular wave. The addition of the frequency divider avoids the problem of output deviation from common mode caused by inconsistent charging and discharging times of capacitors in the integrator. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 This is a circuit diagram of an embodiment of a triangular wave generating circuit in the prior art. Figure 2 This is an ideal waveform diagram of an embodiment of a triangular wave generating circuit in the prior art. Figure 3 This is a capacitor voltage curve of an embodiment of a triangular wave generating circuit in the prior art. Figure 4 This is a schematic diagram of an integrator input with a non-50% duty cycle, representing an embodiment of a triangular wave generation circuit in the prior art. Figure 5 The above is an actual waveform diagram of an embodiment of a triangular wave generating circuit in the prior art. Figure 6 A circuit diagram of an embodiment of the triangular wave generating circuit provided by the present invention; Figure 7 A circuit diagram of two embodiments of the triangular wave generating circuit provided by the present invention; Figure 8 Actual waveform diagrams of two embodiments of the triangular wave generating circuit provided by the present invention; Figure 9 The circuit diagram shows the charge pump circuit in three embodiments of the triangular wave generation circuit provided by the present invention.

[0016] Explanation of icon numbers:

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0020] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0021] Figure 1 This is a circuit diagram of an embodiment of a triangular wave generation circuit in the prior art. It consists of four parts: a reference voltage generation circuit, a charge pump circuit, an oscillator circuit, and an integrator. The reference voltage generation circuit outputs a first input voltage Vrp and a second input voltage Vrn to the oscillator circuit. The oscillator circuit outputs two inverted Q and QB signals to the charge pump circuit. The charge pump feeds back a comparison voltage signal vM to the oscillator circuit. Simultaneously, the charge pump outputs two signals, a first voltage vL and a second voltage vR, to the integrator as inputs. The integrator outputs a triangular wave vo.

[0022] The reference voltage generation circuit consists of Figure 1 As shown in (a), it consists of a reference bandgap generation circuit and a voltage divider resistor connected in series. The output voltage of the reference bandgap generation circuit generates two voltages, Vrp and Vrn, through a voltage divider resistor. The charge pump circuit is as follows: Figure 1 As shown in (b), the oscillator consists of three current branches and embedded switches s1-s6. The currents flowing through branches ① and ③ must be equal, meaning the currents flowing through current sources In1, In2, In5, and In6 must be equal. Similarly, the currents flowing through current sources In3 and In4 in branch ② must also be equal. The output of branch ① is the first voltage vL, the output of branch ② is the comparison voltage signal vM, and the output of branch ③ is the second voltage vR. The first capacitor C1 is connected to the comparison voltage signal vM output from branch ②. The oscillator circuit diagram is shown below. Figure 1As shown in (c), the oscillator outputs two inverted clock signals, Q and QB. These two clock signals control the switching of the charge pump circuit, as follows: Figure 1 As shown in (b), switches s1, s3, and s6 are controlled by clock signal Q, and switches s2, s4, and s5 are controlled by clock signal QB. The integrator circuit is as follows: Figure 1 As shown in (d), the positive input terminal of the amplifier is connected to the first output voltage vL of the charge pump branch ①, and the negative input terminal of the amplifier is also connected to the second output voltage vR of the charge pump branch ③. The differential output of the amplifier is a triangular wave vo.

[0023] It should be noted that the oscillator outputs a periodic square wave signal, the frequency of which is: Freq = I² / (2Vrp - 2Vrn) / C¹; Where I2 represents the current flowing through current sources In3 and In4 in branch ②. The waveforms of the main nodes are as follows: Figure 2 As shown.

[0024] The output amplitude of the triangular waveform is: ; Where I1 is the current flowing through branches ① and ③ in the charge pump circuit, I2 is the current flowing through branch ② in the charge pump, C1 is the first capacitor C1 connected to node vM, C2 is the feedback capacitor of the integrator, i.e., the second capacitor C2, and the capacitance of the third capacitor C3 is equal to the capacitance of the second capacitor C2. As can be seen from the formula, the amplitude of the triangular wave is related to the ratio of (Vrp-Vrn), the current, and the capacitance. The accuracy of this ratio does not change with variations in power supply voltage, temperature, and process angle. Therefore, the amplitude stability is strongly correlated with (Vrp-Vrn). Furthermore, since Vrp and Vrn voltages are derived from the reference bandgap voltage through a resistor series voltage divider, and the reference bandgap voltage and the resistor voltage divider ratio also do not change with variations in power supply voltage, temperature, and process angle, the output amplitude of the triangular wave in this structure will not change with variations in power supply voltage, temperature, and process angle. Figure 2 In the case where the duty cycle of the clock signal Q is 50%, the duty cycle of the triangular wave output by the integral is also 50%.

[0025] In practice, to achieve the ideal output amplitude, the ratio of the first capacitor C1 and the second capacitor C2 needs to be precisely controlled. As shown in the diagram, one end of the first capacitor C1 is connected to vM, and the other end is grounded. One end of the second capacitor C2 is connected to the single-ended output of the triangular wave, and the other end is connected to vL or vR. Since vL and vR are virtual ground and close to common-mode voltages, the voltages on the upper and lower plates of the first capacitor C1 and the second capacitor C2, as well as the voltages on the first capacitor C1 and the third capacitor C3, are inconsistent. Furthermore, to save space, NCAP capacitors are generally used, but NCAP capacitors have relatively poor linearity. Figure 3The capacitor C / V characteristic curve is shown. Under the same process angle conditions, due to the above reasons, the first capacitor C1 and the second capacitor C2 cause proportional errors under different voltage difference conditions, resulting in errors in the output amplitude; under different process angle conditions, the changes in the first capacitor C1 and the second capacitor C2 are also different under different voltage conditions, further causing proportional errors, and the output amplitude is also affected by the process angle, introducing a larger error.

[0026] Furthermore, for Figure 1 In the oscillator circuit in (c), if the first comparator T1 and the second comparator T2 are perfectly ideal, the duty cycle of the two inverted clock signals Q and QB at the oscillator output will achieve an ideal 50%. However, in reality, the offset voltage of the comparators and the toggling threshold of the logic devices will affect the duty cycle. The square wave duty cycle after the RS latch will deviate from 50%, leading to... Figure 1 The control times of the switch in the charge pump circuit shown in (b) are inconsistent; since the output amplitude (U), frequency (F), and capacitance (C) of the integrating capacitor are fixed, the current (I) flowing into the integrating capacitor at both ends is also constant, while the current exceeding or falling below 50% of the duty cycle will be accumulated or extracted from the drive current in the integrator. Figure 4 The section marked with the middle arrow. On one hand, the extra current loss weakens the integrator's driving capability for the subsequent ADC circuit; on the other hand, the excess accumulated or missing current will pull the common-mode voltage Vcm across the original differential output to a larger value (e.g., Figure 4 Vcmo+) and relatively small values ​​(such as Figure 4 The change in Vcmo- ultimately leads to the common-mode voltage Vcm, which was originally required to be zero for differential common-mode, becoming (Vcmo+) - (Vcmo-), thus affecting the operating point of the subsequent ADC circuit. Figure 5 The diagram shows the integrator under conditions other than a 50% duty cycle. When the duty cycle of the clock signal Q is 50%, the duty cycle of the triangular wave output by the integrator is also 50%. In this case, the common-mode voltage Vcm of the differential common-mode circuit becomes (Vcmo+) - (Vcmo-), which is not 0 as in the ideal case.

[0027] Please see Figure 6 The triangular wave generating circuit designed in this invention can solve the problem of unstable output amplitude, and at the same time can output a triangular wave signal with a duty cycle of 50% and without deviating from the common-mode voltage.

[0028] In one embodiment of the present invention, the triangular wave generating circuit includes: a reference voltage generating circuit 100, an oscillator circuit 200, a frequency divider 300, a comparison voltage signal generating circuit 400, a charge pump circuit 500, and an integrator 600; the reference voltage generating circuit 100 is connected to the reference bandgap generating circuit and the oscillator circuit 200, the oscillator circuit 200 is also connected to the frequency divider 300 and the comparison voltage signal generating circuit 400, the charge pump circuit 500 is connected to the frequency divider 300 and the integrator 600, and the output of the comparison voltage signal generating circuit 400 is connected to the oscillator circuit 200; the reference voltage generating circuit 100 is used to generate a first input voltage and a second input voltage and output them to the oscillator circuit 200; the oscillator circuit 200 is used to compare the first input voltage and the second input voltage with a comparison voltage generator 600, respectively. The voltage of the voltage signal is compared, and a first latch signal is output to the frequency divider 300 and the comparison voltage signal generation circuit 400 according to the comparison result. The comparison voltage signal generation circuit 400 is used to adjust the comparison voltage signal according to the first latch signal and output the adjusted comparison voltage signal to the oscillator circuit 200, so that the oscillator circuit 200 outputs a second latch signal. The frequency divider 300 is used to divide the first latch signal or the second latch signal into a duty cycle on / off signal with a 50% duty cycle and output the on / off signal to the charge pump circuit 500. The charge pump circuit 500 is used to adjust the first voltage and the second voltage output to the integrator 600 according to the received on / off signal. The integrator 600 is used to generate and output a triangular wave according to the first voltage and the second voltage.

[0029] It should be noted that the reference bandgap generation circuit adds a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient in a certain ratio to obtain a reference voltage that hardly changes with temperature. The purpose of using the reference bandgap generation circuit to generate voltage is to obtain a first input voltage and a second input voltage that do not change with temperature.

[0030] Understandably, the reference voltage generation circuit 100 generates a first input voltage and a second input voltage. The oscillator circuit 200 compares the voltage of the comparison voltage signal with the first and second input voltages. Based on the comparison result, it outputs a first latch signal to the comparison voltage signal generation circuit 400 and the frequency divider 300. The comparison voltage signal generation circuit 400 receives the first latch signal, adjusts the comparison voltage signal, and outputs the adjusted comparison voltage signal to the oscillator circuit 200. The comparison result between the comparison voltage signal and the first and second input voltages changes, causing the oscillator circuit to... The oscillator circuit 200 outputs a second latch signal. The frequency divider 300 outputs an on / off signal with a duty cycle of 50% based on either the first or second latch signal to the charge pump circuit 500. The oscillator circuit 200 outputs a square wave signal that alternates between the first and second latch signals. Therefore, the frequency divider 300 also outputs a square wave signal with a precise duty cycle of 50%. The charge pump circuit 500 generates a first voltage and a second voltage with a duty cycle of 50%. The integrator 600 outputs a triangular wave with a duty cycle of 50%, thus avoiding the problem of output deviation from common mode caused by inconsistent charging and discharging times of the capacitors in the integrator 600.

[0031] In this embodiment, the reference voltage generation circuit 100 generates a first input voltage and a second input voltage. The oscillator circuit 200 compares the voltage of the comparison voltage signal with these two voltages and outputs a first latch signal to the frequency divider 300 and the comparison voltage signal generation circuit 400 based on the comparison result. The comparison voltage signal generation circuit 400 adjusts the comparison voltage signal according to the first latch signal so that the oscillator circuit 200 outputs a second latch signal. The latch signal output by the oscillator circuit 200 is a square wave signal that alternates between the first latch signal and the second latch signal. The frequency divider 300 outputs an on / off signal with a duty cycle of 50% to the charge pump circuit 500 based on the first latch signal or the second latch signal. The charge pump circuit 500 generates a first voltage and a second voltage with a duty cycle of 50%. The integrator 600 outputs a triangular wave. The addition of a relatively accurate 50% duty cycle from the frequency divider 300 avoids the problem of output deviation from common mode caused by inconsistent charging and discharging times of the capacitors in the integrator 600.

[0032] like Figure 7 The diagram shown is a circuit schematic of the second embodiment of the triangular wave generation circuit proposed in this embodiment.

[0033] Based on the first embodiment described above, a second embodiment of the triangular wave generating circuit of the present invention is proposed.

[0034] The frequency divider 300 is a two-way frequency divider; the input terminal of the two-way frequency divider is connected to the output terminal of the oscillator circuit 200, the output terminal of the two-way frequency divider is connected to the charge pump circuit 500, and the inverting output terminal of the two-way frequency divider is connected to the charge pump circuit 500. Figure 7 In this circuit, the input terminal of the frequency divider is connected to the output terminal of the RS latch in the oscillator circuit 200, the output terminal of the frequency divider is connected to the comparison voltage signal generation circuit 400, the first current circuit and the second current circuit, and the inverted output terminal of the frequency divider is connected to the comparison voltage signal generation circuit 400, the first current circuit and the second current circuit.

[0035] It should be noted that a frequency divider is used to halve the frequency of an input signal. If a square wave with a period of T is input to the frequency divider, the frequency divider will output a square wave with a period of 2T and a duty cycle of 50%, regardless of the duty cycle of the input signal's square wave. The frequency divider receives the square wave signal RSo1 output from the RS latch and also outputs square wave signals Q and QB, where Q and QB are a pair of inverse square wave signals. When Q is high, QB is low, and when Q is low, QB is high. The on / off signals include Q and QB, where Q is an alternating cyclic square wave with a period of 2T, and QB is a square wave with a period of 2T that is the opposite of Q.

[0036] Furthermore, in this embodiment, the reference voltage generation circuit 100 includes: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the first resistor R1 is connected to the power supply VCC, the other end of the first resistor R1 is connected to the second resistor R2 and the oscillator circuit 200 and one end of the second resistor, the other end of the second resistor R2 is connected to the reference bandgap generation circuit and one end of the third resistor R3, the other end of the third resistor R3 is connected to the fourth resistor R4 and the oscillator circuit 200, and the other end of the fourth resistor R4 is grounded.

[0037] It is understandable that the reference voltage generation circuit 100 adjusts the output first input voltage vrp and second input voltage vrn by setting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, wherein the first input voltage vrp is greater than the second input voltage vrn.

[0038] In this embodiment, the oscillator circuit 200 includes: a first comparator T1, a second comparator T2, a first buffer D1, a second buffer D2, and an RS latch; the positive input terminal of the first comparator T1 is connected to the comparison voltage signal generation circuit 400, the negative input terminal of the first comparator T1 is connected to the other end of the first resistor R1 and one end of the second resistor R2, the output terminal of the first comparator T1 is connected to the input terminal of the first buffer D1, the output terminal of the first buffer D1 is connected to the reset terminal of the RS latch, the negative input terminal of the second comparator T2 is connected to the comparison voltage signal generation circuit 400, the positive input terminal of the second comparator T2 is connected to the other end of the third resistor R3 and one end of the fourth resistor R4, the output terminal of the second comparator T2 is connected to the input terminal of the second buffer D2, the output terminal of the second buffer D2 is connected to the set terminal of the RS latch, and the output terminal of the RS latch is connected to the frequency divider 300.

[0039] It is understood that the oscillator circuit 200 consists of a first comparator T1, a second comparator T2, and an RS latch. The positive input terminal of the first comparator T1 and the negative input terminal of the second comparator T2 are connected to the same comparison voltage signal vM, which is the output of the comparison voltage signal generation circuit 400. The negative input terminal of the first comparator T1 is connected to the output Vrp of the first current circuit, and the positive input terminal of the comparator T2 is connected to the output Vrn of the second current circuit. The output terminals of the RS latch are RSo1 and RSo2. The first latch signal is RSo1 at a high level and RSo2 at a low level, and the second latch signal is RSo1 at a low level and RSo2 at a high level. Therefore, the output of the oscillator circuit 200 is two inverted square wave signals RSo1 and RSo2 that alternate between the first latch signal and the second latch signal.

[0040] It should be noted that a comparator has two input terminals, a positive input "+" and a negative input "-", and one output terminal. The input terminals receive analog signals, and the output terminal outputs a digital signal (high or low level). The two input signals are compared; when the positive input voltage is higher than the negative input voltage, the comparator's output becomes high; when the positive input voltage is lower than the negative input voltage, the output becomes low (usually grounded). A buffer is an electronic circuit used for temporary data storage. It can buffer data streams from one circuit to another to better coordinate data exchange between the two circuits. It can buffer input signals and output them to downstream circuits only after the buffer is full. This can eliminate data loss or corruption caused by uneven data transmission rates in downstream circuits. It allows circuits with different speeds to work in coordination, improving the overall performance of the system.

[0041] Specifically, an RS latch is a bistable circuit with two stable states, capable of storing one bit of binary data. When the input S is high, through logical operations, the output RSo1 becomes high and the output RSo2 becomes low; when the input R is high, through logical operations, the output RSo1 becomes low and the output RSo2 becomes high; when both inputs S and R are low, the RS latch maintains its current state.

[0042] The comparison voltage signal generation circuit 400 includes: a third switch s3, a fourth switch s4, and a first capacitor C1; one end of the third switch s3 is connected to the positive terminal of the third current source In3, and the other end of the third switch s3 is connected to the negative terminal of the fourth current source In4, one end of the first capacitor C1, the positive input terminal of the first comparator T1, and the negative input terminal of the second comparator T2; the control terminal of the third switch s3 is connected to the output terminal Q of the RS latch; one end of the fourth switch s4 is connected to the positive terminal of the fourth current source In4, and the other end of the fourth switch s4 is grounded; the control terminal of the fourth switch s4 is connected to the inverting output terminal QB of the RS latch; and the other end of the first capacitor C1 is connected to the common-mode voltage output terminal Vcm of the internal amplifier of the integrator 600.

[0043] It should be noted that, for Figure 1 In the charge pump schematic (b), the output connected to branch ② is the first capacitor C1 on vM, in order to... Figure 1 In the (d) integrator circuit, capacitor matching is required. The grounding potential of the first capacitor C1 should be modified to be connected to the common mode, i.e., the differential output common mode potential Vcm. This is consistent with the voltage environment of the second capacitor C2 and the third capacitor C3, where one end is connected to a virtual short and close to the common mode Vcm (vL, vR), and the other end is connected to a triangular wave (Von, Vop). This maintains the linearity consistency between the first capacitor C1 and the second and third capacitors C3, avoiding output amplitude deviation caused by capacitor nonlinearity. Figure 7 The voltage signal generation circuit 400 is shown in the figure. According to the formula... Where I1 is the current value of the first current circuit and I2 is the output current of the comparison voltage signal generation circuit 400. I1 and I2, the first capacitor C1 and the second capacitor C2 can achieve good matching, that is, the ratio is always a fixed value, thus ensuring the stability of the triangular wave output amplitude Ampl.

[0044] It is understandable that the output current of the current source does not change with the load, the internal resistance of the current source is relatively large compared with the load impedance, the load impedance fluctuation will not change the current magnitude, and the current flowing through the current sources In1, In2, In5 and In6 must be equal.

[0045] Specifically, the reference voltage generation circuit 100 generates two voltages, a first input voltage Vrp and a second input voltage Vrn, and transmits them to the oscillator. If the initial voltage of the comparison voltage signal vM is 0, the output R of the first comparator T1 is 0, and the output voltage S of the second comparator T2 is 1. Then the RS latch outputs the first latch signal, with RSo1 being 1 and RSo2 being 0. Therefore, the third switch s3 in the comparison voltage signal generation circuit 400 is turned on, the fourth switch s4 is turned off, and the voltage vM keeps increasing. When vM > Vrn, the output R of the first comparator T1 is still 0, and the output S of the second comparator T2 becomes 0. Due to the effect of the RS latch, RSo1 and RSo2 maintain the previous state, that is, RSo1 is 1 and RSo2 is 0, so the voltage value of vM continues to increase. When vM > Vrp, the output R of the first comparator T1 becomes 1, while the output S of the second comparator T2 is 0. At this time, the RS latch outputs the second latch signal, RSo1 becomes 0, and RSo2 becomes 1. At this moment, the third switch s3 is turned off, and the fourth switch s4 is turned on, so the node voltage vM starts to drop. When vM < Vrp, the output R of the first comparator T1 becomes 0, and the output of the second comparator T2 becomes 0. Due to the effect of the latch, RSo1 and RSo2 maintain the previous state under this condition, that is, RSo1 is 0 and RSo2 is 1, so the voltage of vM continues to drop until vM < Vrn. At this time, the output R of the first comparator T1 is 0, and the output S of the second comparator T2 is 1. As a result, RSo1 becomes 1 and RSo2 becomes 0, the third switch s3 is turned off, the fourth switch s4 is turned on, and the vM voltage starts to rise again, and the cycle repeats. The waveforms of vM and RSo1 are shown in Figure 8 , the offset voltage of the comparator and the switching threshold of the logic device will both affect the duty cycle, and the duty cycle of the square wave passing through the RS latch will deviate from 50%, resulting in Figure 8 that the duty cycle of RSo1 as shown is not 50%.

[0046] In this embodiment, the other end of the first capacitor C1 is connected to the differential output common-mode potential Vcm, which is consistent with the voltage environment where one ends of the second capacitor C2 and the third capacitor C3 are connected to vL and vR close to the common-mode voltage Vcm, and the other ends are connected to the triangular waves Von and Vop, so that the linearity of the first capacitor C1 is consistent with that of the second capacitor C2 and the third capacitor C3; the output amplitude deviation caused by capacitor non-linearity is avoided, and both the first capacitor C1 and the second capacitor C2 can achieve good matching, that is, the ratio is always a fixed value, thus ensuring the stability of the triangular wave output amplitude Ampl. The output amplitude of the triangular wave is strongly related to the capacitor matching ratio. The present application solves the problem of unstable triangular wave output amplitude caused by capacitor mismatch through the optimization of capacitor matching.

[0047] The integrator 600 includes: a second capacitor C2, a third capacitor C3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a third amplifier T3; the positive input terminal of the third amplifier T3 is connected to one end of the second capacitor C2, one end of the fifth resistor R5, and the other end of the first switch S1 in the charge pump circuit 500; the negative input terminal of the third amplifier T3 is connected to one end of the third capacitor C3, one end of the sixth resistor R6, and the other end of the fifth switch S5 in the charge pump circuit 500; the negative output terminal of the third amplifier T3 is connected to one end of the seventh resistor R7; the positive output terminal of the third amplifier T3 is connected to one end of the eighth resistor R8; the other end of the seventh resistor R7 is connected to the other end of the second capacitor C2 and the other end of the fifth resistor R5; and the other end of the eighth resistor R8 is connected to the other end of the third capacitor C3 and the other end of the sixth resistor R6.

[0048] Specifically, the integrator 600 consists of an amplifier, capacitors, and resistors. The second capacitor C2 and the third capacitor C3 have equal capacitance values. The upper plate of the second capacitor C2 is connected to the positive input terminal of the amplifier, and the lower plate is connected to the negative output terminal. The upper plate of the third capacitor C3 is connected to the negative input terminal of the amplifier, and the lower plate is connected to the positive output terminal. When a voltage is suddenly applied to the circuit, the capacitors begin to charge gradually, and the voltage across the capacitors gradually increases from 0 until it equals the voltage applied across the circuit.

[0049] It should be noted that Vcm is the common-mode voltage, Vcm=0. Since the integrator 600 shapes the square wave into a triangular wave, the output waveform Vo of the integrator 600 is a triangular wave signal. Since vL and vR are periodic signals with a 50% duty cycle, Vo is also a periodic signal with a 50% duty cycle. Doubling the output current in the comparison voltage signal generation circuit 400 halves the period of the comparison voltage signal, causing the period of the latch signal to also be halved. Then, the frequency divider 300 restores the period of the on / off signal to its original value, keeping the periodic frequency of the output triangular wave constant.

[0050] It is understandable that when Q is 1, QB is 0, vL is 1, vR is 0, when vL is 1, vL charges Von, Von increases, and when vR is 0, Vop charges vR, Vop decreases; when Q is 0, QB is 1, vL is 0, vR is 1, when vL is 0, Von charges vL, Von decreases, and when vR is 1, vR charges Vop, Vop increases, and this cycle continues. The waveform is shown in Figure 8, and the output triangular wave is Vo = Vop - Von.

[0051] like Figure 7As shown, the charge pump circuit 500 in this embodiment includes: a first current circuit 501 and a second current circuit 502; the first current circuit 501 is connected to the frequency divider 300 and the integrator 600, and the second current circuit 502 is connected to the frequency divider 300 and the integrator 600; the first current circuit 501 is used to adjust a first voltage according to the on / off signal and output a second voltage to the integrator 600; the second current circuit 502 is used to adjust a second voltage according to the on / off signal and output a second voltage to the integrator 600; wherein, the current of the first current circuit is equal to the current of the second current circuit, and the output current of the comparison voltage signal generation circuit 400 is twice the current of the first current circuit.

[0052] It should be noted that, in the case of Figure 1 (c) input to Figure 1 In process (d), the duty cycle of the square wave output by the original charge pump circuit will deviate from 50%. To solve this problem, the current values ​​of In3 and In4 (comparison voltage signal generation circuit 400) can be doubled first, and then... Figure 1 Adding a frequency divider 300 to the output of (c) divides the frequency by two, and the final output amplitude will not change. The advantage of doing this is that the frequency divider 300 controls the square wave signal controlling the charge pump to a 50% duty cycle, thus avoiding common-mode deviation in the output.

[0053] The first current circuit 501 includes: a first switch s1 and a second switch s2; one end of the first switch s1 is connected to the positive terminal of the first current source In1, the other end of the first switch s1 is connected to the negative terminal of the second current source In2 and the integrator 600, the control terminal of the first switch s1 is connected to the output terminal Q of the frequency divider, one end of the second switch s2 is connected to the positive terminal of the second current source In2, the other end of the second switch s2 is grounded, and the control terminal of the second switch s2 is connected to the inverted output terminal QB of the frequency divider.

[0054] The second current circuit 502 includes a fifth switch s5 and a sixth switch s6; one end of the fifth switch s5 is connected to the positive terminal of the fifth current source In5, the other end of the fifth switch s5 is connected to the negative terminal of the sixth current source In6 and the integrator 600, the control terminal of the fifth switch s5 is connected to the inverted output terminal QB of the frequency divider, one end of the sixth switch s6 is connected to the positive terminal of the sixth current source In6, the other end of the sixth switch s6 is grounded, and the control terminal of the sixth switch s6 is connected to the output terminal Q of the frequency divider.

[0055] It is understandable that, such as Figure 8As shown, RSo1 generates periodic signals Q and QB through frequency divider 300 to control switches s1, s2, s5, and s6 of the first and second current circuits. The first switch s1, which controls the charging of node vL, is controlled by Q; the second switch s2, which controls the discharging of node vL, is controlled by QB; the fifth switch s5, which controls the charging of node vR, is controlled by QB; and the sixth switch s6, which controls the discharging of node vR, is controlled by Q. Since Q and QB are out of phase, either node vL is charging and node vR is discharging, or node vL is discharging and node vR is charging. Because the on / off signals are square waves with a duty cycle of 50%, vL and vR are also square waves with a duty cycle of 50%.

[0056] Further in this embodiment, such as Figure 9 As shown, the charge pump circuit 500 includes: a seventh switch s7, an eighth switch s8, a ninth switch s9, and a tenth switch s10; the positive terminal of the seventh current source In7 is connected to one end of the seventh switch s7 and one end of the ninth switch s9, the other end of the seventh switch s7 is connected to the integrator 600 and one end of the eighth switch s8, the other end of the ninth switch s9 is connected to the integrator 600 and one end of the tenth switch s10, and the other ends of the eighth switch s8 and the tenth switch s10 are connected to the negative terminal of the eighth current source In8.

[0057] Understandably, replacing four current sources with two current sources saves on electronic components, and the input voltages of the integrator 600, the first voltage vL and the second voltage vR, can also be multiplexed using a single current source.

[0058] In this embodiment, the current values ​​of In3 and In4 can be doubled. A frequency divider 300 is added to the output of the RS latch to divide the frequency by two. The amplitude of the final output triangular wave remains unchanged. The frequency divider 300 controls the square wave signal controlling the charge pump to a 50% duty cycle, avoiding common-mode deviation in the output. This invention implements a triangular wave generation circuit, which can solve the instability of the output triangular wave amplitude and better meet the 50% accuracy requirement of the ADC input waveform common-mode voltage and duty cycle, improving the accuracy of the ADC input and providing strong support for high-performance operation.

[0059] The present invention also proposes a signal generator, which includes a triangular wave generating circuit. The specific structure of the triangular wave generating circuit is as described in the above embodiments. Since the signal generator adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0060] The above description is merely an exemplary embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural transformations made based on the technical concept of the present invention and the contents of the specification and drawings of the present invention, or direct / indirect applications in other related technical fields, are included within the protection scope of the present invention.

Claims

1. A triangular wave generating circuit, characterized in that, include: Reference voltage generation circuit, oscillator circuit, frequency divider, comparison voltage signal generation circuit, charge pump circuit, and integrator; The reference voltage generation circuit is connected to the reference bandgap generation circuit and the oscillator circuit. The oscillator circuit is also connected to the frequency divider and the comparison voltage signal generation circuit. The charge pump circuit is connected to the frequency divider and the integrator. The output of the comparison voltage signal generation circuit is connected to the oscillator circuit. The reference voltage generating circuit is used to generate a first input voltage and a second input voltage and output them to the oscillator circuit. The oscillator circuit is used to compare the first input voltage and the second input voltage with the voltage of the comparison voltage signal, respectively, and output a first latch signal to the frequency divider and the comparison voltage signal generation circuit according to the comparison result; The comparison voltage signal generation circuit is used to adjust the comparison voltage signal according to the first latch signal, and output the adjusted comparison voltage signal to the oscillator circuit, so that the oscillator circuit outputs the second latch signal; The frequency divider is used to divide the first latch signal or the second latch signal into an on / off signal with a duty cycle of 50%, and output the on / off signal to the charge pump circuit. The charge pump circuit is used to adjust the first voltage and the second voltage output to the integrator according to the received on / off signal; The integrator is used to generate and output a triangular wave based on the first voltage and the second voltage; The oscillator circuit includes: a first comparator, a second comparator, and an RS latch; The integrator includes: a second capacitor, a third capacitor, and a third amplifier; The comparison voltage signal generation circuit includes: a third switch, a fourth switch, and a first capacitor; One end of the third switch is connected to the positive terminal of the third current source, and the other end of the third switch is connected to the negative terminal of the fourth current source, one end of the first capacitor, the positive input terminal of the first comparator, and the negative input terminal of the second comparator. The control terminal of the third switch is connected to the output terminal of the RS latch. One end of the fourth switch is connected to the positive terminal of the fourth current source, and the other end of the fourth switch is grounded. The control terminal of the fourth switch is connected to the inverting output terminal of the RS latch. The other end of the first capacitor is connected to the common-mode voltage output terminal of the amplifier in the integrator, so as to maintain the linearity of the first capacitor consistent with that of the second and third capacitors.

2. The triangular wave generating circuit as described in claim 1, characterized in that, The frequency divider is a two-division frequency divider; The input terminal of the frequency divider is connected to the output terminal of the oscillator circuit, the output terminal of the frequency divider is connected to the charge pump circuit, and the inverted output terminal of the frequency divider is connected to the charge pump circuit.

3. The triangular wave generating circuit as described in claim 1, characterized in that, The reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first resistor is connected to the power supply, the other end of the first resistor is connected to the second resistor and the oscillator circuit and one end of the second resistor, the other end of the second resistor is connected to the reference bandgap generating circuit and one end of the third resistor, the other end of the third resistor is connected to the fourth resistor and the oscillator circuit, and the other end of the fourth resistor is grounded.

4. The triangular wave generating circuit as described in claim 3, characterized in that, The oscillator circuit further includes: a first buffer and a second buffer; The positive input of the first comparator is connected to the comparison voltage signal generation circuit, the negative input of the first comparator is connected to the other end of the first resistor and one end of the second resistor, the output of the first comparator is connected to the input of the first buffer, the output of the first buffer is connected to the reset terminal of the RS latch, the negative input of the second comparator is connected to the comparison voltage signal generation circuit, the positive input of the second comparator is connected to the other end of the third resistor and one end of the fourth resistor, the output of the second comparator is connected to the input of the second buffer, the output of the second buffer is connected to the set terminal of the RS latch, and the output of the RS latch is connected to the frequency divider.

5. The triangular wave generating circuit as described in claim 4, characterized in that, The integrator also includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The positive input terminal of the third amplifier is connected to one end of the second capacitor, one end of the fifth resistor, and the first output terminal of the charge pump circuit. The negative input terminal of the third amplifier is connected to one end of the third capacitor, one end of the sixth resistor, and the second output terminal of the charge pump circuit. The negative output terminal of the third amplifier is connected to one end of the seventh resistor. The positive output terminal of the third amplifier is connected to one end of the eighth resistor. The other end of the seventh resistor is connected to the other end of the second capacitor, the other end of the fifth resistor, and the other end of the first capacitor. The other end of the eighth resistor is connected to the other end of the third capacitor and the other end of the sixth resistor.

6. The triangular wave generating circuit as described in claim 1, characterized in that, The charge pump circuit includes: a first current circuit and a second current circuit; The first current circuit connects the frequency divider and the integrator, and the second current circuit connects the frequency divider and the integrator. The first current circuit is used to adjust the duty cycle of the first voltage according to the on / off signal, and output the second voltage to the integrator; The second current circuit is used to adjust the duty cycle of the second voltage according to the on / off signal and output the second voltage to the integrator; wherein the current of the first current circuit is equal to the current of the second current circuit, and the output current of the comparison voltage signal generation circuit is twice the current of the first current circuit.

7. The triangular wave generating circuit as described in claim 6, characterized in that, The first current circuit includes: a first switch and a second switch; One end of the first switch is connected to the positive terminal of the first current source, and the other end of the first switch is connected to the negative terminal of the second current source and the first input terminal of the integrator. The control terminal of the first switch is connected to the output terminal of the frequency divider. One end of the second switch is connected to the positive terminal of the second current source, and the other end of the second switch is grounded. The control terminal of the second switch is connected to the inverted output terminal of the frequency divider.

8. The triangular wave generating circuit as described in claim 6, characterized in that, The second current circuit includes: a fifth switch and a sixth switch; One end of the fifth switch is connected to the positive terminal of the fifth current source, and the other end of the fifth switch is connected to the negative terminal of the sixth current source and the second input terminal of the integrator. The control terminal of the fifth switch is connected to the inverting output terminal of the frequency divider. One end of the sixth switch is connected to the positive terminal of the sixth current source, and the other end of the sixth switch is grounded. The control terminal of the sixth switch is connected to the output terminal of the frequency divider.

9. A signal generator, characterized in that, The signal generator includes a triangular wave generating circuit as described in any one of claims 1 to 8.

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