A signal delay circuit

Abstract

The application discloses a signal delay circuit, comprising a signal receiving end, an adjustable time delay circuit and a plurality of fixed time delay circuits; the plurality of fixed time delay circuits are connected in series in a cascade mode, wherein the input end of the fixed time delay circuit of the first stage is connected to the signal receiving end, the output end of the fixed time delay circuit of the last stage is connected to the input end of the adjustable time delay circuit, and the output end of the adjustable time delay circuit is connected to a load. The application can perform discrete coarse delay adjustment processing on a first radio frequency signal to obtain a second radio frequency signal through the combination of the plurality of fixed time delay circuits, and then perform continuous fine delay adjustment processing on the second radio frequency signal through the adjustable time delay circuit to obtain a target radio frequency signal.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a signal delay circuit. Background Technology

[0002] In phased array radar and broadband wireless communication systems, in order to control multiple array elements in the antenna array to transmit beams in a specific direction to achieve beam scanning, it is necessary to adjust the transmission time of each array element (i.e., radio frequency signal).

[0003] In existing technologies, multiple delay units are typically added to the array elements to adjust the transmission time of each array element's beam. However, since existing delay units are usually fixed-delay delay units, multiple fixed-delay delay units can only achieve discrete time delay control with a fixed time. Existing time delay methods are difficult to meet some more precise time delay control requirements. Summary of the Invention

[0004] In view of the above problems, this application provides a signal delay circuit to achieve more accurate radio frequency signal delay transmission. The specific solution is as follows:

[0005] This application provides a signal delay circuit, comprising: a signal receiving end, an adjustable delay circuit, and multiple fixed delay circuits;

[0006] Multiple fixed-delay circuits are connected in series in a cascaded manner, wherein the input terminal of the first-stage fixed-delay circuit is connected to the signal receiving terminal, the output terminal of the last-stage fixed-delay circuit is connected to the input terminal of the adjustable-delay circuit, and the output terminal of the adjustable-delay circuit is connected to the load.

[0007] The signal receiving end is used to receive the first radio frequency signal;

[0008] At least a portion of the fixed delay circuits constitute the current fixed delay circuit corresponding to the first radio frequency signal. The current fixed delay circuit is used to perform a first delay transmission processing on the first radio frequency signal to obtain a second radio frequency signal, and to send the second radio frequency signal to the adjustable delay circuit. The first delay duration is the sum of the fixed delay durations of each fixed delay circuit included in the current fixed delay circuit.

[0009] The adjustable delay circuit is used to perform a second delay transmission process on the second radio frequency signal to obtain a target radio frequency signal, and to send the target radio frequency signal to the load; the second delay duration is any delay duration within the continuously adjustable delay duration range corresponding to the adjustable delay circuit itself.

[0010] In one possible implementation, the adjustable delay circuit includes: an adjustable inductor, a first adjustable capacitor, and a second adjustable capacitor;

[0011] One end of the first adjustable capacitor and one end of the adjustable inductor are connected to the output of the last stage of the fixed delay circuit. The other end of the first adjustable capacitor is connected to the first power supply terminal. The other end of the adjustable inductor and one end of the second adjustable capacitor are connected to the load. The other end of the second adjustable capacitor is connected to the second power supply terminal.

[0012] The delay transmission time of the adjustable delay circuit is adjusted by the supply voltage of the first power supply terminal and the second power supply terminal.

[0013] In one possible implementation, the plurality of fixed delay circuits include at least one of: a small step size fixed delay circuit, a medium step size fixed delay circuit, and a large step size fixed delay circuit;

[0014] The delay propagation time of the small step size fixed delay circuit is smaller than that of the medium step size fixed delay circuit and the large step size fixed delay circuit.

[0015] The delay propagation time of the medium-step fixed delay circuit is smaller than that of the large-step fixed delay circuit.

[0016] In one possible implementation, any one of the fixed delay circuits—the small-step fixed delay circuit, the medium-step fixed delay circuit, and the large-step fixed delay circuit—comprising: a delay branch, a reference branch, an input switch, and an output switch.

[0017] The input terminal of the input switch is connected to the output terminal of the previous stage fixed delay circuit. The first output terminal of the input switch is connected to the input terminal of the delay branch. The second output terminal of the input switch is connected to the input terminal of the reference branch. The output terminal of the delay branch is connected to the first input terminal of the output switch. The output terminal of the reference branch is connected to the second input terminal of the output switch. The output terminal of the output switch is connected to the input terminal of the next stage fixed delay circuit.

[0018] In one possible implementation, the reference branch of the small-step fixed-delay circuit includes: a first unit, a first resistor;

[0019] One end of the first resistor of the first unit is connected to the second output terminal of the input switch and the second input terminal of the output switch, and the other end of the first resistor of the first unit is grounded.

[0020] In one possible implementation, the reference branch of the medium-step fixed delay circuit includes: a first resistor of the second unit, a second resistor of the second unit, and a third resistor of the second unit;

[0021] One end of the first resistor of the second unit and one end of the second resistor of the second unit are connected to the second output terminal of the input switch. The other end of the first resistor of the second unit and one end of the third resistor of the second unit are connected to the second input terminal of the output switch. The other ends of the second resistor of the second unit and the other ends of the third resistor of the second unit are grounded.

[0022] In one possible implementation, the reference branch of the large step size fixed delay circuit includes: a first inductor of the third unit, a second inductor of the third unit, a first resistor of the third unit, and a first capacitor of the third unit;

[0023] One end of the first inductor of the third unit is connected to the second output terminal of the input switch, the other end of the first inductor of the third unit is connected to one end of the second inductor of the third unit and one end of the first resistor of the third unit, the other end of the second inductor of the third unit is connected to the second input terminal of the output switch, the other end of the first resistor of the third unit is connected to one end of the first capacitor of the third unit, and the other end of the first capacitor of the third unit is grounded.

[0024] In one possible implementation, it also includes: at least one positive slope high-pass circuit;

[0025] The positive slope high-pass circuit is connected in series at the front or rear end of the large step fixed delay circuit;

[0026] The positive slope high-pass circuit is used to perform gain compensation on the first radio frequency signal transmitted with a large step delay, and send the first radio frequency signal after gain compensation to the next stage fixed delay circuit or adjustable delay circuit.

[0027] In one possible implementation, the positive slope high-pass circuit includes: a first resistor in the fourth unit, a second resistor in the fourth unit, a third resistor in the fourth unit, a first capacitor in the fourth unit, a second capacitor in the fourth unit, a third capacitor in the fourth unit, and a first inductor in the fourth unit.

[0028] One end of the first resistor of the fourth unit and one end of the first capacitor of the fourth unit are connected to the output terminal of the fixed delay circuit of the previous stage. The other end of the first resistor of the fourth unit, the other end of the first capacitor of the fourth unit, one end of the second resistor of the fourth unit and one end of the second capacitor of the fourth unit are connected to one end of the third resistor of the fourth unit. The other end of the second resistor of the fourth unit and the other end of the second capacitor of the fourth unit are connected to the input terminal of the fixed delay circuit of the next stage. The other end of the third resistor of the fourth unit is connected to one end of the third capacitor of the fourth unit and one end of the first inductor of the fourth unit. The other end of the third capacitor of the fourth unit and the other end of the first inductor of the fourth unit are grounded.

[0029] In one possible implementation, it also includes: at least one positive slope amplifier circuit;

[0030] The positive slope amplifier circuit is connected in series at the front or rear end of the large step fixed delay circuit;

[0031] The positive slope amplifier circuit is used to amplify the power of the first radio frequency signal, perform high-frequency attenuation compensation on the radio frequency signal transmitted through the large step delay, and send the first radio frequency signal after high-frequency attenuation compensation to the next stage of the fixed delay circuit or the adjustable delay circuit.

[0032] In one possible implementation, the positive slope amplifier circuit includes: a fifth unit first inductor, a fifth unit second inductor, a fifth unit third inductor, a fifth unit first capacitor, a fifth unit second capacitor, a fifth unit first amplifier transistor, and a fifth unit second amplifier transistor;

[0033] One end of the first inductor of the fifth unit, the gate of the first amplifier of the fifth unit, and the third power supply terminal are all connected to the output terminal of the fixed delay circuit of the previous stage. The source of the first amplifier of the fifth unit is connected to one end of the second inductor of the fifth unit, and the other end of the second inductor of the fifth unit is grounded. The other end of the first inductor of the fifth unit is connected to one end of the first capacitor of the fifth unit. The other end of the first capacitor of the fifth unit, the drain of the second amplifier of the fifth unit, and one end of the third inductor of the fifth unit are all connected to one end of the second capacitor of the fifth unit. The source of the second amplifier of the fifth unit is connected to the drain of the first amplifier of the fifth unit. The gate of the second amplifier of the fifth unit is connected to the fourth power supply terminal. The other end of the third inductor of the fifth unit is connected to the fifth power supply terminal. The other end of the second capacitor of the fifth unit is connected to the input terminal of the fixed delay circuit of the next stage.

[0034] By means of the above technical solution, this application provides a signal delay circuit, which includes: multiple fixed delay circuits and adjustable delay circuits. Each fixed delay circuit corresponds to a fixed delay transmission duration (e.g., a small-step fixed delay time of 8 ps, and other fixed delay circuits can be fixed delay circuits with delay times of 16 ps, 32 ps, or 64 ps). Therefore, the delay transmission time of the multiple fixed delay circuits is a discrete delay transmission time. A portion of the multiple fixed delay circuits constitute a first radio frequency signal. The current fixed delay circuit can obtain a delay transmission time close to the target delay transmission time in the discrete delay transmission time group. (For example, if the target delay transmission time is 103ps and the delay transmission times of each fixed delay circuit include 10ps, 20ps, 40ps, 80ps, etc., then by using a 20ps fixed delay circuit and an 80ps fixed delay circuit for delay, and turning off the 20ps fixed delay circuit and the 40ps fixed delay circuit, the current fixed delay circuit with a delay transmission time of 100ps can be obtained.)

[0035] The first RF signal is delayed for a first duration by the current fixed delay circuit to obtain a second RF signal with a delay time close to that required for the target signal. Then, since the delay time of the adjustable delay circuit is continuously adjustable (e.g., a continuous delay range of 3ps-11ps based on requirements), the first RF signal is further delayed by the adjustable delay circuit (e.g., by setting an additional 3ps delay) to obtain the target RF signal. The target RF signal has a delay time of 103ps compared to another RF signal without delay.

[0036] By using the coarse delay transmission processing of multiple fixed delay circuits and the fine delay transmission processing of adjustable delay circuits, the delay transmission of radio frequency signals can be precisely and continuously adjusted to meet different delay transmission requirements of radio frequency signals. Attached Figure Description

[0037] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0038] Figure 1 A block diagram of a signal delay circuit provided in this application;

[0039] Figure 2 A circuit diagram of an adjustable delay circuit for a signal delay circuit provided in this application;

[0040] Figure 3 A circuit diagram of a signal delay circuit provided in this application;

[0041] Figure 4 A circuit diagram of a single-pole double-throw switch for a signal delay circuit provided in this application;

[0042] Figure 5 A circuit diagram of a double-pole double-throw switch for a signal delay circuit provided in this application;

[0043] Figure 6 A circuit diagram of a small-step fixed-delay circuit for a signal delay circuit provided in this application;

[0044] Figure 7 A circuit diagram of a medium-step fixed-delay circuit for a signal delay circuit provided in this application;

[0045] Figure 8 A circuit diagram of a large-step fixed-delay circuit for a signal delay circuit provided in this application;

[0046] Figure 9 A schematic diagram illustrating the parasitic amplitude modulation compensation effect of a signal delay circuit provided in this application;

[0047] Figure 10 A circuit diagram of a positive slope high-pass circuit for a signal delay circuit provided in this application;

[0048] Figure 11 A schematic diagram illustrating the gain flatness effect of a signal delay circuit provided in this application;

[0049] Figure 12 A circuit diagram of a positive slope amplifier circuit for a signal delay circuit provided in this application;

[0050] Figure 13 This is a schematic diagram illustrating another gain flatness effect of a signal delay circuit provided in this application. Detailed Implementation

[0051] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0052] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0053] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0054] In existing technologies, multiple delay units are typically added to the array elements to adjust the transmission beam timing of each element. However, since existing delay units are usually fixed-delay units, they can only achieve discrete time delay control with fixed time. Existing delay methods are insufficient for more precise and continuous time delay control requirements. Furthermore, the insertion loss of the delay path and reference path in existing fixed-delay circuits is difficult to perfectly match. When the signal switches between different delay states (i.e., when switching between the delay path and the reference path), amplitude fluctuations occur, leading to parasitic amplitude modulation. Additionally, passive components (inductors and capacitors) are typically placed in the delay path, and due to the inherent frequency-selective loss of these passive components, the insertion loss varies significantly between different delay states, resulting in poor gain flatness of the RF signal across the entire operating frequency band. Therefore, this application provides a signal delay circuit.

[0055] See Figure 1 In this embodiment of the application, the signal delay circuit includes: a signal receiving end, an adjustable delay circuit, and multiple fixed delay circuits;

[0056] Multiple fixed delay circuits are connected in series in a cascaded manner. The input terminal of the first-stage fixed delay circuit is connected to the signal receiving terminal, and the output terminal of the last-stage fixed delay circuit is connected to the input terminal of the adjustable delay circuit. The output terminal of the adjustable delay circuit is connected to the load.

[0057] The signal receiving end is used to receive the first radio frequency signal;

[0058] At least a portion of the fixed delay circuits in the plurality of fixed delay circuits constitute the current fixed delay circuit corresponding to the first radio frequency signal. The current fixed delay circuit is used to perform a first delay transmission processing on the first radio frequency signal to obtain a second radio frequency signal, and to send the second radio frequency signal to the adjustable delay circuit. The first delay duration is the sum of the fixed delay durations corresponding to each fixed delay circuit included in the current fixed delay circuit.

[0059] To achieve efficient and non-redundant fixed-delay circuit combinations to meet different delay time requirements, multiple fixed-delay circuits can be configured such that their delay times are binary relative to each other. That is, the multiple fixed-delay circuits include one fixed-delay circuit with a small-step fixed delay time, and the delay times of the other fixed-delay circuits are 2N times the small-step fixed delay time, where N is a positive integer greater than 1.

[0060] Specifically, the signal delay transmission time of any one of the multiple fixed-delay circuits is fixed (e.g., the delay time of the first fixed-delay circuit is 8ps, the delay time of the second fixed-delay circuit is 16ps, the delay time of the fifth fixed-delay circuit is 32ps, etc.). The delay time of the first fixed-delay circuit is the delay time of the smallest unit, 8ps. The delay times of other fixed-delay circuits can be set to 2N times the delay time of the smallest unit, such as 16ps, 32ps, etc. That is, the delay time of each fixed-delay circuit adopts a binary setting of the minimum delay time X*2N. This binary fixed-delay circuit setting can achieve the combination of fixed-delay circuits with the maximum delay step size using the minimum number of fixed-delay circuits (i.e., based on the required fixed delay time, multiple fixed-delay circuits with binary settings can be combined to obtain the current fixed-delay circuit that meets the delay requirements and has no redundancy).

[0061] Multiple fixed-delay circuits can be combined to achieve current fixed-delay circuits with different delay times (such as a current fixed-delay circuit with an overall delay time of 8ps + 32ps = 40ps, or a current fixed-delay circuit with an overall delay time of 8ps + 16ps = 24ps). If the target delay transmission time of the target radio frequency signal is 28.5ps, the second radio frequency signal can be obtained by forming a current fixed-delay circuit corresponding to the first radio frequency signal by combining some of the fixed-delay circuits among the multiple fixed-delay circuits (such as forming a 24ps current fixed-delay circuit by combining the first fixed-delay circuit and the second fixed-delay circuit) and performing a delay transmission process with a first delay time of 24ps.

[0062] The adjustable delay circuit is used to perform delay transmission processing on the second radio frequency signal for a second delay duration to obtain the target radio frequency signal, and then send the target radio frequency signal to the load; the second delay duration is any delay duration within the continuously adjustable delay duration range corresponding to the adjustable delay circuit itself.

[0063] Specifically, the delay transmission time of the adjustable delay circuit is continuously adjustable. For example, the delay transmission time of the adjustable delay circuit can be selected in the range of 3ps-11ps. The adjustable delay circuit performs a second delay transmission process on the second radio frequency signal (the radio frequency signal that has been delayed by 24ps) for a second delay duration (e.g., 28.5ps-24ps=4.5ps) to obtain the target radio frequency signal. The target radio frequency signal has a delay transmission duration of 28.5ps compared with another radio frequency signal that has not undergone delay transmission.

[0064] With the signal delay circuit set above, the radio frequency signal can be discretely delayed by the current fixed delay circuit composed of multiple fixed delay circuits to obtain a first radio frequency signal that approximates the delay transmission time of the target radio frequency signal. Then, the first radio frequency signal can be continuously delayed by the adjustable delay circuit to obtain the target radio frequency signal. This adjustment method can accurately and continuously control the delay transmission of the radio frequency signal to meet different delay transmission requirements of the radio frequency signal.

[0065] See Figure 2 In some embodiments of this application, the adjustable delay circuit of the signal delay circuit includes: an adjustable inductor L1, a first adjustable capacitor C1, and a second adjustable capacitor C2.

[0066] One end of the first adjustable capacitor C1 and one end of the adjustable inductor L1 are connected together to the output of the last stage of the fixed delay circuit. The other end of the first adjustable capacitor C1 is connected to the first power supply terminal V1. The other end of the adjustable inductor L1 and one end of the second adjustable capacitor C2 are connected together to the load. The other end of the second adjustable capacitor C2 is connected to the second power supply terminal V2.

[0067] The delay propagation time of the adjustable delay circuit is adjusted by the supply voltage of the first power supply terminal V1 and the second power supply terminal V2.

[0068] In addition, to further improve the stability of the adjustable delay circuit, see [link to relevant documentation]. Figure 2 Furthermore, a first resistor R1, a second resistor R2, a third capacitor C3, and a fourth capacitor C4 can also be set;

[0069] Specifically, the aforementioned adjustable inductor can be an adjustable inductor with a ground loop switch. Different switching states of the ground loop switch correspond to different inductance values ​​of the adjustable inductor. Specifically, the inductance value of the adjustable inductor is adjusted by controlling the switching state of the ground loop switch with voltage. For example, when the switching control terminal of the ground loop switch is high, the ground loop switch is closed, and the ground loop is connected to ground. This is equivalent to a decrease in the distance between the adjustable inductor and ground, and the inductance value of the adjustable inductor is the smaller inductance value in the first inductance state. When the switching control terminal of the ground loop switch is low, the ground loop switch is open, and the ground loop is floating. This is equivalent to an increase in the distance between the adjustable inductor and ground, and the inductance value of the adjustable inductor is the larger inductance value in the second inductance state.

[0070] The first and second adjustable capacitors mentioned above can be AMOS voltage-controlled variable capacitors (i.e., accumulation-type MOS variable capacitors). The capacitance values ​​of the first and second adjustable capacitors change continuously with the voltage applied to one end of them (e.g., a certain type of variable capacitor can achieve a capacitance change of 35f-142f based on the voltage change).

[0071] Since the delay propagation time of radio frequency signals is related to the capacitance and inductance values ​​of the adjustable delay circuit, the delay propagation time of radio frequency signals can be adjusted by controlling the inductance value of the adjustable inductor and the capacitance value of the adjustable capacitor. For example, when the ground loop switch of the adjustable inductor with the ground loop switch is closed, the adjustable inductor is in the first inductance state with a small inductance value. At this time, the capacitance of the adjustable capacitor can be continuously adjusted by voltage (specifically, the capacitance values ​​of the first and second adjustable capacitors can be adjusted by the first and second power supply terminals respectively), so that the adjustable delay circuit can adjust the delay propagation time by a small value (such as achieving controllable delay adjustment in the delay range of 3ps-8ps).

[0072] When the ground loop switch controlling the adjustable inductor is turned off, the adjustable inductor is in the second inductor state with a large inductance value. At this time, the capacitance of the adjustable capacitor can be continuously adjusted by voltage (specifically, the capacitance values ​​of the first and second adjustable capacitors can be adjusted by the first and second power supply terminals respectively), which allows the adjustable delay circuit to adjust the delay transmission time by a larger value (such as achieving controllable delay adjustment in the delay range of 7ps-11ps).

[0073] The adjustable delay circuit described above allows for two different ranges of continuous delay transmission time adjustment methods by controlling the switching state of the adjustable inductor's ground loop switch and the capacitance changes of the first and second adjustable capacitors. Based on the delay transmission requirements of the radio frequency signal, the corresponding adjustment method can be selected to achieve more precise and continuous delay transmission processing of the radio frequency signal, flexibly meeting the delay transmission needs of different radio frequency signals.

[0074] In some embodiments of this application, the multiple fixed delay circuits include at least one of: a small step size fixed delay circuit, a medium step size fixed delay circuit, and a large step size fixed delay circuit;

[0075] Among them, the delay propagation time of the small step size fixed delay circuit is smaller than that of the medium step size fixed delay circuit and the large step size fixed delay circuit.

[0076] The delay propagation time of a medium-step fixed delay circuit is smaller than that of a large-step fixed delay circuit.

[0077] Setting up multiple fixed delay circuits with different delay steps allows for more flexible delay transmission processing of RF signals with a first delay duration, ensuring that the first delay duration is as close as possible to the delay duration required by the target RF signal.

[0078] See Figure 3 Specifically, in some embodiments of this application, any one of the fixed delay circuits of small step size, medium step size, and large step size includes: a delay branch (the branches corresponding to 8ps, 64ps, 16ps, 32ps, and 128ps in the figure), a reference branch (the branches symmetrically arranged for each delay branch in the figure), an input switch, and an output switch.

[0079] The input terminal of the input switch is connected to the output terminal of the previous stage fixed delay circuit. The first output terminal of the input switch is connected to the input terminal of the delay branch. The second output terminal of the input switch is connected to the input terminal of the reference branch. The output terminal of the delay branch is connected to the first input terminal of the output switch. The output terminal of the reference branch is connected to the second input terminal of the output switch. The output terminal of the output switch is connected to the input terminal of the next stage fixed delay circuit.

[0080] The delay branch can be composed of at least one second-order all-pass network (as shown in the figure for the 8ps delay branch). The second-order all-pass network consists of two series inductors and one parallel capacitor. The number of second-order all-pass networks in each delay branch affects the delay propagation time of the delay branch. The more second-order all-pass networks are connected in series in the delay branch, the longer the delay propagation time of the delay branch. Different fixed delay circuits can be set with different numbers of second-order all-pass networks to form fixed delay circuits with different fixed delay durations (as shown in the figure for the 8ps fixed delay circuit and the 64ps ​​fixed delay circuit).

[0081] The reference branch is a zero-delay straight-through branch, and the radio frequency signal has almost no delay effect when flowing through the reference branch.

[0082] The input switch is used to control the transmission path of the radio frequency (RF) signal. When the RF signal needs to be delayed through the fixed delay circuit, the input switch closes the sub-switch corresponding to the delay branch and opens the sub-switch corresponding to the reference branch, thereby allowing the RF signal to be transmitted from the delay branch of the fixed delay circuit to the next-level fixed delay circuit or adjustable delay circuit, thus achieving delayed transmission processing of the RF signal. When the RF signal does not need to be delayed through the fixed delay circuit, the input switch closes the sub-switch corresponding to the delay branch and opens the sub-switch corresponding to the delay branch, thereby allowing the RF signal to be transmitted from the reference branch of the fixed delay circuit to the next-level fixed delay circuit or adjustable delay circuit, thus not performing delayed transmission processing of the RF signal.

[0083] See Figure 4 The input switch can be a single-pole double-throw switch or a switch or integrated circuit with one input and two output switching logic to realize the one input and two output control switching logic. The specific switch type is not limited here.

[0084] The output switch is used to transmit the radio frequency (RF) signal from the time delay branch or reference branch to the next-level fixed-delay circuit or adjustable-delay circuit. If the RF signal is output from the time delay branch, the sub-switch of the corresponding time delay branch is closed, so that the RF signal is transmitted from the time delay branch to the next-level fixed-delay circuit or adjustable-delay circuit through the output switch. If the RF signal is output from the reference branch, the sub-switch of the corresponding reference branch is closed, so that the RF signal is transmitted from the reference branch to the next-level fixed-delay circuit or adjustable-delay circuit through the output switch.

[0085] The output switch can be a single-pole double-throw switch or a switch or integrated circuit with one input and two output switching logic to implement the one input and two output control switching logic. The specific switch type is not limited here.

[0086] In addition, see Figure 5 When two fixed-delay circuits are adjacent, the output switch of the preceding fixed-delay circuit and the input switch of the following fixed-delay circuit can be integrated into a single switch (a switch for implementing a 2-to-1 input, 2-to-1 output switching logic). This switch can be a double-pole double-throw switch or other switches or integrated circuits with 2-to-1 input, 2-to-1 output switching logic. The specific switch type is not limited here.

[0087] Based on the above-described fixed delay circuit configuration, multiple fixed delay circuits with different delay transmission durations (such as an 8ps fixed delay circuit and a 64ps ​​fixed delay circuit) can be configured in the signal delay circuit. The RF signal can be controlled by an input switch to perform corresponding delay transmission processing in different fixed delay circuits, thereby enabling flexible adjustment of the first delay duration of the signal delay circuit. This allows for the RF signal to be delayed and transmitted with a fixed delay time close to the target delay time in different target delay times corresponding to different RF signals.

[0088] Different fixed-delay circuits have different numbers of inductors and capacitors in their delay branches. Since inductors and capacitors have fixed frequency-selective losses, after the radio frequency signal is transmitted through the delay branch, in addition to the transmission time being different from that of the reference branch, the amplitude of the radio frequency signal will also be different. That is, the fixed-delay circuit has parasitic amplitude modulation. In order to ensure that the amplitude modulation of the reference branch and the delay branch of the fixed-delay circuit is consistent, it is necessary to perform parasitic amplitude modulation compensation on the reference circuit. In some embodiments of this application, different reference branches are set for fixed-delay circuits with different delay steps. See the following for a detailed explanation.

[0089] See Figure 6 In some embodiments of this application, the delay branch of the small step fixed delay circuit is configured with fewer second-order all-pass networks, resulting in a smaller delay transmission time.

[0090] The reference branch of its corresponding small step fixed delay circuit includes: the first unit first resistor R101;

[0091] One end of the first resistor R101 of the first unit is connected to the second output terminal of the input switch and the second input terminal of the output switch, and the other end of the first resistor R101 of the first unit is grounded.

[0092] For small step size fixed delay circuits, the parasitic amplitude modulation of the reference circuit is small. A parallel resistor (i.e., the first resistor R101 of the first unit) can be set to compensate for the parasitic amplitude modulation of the small step size fixed delay circuit.

[0093] See Figure 7 In some embodiments of this application, the delay branch of the medium step fixed delay circuit is provided with more second-order all-pass networks, and the delay transmission time is relatively long, such as a 64ps ​​fixed delay circuit. The medium step fixed delay circuit is used to delay the transmission of the input radio frequency signal to the next stage fixed delay circuit or adjustable delay circuit with a medium step fixed delay time.

[0094] The reference circuit for the medium-step fixed delay circuit includes: a first resistor R201 in the second unit, a second resistor R202 in the second unit, and a third resistor R203 in the second unit;

[0095] One end of the first resistor R201 of the second unit and one end of the second resistor R202 of the second unit are connected to the second output terminal of the input switch. The other end of the first resistor R201 of the second unit and one end of the third resistor R203 of the second unit are connected to the second input terminal of the output switch. The other end of the second resistor R202 of the second unit and the other end of the third resistor R203 of the second unit are grounded.

[0096] The reference circuit of the medium-step fixed delay circuit has a large parasitic amplitude modulation. A Π-type resistor network (i.e., the first resistor R201 of the second unit, the second resistor R202 of the second unit, and the third resistor R203 of the second unit) can be set up to compensate for the parasitic amplitude modulation of the medium-step fixed delay circuit.

[0097] See Figure 8 In some embodiments of this application, the delay branch of the large step fixed delay circuit is configured with multiple second-order all-pass networks, and the delay transmission time is relatively long, such as a fixed delay circuit of 128ps. The large step fixed delay circuit is used to delay the transmission of the input radio frequency signal to the next stage fixed delay circuit or the adjustable delay circuit with a large step fixed delay time.

[0098] The reference circuit for the large step delay circuit includes: the first inductor L301 of the third unit, the second inductor L302 of the third unit, the first resistor R301 of the third unit, and the first capacitor C301 of the third unit;

[0099] One end of the first inductor L301 of the third unit is connected to the second output terminal of the input switch. The other end of the first inductor L301 of the third unit is connected to one end of the second inductor L302 of the third unit and one end of the first resistor R301 of the third unit. The other end of the second inductor L302 of the third unit is connected to the second input terminal of the output switch. The other end of the first resistor R301 of the third unit is connected to one end of the first capacitor C301 of the third unit. The other end of the first capacitor C301 of the third unit is grounded.

[0100] The reference circuit of the large step delay circuit uses the characteristics of inductors and capacitors to form a negative slope low-pass circuit (i.e., the higher the frequency in the radio frequency signal band, the greater the attenuation). The negative slope low-pass network suppresses high-frequency signals.

[0101] The delay branch of a large step delay circuit incorporates multiple second-order all-pass networks. When these networks are cascaded, the skin effect (where eddy currents are induced inside a conductor at high frequencies, pushing the current into a very thin "skin layer" on the conductor's surface; the higher the frequency, the shallower the skin depth, the smaller the effective current cross-sectional area, and the AC resistance increases proportionally to the square root of the frequency, leading to a sharp increase in high-frequency loss) causes the insertion loss of the RF signal flowing through the delay branch to continuously increase with frequency (exhibiting a negative slope gain). To address this, the negative slope low-pass network formed by the aforementioned reference branch enables the RF signal flowing through the reference branch to also achieve a negative slope gain with continuously increasing insertion loss as the frequency increases. This achieves parasitic amplitude modulation compensation for the reference branch, ensuring that the insertion loss of the delay branch in the large step delay circuit is consistent with that of the reference branch, thus eliminating the parasitic amplitude modulation problem present in the large step delay circuit.

[0102] Furthermore, in some embodiments of this application, the delay branch of the large step size fixed delay circuit includes: multiple delay transmission lines and multiple second-order all-pass networks;

[0103] Multiple delay transmission lines are interconnected with multiple second-order all-pass networks. For details, see [link to documentation]. Figure 8 In one feasible approach, two delay transmission lines and four second-order all-pass networks can be configured. The two delay transmission lines and four second-order all-pass networks are connected in series. The two delay transmission lines are positioned in the middle to provide a larger delay, thereby reducing the design area of ​​the delay branch. The four second-order all-pass networks are symmetrically distributed on both sides of the delay transmission lines to provide a smaller delay, thereby ensuring the accuracy of the delay branch.

[0104] While using a single delay transmission line to set up a large step fixed delay circuit occupies a smaller area, it lacks accuracy. Using a single second-order all-pass network to set up a large step fixed delay circuit has higher accuracy, but it requires more cascaded inductors and capacitors, resulting in a larger area occupation. The large step fixed delay circuit set up in this application can simultaneously take into account the area advantage of the delay transmission line and the accuracy advantage of the second-order all-pass network.

[0105] See Figure 9 The reference circuit of the large step delay circuit is set as a negative slope low-pass circuit for amplitude modulation compensation with negative slope low-pass compensation, such as... Figure 9 As shown in L3, the reference circuit of the large step delay circuit is set as a Π-type circuit amplitude compensation, as follows. Figure 9As shown in L4, the more similar the curve trend is to the delay state curve L1, the better the amplitude modulation compensation effect. Compared with the compensation effect curve L4 set as a Π-type circuit for parasitic amplitude modulation compensation, the compensation effect curve L3 set as a negative slope low-pass circuit for parasitic amplitude modulation compensation is closer to the delay state compensation effect curve L1 in the low frequency and high frequency regions. Therefore, setting the reference circuit of the large step delay circuit as a negative slope low-pass circuit can achieve better parasitic amplitude modulation compensation for the large compensation delay circuit.

[0106] In addition, to further improve the signal transmission quality of the signal delay circuit with a large step length fixed delay circuit, in some embodiments of this application, the signal delay circuit further includes: at least one positive slope high-pass circuit.

[0107] A positive slope high-pass circuit is placed at the front or rear end of a large step fixed delay circuit;

[0108] The positive slope high-pass circuit is used to perform gain compensation on the first radio frequency signal that needs to be transmitted with a large step delay, and to send the gain-compensated radio frequency signal to the next stage of the fixed delay circuit or the adjustable delay circuit.

[0109] The gain of a positive slope high-pass circuit increases linearly with the signal frequency. When a large step delay circuit is set, the RF signal will be affected by the negative slope gain when passing through the delay branch or reference branch of the large step delay circuit. This results in lower low-frequency loss and higher high-frequency loss of the RF signal, and an imbalance in the gain flatness of the RF signal. Therefore, a positive slope high-pass circuit can compensate for the positive slope gain of the RF signal, making the low-frequency loss of the RF signal higher and the high-frequency loss lower. This ensures that the RF signal can be conditioned by the positive slope high-pass circuit after flowing through the large step fixed delay circuit, thereby improving the gain flatness of the RF signal.

[0110] See Figure 10 In some embodiments of this application, the positive slope high-pass circuit includes: a first resistor R401 of the fourth unit, a second resistor R402 of the fourth unit, a third resistor R403 of the fourth unit, a first capacitor C401 of the fourth unit, a second capacitor C402 of the fourth unit, a third capacitor C403 of the fourth unit, and a first inductor L401 of the fourth unit.

[0111] One end of the first resistor R401 and one end of the first capacitor C401 of the fourth unit are connected to the output of the previous fixed delay circuit. The other end of the first resistor R401, the other end of the first capacitor C401, one end of the second resistor R402, and one end of the second capacitor C402 of the fourth unit are connected to one end of the third resistor R403 of the fourth unit. The other end of the second resistor R402 and the other end of the second capacitor C402 of the fourth unit are connected to the input of the next fixed delay circuit. The other end of the third resistor R403 of the fourth unit is connected to one end of the third capacitor C403 of the fourth unit and one end of the first inductor L401 of the fourth unit. The other end of the third capacitor C403 and the other end of the first inductor L401 of the fourth unit are grounded.

[0112] The positive slope high-pass circuit described above is based on the fourth unit first capacitor C401 and fourth unit second capacitor C402 connected in series and the fourth unit first inductor L401 connected in parallel. This makes the insertion loss of the positive slope high-pass network decrease as the frequency increases, that is, the gain increases as the frequency increases, forming a positive slope gain curve. This allows for gain adjustment of the RF signal flowing through the large step length fixed delay circuit, ensuring the gain flatness of the RF signal.

[0113] For details on gain flatness effects, please refer to [link / reference]. Figure 11 After setting up a positive slope high-pass circuit, the gain flatness is around 0.7dB. The worst parasitic amplitude modulation is around ±0.6dB near 7GHz.

[0114] In addition, to further improve the signal transmission quality of the signal delay circuit with a large step length fixed delay circuit, in some embodiments of this application, the signal delay circuit further includes: at least one positive slope amplifier circuit.

[0115] A positive slope amplifier circuit is connected in series at the front or rear end of a large step fixed delay circuit;

[0116] The positive slope amplifier circuit is used to amplify the power of the first radio frequency signal, perform high-frequency attenuation compensation on the radio frequency signal transmitted with a large step delay, and send the first radio frequency signal after high-frequency attenuation compensation to the next stage fixed delay circuit or adjustable delay circuit.

[0117] When a large step-length delay circuit is set, the RF signal will be affected by the negative slope gain when passing through the delay branch or reference branch of the large step-length delay circuit. This results in low-frequency loss of the RF signal being small and high-frequency loss being large, causing an imbalance in the gain flatness of the RF signal. By setting a positive slope amplifier circuit, the positive slope gain of the RF signal can be compensated, making the low-frequency loss of the RF signal large and the high-frequency loss small. This compensates for the negative slope gain of the large step-length delay circuit and improves the gain flatness of the RF signal. Furthermore, since the total loss of the RF signal is too large after being processed by the negative slope gain of the large step-length delay circuit and the positive slope gain of the positive slope amplifier circuit, the amplification effect of the positive slope amplifier circuit across the entire frequency band can make up for the loss of the RF signal and ensure the output power of the RF signal.

[0118] See Figure 12 In some embodiments of this application, the positive slope amplifier circuit includes: a fifth unit first inductor L501, a fifth unit second inductor L502, a fifth unit third inductor L503, a fifth unit first capacitor C501, a fifth unit second capacitor C502, a fifth unit first amplifier transistor M1, and a fifth unit second amplifier transistor M2.

[0119] One end of the first inductor L501 of the fifth unit, the gate of the first amplifier M1 of the fifth unit, and the third power supply terminal V3 are connected to the output terminal of the previous fixed delay circuit. The source of the first amplifier M1 of the fifth unit is connected to one end of the second inductor L502 of the fifth unit. The other end of the second inductor L502 of the fifth unit is grounded. The other end of the first inductor L501 of the fifth unit is connected to one end of the first capacitor C501 of the fifth unit through the first resistor R501 of the fifth unit. The other end of the first capacitor C501 of the fifth unit, the drain of the second amplifier M2 of the fifth unit, and one end of the third inductor L503 of the fifth unit are connected to one end of the second capacitor of the fifth unit. The source of the second amplifier M2 of the fifth unit is connected to the drain of the first amplifier M1 of the fifth unit. The gate of the second amplifier M2 of the fifth unit is connected to the fourth power supply terminal V4. The other end of the third inductor L503 of the fifth unit is connected to the fifth power supply terminal V5. The other end of the second capacitor C502 of the fifth unit is connected to the input terminal of the next fixed delay circuit.

[0120] In addition, feedback capacitors or resistors, as shown in the figure, can be added to improve the performance of the positive slope amplifier circuit.

[0121] The aforementioned positive slope amplifier circuit uses a Cascode (common source, common gate) MOS transistor topology composed of the first amplifier transistor M1 and the second amplifier transistor M2 of the fifth unit as the amplification core to amplify the RF signal across the entire frequency band. It relies on the first inductor L501 of the fifth unit to generate a positive slope basis with the gain increasing with frequency, and uses the second inductor L502 and the third inductor L503 of the fifth unit to enhance the gain difference between high and low frequencies, thereby further enhancing the positive slope gain. Then, the first resistor R501 and the first capacitor C501 of the fifth unit are used to further increase the operating bandwidth of the positive slope amplifier circuit, so as to achieve positive slope gain amplification over a wider operating frequency range. This allows for compensation of high-frequency losses in large-step fixed-delay circuits while amplifying the RF signal power, thereby optimizing the gain flatness of the RF signal.

[0122] In some embodiments of this application, a positive slope amplifier circuit and a positive slope high-pass circuit can be simultaneously configured to compensate for the RF signal delayed by the large step size fixed delay circuit. Specifically, the effect of improving gain flatness is as follows: Figure 13 As shown, after setting up the positive slope amplifier circuit and the positive slope high-pass circuit, the overall gain flatness of the RF signal is significantly improved by about 0.5dB compared with setting up only the positive slope high-pass circuit.

[0123] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0125] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0126] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A signal delay circuit, characterized in that, include: Signal receiver, adjustable delay circuit and multiple fixed delay circuits; Multiple fixed-delay circuits are connected in series in a cascaded manner, wherein the input terminal of the first-stage fixed-delay circuit is connected to the signal receiving terminal, the output terminal of the last-stage fixed-delay circuit is connected to the input terminal of the adjustable-delay circuit, and the output terminal of the adjustable-delay circuit is connected to the load. The signal receiving end is used to receive the first radio frequency signal; At least a portion of the fixed delay circuits constitute the current fixed delay circuit corresponding to the first radio frequency signal. The current fixed delay circuit is used to perform a first delay transmission processing on the first radio frequency signal to obtain a second radio frequency signal, and to send the second radio frequency signal to the adjustable delay circuit. The first delay duration is the sum of the fixed delay durations of each fixed delay circuit included in the current fixed delay circuit. The adjustable delay circuit is used to perform a second delay transmission process on the second radio frequency signal to obtain a target radio frequency signal, and to send the target radio frequency signal to the load; the second delay duration is any delay duration within the continuously adjustable delay duration range corresponding to the adjustable delay circuit itself.

2. The signal delay circuit according to claim 1, characterized in that, The adjustable delay circuit includes: an adjustable inductor, a first adjustable capacitor, and a second adjustable capacitor; One end of the first adjustable capacitor and one end of the adjustable inductor are connected together to the output terminal of the last stage of the fixed delay circuit. The other end of the first adjustable capacitor is connected to the first power supply terminal. The other end of the adjustable inductor and one end of the second adjustable capacitor are connected together to the load. The other end of the second adjustable capacitor is connected to the second power supply terminal. The delay transmission time of the adjustable delay circuit is adjusted by the supply voltage of the first power supply terminal and the second power supply terminal.

3. The signal delay circuit according to claim 1, characterized in that, The plurality of fixed delay circuits include: a small step size fixed delay circuit, a medium step size fixed delay circuit, and a large step size fixed delay circuit; The delay propagation time of the small step size fixed delay circuit is smaller than that of the medium step size fixed delay circuit and the large step size fixed delay circuit. The delay propagation time of the medium-step fixed delay circuit is smaller than that of the large-step fixed delay circuit.

4. The signal delay circuit according to claim 3, characterized in that, Each of the following fixed delay circuits—the small-step fixed delay circuit, the medium-step fixed delay circuit, and the large-step fixed delay circuit—comprising: a delay branch, a reference branch, an input switch, and an output switch. The input terminal of the input switch is connected to the output terminal of the previous stage fixed delay circuit. The first output terminal of the input switch is connected to the input terminal of the delay branch. The second output terminal of the input switch is connected to the input terminal of the reference branch. The output terminal of the delay branch is connected to the first input terminal of the output switch. The output terminal of the reference branch is connected to the second input terminal of the output switch. The output terminal of the output switch is connected to the input terminal of the next stage fixed delay circuit.

5. The signal delay circuit according to claim 4, characterized in that, The reference branch of the small-step fixed-delay circuit includes: a first unit, a first resistor; One end of the first resistor of the first unit is connected to the second output terminal of the input switch and the second input terminal of the output switch, and the other end of the first resistor of the first unit is grounded.

6. The signal delay circuit according to claim 4, characterized in that, The reference branch of the medium-step fixed delay circuit includes: a first resistor of the second unit, a second resistor of the second unit, and a third resistor of the second unit; One end of the first resistor of the second unit and one end of the second resistor of the second unit are connected to the second output terminal of the input switch. The other end of the first resistor of the second unit and one end of the third resistor of the second unit are connected to the second input terminal of the output switch. The other ends of the second resistor of the second unit and the other ends of the third resistor of the second unit are grounded.

7. The signal delay circuit according to claim 4, characterized in that, The reference branch of the large step fixed delay circuit includes: the first inductor of the third unit, the second inductor of the third unit, the first resistor of the third unit, and the first capacitor of the third unit; One end of the first inductor of the third unit is connected to the second output terminal of the input switch, the other end of the first inductor of the third unit is connected to one end of the second inductor of the third unit and one end of the first resistor of the third unit, the other end of the second inductor of the third unit is connected to the second input terminal of the output switch, the other end of the first resistor of the third unit is connected to one end of the first capacitor of the third unit, and the other end of the first capacitor of the third unit is grounded.

8. The signal delay circuit according to claim 4, characterized in that, The delay branch of the large step fixed delay circuit includes: multiple delay transmission lines and multiple second-order all-pass networks; The multiple delay transmission lines are connected in series with the multiple second-order all-pass networks.

9. The signal delay circuit according to claim 7, characterized in that, Also includes: At least one positive slope high-pass circuit; The positive slope high-pass circuit is connected in series at the front or rear end of the large step fixed delay circuit; The positive slope high-pass circuit is used to perform gain compensation on the first radio frequency signal transmitted with a large step delay, and send the first radio frequency signal after gain compensation to the next stage fixed delay circuit or adjustable delay circuit.

10. The signal delay circuit according to claim 9, characterized in that, The positive slope high-pass circuit includes: a first resistor in the fourth unit, a second resistor in the fourth unit, a third resistor in the fourth unit, a first capacitor in the fourth unit, a second capacitor in the fourth unit, a third capacitor in the fourth unit, and a first inductor in the fourth unit; One end of the first resistor of the fourth unit and one end of the first capacitor of the fourth unit are connected to the output terminal of the fixed delay circuit of the previous stage. The other end of the first resistor of the fourth unit, the other end of the first capacitor of the fourth unit, one end of the second resistor of the fourth unit and one end of the second capacitor of the fourth unit are connected to one end of the third resistor of the fourth unit. The other end of the second resistor of the fourth unit and the other end of the second capacitor of the fourth unit are connected to the input terminal of the fixed delay circuit of the next stage. The other end of the third resistor of the fourth unit is connected to one end of the third capacitor of the fourth unit and one end of the first inductor of the fourth unit. The other end of the third capacitor of the fourth unit and the other end of the first inductor of the fourth unit are grounded.

11. The signal delay circuit according to claim 7, characterized in that, Also includes: At least one positive slope amplifier circuit; The positive slope amplifier circuit is connected in series at the front or rear end of the large step fixed delay circuit; The positive slope amplifier circuit is used to amplify the power of the first radio frequency signal, perform high-frequency attenuation compensation on the radio frequency signal transmitted through the large step delay, and send the first radio frequency signal after high-frequency attenuation compensation to the next stage of the fixed delay circuit or the adjustable delay circuit.

12. The signal delay circuit according to claim 11, characterized in that, The positive slope amplifier circuit includes: a first inductor of the fifth unit, a second inductor of the fifth unit, a third inductor of the fifth unit, a first capacitor of the fifth unit, a second capacitor of the fifth unit, a first amplifying transistor of the fifth unit, and a second amplifying transistor of the fifth unit; One end of the first inductor of the fifth unit, the gate of the first amplifier of the fifth unit, and the third power supply terminal are all connected to the output terminal of the fixed delay circuit of the previous stage. The source of the first amplifier of the fifth unit is connected to one end of the second inductor of the fifth unit, and the other end of the second inductor of the fifth unit is grounded. The other end of the first inductor of the fifth unit is connected to one end of the first capacitor of the fifth unit. The other end of the first capacitor of the fifth unit, the drain of the second amplifier of the fifth unit, and one end of the third inductor of the fifth unit are all connected to one end of the second capacitor of the fifth unit. The source of the second amplifier of the fifth unit is connected to the drain of the first amplifier of the fifth unit. The gate of the second amplifier of the fifth unit is connected to the fourth power supply terminal. The other end of the third inductor of the fifth unit is connected to the fifth power supply terminal. The other end of the second capacitor of the fifth unit is connected to the input terminal of the fixed delay circuit of the next stage.

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