Regulation circuit, method and device for minimum duty cycle of pfc

Abstract

The application relates to a PFC minimum duty cycle adjusting circuit, method and device. The adjusting circuit comprises a desaturation (DESAT) detection circuit for outputting a desaturation voltage signal, a gate charge integration circuit for outputting an integrated voltage signal, a temperature detection circuit for outputting a temperature signal, and a controller connected with the DESAT detection circuit, the gate charge integration circuit and the temperature detection circuit respectively and configured to acquire a current conduction time of an IGBT switch according to the desaturation voltage signal, acquire a current gate charge related quantity of the IGBT switch according to the integrated voltage signal, acquire a current temperature of the IGBT switch according to the temperature signal, determine a comprehensive aging coefficient of the IGBT switch according to the current conduction time, the current gate charge related quantity and the current temperature, and adjust a current minimum duty cycle of a PFC circuit according to the comprehensive aging coefficient. The minimum duty cycle is dynamically adjusted based on the comprehensive aging coefficient, so that the IGBT can always work in a safe switching time range.

Description

Technical Field

[0001] The present application relates to the technical field of air conditioners, and in particular to a circuit, method and apparatus for adjusting the minimum duty cycle of PFC. Background Art

[0002] Power Factor Correction (PFC) circuits are widely used in power electronic devices such as air conditioners and power supplies, for improving the input power factor and reducing harmonic current. A PFC circuit usually adopts an Insulated Gate Bipolar Transistor (IGBT) as a switching tube, and controls the turn-on and turn-off of the IGBT through a Pulse Width Modulation (PWM) signal, so as to realize shaping of the input current and stabilization of the bus voltage.

[0003] In the PFC control strategy, the minimum duty cycle (D_min) is a key parameter set by the controller. In the prior art, when the current duty cycle D calculated by the PFC circuit according to the input voltage V_in and the bus voltage V_Bus is less than D_min, the duty cycle is forcibly set to 0, which causes the PFC circuit to stop working, triggers oscillation of the input current waveform, and may damage the IGBT switching tube in severe cases. Therefore, D_min is required to be as small as possible to ensure that the PFC circuit can still work normally under high input voltage working conditions.

[0004] However, the IGBT switching tube will age with the working time and environmental conditions during use, and the switching time will gradually increase, while the minimum duty cycle remains unchanged, which will lead to a series of problems such as damage to the IGBT switching tube or failure of the equipment to work, affecting the user's use experience. Summary of the Invention

[0005] The present application provides a circuit, method and apparatus for adjusting the minimum duty cycle of PFC, so as to solve the technical contradiction in the existing PFC control strategy that the value of the minimum duty cycle cannot simultaneously meet the two working condition requirements of "preventing shutdown under high input voltage" and "ensuring turn-off after IGBT aging", which further leads to the technical problem that the minimum duty cycle of PFC is not adapted to the aging of the IGBT switching tube.

[0006] In a first aspect, the present application provides a regulation circuit for the minimum duty cycle of Power Factor Correction PFC, which is applied to a PFC circuit, the PFC circuit includes an Insulated Gate Bipolar Transistor IGBT switching tube, and the regulation circuit includes: A desaturation DESAT detection circuit, whose input terminal is connected to the collector of the IGBT switching tube, and whose output terminal is connected to the controller, configured to output a desaturation voltage signal; A gate charge integration circuit, whose input terminal is connected to the gate drive branch of the IGBT switch and whose output terminal is connected to the controller, is used to output an integrated voltage signal. A temperature detection circuit is installed at the IGBT switching transistor, and its output terminal is connected to the controller to output a temperature signal. The controller, connected to the DESAT detection circuit, the gate charge integration circuit, and the temperature detection circuit respectively, is configured as follows: The current on-time of the IGBT switch is obtained based on the desaturation voltage signal; the current gate charge correlation value of the IGBT switch is obtained based on the integral voltage signal; and the current temperature of the IGBT switch is obtained based on the temperature signal. Based on the current on-time, the current gate charge correlation value, and the current temperature, determine the comprehensive aging factor of the IGBT switch; and based on the comprehensive aging factor, adjust the current minimum duty cycle of the PFC circuit.

[0007] In one possible implementation, the DESAT detection circuit further includes a resistor divider circuit and an RC filter circuit. The input terminal of the resistor divider circuit is connected to the collector of the IGBT switch, and the output terminal of the resistor divider circuit is connected to the controller via the RC filter circuit.

[0008] In one possible implementation, the resistor divider circuit includes a first resistor and a second resistor connected in series between the collector of the IGBT switch and ground; The RC filter circuit includes a third resistor and a first capacitor; the connection node between the first resistor and the second resistor is connected to the input terminal of the controller via the third resistor, one end of the first capacitor is connected to the connection node between the third resistor and the input terminal of the controller, and the other end is grounded.

[0009] In one possible implementation, the gate charge integration circuit includes: An operational amplifier with its non-inverting input terminal grounded and its inverting input terminal serving as a current input terminal, is used to receive the gate drive current of the IGBT switching transistor. An integrating capacitor is connected between the inverting input and the output of the operational amplifier. The sampling resistor has one end connected to the gate drive branch of the IGBT switch and the other end connected to the inverting input of the operational amplifier. The output of the operational amplifier is connected to the controller as the output of the gate charge integration circuit.

[0010] In one possible implementation, the controller latches the integrated voltage signal on the falling edge of each PWM cycle and clears the charge on the integrating capacitor before the start of the next PWM cycle; during the PWM high level, the integrating capacitor integrates the gate drive current.

[0011] In one possible implementation, the amplitude of the integrated voltage signal is proportional to the total gate charge of the IGBT switch, where the total gate charge Q = IG × t, and IG is the gate drive current and t is the duration of the PWM high level.

[0012] In one possible implementation, the controller obtains the current on-time based on the time difference between the desaturation voltage signal dropping from the first threshold voltage to the second threshold voltage.

[0013] In one possible implementation, the controller determines the overall aging factor according to the following formula: K1=(t_now / t_base)×[1+α×(t_now-t_base)]; K2=(V_now / V_base)×[1+β×(V_now-V_base)]; K3=(T_now / T_base)×[1+γ×(T_now-T_base)]; K4 = K1 × K2 × K3; Wherein, t_now is the current on-time, and t_base is the preset reference on-time; V_now is the current gate charge correlation quantity, and V_base is the preset reference gate charge correlation quantity; T_now is the current temperature, and T_base is the preset reference temperature; α, β, and γ are preset correction coefficients; and K4 is the comprehensive aging coefficient.

[0014] In one possible implementation, the controller adjusts the current minimum duty cycle of the PFC circuit based on the overall aging factor, including: The controller increases the current minimum duty cycle of the PFC circuit by a preset multiplier corresponding to the preset value range where the comprehensive aging coefficient is located; wherein, the larger the comprehensive aging coefficient is, the larger the preset multiplier is.

[0015] Secondly, this application provides a method for adjusting the minimum duty cycle of a PFC circuit, applied to the circuit described in the first aspect, the method comprising: Obtain the desaturation voltage signal output by the DESAT detection circuit, and obtain the current on-time of the IGBT switch based on the desaturation voltage signal; Obtain the integrated voltage signal output by the gate charge integration circuit, and obtain the current gate charge related quantity of the IGBT switch based on the integrated voltage signal; The temperature signal output by the temperature detection circuit is obtained, and the current temperature of the IGBT switch is obtained based on the temperature signal. The overall aging factor of the IGBT switch is determined based on the current conduction time, the current gate charge correlation value, and the current temperature. Based on the comprehensive aging factor, adjust the current minimum duty cycle of the PFC circuit.

[0016] Thirdly, this application provides a PFC minimum duty cycle adjustment device, applied to the circuit described in the first aspect, the device comprising: The on-time acquisition module is used to acquire the desaturation voltage signal output by the DESAT detection circuit, and to acquire the current on-time of the IGBT switch based on the desaturation voltage signal. The gate charge acquisition module is used to acquire the integrated voltage signal output by the gate charge integration circuit, and to acquire the current gate charge related quantity of the IGBT switch based on the integrated voltage signal. A temperature acquisition module is used to acquire the temperature signal output by the temperature detection circuit and to acquire the current temperature of the IGBT switching transistor based on the temperature signal. The aging coefficient determination module is used to determine the comprehensive aging coefficient of the IGBT switch based on the current conduction time, the current gate charge correlation quantity, and the current temperature. The duty cycle adjustment module is used to adjust the current minimum duty cycle of the PFC circuit according to the comprehensive aging coefficient.

[0017] Fourthly, this application provides a PFC circuit, comprising: The PFC main circuit includes inductors, IGBT switching transistors, diodes, and bus capacitors; The PFC minimum duty cycle adjustment circuit described in the first aspect is connected to the IGBT switching transistor and is used to adjust the minimum duty cycle of the PFC circuit.

[0018] Fifthly, this application provides an air conditioner including the PFC circuit described in the fourth aspect.

[0019] Sixthly, this application also provides a computer storage medium storing computer-executable instructions for executing the PFC minimum duty cycle adjustment method described in any of the preceding claims of this application.

[0020] Compared with the prior art, the technical solution provided in this application has the following advantages: The adjustment circuit provided in this application includes: a desaturation DESAT detection circuit for outputting a desaturation voltage signal; a gate charge integration circuit for outputting an integration voltage signal; a temperature detection circuit for outputting a temperature signal; and a controller connected to the DESAT detection circuit, the gate charge integration circuit, and the temperature detection circuit, respectively, configured to: obtain the current on-time of the IGBT switch based on the desaturation voltage signal; obtain the current gate charge correlation quantity of the IGBT switch based on the integration voltage signal; obtain the current temperature of the IGBT switch based on the temperature signal; determine the comprehensive aging coefficient of the IGBT switch based on the current on-time, the current gate charge correlation quantity, and the current temperature; and adjust the current minimum duty cycle of the PFC circuit based on the comprehensive aging coefficient.

[0021] By employing a three-channel detection system—DESAT detection circuit, gate charge integration circuit, and temperature detection circuit—the comprehensive aging factor of the IGBT is calculated in real time. Based on this comprehensive aging factor, the minimum duty cycle is adaptively and dynamically adjusted to ensure the IGBT always operates within a safe switching time range. This avoids incomplete turn-off due to an excessively small duty cycle and voltage spikes caused by aging accumulation, effectively slowing down the IGBT's degradation rate and extending its lifespan. Simultaneously, by detecting the IGBT's conduction time (reflecting switching speed degradation), gate charge correlation (reflecting gate oxide damage), and temperature (reflecting thermal stress accumulation), the aging state of the IGBT is comprehensively characterized from the perspectives of electrical parameters, physical structure, and thermal stress. This avoids the limitations of single-parameter detection (such as misjudging high temperature as aging by measuring only temperature), thereby improving the accuracy and reliability of IGBT aging assessment. Furthermore, dynamically adjusting the minimum duty cycle based on the comprehensive aging factor ensures that the PFC minimum duty cycle always adapts to the aging degree of the IGBT switch, thus ensuring the IGBT always operates within a safe switching time range. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0025] Figure 1 A schematic diagram of a PFC minimum duty cycle adjustment circuit provided for an embodiment of this application; Figure 2 A schematic diagram of a PFC circuit provided in an embodiment of this application; Figure 3 A flowchart illustrating an embodiment of a method for adjusting the minimum duty cycle of a PFC provided in this application; Figure 4 A flowchart illustrating a method for adjusting the minimum duty cycle of a PFC, provided in an embodiment of this application; Figure 5 A block diagram of a PFC minimum duty cycle adjustment device provided in this application; Figure 6 This is a schematic diagram of the structure of an air conditioner device provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0028] To address the technical contradiction in existing PFC control strategies where the minimum duty cycle cannot simultaneously meet the requirements of "anti-shutdown under high input voltage" and "IGBT turn-off protection after aging," leading to a mismatch between the PFC minimum duty cycle and the aging of the IGBT switching transistor, this application provides a circuit, method, and apparatus for adjusting the PFC minimum duty cycle. Through three-channel detection—a DESAT detection circuit, a gate charge integration circuit, and a temperature detection circuit—the comprehensive aging coefficient of the IGBT is calculated in real time. Based on this comprehensive aging coefficient, the minimum duty cycle is adaptively and dynamically adjusted. This ensures that the IGBT always operates within a safe switching time range, avoiding incomplete turn-off due to an excessively small duty cycle and voltage spikes caused by aging accumulation. This effectively slows down the degradation rate of the IGBT and extends its service life. Meanwhile, by detecting the IGBT's conduction time (reflecting switching speed degradation), gate charge correlation (reflecting gate oxide damage), and temperature (reflecting thermal stress accumulation), the aging state of the IGBT is comprehensively characterized from the perspectives of electrical parameters, physical structure, and thermal stress, respectively. This avoids the limitations of single-parameter detection (such as misjudging high temperature as aging when only temperature is measured), thereby improving the accuracy and reliability of IGBT aging assessment. Furthermore, by dynamically adjusting the minimum duty cycle based on the comprehensive aging coefficient, it is possible to ensure that the PFC minimum duty cycle always matches the aging degree of the IGBT switch, thus enabling the IGBT to always operate within a safe switching time range.

[0029] Figure 1 This diagram illustrates a PFC minimum duty cycle adjustment circuit provided in an embodiment of this application. The circuit is applied to a PFC circuit, which includes an IGBT switch. The PFC minimum duty cycle adjustment circuit includes: a desaturation DESAT detection circuit 100, a gate charge integration circuit 200, a temperature detection circuit 300, and a controller 400. The desaturation DESAT detection circuit 100, the gate charge integration circuit 200, and the temperature detection circuit 300 are respectively connected to the controller 400. The controller 400 is used to calculate the IGBT comprehensive aging coefficient based on the three detection signals and adaptively adjust the minimum duty cycle of the PFC circuit. The following will combine... Figure 1 Each component is described in detail.

[0030] See Figure 1 As shown, the input terminal of the desaturation DESAT detection circuit 100 is connected to the collector of the IGBT switching transistor, and the output terminal is connected to the controller 400 to output the desaturation voltage signal.

[0031] The DESAT (Desaturation) detection circuit is a protection circuit used to monitor whether an IGBT has exited the saturation region. When an IGBT is normally conducting, it operates in the saturation region, with a low collector-emitter voltage (Vce), typically between 1.5V and 3V. When a short circuit or overcurrent fault occurs, the IGBT exits the saturation region and enters a desaturation state, causing Vce to rise rapidly to the bus voltage level, i.e., a sharp increase. The DESAT detection circuit monitors the change in Vce voltage to determine if a desaturation fault has occurred and sends a signal to the controller when a fault is detected.

[0032] In one embodiment, the DESAT detection circuit further includes a resistor divider circuit 110 and an RC filter circuit 120. The input terminal of the resistor divider circuit is connected to the collector of the IGBT switch, and the output terminal of the resistor divider circuit is connected to the controller via the RC filter circuit.

[0033] A resistor voltage divider circuit is a voltage divider network consisting of two or more resistors connected in series. It is used to proportionally reduce high voltage to a range suitable for detection by low-voltage circuits. Since the collector voltage of IGBTs can reach hundreds or even thousands of volts, while controllers typically only handle low-voltage signals of 3.3V or 5V, a resistor voltage divider circuit is needed to convert the high voltage into a low-voltage signal. Its basic principle is to utilize the voltage-dividing characteristics of series resistors to proportionally reduce the high voltage to a range detectable by the controller.

[0034] An RC filter circuit refers to a first-order low-pass filter composed of a resistor (R) and a capacitor (C), used to filter out high-frequency noise and spike interference in signals. In power electronics applications, the high-speed switching of IGBTs generates strong electromagnetic interference, which, when superimposed on the detection signal, may cause misjudgment by the controller. RC filter circuits can effectively suppress this high-frequency noise, ensuring the accuracy of the detection signal.

[0035] In one embodiment, such as Figure 1 As shown, the resistor divider circuit includes a first resistor R1 and a second resistor R2 connected in series between the collector of the IGBT switch and ground; the RC filter circuit includes a third resistor R3 and a first capacitor C1; the connection node of the first resistor R1 and the second resistor R2 is connected to the input terminal of the controller through the third resistor R3, one end of the first capacitor C1 is connected to the connection node of the third resistor R3 and the input terminal of the controller, and the other end is grounded.

[0036] The high voltage at the IGBT collector is divided by the first resistor R1 and the second resistor R2, and then output to the RC filter circuit through the connection node of the first resistor R1 and the second resistor R2. The third resistor R3 and the first capacitor C1 form a first-order RC filter, which filters the voltage signal after it has been stepped down by the resistor divider circuit, and sends it to the controller after filtering out high-frequency switching noise.

[0037] Understandably, a resistor divider circuit safely converts the high voltage (up to hundreds to thousands of volts) at the IGBT collector into a low-voltage signal detectable by the controller, eliminating the need for high-voltage isolation devices and reducing circuit cost and complexity. The RC filter circuit effectively filters out high-frequency noise and voltage spikes generated by the high-speed switching of the IGBT, preventing misjudgments by the controller due to noise interference and improving the accuracy of conduction time detection and system reliability. Furthermore, the DESAT detection circuit in this application, while maintaining the original short-circuit protection function, introduces the detection signal into the controller through resistor divider and RC filtering, achieving accurate measurement of the IGBT conduction time and providing key parameters for aging assessment without the need for additional hardware.

[0038] See Figure 1 As shown, the input terminal of the gate charge integration circuit is connected to the gate drive branch of the IGBT switch, and the output terminal is connected to the controller to output the integrated voltage signal.

[0039] The gate charge integrator circuit is an analog integrator based on an operational amplifier and an integrating capacitor. It is used to integrate the gate drive current during the PWM high level to obtain an integrated voltage signal that is proportional to the total gate charge.

[0040] In one embodiment, the gate charge integration circuit includes: an operational amplifier U1, whose non-inverting input is grounded and whose inverting input is a current input for receiving the gate drive current of the IGBT switch; an integrating capacitor C2 connected between the inverting input and the output of the operational amplifier U1; a sampling resistor R4, one end of which is connected to the gate drive branch of the IGBT switch and the other end of which is connected to the inverting input of the operational amplifier U1; and the output of the operational amplifier U1 is connected to the controller as the output of the gate charge integration circuit.

[0041] The operational amplifier U1 described above is a high-gain DC-coupled differential amplifier with a non-inverting input (+), an inverting input (-), and an output. In the integrator configuration of this application, the non-inverting input is grounded, and the inverting input serves as the current input, receiving the gate drive current. Due to the "virtual ground" characteristic of operational amplifier U1, the potential of the inverting input is clamped to near ground potential (0V), making the voltage drop across the sampling resistor R4 approximately zero. This allows all the current in the sampling resistor R4 to flow into the integrating capacitor C2 for integration, thus ensuring integration accuracy.

[0042] The sampling resistor R4 is a small resistor (usually tens to hundreds of ohms) connected in series in the gate drive branch, used to convert the gate drive current signal into a current input signal that can be processed by the analog integrator.

[0043] The integrating capacitor C2 is a capacitor connected between the inverting input and output of operational amplifier U1. The gate drive current flowing into the inverting input charges the integrating capacitor C2, and the amount of charge accumulated across the capacitor is the time integral of the input current. The voltage across the integrating capacitor C2 (i.e., the op-amp output voltage) is proportional to the time integral of the input current (i.e., the total charge).

[0044] In one embodiment, the controller latches the integral voltage signal on the falling edge of each PWM cycle and clears the charge on the integral capacitor C2 before the start of the next PWM cycle; during the PWM high level, the integral capacitor C2 integrates the gate drive current.

[0045] A PWM (Pulse Width Modulation) signal is a periodically repeating square wave signal. A complete PWM cycle includes a high-level time (i.e., the IGBT turn-on time) and a low-level time (i.e., the IGBT turn-off time).

[0046] The PWM high-level period refers to the time during which the PWM signal is high, i.e., the period during which the IGBT receives the turn-on command and the gate drive current flows continuously. During this period, the integrating capacitor C2 integrates the gate drive current.

[0047] The falling edge of a PWM signal refers to the instantaneous transition of the PWM signal from a high level to a low level (i.e., the moment the shutdown command is issued). This is an instantaneous level transition edge, which the controller uses as a trigger signal to latch the integral voltage signal at this moment.

[0048] The PWM signal is a control command sent by the controller to the IGBT driver chip. It is a periodic square wave signal that controls the conduction time of the IGBT by adjusting the duration of the high level (i.e., the pulse width). The larger the duty cycle of the PWM signal (i.e., the proportion of the high level time to the entire cycle), the longer the IGBT conducts within one cycle.

[0049] Latching refers to the controller reading the amplitude of the integral voltage signal at a specific moment (the falling edge of the PWM) and storing it in a register for subsequent analog-to-digital conversion and data processing. The latching action ensures that the controller captures the integral voltage value at the instant the IGBT is turned off, which represents the total gate charge accumulated during the entire IGBT conduction period.

[0050] Resetting (or clearing) refers to completely releasing the residual charge on the integrating capacitor C2 before the start of the next PWM cycle, causing the output voltage of the integrating circuit to return to zero. Resetting ensures that the integration of each PWM cycle starts from a zero initial state, avoiding the cumulative error caused by residual charge from the previous cycle in the current cycle's measurement.

[0051] The integrated voltage signal refers to the voltage signal output by the gate charge integrating circuit, and its amplitude is equal to the voltage across the integrating capacitor C2. According to the capacitor voltage formula V=Q / C, this voltage value (V) is proportional to the amount of charge (Q) accumulated on the integrating capacitor C2, that is, proportional to the total gate charge of the IGBT switch.

[0052] In one embodiment, the amplitude of the integrated voltage signal is proportional to the total gate charge of the IGBT switch, where the total gate charge Q = IG × t, IG is the gate drive current, and t is the duration of the PWM high level.

[0053] The total gate charge refers to the total charge injected into the gate of an IGBT to transition it from the off state to the fully on state. The gate of an IGBT is essentially a capacitor (formed by the gate oxide layer). To turn on the IGBT, sufficient charge must be injected into this capacitor to charge the gate voltage from 0V to the turn-on threshold voltage. The total gate charge Q = IG × t, where IG is the gate drive current and t is the duration of the PWM high level. As the IGBT ages, the gate oxide layer degrades, causing the gate capacitance to increase. In the same on-time, more charge is needed to raise the gate voltage to the turn-on threshold voltage, i.e., Q increases.

[0054] For example, see Figure 1 As shown, the gate charge integration circuit includes operational amplifier U1, integrating capacitor C2, and sampling resistor R4. One GPIO pin of the controller (such as an MCU) is used to detect the edge of the PWM signal, one ADC pin is used to read the integrated voltage signal, and another GPIO pin is used to control a reset switch (such as a MOSFET or analog switch), which is connected in parallel across integrating capacitor C2. The entire operation is divided into three stages, which are executed cyclically within each PWM cycle: During the integration phase, the PWM signal is high, the IGBT is turned on, and the gate drive current IG flows continuously. The gate drive current flows into the integrating capacitor C2 through the sampling resistor R4, and the integrating capacitor C2 integrates the gate drive current over time. The output voltage of the operational amplifier U1 gradually increases from 0V.

[0055] During the latching phase, the controller detects the instant the PWM signal transitions from high to low (falling edge), immediately triggers ADC sampling, reads the amplitude of the current integrated voltage signal, and latches this value into an internal register. This latched value, V_now, is the gate charge correlation value for this cycle, used for subsequent aging factor calculation.

[0056] During the reset phase, the controller outputs a reset pulse signal to turn on the reset switch (such as a MOSFET) connected in parallel across the integrating capacitor C2, short-circuiting and discharging the integrating capacitor C2. The charge on the integrating capacitor C2 is completely released, and the output voltage of the operational amplifier U1 returns to zero. Subsequently, the reset switch turns off, and the integrating circuit returns to its initial zero state, awaiting the arrival of the next PWM cycle.

[0057] It is important to note that in circuit design, the clearing operation must be completed after the PWM falling edge latch is finished and before the next PWM high level arrives. That is, clearing occurs during the PWM low level period. If clearing is not timely (later than the arrival of the next PWM high level), the integration in the next cycle will start from a non-zero initial state, resulting in measurement errors.

[0058] Based on the above description, the integration, latching, and clearing actions are completed sequentially within each PWM cycle, achieving real-time tracking of IGBT gate charge changes cycle by cycle and enabling timely detection of aging trends. Latching is performed by the controller's internal ADC and registers, while clearing is achieved by the controller's GPIO controlling an electronic switch, eliminating the need for external sample-and-hold circuits or reset circuits, thus reducing hardware costs. Integration, latching, and clearing are all completed within a single PWM cycle (e.g., 50μs), meaning that an aging detection result can be output every PWM cycle (tens of microseconds), significantly improving response speed compared to offline detection or periodic inspection schemes.

[0059] See Figure 1 As shown, Figure 1 The temperature detection circuit can be located at the IGBT switching transistor, and its output is connected to the controller to output the temperature signal.

[0060] A temperature detection circuit is a circuit located at the IGBT switching transistor to sense the IGBT's operating temperature and convert it into an electrical signal (such as voltage or current). Its output is connected to a controller to output the temperature signal. Commonly used temperature sensing elements in the above-mentioned temperature detection circuit include negative temperature coefficient thermistors (such as NTC), positive temperature coefficient thermistors (such as PTC), or temperature sensor chips (such as LM35, DS18B20, etc.).

[0061] The temperature signal refers to the electrical signal (usually a voltage value or a resistor voltage divider value) output by the temperature detection circuit to the controller. The controller samples this signal and converts it into the current temperature value T_now of the IGBT according to the characteristic curve of the temperature sensor (which describes the correspondence between the resistance value of the temperature sensor and the temperature; this curve is usually stored in the controller in the form of a temperature-resistance value lookup table).

[0062] In one embodiment, the temperature detection circuit is implemented by using an NTC thermistor connected in series with a fixed resistor to form a resistive voltage divider circuit. The NTC thermistor is mounted close to the casing or heat sink of the IGBT switching transistor, and its resistance decreases as the temperature rises. When the temperature changes, the voltage at the voltage divider node changes accordingly. The controller samples this voltage value through an ADC and converts it into the current temperature value T_now according to the temperature characteristic curve of the NTC (or a lookup table method).

[0063] See Figure 1 As shown, the controller is connected to the DESAT detection circuit, the gate charge integration circuit, and the temperature detection circuit, and is configured to: obtain the current on-time of the IGBT switch based on the desaturation voltage signal; obtain the current gate charge correlation quantity of the IGBT switch based on the integrated voltage signal; obtain the current temperature of the IGBT switch based on the temperature signal; determine the comprehensive aging factor of the IGBT switch based on the current on-time, the current gate charge correlation quantity, and the current temperature; and adjust the current minimum duty cycle of the PFC circuit based on the comprehensive aging factor.

[0064] Optionally, the controller 400 mentioned above can be a microcontroller (MCU), digital signal processor (DSP), etc. It is the core control unit of the circuit and has functions such as analog-to-digital conversion, digital signal processing, and PWM (Pulse Width Modulation) signal generation.

[0065] In this application, the controller is responsible for receiving the desaturation voltage signal output by the DESAT detection circuit, the integral voltage signal output by the gate charge integration circuit, and the temperature signal output by the temperature detection circuit, and performing calculations such as aging coefficient calculation and minimum duty cycle adjustment.

[0066] The desaturation voltage signal is the voltage signal output from the DESAT detection circuit to the controller. This signal is proportional to the IGBT collector-emitter voltage Vce (after resistor voltage division and RC filtering). The controller obtains the current conduction time of the IGBT by monitoring the time difference between the drop of this signal from the first threshold voltage to the second threshold voltage.

[0067] The integrated voltage signal refers to the voltage signal output from the gate charge integration circuit to the controller. The amplitude of this signal is proportional to the total gate charge Q of the IGBT switch. After reading this signal, the controller uses it as the current gate charge correlation quantity V_now to calculate the gate charge aging factor.

[0068] In one embodiment, the controller obtains the current on-time based on the time difference between the desaturation voltage signal dropping from the first threshold voltage to the second threshold voltage.

[0069] The first and second threshold voltages can be two preset voltage comparison points within the controller, used to define two critical moments in the IGBT conduction process. During IGBT conduction, the collector-emitter voltage Vce gradually decreases from a high level (off state) to a low level (fully on state). The controller monitors the desaturation voltage signal output by the DESAT detection circuit: when this signal drops to the first threshold voltage (e.g., corresponding to Vce≈5V), it indicates that the IGBT has started conducting; when this signal continues to drop to the second threshold voltage (e.g., corresponding to Vce≈2V), it indicates that the IGBT has fully conducted. The time difference between the two moments is the current conduction time of the IGBT.

[0070] The first threshold voltage and the second threshold voltage mentioned above can be adaptively adjusted and calibrated based on the saturation voltage drop characteristics, Vce drop curve during conduction, and voltage division ratio of the DESAT detection circuit given in the datasheet of the selected IGBT device. They are not fixed physical constants.

[0071] The current on-time t_now refers to the time required for the IGBT to go from starting to conduct (the desaturation voltage signal drops to the first threshold voltage) to fully conducting (the desaturation voltage signal drops to the second threshold voltage) in the current state. The shorter this time, the faster the IGBT switching speed and the healthier the device; the longer this time, the slower the IGBT switching speed and the more severe the device aging.

[0072] The reference conduction time t_base refers to the conduction time of the IGBT under healthy conditions (no aging, rated temperature operating conditions). This value is obtained through testing during the IGBT's initial power-on or factory calibration phase and serves as a benchmark for subsequent aging assessments, stored in the controller's memory.

[0073] In one embodiment, the controller determines the overall aging factor according to the following formula: K1=(t_now / t_base)×[1+α×(t_now-t_base)]; K2=(V_now / V_base)×[1+β×(V_now-V_base)]; K3=(T_now / T_base)×[1+γ×(T_now-T_base)]; K4 = K1 × K2 × K3; Where t_now is the current on-time, t_base is the preset reference on-time; V_now is the current gate charge correlation quantity, V_base is the preset reference gate charge correlation quantity; T_now is the current temperature, T_base is the preset reference temperature; α, β, γ are preset correction coefficients; K4 is the comprehensive aging coefficient.

[0074] The current gate charge correlation value V_now refers to the amplitude of the integrated voltage signal read by the controller in the current state. This amplitude is proportional to the total current gate charge Q of the IGBT switch. The larger V_now is, the larger the total gate charge and the more severe the IGBT aging.

[0075] The reference gate charge correlation value V_base refers to the amplitude of the integrated voltage signal read by the controller when the IGBT is in a healthy state (unaged, rated temperature operating condition). This value is obtained during the IGBT's initial power-on or factory calibration phase and is stored in the controller's memory as a benchmark for subsequent aging assessments.

[0076] The current temperature T_now refers to the IGBT operating temperature value (in °C) obtained in real time by the controller through the temperature detection circuit. The higher the IGBT temperature, the more severe the aging and the longer the switching time.

[0077] The reference temperature T_base refers to the normal operating temperature of the IGBT under rated conditions (e.g., 25°C or 40°C). The conduction time and gate charge related quantities measured at this temperature are used as the reference value. T_base is used to compare with the current temperature T_now to assess the impact of temperature on the degree of aging.

[0078] α, β, and γ are preset correction coefficients used to nonlinearly correct the conduction time aging coefficient K1, gate charge aging coefficient K2, and temperature aging coefficient K3, respectively. These coefficients are calibrated based on the IGBT device datasheet characteristics, aging test data, or actual operating conditions, making the calculation of the aging coefficients more accurately reflect the actual aging degree of the IGBT.

[0079] The conduction time aging factor K1 reflects the degree of aging of the IGBT due to prolonged conduction time; a larger value indicates more severe aging. The gate charge aging factor K2 reflects the degree of aging of the IGBT due to increased gate charge; a larger value indicates more severe aging. The temperature aging factor K3 reflects the effect of temperature on the degree of IGBT aging; a larger value indicates higher temperatures and more severe aging.

[0080] The comprehensive aging coefficient is a comprehensive index obtained by multiplying the conduction time aging coefficient K1, the gate charge aging coefficient K2, and the temperature aging coefficient K3. This coefficient comprehensively reflects the overall aging degree of IGBT in three dimensions: switching time, gate charge, and temperature. The larger the value of this coefficient, the more serious the aging of IGBT, and the greater the need to increase the minimum duty cycle of PFC.

[0081] In one embodiment, the controller adjusts the current minimum duty cycle of the PFC circuit according to the comprehensive aging coefficient, including: the controller increases the current minimum duty cycle of the PFC circuit by a preset multiplier corresponding to the preset value range where the comprehensive aging coefficient is located; wherein, the larger the comprehensive aging coefficient, the larger the preset multiplier.

[0082] The preset value range is a set of value intervals pre-stored within the controller to divide the range of the comprehensive aging factor K4. Each interval corresponds to a different minimum duty cycle adjustment factor. The preset factor is a factor that increases the current minimum duty cycle of the PFC circuit, corresponding one-to-one with the preset value interval. The larger the comprehensive aging factor K4, the more severe the IGBT aging, and the larger the corresponding preset factor, to provide more sufficient protection margin. For example, the mapping relationship between the preset value intervals and the corresponding preset factors is shown in Table 1 below: Table 1

[0083] The controller applies the adjusted minimum duty cycle to the PFC control algorithm: when the current duty cycle calculated by the PFC circuit is less than the adjusted minimum duty cycle, it forces the output to use the adjusted minimum duty cycle, effectively avoiding waveform oscillations caused by directly setting the duty cycle to 0 when the calculated current duty cycle is less than the minimum duty cycle.

[0084] The overall working principle of the PFC minimum duty cycle adjustment circuit provided in this application embodiment is as follows: The controller acquires three physical quantities in each PWM cycle: current on-time t_now, current gate charge related quantity V_now, and current temperature T_now. For example, the controller continuously samples the desaturation voltage signal output by the DESAT detection circuit and compares it with internally preset first and second threshold voltages: when the desaturation voltage signal drops to the first threshold voltage, the controller records time t1; when the desaturation voltage signal continues to drop to the second threshold voltage, the controller records time t2; and calculates the current on-time t_now = t2 - t1.

[0085] Furthermore, the controller triggers ADC sampling on the falling edge of the PWM, reads the integrated voltage signal output by the gate charge integration circuit, and latches this value as the current gate charge related quantity V_now; the controller samples the temperature signal (voltage value) output by the temperature detection circuit through the ADC, and converts it into the current temperature value T_now according to the characteristic curve of the temperature sensor.

[0086] The controller calculates three aging coefficients K1, K2, and K3 based on the three physical quantities obtained above, and then obtains the comprehensive aging coefficient K4. Based on the preset value range of the comprehensive aging coefficient K4 (see Table 1 above), the controller increases the current minimum duty cycle of the PFC circuit using the corresponding preset multiplier.

[0087] For example, taking an air conditioner inverter driver with a 380V DC bus voltage as an example, assuming that the reference values ​​for the factory calibration stage of the air conditioner are: at a room temperature of 25℃ (T_base), the IGBT conduction time t_base = 1.0μs and the gate charge integral voltage V_base = 0.8V; the above reference values ​​are stored in the controller EEPROM.

[0088] Assuming the equipment has been running for 2 years, the controller detects a time difference t_now = 1.5μs between the DESAT desaturation voltage signal dropping from the first threshold voltage to the second threshold voltage; the controller latches the integrated voltage signal V_now = 1.2V on the falling edge of the PWM; the temperature detection circuit output signal is converted to T_now = 85℃; preset correction coefficients: α = 0.1, β = 0.2, γ = 0.01. The controller calculates: K1=(1.5 / 1.0)×[1+0.1×(1.5-1.0)]=1.5×1.05=1.575; K2=(1.2 / 0.8)×[1+0.2×(1.2-0.8)]=1.5×1.08=1.62; K3=(85 / 25)×[1+0.01×(85-25)]=3.4×1.6=5.44; K4 = 1.575 × 1.62 × 5.44 ≈ 13.87. Since K4=13.87≥1.35, the controller determines that the IGBT is severely aged and adjusts the minimum duty cycle of the PFC to 1.3 times the original value; at the same time, it issues an IGBT aging alarm, prompting that maintenance and inspection are required.

[0089] It can be understood that before adjusting the minimum duty cycle, assuming the original D_min=0.022, when the peak input voltage is 372V, the calculated duty cycle D=0.021<D_min, and the system forcibly sets the duty cycle to 0, which will cause waveform oscillation. After adopting the minimum duty cycle adjustment method provided in the embodiments of the present application, D_min=0.022×1.3=0.0286, the calculated current duty cycle is 0.021<0.0286, and the system outputs at the minimum duty cycle of 0.0286, which can effectively avoid waveform oscillation and IGBT turn-off failure.

[0090] The above adaptive adjustment for the PFC minimum duty cycle is an adjustment method proposed mainly in view of two conflicting requirements existing in the value of the existing PFC minimum duty cycle D_min.

[0091] Specifically, on the one hand, in the existing processing logic of the PFC minimum duty cycle, the current actual duty cycle is calculated based on the duty cycle formula D=1-V_in / V_Bus. When the input voltage V_in is high, the calculated actual duty cycle D is very small. If the preset minimum duty cycle D<D_min, the duty cycle will be forcibly set to 0, that is, the PFC is completely turned off, causing waveform oscillation. Due to the excessively high input voltage, the IGBT may even be damaged. That is to say, D_min must be made as small as possible to ensure that the calculated current actual duty cycle D>D_min, so as to ensure that the PFC can be normally turned on.

[0092] On the other hand, if D_min is set smaller, another problem will arise: as the switching time of the IGBT becomes longer after aging, the on-time corresponding to the minimum duty cycle D_min is not sufficient to completely turn off the IGBT, and the collector-emitter voltage spike will burn out the IGBT. It can be seen that this requires that D_min cannot be set too small. At this time, the two requirements are contradictory, and D_min cannot simultaneously be greater than the value required for aging to avoid the burnout phenomenon caused by the IGBT being too late to switch when the value is too small, so as to meet the actual switching requirements of the IGBT, and be less than the required value under the condition of excessively high voltage, thereby preventing the controller from directly turning off the current IGBT due to D>D_min, and avoiding high input voltage waveform oscillation.

[0093] In the present application, through dynamic calculation of K4 and segmented adjustment of D_min, D_min can be small enough to cope with high input voltage (avoid oscillation) and large enough to meet the switching time requirement of the aged IGBT (avoid burnout). In addition, the whole process does not require manual intervention, and the controller automatically adjusts D_min according to the real-time aging state of the IGBT, so as to adapt to the degradation process of the device throughout the life cycle.

[0094] Based on the above description, this application solves the technical contradiction that "D_min needs to be as small as possible (to avoid high input voltage waveform oscillation) but cannot be less than the actual switching time requirement (to avoid IGBT turn-off failure after aging)" by using three-way aging detection and dynamic calculation of the comprehensive aging coefficient K4; by adaptively adjusting the minimum duty cycle, it ensures that the IGBT always works within a safe switching time range, avoiding incomplete turn-off due to excessively small duty cycle and burnout due to aging accumulation, effectively extending the service life of the IGBT.

[0095] also, Figure 1 The system also includes mains power, a rectifier bridge, input voltage detection, bus voltage detection, an isolation driver chip, drive resistors, and gate capacitors. DESAT is a "built-in module" of the isolation driver chip, and its protection circuit is typically integrated on the "output side" of the chip. The mains power refers to the AC power supply entering the device from the power grid; typically, it's 220V / 50Hz single-phase AC (like in a household air conditioner), which is the energy source for the entire system. The rectifier bridge can be a bridge circuit composed of multiple power diodes, its core function being to convert AC power into pulsating DC power. The input voltage detection can be a sampling circuit consisting of a high-resistance resistor voltage divider network and optocoupler isolation sampling, responsible for real-time reading of the instantaneous voltage value before or after the rectifier bridge. Bus voltage detection refers to sampling the voltage on the smooth DC bus section after the rectifier bridge and before the inverter module.

[0096] The adjustment circuit provided in this application embodiment includes: a desaturation detection circuit for outputting a desaturation voltage signal; a gate charge integration circuit for outputting an integrated voltage signal; a temperature detection circuit for outputting a temperature signal; and a controller connected to the desaturation detection circuit, the gate charge integration circuit, and the temperature detection circuit, respectively, configured to: obtain the current on-time of the IGBT switch based on the desaturation voltage signal; obtain the current gate charge correlation quantity of the IGBT switch based on the integrated voltage signal; obtain the current temperature of the IGBT switch based on the temperature signal; determine the comprehensive aging coefficient of the IGBT switch based on the current on-time, the current gate charge correlation quantity, and the current temperature; and adjust the current minimum duty cycle of the PFC circuit based on the comprehensive aging coefficient.

[0097] By employing a three-channel detection system—DESAT detection circuit, gate charge integration circuit, and temperature detection circuit—the comprehensive aging factor of the IGBT is calculated in real time. Based on this comprehensive aging factor, the minimum duty cycle is adaptively and dynamically adjusted to ensure the IGBT always operates within a safe switching time range. This avoids incomplete turn-off due to an excessively small duty cycle and voltage spikes caused by aging accumulation, effectively slowing down the IGBT's degradation rate and extending its lifespan. Simultaneously, by detecting the IGBT's conduction time (reflecting switching speed degradation), gate charge correlation (reflecting gate oxide damage), and temperature (reflecting thermal stress accumulation), the aging state of the IGBT is comprehensively characterized from the perspectives of electrical parameters, physical structure, and thermal stress. This avoids the limitations of single-parameter detection (e.g., measuring only temperature may misjudge high temperature as aging), thereby improving the accuracy and reliability of IGBT aging assessment. Furthermore, dynamically adjusting the minimum duty cycle based on the comprehensive aging factor ensures that the PFC minimum duty cycle always adapts to the aging degree of the IGBT switch, thus ensuring the IGBT always operates within a safe switching time range.

[0098] In addition, see Figure 2 As shown, Figure 2 This application provides a schematic diagram of a PFC circuit, wherein the PFC main circuit includes an inductor 1, an IGBT switch 3, a diode 2, and a bus capacitor 4, as well as the aforementioned... Figure 1 The PFC minimum duty cycle adjustment circuit 5 is shown above; wherein, the PFC minimum duty cycle adjustment circuit is connected to the IGBT switching transistor and is used to adjust the minimum duty cycle of the PFC circuit. For details regarding the PFC minimum duty cycle adjustment circuit 5, please refer to the above description. Figure 1 The relevant description of the illustrated embodiment.

[0099] For details, see Figure 2 As shown, the PFC main circuit includes inductor 1, IGBT switch 3, diode 2, and bus capacitor 4. Their connections are as follows: one end of inductor 1 is connected to the mains power, and the other end is connected to IGBT switch 3 and diode 2. One end of IGBT switch 3 is connected to the inductor, and the other end is grounded; one end of the bus capacitor is connected to diode 2, and the other end is grounded.

[0100] Figure 3 A flowchart illustrating an embodiment of a method for adjusting the minimum duty cycle of a PFC provided in this application includes the following steps: Step 301: Obtain the desaturation voltage signal output by the DESAT detection circuit, and obtain the current conduction time of the IGBT switch based on the desaturation voltage signal.

[0101] The DESAT detection circuit can refer to a desaturation detection circuit, whose input is connected to the collector of the IGBT switch and whose output is connected to a controller to output a desaturation voltage signal; see details. Figure 1 The circuit diagram shown is illustrated. This circuit utilizes the physical characteristic that the collector-emitter voltage Vce drops from a high voltage to the saturation voltage drop when the IGBT is turned on, to detect the on-time.

[0102] The desaturation voltage signal refers to the voltage signal output by the DESAT detection circuit, which is proportional to the collector-emitter voltage Vce of the IGBT (after voltage division by resistors and RC filtering), reflecting whether the IGBT is currently in the off, conduction, or fully conduction state.

[0103] The current conduction time can be obtained from the time difference between the desaturation voltage signal dropping from the first threshold voltage to the second threshold voltage, reflecting the current switching speed of the IGBT and indicating the degree of aging.

[0104] The first threshold voltage can refer to a preset voltage comparison point, such as 5V. When the desaturation voltage signal drops to this value, it indicates that the IGBT has started to conduct. The second threshold voltage can refer to another preset voltage comparison point, such as 2V. When the desaturation voltage signal drops to this value, it indicates that the IGBT is fully turned on.

[0105] In one embodiment, the controller internally presets a first threshold voltage V_th1 and a second threshold voltage V_th2, and continuously samples the desaturation voltage signal output by the DESAT detection circuit. The process is as follows: The controller continuously samples the desaturation voltage signal through the ADC; it determines whether the desaturation voltage signal has dropped to the first threshold voltage V_th1. If so, it records the current time as t1 and marks it as "conduction start". It continues to sample the desaturation voltage signal and determines whether it continues to drop to the second threshold voltage V_th2. If so, it records the current time as t2 and marks it as "conduction end". It calculates the current conduction time t_now = t2 - t1, which is used to calculate the conduction time aging coefficient later.

[0106] For example, suppose the controller presets V_th1 to correspond to Vce≈5V and V_th2 to correspond to Vce≈2V. When the IGBT is newly manufactured, after the controller sends a PWM high level, the desaturation voltage signal drops rapidly; the time difference from V_th1 to V_th2 is 1.0μs; the controller records this value as the reference on-time t_base=1.0μs. After the IGBT has been running for 2 years, the gate oxide layer degrades, causing the gate capacitance to increase and the switching speed to slow down; the controller detects the drop in the desaturation voltage signal again; the time difference from V_th1 to V_th2 has changed to 1.5μs; the controller records t_now=1.5μs for subsequent aging calculations.

[0107] The above steps utilize the existing DESAT protection circuit in the PFC circuit, obtaining the IGBT conduction time without adding additional hardware, resulting in low cost and high reliability. Furthermore, by detecting the time difference between the desaturation voltage signal dropping from the first threshold to the second threshold, the start and end times of the IGBT conduction process are precisely defined, enabling direct measurement of switching speed degradation. The time difference detection is unaffected by voltage amplitude fluctuations and absolute voltage errors, relying only on the threshold comparison time point, resulting in high detection accuracy and good repeatability.

[0108] Step 302: Obtain the integrated voltage signal output by the gate charge integration circuit, and obtain the current gate charge related quantity of the IGBT switch based on the integrated voltage signal.

[0109] The gate charge integrator circuit integrates the gate drive current during the PWM high level to obtain an integrated voltage signal that is proportional to the total gate charge. The integrated voltage signal refers to the voltage signal output by the gate charge integrator circuit, the amplitude of which is proportional to the total gate charge of the IGBT switch, reflecting the magnitude of the total gate charge.

[0110] The current gate charge related quantity refers to the value V_now obtained by the controller based on the integrated voltage signal, which characterizes the total gate charge of the IGBT. This value is latched by the controller on the falling edge of the PWM. The larger V_now is, the greater the total gate charge and the more severe the IGBT aging.

[0111] In one embodiment, during the PWM high level, the controller controls the reset switch to open, and the integrating capacitor integrates the gate drive current; the controller monitors the PWM signal edge in real time; when the PWM falling edge arrives, the controller samples and latches the integrated voltage signal through the ADC to obtain the current gate charge related quantity V_now, which is used to calculate the gate charge aging coefficient later; furthermore, before the start of the next PWM cycle, the controller controls the reset switch to turn on to clear the charge on the integrating capacitor to zero; waits for the next PWM high level to arrive, and repeats the above process.

[0112] For example, suppose the IGBT's integral voltage signal V_base = 0.8V under the reference state; the controller latches this value V_base = 0.8V on the falling edge of the PWM; after the air conditioner has been running for a period of time, the IGBT ages, and the gate oxide layer degrades, causing the gate capacitance to increase. During the same 10μs conduction time, the charging current becomes smoother, and the total gate charge increases; the current integral voltage signal V_now = 1.2V is sampled; the controller latches V_now = 1.2V on the falling edge of the PWM.

[0113] The above steps utilize an integrator to directly measure the total gate charge, accurately reflecting the degradation state of the IGBT gate oxide layer and enabling early detection of microscopic physical changes caused by aging. Integration, latching, and clearing operations are performed in each PWM cycle, achieving real-time tracking of IGBT gate charge changes cycle by cycle, and timely detection of aging trends.

[0114] Step 303: Obtain the temperature signal output by the temperature detection circuit, and obtain the current temperature of the IGBT switching transistor based on the temperature signal.

[0115] The temperature detection circuit outputs a temperature signal. Common components in this temperature monitoring circuit include NTC thermistors, PTC thermistors, or temperature sensor chips. The temperature signal can refer to the electrical signal output by the temperature detection circuit, typically a voltage value or a resistor divider value. The controller samples this signal using an ADC and converts it to obtain the current temperature value T_now. The current temperature is measured in °C. The higher the temperature, the more severe the IGBT aging and the longer the switching time.

[0116] In one embodiment, the controller samples the voltage signal output by the temperature detection circuit via an ADC; the controller converts the sampled voltage into the current temperature value T_now using a lookup table or interpolation method based on the RT characteristic table (resistance-temperature characteristic table, which records the correspondence between resistance value and temperature) of the NTC thermistor; the controller temporarily stores T_now for subsequent calculation of the temperature aging coefficient.

[0117] The aforementioned RT characteristic table can refer to a resistance-temperature characteristic table, used to describe the relationship between the resistance value of a temperature sensor, such as an NTC thermistor, and the temperature. In this embodiment, the controller obtains the voltage value of the voltage divider node through ADC sampling, calculates the current resistance value of the NTC according to the series voltage divider principle, and then looks up the RT characteristic table to obtain the corresponding temperature value, thus obtaining the current temperature T_now.

[0118] For example, assuming the NTC model is 10kΩ@25℃ B=3435, this model of NTC has a resistance of 10kΩ at 25℃ and a voltage divider voltage of approximately 2.5V; at 85℃, the resistance is approximately 1.45kΩ and the voltage divider voltage is approximately 0.63V, which is the sampling voltage of the controller. The controller looks up the RT characteristic table and finds that 0.63V corresponds to 85℃. Therefore, the controller records the current temperature T_now=85℃.

[0119] The temperature detection in the above steps provides thermal stress dimension information for aging assessment. Increased temperature leads to changes in switching time, and temperature correction effectively distinguishes between "slower switching due to high temperature" and "slower switching due to aging." Under high-temperature conditions, the temperature aging coefficient automatically increases, and the overall aging coefficient increases accordingly, causing D_min to increase earlier, reserving a safety margin for temperature-induced changes in switching speed.

[0120] Step 304: Determine the overall aging coefficient of the IGBT switch based on the current conduction time, the current gate charge correlation quantity, and the current temperature.

[0121] In one embodiment, the controller reads a preset reference on-time t_base, a reference gate charge correlation value V_base, and a reference temperature T_base from the memory; the controller calculates the on-time aging coefficient K1 according to the following formula (a): K1=(t_now / t_base)×[1+α×(t_now-t_base)]; Formula (1); Where t_now is the current on-time, t_base is the baseline on-time, and α is the preset correction coefficient.

[0122] Furthermore, the controller calculates the gate charge aging factor K2 according to the following formula (II): K2=(V_now / V_base)×[1+β×(V_now-V_base)]; Formula (II); Where V_now is the current gate charge correlation quantity, V_base is the reference gate charge correlation quantity, and β is the preset correction coefficient.

[0123] Furthermore, the controller calculates the temperature aging coefficient K3 according to the following formula (iii): K3=(T_now / T_base)×[1+γ×(T_now-T_base)]; Formula (3); Where T_now is the current temperature, T_base is the reference temperature, and γ is the preset correction coefficient.

[0124] Furthermore, the controller calculates the overall aging factor K4 according to the following formula (iv): K4 = K1 × K2 × K3; Formula (IV).

[0125] Specifically, the aforementioned comprehensive aging coefficient can include a conduction time aging coefficient K1, which reflects the degree of aging of the IGBT due to the extension of conduction time; a gate charge aging coefficient, which reflects the degree of aging of the IGBT due to the increase of gate charge; and a temperature aging coefficient, which reflects the effect of temperature on the aging degree of the IGBT. This comprehensive aging coefficient can comprehensively reflect the overall aging degree of the IGBT in three dimensions: conduction time, gate charge, and temperature. The correction coefficients α, β, and γ can refer to preset correction coefficients, calibrated according to the characteristics of the IGBT device datasheet, aging test data, or actual operating conditions, and are used to perform nonlinear correction on the three aging coefficients.

[0126] For example, assume the factory baseline values ​​for the PFC are t_base=1.0μs, V_base=0.8V, and T_base=25℃; preset correction coefficients: α=0.1, β=0.2, γ=0.01. Based on the current values ​​obtained from the above steps, t_now=1.5μs, V_now=1.2V, and T_now=85℃; the controller calculates the following values ​​according to the above formulas: K1=(1.5 / 1.0)×[1+0.1×(1.5-1.0)]=1.5×1.05=1.575; K2=(1.2 / 0.8)×[1+0.2×(1.2-0.8)]=1.5×1.08=1.62; K3=(85 / 25)×[1+0.01×(85-25)]=3.4×1.6=5.44. Overall aging coefficient: K4 = 1.575 × 1.62 × 5.44 ≈ 13.87.

[0127] The above steps characterize aging based on three dimensions: conduction time (K1), gate oxide state (K2), and temperature aging coefficient (K3). This comprehensive evaluation avoids misjudgment based on a single dimension.

[0128] Step 305: Adjust the current minimum duty cycle of the PFC circuit according to the overall aging factor.

[0129] Minimum duty cycle (D_min) can refer to the key parameter set in the PFC control strategy. When the current duty cycle calculated by the PFC circuit is less than this value, the controller forces the output to the minimum duty cycle to prevent the system from going out of control due to the duty cycle being too low.

[0130] The preset value range can refer to a set of value ranges that are pre-stored inside the controller to divide the range of values ​​for the comprehensive aging coefficient K4. Each range corresponds to a different minimum duty cycle adjustment ratio.

[0131] The preset magnification may refer to an increase factor in one-to-one correspondence with a preset numerical interval. The larger the comprehensive aging coefficient, the larger the preset magnification. For example, K4 corresponds to a factor of ×1.1 in the interval of 1.05~1.15, and corresponds to a factor of ×1.2 in the interval of 1.15~1.25, etc.

[0132] Adjusting the minimum duty cycle may refer to that the controller increases the current minimum duty cycle of the PFC circuit by adopting the corresponding preset magnification according to the preset numerical interval where the comprehensive aging coefficient K4 is located, so as to realize the transition of D_min from a fixed value to a dynamic adaptive value.

[0133] In one embodiment, the controller determines the preset numerical interval where the comprehensive aging coefficient K4 is located, selects the corresponding preset magnification according to the interval where K4 is located, calculates the adjusted minimum duty cycle according to the preset magnification, and applies the adjusted minimum duty cycle to the PFC control algorithm. When the current duty cycle calculated by the PFC circuit is smaller than the adjusted minimum duty cycle, the adjusted minimum duty cycle is forcibly output to control the IGBT.

[0134] For example, assume that the minimum duty cycle in the initial state is D_min=0.022; according to the current input voltage peak value of 372V and the bus voltage of 380V, the calculated duty cycle is D=0.021. The currently calculated comprehensive aging coefficient K4<1.05. With reference to Table 1 above, it can be seen that the preset magnification=1.0, and the calculated adjusted minimum duty cycle D_min_new=0.022; the currently calculated duty cycle D=0.021<D_min_new=0.022; the system outputs with the currently calculated duty cycle of 0.021 without forced transition, so that the waveform is smooth and free of oscillation. After a period of operation, due to IGBT aging, the calculated K4≥1.35, the preset magnification=1.3, D_min_new=0.022×1.3=0.0286; the currently calculated duty cycle D=0.021<D_min_new=0.0286; the system outputs with D_min_new=0.0286; the on-time is extended to ensure that the aged IGBT can be completely turned off; at the same time, an aging alarm is triggered to prompt maintenance.

[0135] The above steps adopt a segmented adjustment strategy, which appropriately adjusts to ensure efficiency during mild aging and makes large adjustments to ensure safety during severe aging, taking into account both system efficiency and reliability; the minimum duty cycle D_min increases monotonically with K4, and always matches the actual aging degree of the IGBT, which not only avoids excessive protection affecting efficiency, but also ensures a sufficient safety margin.

[0136] As can be seen, the above embodiment, by adaptively adjusting the minimum duty cycle, fundamentally solves the technical contradiction in the background technology that "D_min needs to be as small as possible (to avoid oscillations in the high input voltage waveform) but cannot be less than the actual switching time requirement (to avoid IGBT turn-off failure after aging)". When aging reaches its limit (K4≥1.35), the controller issues an aging alarm while maintaining the maximum protection ratio, providing a clear basis for system maintenance and avoiding sudden failures.

[0137] Figure 4 A flowchart of a method for adjusting the minimum duty cycle of a PFC provided in this application embodiment is shown below. Figure 4 As shown: First, the existing PFC minimum duty cycle design has the following problems: Question 1: When the input voltage is high, such as 1.2 times 220V, that is, when the peak input voltage is 372V, the PFC bus voltage is 380V. The calculated duty cycle D = 1 - 372 / 380 ≈ 0.021. If the minimum duty cycle (D_min) of PFC is > 0.021, the system will force the duty cycle to be set to 0, which can easily cause waveform oscillation or even damage the IGBT.

[0138] Question 2 (IGBT Aging): As the IGBT and peripheral circuitry age, the switching time (t_sw) gradually increases (e.g., from 1μs to 3μs). If D_min remains at its initial value (e.g., 0.022), the IGBT's switching time may be insufficient in low duty cycle scenarios, potentially resulting in incomplete turn-off and collector-emitter voltage spikes, ultimately causing the IGBT to burn out.

[0139] Based on the above two issues, it can be seen that there is a contradiction between them: D_min needs to be as small as possible (to avoid waveform oscillation when the input voltage is high), but it cannot be less than the actual switching time requirement (to avoid the IGBT switching time increasing after aging). Therefore, a method is needed to detect the IGBT switching time and adaptively adjust the minimum duty cycle of PFC.

[0140] This application proposes an adaptive dynamic adjustment method for the minimum duty cycle of PFC. The controller calculates the PFC duty cycle D = 1 - V_in / V_Bus in real time. If the calculated duty cycle < Dmin, the adaptive adjustment method for the minimum duty cycle of PFC is executed. The specific idea is as follows: The original DESAT short-circuit protection circuit, in addition to retaining its original short-circuit protection function, is connected to the controller after adding a resistor voltage divider circuit and RC filter for detecting switching time. When the IGBT is turned on, Vce drops from the high bus voltage (e.g., 48V) to the saturation voltage (approximately 2V). That is, when the Vce voltage drops to Vth1 (threshold voltages 1 and 2) (e.g., 5V), it indicates that the IGBT has started to turn on, and when Vdesat drops to Vth2 (e.g., 2V), it indicates that the IGBT has ended its conduction. The controller uses this characteristic to detect Vce=5V, and the controller determines the start time of conduction. When Vce=2V, the controller determines the end time of conduction. The controller calculates the current IGBT conduction time t_now, compares it with the previously calculated IGBT conduction time t_base, and determines the aging coefficient K1=t_now / t_base×[1+α(t_now-t_base)].

[0141] A new gate charge integration circuit is added to detect the gate charge. When the IGBT ages, the gate oxide layer degrades, leading to an increase in the gate charge Q. By detecting the change in the cumulative gate charge voltage, the degradation of the switching speed is indirectly reflected. The controller sends PWM to the isolated driver chip. At the rising edge of the PWM, the integrator starts integrating the gate current. At the falling edge of the PWM, the charge integration is reset, and the controller records the voltage value V_now at this time. This voltage value is proportional to the amount of charge. The higher the voltage, the greater the charge and the more severe the IGBT aging. It is compared with the voltage value V_base calculated under the same duty cycle in the previous period to determine the aging coefficient K2 = V_now / V_base × [1 + β(V_now - V_base)].

[0142] The higher the IGBT temperature, the more severe the IGBT aging and the longer the switching time. The controller detects the current IGBT temperature T_now and compares it with the IGBT temperature T_base measured under the previous rated operating conditions to determine the aging coefficient K3=T_now / T_base×[1+γ(T_now-T_base)].

[0143] IGBT aging index K4 = K1 × K2 × K3. When K4 is less than 1.05, slight aging is indicated; since a margin was allowed in the early stages, the problem is not significant, and the current minimum duty cycle is maintained. When K4 is between 1.05 and 1.15, the minimum duty cycle increases by 1.1 times. When K4 is between 1.15 and 1.25, the minimum duty cycle increases by 1.2 times. When K4 is between 1.25 and 1.35, the minimum duty cycle increases by 1.3 times. When K4 is greater than 1.35, the minimum duty cycle is maintained at 1.3 times, and an aging alarm is triggered. α, β, and γ are set according to actual conditions.

[0144] The above embodiment comprehensively evaluates the aging status of the IGBT through a three-channel aging detection circuit (DESAT conduction time detection, gate charge integration detection, and temperature detection), calculates the comprehensive aging coefficient K4, and dynamically adjusts D_min based on K4, ensuring that D_min always matches the actual switching time requirements of the IGBT, fundamentally resolving the aforementioned contradiction. The product operation is highly sensitive to simultaneous degradation across multiple dimensions. When all three dimensions show slight aging, the product effect of the three dimensions is far greater than that of a single dimension, triggering protection earlier. Any anomaly in any dimension will be reflected in K4, avoiding the "barrel effect"—that is, when a single dimension is severely aged while other dimensions are normal, K4 can still accurately reflect the overall risk and will not mask extreme anomalies due to averaging.

[0145] Figure 5 A block diagram of a PFC minimum duty cycle adjustment device provided in this application, the device comprising: The conduction time acquisition module 51 is used to acquire the desaturation voltage signal output by the DESAT detection circuit, and to acquire the current conduction time of the IGBT switch based on the desaturation voltage signal.

[0146] The gate charge acquisition module 52 is used to acquire the integrated voltage signal output by the gate charge integration circuit, and to acquire the current gate charge related quantity of the IGBT switch based on the integrated voltage signal.

[0147] The temperature acquisition module 53 is used to acquire the temperature signal output by the temperature detection circuit and to acquire the current temperature of the IGBT switching transistor based on the temperature signal.

[0148] The aging coefficient determination module 54 is used to determine the comprehensive aging coefficient of the IGBT switch based on the current conduction time, the current gate charge correlation quantity, and the current temperature.

[0149] The duty cycle adjustment module 55 is used to adjust the current minimum duty cycle of the PFC circuit according to the comprehensive aging coefficient.

[0150] like Figure 6 As shown, Figure 6 A schematic diagram of an air conditioning device provided in this application embodiment includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114. Memory 113 is used to store computer programs; In one embodiment of this application, when the processor 111 executes a program stored in the memory 113, it implements the PFC minimum duty cycle adjustment method provided in any of the foregoing method embodiments, including: Obtain the desaturation voltage signal output by the DESAT detection circuit, and obtain the current on-time of the IGBT switch based on the desaturation voltage signal; Obtain the integrated voltage signal output by the gate charge integration circuit, and obtain the current gate charge related quantity of the IGBT switch based on the integrated voltage signal; The temperature signal output by the temperature detection circuit is obtained, and the current temperature of the IGBT switch is obtained based on the temperature signal. The overall aging factor of the IGBT switch is determined based on the current conduction time, the current gate charge correlation value, and the current temperature. Based on the comprehensive aging factor, adjust the current minimum duty cycle of the PFC circuit.

[0151] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the PFC minimum duty cycle adjustment method provided in any of the foregoing method embodiments.

[0152] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0154] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0155] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A power factor correction (PFC) minimum duty cycle adjustment circuit, applied to a PFC circuit, wherein the PFC circuit includes an insulated gate bipolar transistor (IGBT) switch, characterized in that, include: The desaturation detection circuit has its input terminal connected to the collector of the IGBT switching transistor and its output terminal connected to the controller, and is used to output a desaturation voltage signal. A gate charge integration circuit, whose input terminal is connected to the gate drive branch of the IGBT switch and whose output terminal is connected to the controller, is used to output an integrated voltage signal. A temperature detection circuit is installed at the IGBT switching transistor, and its output terminal is connected to the controller to output a temperature signal. The controller, connected to the DESAT detection circuit, the gate charge integration circuit, and the temperature detection circuit respectively, is configured as follows: The current on-time of the IGBT switch is obtained based on the desaturation voltage signal; the current gate charge correlation value of the IGBT switch is obtained based on the integral voltage signal; and the current temperature of the IGBT switch is obtained based on the temperature signal. Based on the current on-time, the current gate charge correlation, and the current temperature, determine the overall aging factor of the IGBT switch; and based on the overall aging factor, adjust the current minimum duty cycle of the PFC circuit.

2. The circuit according to claim 1, characterized in that, The DESAT detection circuit also includes a resistor divider circuit and an RC filter circuit. The input terminal of the resistor divider circuit is connected to the collector of the IGBT switch, and the output terminal of the resistor divider circuit is connected to the controller via the RC filter circuit.

3. The circuit according to claim 2, characterized in that, The resistor voltage divider circuit includes a first resistor and a second resistor connected in series between the collector of the IGBT switch and ground; The RC filter circuit includes a third resistor and a first capacitor; the connection node between the first resistor and the second resistor is connected to the input terminal of the controller via the third resistor, one end of the first capacitor is connected to the connection node between the third resistor and the input terminal of the controller, and the other end is grounded.

4. The circuit according to claim 1, characterized in that, The gate charge integration circuit includes: An operational amplifier with its non-inverting input terminal grounded and its inverting input terminal serving as a current input terminal, is used to receive the gate drive current of the IGBT switching transistor. An integrating capacitor is connected between the inverting input and the output of the operational amplifier. The sampling resistor has one end connected to the gate drive branch of the IGBT switch and the other end connected to the inverting input of the operational amplifier. The output of the operational amplifier is connected to the controller as the output of the gate charge integration circuit.

5. The circuit according to claim 4, characterized in that, The controller latches the integral voltage signal on the falling edge of each PWM cycle and clears the charge on the integral capacitor before the start of the next PWM cycle; during the PWM high level, the integral capacitor integrates the gate drive current.

6. The circuit according to claim 4, characterized in that, The amplitude of the integrated voltage signal is proportional to the total gate charge of the IGBT switch, where the total gate charge Q = IG × t, IG is the gate drive current, and t is the duration of the PWM high level.

7. The circuit according to claim 1, characterized in that, The controller obtains the current conduction time based on the time difference between the desaturation voltage signal dropping from the first threshold voltage to the second threshold voltage.

8. The circuit according to claim 1, characterized in that, The controller determines the overall aging coefficient according to the following formula: K1=(t_now / t_base)×[1+α×(t_now-t_base)]; K2=(V_now / V_base)×[1+β×(V_now-V_base)]; K3=(T_now / T_base)×[1+γ×(T_now-T_base)]; K4 = K1 × K2 × K3; Wherein, t_now is the current on-time, and t_base is the preset reference on-time; V_now is the current gate charge correlation quantity, and V_base is the preset reference gate charge correlation quantity; T_now is the current temperature, and T_base is the preset reference temperature; α, β, and γ are preset correction coefficients; and K4 is the comprehensive aging coefficient.

9. The circuit according to claim 1, characterized in that, The controller adjusts the current minimum duty cycle of the PFC circuit based on the comprehensive aging factor, including: The controller increases the current minimum duty cycle of the PFC circuit by a preset multiplier corresponding to the preset value range where the comprehensive aging coefficient is located; wherein, the larger the comprehensive aging coefficient is, the larger the preset multiplier is.

10. A method for adjusting the minimum duty cycle of a PFC, characterized in that, Applied to the circuit according to any one of claims 1-9, the method comprises: Obtain the desaturation voltage signal output by the DESAT detection circuit, and obtain the current on-time of the IGBT switch based on the desaturation voltage signal; Obtain the integrated voltage signal output by the gate charge integration circuit, and obtain the current gate charge related quantity of the IGBT switch based on the integrated voltage signal; The temperature signal output by the temperature detection circuit is obtained, and the current temperature of the IGBT switch is obtained based on the temperature signal. The overall aging factor of the IGBT switch is determined based on the current conduction time, the current gate charge correlation value, and the current temperature. Based on the comprehensive aging factor, adjust the current minimum duty cycle of the PFC circuit.

11. A device for adjusting the minimum duty cycle of a PFC, characterized in that, Applied to the circuit according to any one of claims 1-9, the device comprises: The on-time acquisition module is used to acquire the desaturation voltage signal output by the DESAT detection circuit, and to acquire the current on-time of the IGBT switch based on the desaturation voltage signal. The gate charge acquisition module is used to acquire the integrated voltage signal output by the gate charge integration circuit, and to acquire the current gate charge related quantity of the IGBT switch based on the integrated voltage signal. A temperature acquisition module is used to acquire the temperature signal output by the temperature detection circuit and to acquire the current temperature of the IGBT switching transistor based on the temperature signal. The aging coefficient determination module is used to determine the comprehensive aging coefficient of the IGBT switch based on the current conduction time, the current gate charge correlation quantity, and the current temperature. The duty cycle adjustment module is used to adjust the current minimum duty cycle of the PFC circuit according to the comprehensive aging coefficient.

12. A PFC circuit, characterized in that, include: The PFC main circuit includes inductors, IGBT switching transistors, diodes, and bus capacitors; The PFC minimum duty cycle adjustment circuit according to any one of claims 1-9 is connected to the IGBT switching transistor and is used to adjust the minimum duty cycle of the PFC circuit.

13. An air conditioner, characterized in that, Includes the PFC circuit as described in claim 12.

14. A storage medium, characterized in that, The storage medium stores one or more programs, which can be executed by one or more processors to implement the PFC minimum duty cycle adjustment method of claim 10.

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