Signal duty cycle adjustment circuit, method, modulated signal module and chip

Abstract

The present disclosure relates to the technical field of integrated circuits, and provides a signal duty cycle adjusting circuit, a method, a modulated signal module and a chip, which comprise: a first signal input end configured to receive an original clock signal; a reference delay chain comprising N delay units connected in series, and a delay length of each delay unit being obtained by dividing a first period length of the original clock signal by N; and at least one signal generating circuit component comprising a mirror delay chain configured in mirror to the reference delay chain and a signal synthesizer, the signal synthesizer being configured to synthesize a to-be-adjusted signal at a second signal input end and an output signal of a delay unit in the mirror delay chain, and output a signal with a precisely adjusted duty cycle. The mirror delay chain replicates the precise delay characteristics of the reference delay chain, and the signal synthesizer is configured to perform logical operation, so that the duty cycle is step-adjusted at a picosecond level, and the circuit does not rely on complex digital logic circuits and has low cost.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to signal duty cycle adjustment circuits, methods, modulation signal modules, and chips. Background Technology

[0002] In general-purpose microcontroller unit (MCU) chip design, ordinary pulse-width modulation (PWM) modules are typically used. The adjustment step size of an ordinary PWM module is equal to the system master clock cycle, and the resolution is hard-limited by the clock frequency. In high-frequency applications, the duty cycle granularity is extremely large: after the switching frequency is increased to several MHz, a PWM cycle itself is very short, consisting of only a few clock steps, resulting in very few duty cycle levels and making continuous fine-tuning impossible.

[0003] Sub-nanosecond / picosecond level edge precision PWM modules can achieve extremely small duty cycle steps under high-frequency operating conditions, making up for the problems of ordinary PWM being limited by system clock and insufficient resolution. They are mainly used in the fields of power electronics, motors, radio frequency, and precision analog control.

[0004] Existing high-precision pulse-width modulation (PWM) modules generally adopt digital delay unit modulation schemes, relying on standard digital cells to achieve picosecond-level delays, thereby obtaining high-resolution duty cycle adjustment capabilities.

[0005] However, the delay characteristics of digital delay units are quite sensitive to changes in process, temperature and power supply voltage. They are easily affected by temperature drift and power supply voltage fluctuations, causing the actual delay to deviate from the design nominal value, introducing a large delay error, and directly degrading the modulation accuracy of PWM output.

[0006] To improve the accuracy of digital delay solutions, some high-precision PWM modules have switched to using analog delay units to construct the delay path. However, this architecture still requires large-scale digital logic circuitry to synthesize the final PWM output signal. Furthermore, to compensate for deviations caused by device mismatch and drift in analog components, a software calibration process is typically necessary. This not only incurs significant chip area overhead but also increases firmware configuration steps, raising the overall system complexity. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide a signal duty cycle adjustment circuit, method, modulation signal module and chip, which uses a mirror delay chain in conjunction with a signal synthesizer in a signal generation circuit to finely adjust the duty cycle of the input signal by utilizing the precise delay of the reference delay chain.

[0008] A first aspect of the present disclosure provides a signal duty cycle adjustment circuit, comprising: a first signal input terminal, configured to receive an original clock signal having a clock period duration; a reference delay chain, comprising N cascaded delay units; the input terminal of the first delay unit is connected to the first signal input terminal to input the original clock signal, so as to receive the original clock signal and delay the original clock signal stage by stage through the N delay units; wherein the delay length of each of the delay units is obtained by equally dividing the first period duration of the original clock signal by N; at least one signal generation circuit assembly, comprising: a mirror delay chain, configured in mirror symmetry with the reference delay chain; the N delay units included in the mirror delay chain are each also set with a delay length by a delay adjustment signal; the input terminal of the first delay unit in the mirror delay chain is connected to a second signal input terminal, so as to receive a to-be-adjusted signal having a signal period duration and a first signal duty cycle and delay the to-be-adjusted signal stage by stage through the N delay units; the delay length of each delay unit in the mirror delay chain is obtained by equally dividing the first period duration of the to-be-adjusted signal by N; a signal generation circuit, comprising at least one signal synthesizer, a pair of input terminals of each said signal synthesizer are respectively connected to the second signal input terminal and the output terminal of a stage of delay unit in the mirror delay chain, and the output terminal of the signal synthesizer outputs an adjusted signal; wherein the second signal duty cycle of the adjusted signal is obtained by adjusting the first signal duty cycle using the delay of the output signal of that stage of delay unit.

[0009] In the embodiment of the first aspect, the signal synthesizer is implemented as a logic gate circuit; and / or, the signal synthesizer is implemented as an AND gate or an OR gate, and the AND gate and the OR gate are respectively used for signal duty cycle adjustment in opposite directions.

[0010] In the embodiment of the first aspect, each said signal generation circuit includes k said signal synthesizers, which are respectively connected to the output terminals of k delay units in the mirror delay chain and the second signal input terminal to form k adjusted signal outputs, where 1<k≤N; the signal generation circuit assembly further comprises a multiplexer, which is respectively connected to the output terminals of the k said signal synthesizers to obtain k adjusted signal inputs, and is configured to select and output one of the adjusted signals.

[0011] In the embodiment of the first aspect, the number of the signal generation circuit assemblies is multiple, forming a plurality of adjusted signal outputs for selection.

[0012] In an embodiment of the first aspect, the device further includes: a clock comparator, a pair of input terminals of which are respectively connected to the first signal input terminal and the output terminal of the final stage delay unit of the reference delay chain, and its output terminal is connected to each delay unit in the reference delay chain and the mirror delay chain; the clock comparator and the reference delay chain form a time-locked loop, which is used to output the delay adjustment signal based on comparing the phase difference between the original clock signal and the clock signal output by the final stage delay unit, so as to adjust the delay length with the goal of eliminating the phase difference.

[0013] A second aspect of this disclosure provides a signal duty cycle adjustment method, comprising: providing a delay phase-locked loop, including: a reference delay chain, including: N delayers connected in series; the input terminal of the first delayer is connected to a first signal input terminal to input an original clock signal, to receive the original clock signal and delay it stage by stage through the N delayers; a clock comparator, a pair of its input terminals being respectively connected to the first signal input terminal and the output terminal of the last stage delayer of the reference delay chain, and its output terminal being connected to each delayer in the reference delay chain; the clock comparator is used to compare the phase difference between the original clock signal and the clock signal output by the last stage delayer, and to generate and output a delay adjustment signal to each delayer with the goal of eliminating the phase difference, such that the delay length of each delayer is 1 / N of the clock cycle duration; and providing at least one signal generation circuit component, including: A mirror delay chain is configured mirrorally with the reference delay chain. The input of the first delay unit in the mirror delay chain is connected to a second signal input to receive a signal to be adjusted having a signal period and a first signal duty cycle, and the signal is delayed step-by-step by N delay units. The N delay units in the mirror delay chain are also controlled by the delay adjustment signal so that the delay length of each delay unit is 1 / N of the signal period of the signal to be adjusted. A signal generation circuit includes at least one signal synthesizer. A pair of inputs of each signal synthesizer are respectively connected to the second signal input and the output of a first-stage delay unit in the mirror delay chain. The output of the signal synthesizer outputs the adjusted signal. The second signal duty cycle of the adjusted signal is obtained by delaying the first signal duty cycle by the output signal of the delay unit.

[0014] In a second aspect embodiment, the signal synthesizer is implemented as a logic gate circuit; and / or, the signal synthesizer is implemented as an AND gate or an OR gate, the AND gate and the OR gate being used for signal duty cycle adjustment in opposite directions, respectively.

[0015] In an embodiment of the second aspect, each of the signal generation circuits includes k of the signal synthesizers, configured to respectively synthesize the output signals of k delay units in the mirror delay chain with the signal to be adjusted, so as to form k adjusted signals for output, where 1<k≤N; the signal duty ratio adjustment method further comprises: providing at least one multiplexer, which is configured to select and output one of the k adjusted signals.

[0016] In an embodiment of the second aspect, the number of the signal generation circuit assemblies is multiple, forming a plurality of adjusted signal outputs for selection.

[0017] A third aspect of the present disclosure provides a modulation signal module, comprising the signal duty ratio adjustment circuit according to any one of the first aspect.

[0018] A fourth aspect of the present disclosure provides an integrated circuit chip, comprising the signal duty ratio adjustment circuit according to any one of the first aspect; or comprising the modulation signal module according to the third aspect.

[0019] As described above, the present disclosure relates to the technical field of integrated circuits, and provides a signal duty ratio adjustment circuit, a method, a modulation signal module and a chip, comprising: a first signal input terminal, configured to receive an original clock signal; a reference delay chain, comprising N cascaded delay units, wherein the delay length of each delay unit is obtained by equally dividing the first period duration of the original clock signal by N; at least one signal generation circuit assembly, comprising a mirror delay chain arranged in mirror configuration relative to the reference delay chain and a signal synthesizer, wherein the signal synthesizer synthesizes the signal to be adjusted at the second signal input terminal with the output signal of one stage of delay unit in the mirror delay chain, and outputs a signal with precisely adjusted duty ratio. By replicating the precise delay characteristic of the reference delay chain through the mirror delay chain and cooperating with the logical operation of the signal synthesizer, picosecond-level duty ratio step adjustment is realized, which does not rely on complex digital logic circuits and has low cost. Brief Description of the Drawings

[0020] Figure 1 A schematic structural diagram of a signal duty ratio adjustment circuit in an embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic signal timing waveform diagram of the signal duty ratio adjustment circuit in an embodiment of the present disclosure is shown.

[0022] Figure 3 A schematic circuit structure diagram of a signal duty ratio adjustment circuit in another embodiment of the present disclosure is shown.

[0023] Figure 4 A schematic signal waveform diagram of a signal duty ratio adjustment circuit in another embodiment of the present disclosure is shown.

[0024] Figure 5A schematic diagram of the signal timing waveform of a signal duty cycle adjustment circuit in another embodiment of this disclosure is shown.

[0025] Figure 6 A schematic diagram illustrating the signal duty cycle adjustment process in one embodiment of this disclosure is shown. Detailed Implementation

[0026] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can also be modified or changed according to different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0028] In the description of this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this disclosure, as well as the features of those different embodiments or examples.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0030] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0031] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0032] While the terms first, second, etc., are used in some examples herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, descriptions such as first interface and second interface, etc. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

[0033] The technical terms used herein are used only in reference to specific embodiments and are not intended to limit this disclosure.

[0034] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0035] Sub-nanosecond / picosecond level edge precision PWM modules can achieve extremely small duty cycle steps under high-frequency operating conditions, making up for the problems of ordinary PWM being limited by system clock and insufficient resolution. They are mainly used in the fields of power electronics, motors, radio frequency, and precision analog control.

[0036] Existing high-precision pulse-width modulation (PWM) modules generally adopt digital delay unit modulation schemes, relying on standard digital cells to achieve picosecond-level delays, thereby obtaining high-resolution duty cycle adjustment capabilities.

[0037] However, the delay characteristics of digital delay units are quite sensitive to changes in process, temperature and power supply voltage. They are easily affected by temperature drift and power supply voltage fluctuations, causing the actual delay to deviate from the design nominal value, introducing a large delay error, and directly degrading the modulation accuracy of PWM output.

[0038] To improve the accuracy of digital delay solutions, some high-precision PWM modules have switched to using analog delay units to construct the delay path. However, this architecture still requires large-scale digital logic circuitry to synthesize the final PWM output signal. Furthermore, to compensate for deviations caused by device mismatch and drift in analog components, a software calibration process is typically necessary. This not only incurs significant chip area overhead but also increases firmware configuration steps, raising the overall system complexity.

[0039] Therefore, this embodiment provides a signal duty cycle adjustment circuit that utilizes a reference delay chain that divides the original period of a reference clock signal into equal parts (1 / N) and delays it step-by-step. A mirror delay chain is then set up to mirror the reference delay chain. This allows the mirror delay chain to also delay the input signal to be adjusted by equal parts (1 / N). The duty cycle of the signal to be adjusted is adjusted by synthesizing the signal to be adjusted and the output signal after any stage of delay. The overall circuit implementation is simple and effectively solves the problems in related technologies.

[0040] like Figure 1 The diagram shows a schematic representation of a signal duty cycle adjustment circuit 100 according to an embodiment of this disclosure. The signal duty cycle adjustment circuit 100 includes a first signal input terminal 110, a time-delay phase-locked loop 120, and a signal generation circuit assembly 130. The components and their corresponding relationships are described below with reference to the accompanying drawings.

[0041] The first signal input terminal 110 is used to receive the original clock signal (identified as "TCLK" in the figure). In some embodiments, the original clock signal may be provided by an external crystal oscillator, phase-locked loop (PLL) or other clock source, and has a first cycle duration T.

[0042] The delay phase-locked loop 120 includes a reference delay chain 121 and a clock comparator 122.

[0043] The reference delay chain 121 includes delay units connected in series (represented by labels 1_1, 1_2, ..., 1_N in the figure), where N is an integer greater than or equal to 2. Each delay unit (1_1~1_N) is connected to a power supply to receive the power supply voltage (VDD). The delay units are connected sequentially, with the input terminal of the first delay unit (labeled 1_1) connected to the first signal input terminal 110 to receive the original clock signal "TCLK", which is then delayed stage by stage. Each delay unit (1_1~1_N) outputs the clock signal from its preceding stage after a fixed delay. In some embodiments, the reference delay chain 121 can be implemented as an analog adjustable reference delay chain, where the delay can be set by a delay adjustment signal (e.g., ADJ in the figure). Exemplarily, the reference delay chain 121 can be implemented as a voltage-controlled reference delay chain (VCDL). In a VCDL, the delay units can adjust their charging and discharging current by adjusting the control voltage, thereby adjusting the signal delay. For example, the delay can be implemented as a current-starved inverter composed of an NMOS current mirror and a PMOS current mirror. By adjusting the current in the inverter via ADJ, the charging and discharging time of the inverter with respect to the load capacitance (equivalent to the sum of the parasitic capacitances of the NMOS and PMOS) changes, thereby causing a change in the delay.

[0044] The clock comparator 122 includes a pair of input terminals and an output terminal. Its input terminals are respectively connected to the first signal input terminal and the output terminal of the final stage delay unit in the reference delay chain 121. Its output terminal is connected to each delay unit in the reference delay chain 121 and the mirror delay chain 131. The clock comparator 122 is used to output a delay adjustment signal ADJ to each delay unit based on the phase difference between the original clock signal TCLK and the clock signal TCLK_N output by the final stage delay unit, aiming to eliminate the phase difference. This limits the total delay of the reference delay chain to the first cycle length T of the original clock signal. That is,

[0045] The total delay of the constraint delay unit is precisely equal to one period T of the original clock signal, and the clock signal output by the final stage delay unit is in phase with the original clock signal "TCLK" (i.e., the phase difference is zero). If the delay length deviates from T due to process deviations, temperature changes, or voltage fluctuations, a phase difference will appear between the clock signal output by the final stage delay unit and the original clock signal. This phase difference is detected by the clock comparator 122, and a corresponding delay adjustment signal ADJ (e.g., a voltage-controlled signal) is output to adjust the delay length of each delay unit so that the total delay reaches T. The delay adjustment signal ADJ sets the delay length of each of the delay units (1~N) to achieve the total delay T.

[0046] Since each delay unit in the reference delay chain 121 can evenly divide the original clock signal into N equally spaced clock signals on the time axis, the delay length of each delay unit is obtained by dividing the first cycle duration (T) of the original clock signal by N, i.e., the delay length τ of each delay unit = T / N. After passing through the delay units, the original clock signal and the output terminals of the 1st to N-1th delay units output clock signals with different phases, respectively denoted as "TCLK" (original clock signal, 0th), "TCLK_1" (output of the 1st delay unit, labeled 1), "TCLK_2" (output of the 2nd delay unit, labeled 2)... "TCLK_N-1" (output of the N-1th delay unit, labeled N-1). The delay between two adjacent clock signals is exactly equal to the delay length τ of one delay unit. The "TCLK_N" output by the Nth delay unit is delayed by (N / N)*T=T compared to the original clock signal, which is ideally delayed by a full original period T, and should be in phase with TCLK.

[0047] Furthermore, the DLL structure does not introduce the jitter accumulation effect of the input clock, and the locking process is faster and more stable. Therefore, using the DLL structure to calibrate the reference delay chain can effectively improve the output accuracy and environmental adaptability of the signal duty cycle adjustment circuit 100.

[0048] Since each delay unit in the reference delay chain 121 has a delay length τ (τ = T / N), it generates a delay of τ on the input signal of the previous stage. Therefore, the delay difference between the rising / falling edges of any two clock signals in TCLK~TCLK_N-1 is in units of τ. The value of N can be flexibly set according to the resolution / precision required by the actual application. Taking N=4 as an example, the reference delay chain 121 contains 4 delay units, and 4 clock signals can be obtained from the reference delay chain, namely "TCLK", "TCLK_1", "TCLK_2" and "TCLK_3". The delay length between adjacent clock signals is τ = T / 4. Then, "TCLK_1", "TCLK_2" and "TCLK_3" can achieve delays of τ (i.e., T / 4), (2τ, i.e., T / 2), and 3τ (i.e., 3T / 4) respectively compared to "TCLK".

[0049] like Figure 1As shown, the signal generation circuit assembly 130 includes a mirror delay chain 131 and a signal generation circuit 132. The mirror delay chain 131 is configured as a mirror of the reference delay chain 121. The mirror configuration means that the mirror delay chain 131 completely replicates the reference delay chain 121, and is identical to the reference delay chain 121 in structure, components, delay length, etc. The mirror delay chain 131 contains the same number of delay units as the reference delay chain 121 (labeled as 2_1~2_N in the figure), and the component selection and parameters of the delay units can be identical. Furthermore, the delay length of each delay unit is also set by the same delay adjustment signal (ADJ) to constrain the total delay duration to the signal period of the input signal. Since each delay unit in the mirror delay chain 131 is identical, its delay length is also equal to 1 / N of the signal period of the input signal. For example, each of the delay units (2_1~2_N) in the mirror delay chain 131 is also connected to the output of the clock comparator 122 to receive the delay adjustment signal ADJ.

[0050] Unlike the reference delay chain 121, where the input signal is the original clock signal, the input of the first delay unit in the mirror delay chain 131 is connected to the second signal input unit 150 to receive the signal to be adjusted with a first signal duty cycle and delay it step by step through the delay units. For example, the signal to be adjusted can be a pulse width modulation (PWM) signal, labeled "PWM1" in the figure. It should be noted that the signal type of the signal to be adjusted can be changed as needed, and may also be other modulation signals, not limited to PWM signals.

[0051] Therefore, the signal to be adjusted is delayed stage by stage through the delay units of the mirror delay chain 131, and the delay length of each stage delay unit is 1 / N of the second cycle length of the signal to be adjusted. Let the second cycle length be T1, then the N stages of delay units in the mirror delay chain 131 generate a delay of T1 / N relative to the output signal of the previous stage. Thus, signals with different delay lengths are output from the output terminals of each delay unit, respectively denoted as "PWM_1" (original signal to be adjusted), "PWM_1_1" (output of the first delay unit), "PWM_1_2" (output of the second delay unit) ... "PWM_1_N-1" (output of the (N-1)th delay unit). Among them, the output "PWM_1_N" of the Nth delay should be in phase with "PWM_1", but its accuracy may not be as good as "PWM_1". Therefore, taps can be set at the second signal input terminal and the output terminals of the 1st to N-1st delays to select the output signal, that is, to select the output signal from PWM_1 to PWM_1_N-1.

[0052] The signal generation circuit 132 includes at least one signal synthesizer 133. Figure 1An exemplary signal synthesizer 133 is shown. Each signal synthesizer 133 has a pair of input terminals connected to a second signal input terminal 150 (receiving the signal to be adjusted, PWM1) and an output terminal connected to the output terminal of any stage delay unit in the mirror delay chain 131 (receiving delayed signals PWM1_n, n=1,2,...,N-1). The output terminal of the signal synthesizer outputs the adjusted signal. The second signal duty cycle of the adjusted signal is obtained by adjusting the first signal duty cycle by the delay of the output signal of the stage delay unit.

[0053] In some embodiments, the signal synthesizer 133 is implemented as a logic gate circuit to perform logical operations on the signal values ​​of the signal to be adjusted, PWM_1, and the output signal of the first-stage delay (e.g., PWM_1_n) along the time axis to achieve the synthesis, thereby obtaining the regulated signal. As an example, the signal synthesizer 133 can be implemented as an OR gate or an AND gate to obtain the synthesized regulated signal by performing an OR or AND operation on PWM_1 and the output signal of the delay stage.

[0054] Taking the signal synthesizer 133 as an OR gate as an example, the principle of adjusting the duty cycle through logical operations is explained. Figure 2As shown, within a first signal period T1 of PWM1, there is a high-level duration with a signal value of "1" starting from its rising edge a, and a low-level duration with a signal value of "0" starting from the falling edge at the end of the high-level duration. PWM1_1 has a delay of T1 / N relative to PWM1, so the falling edge b in PWM1_1 is delayed by T1 / N relative to the falling edge of PWM1. Therefore, when the signal values of PWM1 and PWM1_1 are subjected to an OR operation aligned along the time axis, "1" OR "1" is "1", "1" OR "0" is "1", and "0" OR "0" is "0". As a result, PWM1 and PWM1_1 are combined into PWM1_OR1. In this embodiment, the rising edge of PWM1_OR1 is determined by the rising edge a of PWM1. At the time position of the rising edge a of PWM1, a rising edge "1" in PWM1_OR1 is generated through synthesis (obtained by the OR operation of "1" of PWM1 and "0" of PWM1_1), and at the time position of the falling edge b of PWM1, a "1" in PWM1_OR1 is generated through synthesis (obtained by the OR operation of "0" of PWM1 and "1" of PWM1_1), while the falling edge in PWM1_OR1 is determined by the delayed falling edge of PWM1_1, that is, obtained by the OR operation of "0" of PWM1 and "0" of PWM1_1. The rising edge of the next cycle of PWM1_OR1 is also determined by the rising edge a of PWM1 in the next cycle, so the signal period of PWM1_OR1 remains the first period duration T1 unchanged. It can be seen that compared with PWM1, the high-level duration of PWM1_OR1 within the same first period duration is increased by T1 / N, and the low-level duration is correspondingly reduced, realizing the adjustment of increasing the duty cycle.

[0055] In some optional embodiments, k output signals can be selected from PWM1_1 to PWM1_N, and k OR gates (i.e., OR1 to ORk) are provided in one-to-one correspondence as the signal synthesizer, where 1<k≤N. Each of the OR gates is respectively connected to the output terminals of different stages of delayers in the mirror delay chain 131 and the second signal input terminal 150, so as to form adjusted signal outputs with different duty cycle adjustment amounts. The k OR gates are configured to respectively combine the k output signals with the PWM1 to obtain k adjusted signals.

[0056] Reference may be made to Figure 3 which shows a schematic diagram of the circuit structure of the signal duty cycle adjustment circuit in another embodiment of the present disclosure.

[0057] In Figure 3 , taking k=N as an example, that is, N signal synthesizers are provided. In this embodiment, the signal synthesizers are exemplified as OR gates, so N OR gates OR1, OR2, ..., ORN are obtained, correspondingly forming N adjusted signals PWM1OR1, PWM1OR2, ..., PWM1ORN.

[0058] The signal generation circuit assembly 130 further includes a multiplexer 134, which is connected to the output terminals of each of the signal synthesizers (OR1~ORN) to obtain k regulated signal inputs and is configured to select one of the regulated signals for output. Through the selection by the multiplexer 134, a precise duty cycle adjustment result corresponding to any level of delay can be obtained. For example, if k=N, the multiplexer 134 can select one of the N regulated signals PWM1_OR1, PWM1_OR2, ..., PWM1_ORN to output as the target regulated signal PWM1_OUT.

[0059] Furthermore, you can refer to Figure 4 As shown, the display Figure 3 The diagram illustrates the signal waveforms of the duty cycle adjustment circuit in this embodiment. Only representative waveforms are shown here, illustrating the synthesis of PWM1OR1 and PWM1OR2 from PWM1_1 and PWM1_2 respectively, and the selection of PWM1OR1 as the target adjusted signal for the multiplexer output, i.e., PWM1_OUT = PWM1OR1. It can be seen that, due to the delays of T1 / N and 2T1 / N between PWM1_1 and PWM1_2 relative to PWM1, the synthesized PWM1OR1 has a higher high-level duration than PWM1 by τ1 = T1 / N, and the synthesized PWM1OR2 has a higher high-level duration than PWM1 by 2T1 / N. For example, the diagram selects PWM1OR1 with a relatively low duty cycle (duty cycle being the proportion of high-level duration in the cycle duration) for output. Similarly, if N regulated signals are formed, namely PWM1OR1, PWM1OR2, ..., PWM1ORN, their high-level durations are extended by T1 / N, 2T1 / N, ..., T1 respectively compared to PWM1, thus realizing N regulated signals with gradually increasing duty cycles for selection and output.

[0060] Compared to Figure 2 , Figure 4 The falling edge of PWM1OR2 is determined by the falling edge d of PWM1_2. It can be seen that the high level duration of PWM1OR2 is increased by T1 / N compared to PWM1OR1, and the high level duration is increased by 2τ1=2T1 / N compared to PWM1.

[0061] In other embodiments, the signal synthesizer may also be implemented as an AND gate. Compared to an OR gate, the AND gate can be used to adjust the signal duty cycle in the opposite direction. For example, if the PWM1 signal period starts from the rising edge, then as previously analyzed, an OR gate can increase the signal duty cycle of the adjusted signal, while an AND gate can decrease the signal duty cycle of the adjusted signal.

[0062] Specifically, let τ1 = T1 / N. When the signal synthesizer 133 is implemented as an AND gate, since the AND operation results in "0" and "1", "0" and "0", and "1" and "0" all being "0", only "1" and "1" are "1". Therefore, during the first cycle, at the rising edge of PWM1, it will be pulled low to "0" by the delayed output signal (one of PWM1_1~PWM1_N) synthesized with it. The AND operation between the "1" at the rising edge of the output signal and the "1" of PWM1 is "1", meaning the rising edge of the synthesized regulated signal is determined by the rising edge of the delayed output signal. The falling edge of PWM1 is earlier than the falling edge of the output signal and is "0", making the AND operation result for the remaining duration "0". Thus, the falling edge of the synthesized regulated signal is determined by the falling edge of PWM1. As can be seen, the adjusted signal obtained by AND operation has a shorter high-level duration compared to PWM1, and the next rising edge is determined by the rising edge of the next cycle of the delayed output signal. Therefore, by keeping the first cycle duration unchanged, the signal duty cycle is reduced, and the reduction is determined by the respective delay amounts τ1~N*τ1 of PWM1_1~PWM1_N.

[0063] like Figure 5 The diagram shown illustrates the signal timing waveform of a signal duty cycle adjustment circuit in another embodiment of this disclosure.

[0064] In this embodiment, we still take the synthesis of PWM1 with PWM1_1 and PWM1_2 as an example. The signal synthesizer used is an AND gate, which synthesizes the adjusted signals PWM1AND1 and PWM1AND2 respectively. It can be seen that the rising edge of the high-level duration of PWM1AND1 is determined by the rising edge e of PWM1_1, and the falling edge is determined by the falling edge f of PWM1. The high-level duration of PWM1AND1 is reduced compared to PWM1 by a reduction of T1 / N. Similarly, the rising edge of the high-level duration of PWM1AND2 is determined by the rising edge g of PWM1_2, and the falling edge is determined by the falling edge f of PWM1. The high-level duration of PWM1AND2 is further reduced compared to PWM1 by a reduction of 2T1 / N. Moreover, the rising edge of the next signal cycle of PWM1AND1 is determined by the rising edge h of the next signal cycle of PWM1_1, and the rising edge of PWM1AND2 is determined by the rising edge i of the next signal cycle of PWM1_2. This maintains the length of the first signal cycle T1 unchanged, while the shortened high-level duration achieves a gradual decrease in the duty cycle.

[0065] By analogy, in the case where k signal synthesizers are provided, the high-level duration of the adjusted signals output by the k signal synthesizers is reduced by k times the delay amount of the delay length of the correspondingly connected delay units relative to the to-be-adjusted signal PWM_1, that is, τ1_k=k*τ1, 1<k≤N, thereby realizing multi-stage adjustment in the direction of decreasing the duty cycle.

[0066] Conversely, when the signal synthesizer 133 is implemented as an OR gate, the high-level duration output by the OR gate is increased by τ_k relative to the to-be-adjusted signal PWM_1, realizing adjustment in the direction of increasing the duty cycle.

[0067] In some embodiments, the delay adjustment signal ADJ input to the mirror delay chain 131 and the reference delay chain 121 may come from the same signal source. For example, in Figure 1 , the output terminal of the clock comparator 122 is connected to each delay unit in the reference delay chain 121 and the mirror delay chain 131. Since the reference delay chain 121 and the mirror delay chain 131 share the same delay adjustment signal ADJ, the delay length of each delay unit in the mirror delay chain 131 is consistent with the delay length of the corresponding delay unit in the reference delay chain 121, thereby ensuring that the duty cycle adjustment accuracy is not affected by device deviation between the two chains.

[0068] The clock comparator 122 and the reference delay chain 121 constitute a delay-locked loop (DLL), which can output the delay adjustment signal ADJ to the reference delay chain 121 and the mirror delay chain 131 based on comparing the phase difference between the original clock signal TCLK and the clock signal TCLK_N output by the last-stage delay unit, so as to adjust the delay length of each of the delay units with the goal of eliminating the phase difference. After the DLL is locked, the total delay of the delay units in the reference delay chain 121 is exactly equal to a first period duration T of the original clock signal, and the delay length τ=T / N of each delay unit does not drift with changes such as temperature. Since the mirror delay chain 131 shares the same delay adjustment signal ADJ, the mirror delay chain 131 also obtains accurate delay characteristics that do not vary with the environment.

[0069] It is worth mentioning that although in Figure 1 the embodiment, the output terminal of the clock comparator 122 is directly connected to the reference delay chain 121 and the mirror delay chain 131, which is beneficial to ensuring the synchronization of the delay settings between the two. However, in other embodiments, the ADJ signal output from the output terminal of the clock comparator 122 may also be transmitted to the mirror delay chain 131 indirectly or by forming other parallel ADJ signal sources, which is not limited to what is shown in the drawings.

[0070] In some embodiments, the original clock signal may be, for example, a clock signal on the order of hundreds of MHz, and its phase can be subdivided into N stages by N stages of delay units, generating N equal parts of picosecond-level delays that do not vary with drift such as temperature. Further, by mirroring and replicating the reference delay chain 121 through the mirror delay chain 131, and only replacing the input source of the delay chain with a low-precision signal to be adjusted (such as a PWM signal), high-precision signals with different picosecond-level delays can be generated at each tap of the mirror delay chain 131.

[0071] In some embodiments, in terms of an exemplary circuit implementation, the signal duty cycle adjustment circuit may be divided into an analog circuit part and a digital circuit part. The analog circuit part includes the delay-locked loop 120, which accurately locks the output clock signal to one clock cycle duration relative to the input original clock signal, so that the reference delay chain 121 can evenly divide the clock cycle duration into N equal parts, realizing that the delay time of each delay unit does not vary with temperature and voltage drift. In the digital part, the delay chain structure in the analog part is replicated to form the mirror delay chain 131, and by setting the input source of the mirror delay chain 131 as the signal to be adjusted (PWM_1), N PWM signals with different delay phases, that is, PWM1_1 to PWM1_N, are generated. By synthesizing each of the k delayed PWM signals (selected from PWM_1_1 to PWM_1_N) with the pre-delay PWM_1 signal through logical operation of an OR gate or an AND gate, k adjusted signals with picosecond-level duty cycle errors can be generated, where 1<k≤N. Using a k-to-1 multiplexer 134, any path of accurate PWM output signal can be obtained.

[0072] The description is given by taking k=N=4 as an example. The reference delay chain 121 includes 4 delay units, and 4 clock signals "TCLK", "TCLK_1", "TCLK_2", and "TCLK_3" can be obtained from the reference delay chain, and the delay length between adjacent clock signals is τ=T / 4. The mirror delay chain 131 also includes 4 delay units, and 4 output signals "PWM1_1", "PWM1_2", "PWM1_3", and "PWM1_4" can be obtained from the mirror delay chain, and the delay length τ1 between adjacent signals is T1 / 4. Four signal synthesizers configured as AND gates are provided, one input terminal of each AND gate is connected to the second signal input terminal 150 (receiving PWM_1), and the other input terminal is connected to the output terminal of one stage of delay unit in the mirror delay chain 131, so that 4 adjusted signals with duty cycles reduced by τ1 (i.e., T1 / 4), 2τ1 (i.e., T1 / 2), 3τ1 (i.e., 3T1 / 4), and 4τ1 (i.e., T1) can be obtained respectively. Through the multiplexer 134, any one of them can be selected as the final precise PWM output.

[0073] Since each of the N delay units in the mirror delay chain 131 generates a delay τ1 (τ1=T1 / N) on the input signal of the previous stage, the delay difference between any signal in PWM_1 to PWM_1_N-1 and the original signal to be adjusted PWM_1 is in units of τ1. When the signal synthesizer 133 performs logical operations on the signal to be adjusted PWM1 and a certain delay signal PWM1_k, the duty cycle of the output signal will be precisely adjusted by an amount of k*τ1. Therefore, by selecting different delay stages k, duty cycle adjustment with τ1=T1 / N as the smallest step unit can be achieved, and the adjustment accuracy can reach the picosecond level.

[0074] Therefore, the implementation of the signal duty cycle adjustment circuit in this embodiment does not rely on complex digital logic control. It can achieve the PWM function with a very small duty cycle step by simply using a mirror copy delay chain and a simple logic gate, and can be applied to any PWM module with different functions.

[0075] Of course, if only one fixed adjusted signal output is needed, only one signal synthesizer can be set up, and it is not limited to the above k examples.

[0076] In some embodiments, the number of signal generation circuit components 130 can also be multiple. When multiple signal generation circuit components 130 are provided, each component can correspond to different input signals to be adjusted, realizing multi-channel independent duty cycle adjustment. The number k of signal synthesizers 133 in each signal generation circuit component can also be flexibly set; the larger k is, the more duty cycle adjustment levels can be provided. In addition, the specific implementation of the signal synthesizer 133 is not limited to AND gates or OR gates; any logic gate circuit that can realize the logical combination of two input signals and produce the duty cycle adjustment effect is within the protection scope of this disclosure.

[0077] Based on the structure and working principle of the signal duty cycle adjustment circuit described above, this disclosure also provides a signal duty cycle adjustment method.

[0078] like Figure 6 The diagram shown illustrates a flowchart of a signal duty cycle adjustment method according to an embodiment of this disclosure.

[0079] It should be noted that the signal duty cycle adjustment method described above can be applied to previous signal duty cycle adjustment circuits. The principle of the signal duty cycle adjustment method can be referred to in previous signal duty cycle adjustment circuits, and the same technical features will not be repeated in this embodiment.

[0080] exist Figure 6 The process includes:

[0081] Step S601: Provide a time-delayed phase-locked loop.

[0082] wherein, the phase-locked loop comprises: a reference delay chain, comprising N delay units connected in series; the input end of the first delay unit is connected to the first signal input end to input an original clock signal, so as to receive the original clock signal and perform stepwise delay through the N delay units; a clock comparator, a pair of input ends of which are respectively connected to the first signal input end and the output end of the last-stage delay unit of the reference delay chain, and the output end of which is connected to each delay unit in the reference delay chain; the clock comparator is configured to compare the phase difference between the original clock signal and the clock signal output by the last-stage delay unit, and generate and output a delay adjustment signal to each of the delay units with the goal of eliminating the phase difference, so that the delay length of each of the delay units is 1 / N of the duration of the clock period;

[0083] Step S602: providing at least one signal generation circuit assembly.

[0084] wherein, the signal generation circuit assembly comprises: a mirror delay chain, configured in mirror symmetry with the reference delay chain; the input end of the first delay unit in the mirror delay chain is connected to a second signal input end, so as to receive a to-be-adjusted signal having a signal period duration and a first signal duty cycle and perform stepwise delay through the N delay units, and the N delay units included in the mirror delay chain are also controlled by the delay adjustment signal, so that the delay length of each of the delay units is 1 / N of the signal period duration of the to-be-adjusted signal; a signal generation circuit, comprising at least one signal synthesizer, a pair of input ends of each of the signal synthesizers are respectively connected to the second signal input end and the output end of one stage of delay unit in the mirror delay chain, and the output end of the signal synthesizer outputs an adjusted signal; wherein the second signal duty cycle of the adjusted signal is obtained by adjusting the first signal duty cycle through the delay of the output signal of this stage of delay unit.

[0085] In some embodiments, the signal synthesizer is implemented as a logic gate circuit; and / or, the signal synthesizer is implemented as an AND gate or an OR gate, and the AND gate and the OR gate are respectively used for signal duty cycle adjustment in opposite directions.

[0086] In some embodiments, each of the signal generation circuits includes k of the signal synthesizers, configured to respectively synthesize the output signals of k delay units in the mirror delay chain with the to-be-adjusted signal, so as to form and output k adjusted signals, where 1<k≤N; the signal duty cycle adjustment method further comprises: providing at least one multiplexer, configured to selectively output one of the k adjusted signals.

[0087] In some embodiments, the number of the signal generation circuit assemblies is multiple, forming a plurality of adjusted signal outputs for selection.

[0088] In some embodiments, the method further includes: providing a clock comparator connected to the reference delay chain to form a delay phase-locked loop, for outputting the delay adjustment signal to the reference delay chain and the mirror delay chain based on comparing the phase difference between the original clock signal and the clock signal output by the final stage delayer, so as to adjust the delay length of each delayer with the goal of eliminating the phase difference.

[0089] In some embodiments, this disclosure may also provide a modulation signal module, including the signal duty cycle adjustment circuit described in any of the above embodiments. Exemplarily, the modulation signal module may be a PWM module, but it can also be a circuit module of other modulation signal types, and is not limited to PWM.

[0090] This disclosure may also provide an integrated circuit chip in some embodiments, which may include the signal duty cycle adjustment circuit described in any of the above embodiments. Alternatively, the integrated circuit chip may include the modulation signal module. Exemplarily, the integrated circuit chip may include any one of a general-purpose microcontroller (MCU), a digital signal processor (DSP), a system-on-a-chip (SoC), a power controller with an integrated PWM generator, a motor drive chip with an integrated PWM generator, etc.

[0091] In summary, this disclosure relates to the field of integrated circuit technology, providing a signal duty cycle adjustment circuit, method, modulation signal module, and chip, comprising: a first signal input terminal for receiving an original clock signal; a reference delay chain including N delayers connected in series, the delay length of each delayer being obtained by equally dividing the first cycle duration of the original clock signal by N; and at least one signal generation circuit component including a mirror delay chain configured relative to the reference delay chain and a signal synthesizer, wherein the signal synthesizer combines the signal to be adjusted at the second signal input terminal with the output signal of a first-stage delayer in the mirror delay chain to output a signal with precisely adjusted duty cycle. By replicating the precise delay characteristics of the reference delay chain through the mirror delay chain, and in conjunction with the logic operations of the signal synthesizer, picosecond-level duty cycle step adjustment is achieved without relying on complex digital logic circuits, resulting in low cost.

[0092] The above embodiments are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Those skilled in the art can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure, and all such changes, substitutions, and modifications should be included within the scope of protection of this disclosure.

[0093] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0094] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A signal duty cycle adjustment circuit, characterized in that, include: The first signal input terminal is used to receive the original clock signal with a clock cycle duration. A time-delay phase-locked loop (PDL) includes: a reference delay chain, comprising: N delayers connected in series; the input terminal of the first delayer is connected to the first signal input terminal to input the original clock signal, so as to receive the original clock signal and delay it step by step through the N delayers; a clock comparator, whose pair of input terminals are respectively connected to the first signal input terminal and the output terminal of the last delayer in the reference delay chain, and whose output terminal is connected to each delayer in the reference delay chain; the clock comparator is used to compare the phase difference between the original clock signal and the clock signal output by the last delayer, and to generate and output a delay adjustment signal to each delayer with the goal of eliminating the phase difference, so that the delay length of each delayer is 1 / N of the clock period; At least one signal generation circuit component, including: A mirror delay chain is configured mirrorally with the reference delay chain. The input of the first delay unit in the mirror delay chain is connected to a second signal input to receive the signal to be adjusted, which has a signal period and a first signal duty cycle, and delays it step by step through N delay units. The N delay units included in the mirror delay chain are also controlled by the delay adjustment signal so that the delay length of each delay unit is 1 / N of the signal period of the signal to be adjusted. A signal generation circuit includes: at least one signal synthesizer, wherein a pair of input terminals of each signal synthesizer are respectively connected to a second signal input terminal and an output terminal connected to a first-stage delay unit in a mirror delay chain, and the output terminal of the signal synthesizer outputs an adjusted signal; wherein the second signal duty cycle of the adjusted signal is obtained by delaying the first signal duty cycle by the output signal of the delay unit.

2. The signal duty cycle adjustment circuit according to claim 1, characterized in that, The signal synthesizer is implemented as a logic gate circuit; and / or, the signal synthesizer is implemented as an AND gate or an OR gate, the AND gate and the OR gate being used for signal duty cycle adjustment in opposite directions, respectively.

3. The signal duty cycle adjustment circuit according to claim 1, characterized in that, Each of the signal generation circuits includes k signal synthesizers, which are respectively connected to the output terminals of k delay units in the mirror delay chain and the second signal input terminal to form k regulated signal outputs. <k≤N; The signal generation circuit assembly further includes: A multiplexer is connected to the outputs of k signal synthesizers to obtain k regulated signal inputs, and is configured to select one of the regulated signal outputs.

4. The signal duty cycle adjustment circuit according to claim 1, characterized in that, The signal generation circuit components are multiple, forming multiple adjusted signal outputs for selection.

5. A method for adjusting the duty cycle of a signal, characterized in that, include: A time-locked loop (PLL) is provided, comprising: a reference delay chain, including: N delayers connected in series; the input terminal of the first delayer is connected to a first signal input terminal to input an original clock signal, so as to receive the original clock signal and delay it step by step through the N delayers; a clock comparator, whose pair of input terminals are respectively connected to the first signal input terminal and the output terminal of the last delayer in the reference delay chain, and whose output terminal is connected to each delayer in the reference delay chain; the clock comparator is used to compare the phase difference between the original clock signal and the clock signal output by the last delayer, and to generate and output a delay adjustment signal to each delayer with the goal of eliminating the phase difference, so that the delay length of each delayer is 1 / N of the clock period; A signal generation circuit component is provided, comprising: a mirror delay chain configured mirrorly to the reference delay chain; the input terminal of the first delayer in the mirror delay chain is connected to a second signal input terminal to receive an adjustable signal having a signal period duration and a first signal duty cycle and delaying it stepwise through N delayers, and the N delayers included in the mirror delay chain are also controlled by the delay adjustment signal so that the delay length of each delayer is 1 / N of the signal period duration of the signal to be adjusted; a signal generation circuit, comprising: at least one signal synthesizer, a pair of input terminals of each signal synthesizer being respectively connected to the second signal input terminal and connected to the output terminal of a first-stage delayer in the mirror delay chain, the output terminal of the signal synthesizer outputting the adjusted signal; wherein the second signal duty cycle of the adjusted signal is obtained by delaying the first signal duty cycle by the output signal of the delayer at that stage.

6. The signal duty cycle adjustment method according to claim 5, characterized in that, The signal synthesizer is implemented as a logic gate circuit; and / or, the signal synthesizer is implemented as an AND gate or an OR gate, the AND gate and the OR gate being used for signal duty cycle adjustment in opposite directions, respectively.

7. The signal duty cycle adjustment method according to claim 5, characterized in that, Each of the signal generation circuits includes k signal synthesizers, used to synthesize the output signals of the k delayers in the mirror delay chain with the signal to be adjusted, respectively, to form k adjusted signal outputs. <k≤N; The signal duty cycle adjustment method further includes: At least one multiplexer is provided, configured to selectively output one of the k regulated signals.

8. The signal duty cycle adjustment method according to claim 5, characterized in that, The signal generation circuit components are multiple, forming multiple adjusted signal outputs for selection.

9. A modulation signal module, characterized in that, include: The signal duty cycle adjustment circuit as described in any one of claims 1 to 4.

10. An integrated circuit chip, characterized in that, include: The signal duty cycle adjustment circuit as described in any one of claims 1 to 4; or, including the modulation signal module as described in claim 9.

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