An anti-interference gate drive circuit based on current source operating region switching
Patent Information
- Application Number
- CN202611153854.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-31
- Publication Date
- 2026-10-27
AI Technical Summary
[0053]本发明的有益效果：本公开中通过逻辑处理电路101，第一开关S1与第二开关S2状态交换，初始阶段的第十PMOS管210处于饱和区，以恒定的速度对寄生电容Cgs放电，Vd-210开始线性降低。在经历米勒平台后，随着Vd-210被逐渐拉低，当第四NMOS管204也会逐渐关闭。第一电流源201，第三NMOS管203，第四NMOS管204所在支路通过的电流最终趋近于0。Vg-210会直接被硬拉到LSPD_H，那么第十PMOS管210会完全打开，进入线性区后，同样是由于晶体管两端电阻较小，放电电流增大，加速Vd-210下拉到LSPD_L。
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Figure CN122993677A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of gate drive circuit technology, and specifically relates to an anti-interference gate drive circuit based on current source operating area switching. Background Technology
[0002] In the field of power semiconductor gate drive control, the core issues that urgently need to be addressed are mainly concentrated in four aspects: anti-interference capability, efficiency optimization, reliability improvement, and high-frequency adaptability. For example, the common-mode transient anti-interference problem caused by parasitic capacitance: when a MOSFET is switching, the parasitic capacitance Cgd couples the sudden change in drain voltage to the gate, leading to false triggering or gate voltage overshoot. Furthermore, parasitic capacitance can also cause switching losses. For example, GaN devices have switching frequencies at the MHz level, and traditional drive circuits suffer from charging and discharging delays due to parasitic inductance or capacitance, increasing switching losses.
[0003] There are two traditional solutions to the problems caused by parasitic capacitance.
[0004] The first type: Traditional Miller clamping circuits require additional detection and control, increasing cost and complexity.
[0005] The second type: SelVCD technology dynamically adjusts the drive speed through a programmable current source, but requires external control logic;
[0006] The two solutions mentioned above have the drawbacks of requiring additional detection and isolation circuits and incurring significant losses at high frequencies. Summary of the Invention
[0007] In view of the above problems, this invention proposes an anti-interference gate drive circuit based on current source operating region switching. This circuit controls the operating state of the auxiliary transistor through gate voltage, maintains high impedance during the Miller plateau period, blocks coupling paths, eliminates the need for external detection circuits, and directly connects to power supply or ground after the Miller plateau, eliminating tail delay and making it suitable for high-frequency scenarios.
[0008] This application provides an anti-interference gate drive circuit based on current source operating region switching, including:
[0009] Logic processing circuit, pre-drive circuit, current biasing circuit and control module;
[0010] The input terminal of the logic processing circuit is used as the input terminal of the drive circuit to receive the input signal. The logic processing circuit is used to modulate the input signal into a standard control signal. The output terminal of the logic processing circuit is connected to the first input terminal of the pre-drive circuit.
[0011] The second input terminal of the pre-drive circuit is connected to the output terminal of the current bias circuit. The pre-drive circuit is used to generate a drive signal according to the control signal and the power supply signal.
[0012] The current bias circuit is used to generate a standard current source to supply the pre-drive circuit, the control module is used to control the output signal, and the output terminal of the control module serves as the output terminal of the drive circuit.
[0013] Preferably, the pre-drive circuit includes:
[0014] A low-side pre-drive circuit, comprising: a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
[0015] The drain of the third NMOS transistor is connected to the gate, and the drain is connected to a first current source through a first switch. The first current source is connected to a low-side high level.
[0016] The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to a low-side low level.
[0017] The drain of the fifth NMOS transistor is connected to the gate, and the drain is connected to the second current source through the second switch. The second current source is connected to the low-side high level, and the source of the fifth NMOS transistor is connected to the low-side low level.
[0018] Preferably, the low-side pre-drive circuit further includes:
[0019] The sixth NMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor;
[0020] The source of the eighth PMOS transistor is connected to a low-side high level, and the drain of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor.
[0021] The gate and drain of the seventh PMOS transistor are connected, and the drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor.
[0022] The gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the source of the sixth NMOS transistor is connected to the low-side low level.
[0023] Preferably, the low-side pre-drive circuit further includes:
[0024] The ninth PMOS transistor and the tenth NMOS transistor;
[0025] The source of the ninth PMOS transistor is connected to a low-side high level, and the gate of the ninth PMOS transistor is connected to the gate of the seventh PMOS transistor.
[0026] The drain of the ninth PMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate of the tenth NMOS transistor is connected to the gate of the third NMOS transistor.
[0027] A terminal is led out between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor to connect to the gate of the eighth PMOS transistor.
[0028] A terminal is led out between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor to connect to the gate of the fourth NMOS transistor.
[0029] Preferably, the control module includes:
[0030] The first transistor, with its drain serving as the output terminal of the driving circuit.
[0031] The gate of the first transistor is connected to a terminal between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor.
[0032] The source of the first transistor is connected to a low-side low level.
[0033] Preferably, the pre-drive circuit includes:
[0034] A high-side pre-drive circuit, comprising: a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor;
[0035] The drain of the thirteenth NMOS transistor is connected to the gate, and the drain is connected to a third current source through a third switch. The third current source is connected to a high-side high-level circuit.
[0036] The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to a high-side low level.
[0037] The drain of the fifteenth NMOS transistor is connected to the gate, and the drain is connected to the fourth current source through the fourth switch. The fourth current source is connected to the high-side high level, and the source of the fifteenth NMOS transistor is connected to the high-side low level.
[0038] Preferably, the high-side pre-drive circuit further includes:
[0039] The sixteenth NMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor;
[0040] The source of the eighteenth PMOS transistor is connected to a high-side high level, and the drain of the eighteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor.
[0041] The gate and drain of the seventeenth PMOS transistor are connected, and the drain of the seventeenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor.
[0042] The gate of the sixteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor, and the source of the sixteenth NMOS transistor is connected to a high-side low level.
[0043] Preferably, the high-side pre-drive circuit further includes:
[0044] The nineteenth PMOS transistor and the twentieth NMOS transistor;
[0045] The source of the nineteenth PMOS transistor is connected to a high-side high level, and the gate of the nineteenth PMOS transistor is connected to the gate of the seventeenth PMOS transistor.
[0046] The drain of the nineteenth PMOS transistor is connected to the drain of the twentieth NMOS transistor, and the gate of the twentieth NMOS transistor is connected to the gate of the thirteenth NMOS transistor.
[0047] A terminal is led out between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor to connect to the gate of the eighteenth PMOS transistor.
[0048] A terminal is led out between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor to connect to the gate of the fourteenth NMOS transistor.
[0049] Preferably, the control module includes:
[0050] The second transistor, with its drain serving as the output terminal of the drive circuit,
[0051] The gate of the second transistor is connected to a terminal between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor.
[0052] The source of the second transistor is connected to a high-side high-level circuit.
[0053] The beneficial effects of this invention are as follows: In this disclosure, through the logic processing circuit 101, the states of the first switch S1 and the second switch S2 are exchanged. In the initial stage, the tenth PMOS transistor 210 is in the saturation region and discharges the parasitic capacitance Cgs at a constant rate, causing Vd-210 to decrease linearly. After passing through the Miller plateau, as Vd-210 is gradually pulled down, the fourth NMOS transistor 204 will also gradually turn off. The current flowing through the branches containing the first current source 201, the third NMOS transistor 203, and the fourth NMOS transistor 204 eventually approaches 0. Vg-210 will be directly pulled down to LSPD_H, and the tenth PMOS transistor 210 will be fully turned on. After entering the linear region, due to the small resistance at both ends of the transistor, the discharge current increases, accelerating the pull-down of Vd-210 to LSPD_L.
[0054] Therefore, the change of Vd-210 realizes the switching of the working regions of the fourth NMOS transistor 204 and the eighth PMOS transistor 208, and finally realizes the switching of the working regions of the tenth PMOS transistor 210 and the ninth PMOS transistor 209 through the causal chain, thus achieving the dynamic resistance effect, accelerating the tail-end transition, and reducing switching losses. Attached Figure Description
[0055] To more clearly illustrate the implementation of this invention, the operating state of the auxiliary transistor is controlled by the gate voltage, maintaining high impedance during the Miller plateau period, blocking the coupling path, eliminating the need for external detection circuits, and directly connecting to power supply or ground after the Miller plateau, thus eliminating tail delay and making it suitable for high-frequency scenarios.
[0056] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description and the drawings.
[0057] The following is a brief introduction to the accompanying drawings used in the description of the embodiments or prior art, which are examples of technical solutions in the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0058] Figure 1 A schematic diagram of an anti-interference gate drive circuit based on current source operating region switching is shown.
[0059] Figure 2 The following diagram shows the low-side pre-drive circuit topology of an embodiment of this application;
[0060] Figure 3 The topology diagram of the high-side pre-drive circuit according to an embodiment of this application is shown. Detailed Implementation
[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0062] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.
[0063] This application provides an anti-interference gate drive circuit based on current source operating area switching. See [link to relevant documentation]. Figure 1 ,include:
[0064] The logic processing circuit 101, the pre-drive circuit 102, the current bias circuit 103, and the control module 104;
[0065] The input terminal of the logic processing circuit 101 is used as the input terminal of the driving circuit to receive the input signal. The logic processing circuit 101 is used to modulate the input signal into a standard control signal. The output terminal of the logic processing circuit 101 is connected to the first input terminal of the pre-driving circuit.
[0066] The second input terminal of the pre-drive circuit 102 is connected to the output terminal of the current bias circuit 103. The pre-drive circuit 102 is used to generate a drive signal according to the control signal and the power supply signal.
[0067] The current bias circuit 103 is used to generate a standard current source to supply the pre-drive circuit 102, and the control module 104 is used to control the output of the output signal. The output terminal of the control module 104 serves as the output terminal of the drive circuit.
[0068] It should be noted that MOSFET devices are used as the basic components in this application. It is understood that a MOSFET is an insulated-gate bipolar transistor. Figure 2 and Figure 3 In the diagram, NMOS transistor represents an N-type MOS transistor, and PMOS transistor represents a P-type MOS transistor. The first to fourth current sources are... Figure 1 The medium current bias circuit provides the current. Switches one through four are provided by... Figure 1 Controlled by logic processing circuitry.
[0069] Specifically, see Figure 2 The pre-drive circuit 102 includes:
[0070] The low-side pre-drive circuit 200 includes: a third NMOS transistor 203, a fourth NMOS transistor 204, and a fifth NMOS transistor 205;
[0071] The drain of the third NMOS transistor 203 is connected to the gate, and the drain is connected to the first current source 201 through the first switch S1. The first current source 201 is connected to the low-side high level.
[0072] The source of the third NMOS transistor 203 is connected to the drain of the fourth NMOS transistor 204, and the source of the fourth NMOS transistor 204 is connected to a low-side low level.
[0073] The drain of the fifth NMOS transistor 205 is connected to the gate, and the drain is connected to the second current source 202 through the second switch S2. The second current source 202 is connected to the low-side high level, and the source of the fifth NMOS transistor 205 is connected to the low-side low level.
[0074] The low-side pre-drive circuit 200 further includes:
[0075] The sixth NMOS transistor 206, the seventh PMOS transistor 207, and the eighth PMOS transistor 208;
[0076] The source of the eighth PMOS transistor 208 is connected to a low-side high level, and the drain of the eighth PMOS transistor 208 is connected to the source of the seventh PMOS transistor 207.
[0077] The gate and drain of the seventh PMOS transistor 207 are connected, and the drain of the seventh PMOS transistor 207 is connected to the drain of the sixth NMOS transistor 206.
[0078] The gate of the sixth NMOS transistor 206 is connected to the gate of the fifth NMOS transistor 205, and the source of the sixth NMOS transistor 206 is connected to the low-side low level.
[0079] The low-side pre-drive circuit 200 further includes:
[0080] The ninth PMOS transistor 209 and the tenth NMOS transistor 210;
[0081] The source of the ninth PMOS transistor 209 is connected to a low-side high level, and the gate of the ninth PMOS transistor 209 is connected to the gate of the seventh PMOS transistor 207.
[0082] The drain of the ninth PMOS transistor 209 is connected to the drain of the tenth NMOS transistor 210, and the gate of the tenth NMOS transistor 210 is connected to the gate of the third NMOS transistor 203.
[0083] A terminal is led out between the drain of the ninth PMOS transistor 209 and the drain of the tenth NMOS transistor 210 to connect to the gate of the eighth PMOS transistor 208;
[0084] A terminal is led out between the drain of the ninth PMOS transistor 209 and the drain of the tenth NMOS transistor 210 to connect to the gate of the fourth NMOS transistor 204.
[0085] Specifically, see Figure 2 The control module 104 includes:
[0086] The first transistor 104, with its drain serving as the output terminal of the driving circuit,
[0087] The gate of the first transistor 104 is connected to a terminal between the drain of the ninth PMOS transistor 209 and the drain of the tenth NMOS transistor 210.
[0088] The source of the first transistor 104 is connected to a low-side low level.
[0089] The driving principle of the low-side pre-drive circuit in this drive circuit will be explained in detail below.
[0090] Specifically, see Figure 1 and Figure 2 The input IN is a low-side control signal. When the input is high, the logic processing circuit 101 controls the state of the first switch S1 and the second switch S2 connected to the pre-drive circuit 102.
[0091] like Figure 2 As shown, when the logic processing circuit 101 controls the first switch S1 to open and the second switch S2 to close, the branch containing the second switch S2 operates normally. Through the replication of the current mirror, the ninth PMOS transistor 209 turns on. The ninth PMOS transistor 209 begins to operate normally, providing an upward pull-up current to the gate Vd-210 of the first transistor 104, causing Vd-210 to rise. At the same time, the first switch S1 opens, and the current in this branch approaches zero, causing the tenth NMOS transistor 210 to turn off, no longer providing a downward pull-up current to the gate of the first transistor 104.
[0092] According to the working principle of the current mirror, the current provided by the ninth PMOS transistor 209 is a proportional replication of the current from the current source 202. At this time, the ninth PMOS transistor 209 charges the parasitic capacitance Cgs of the first transistor 104 with a constant current. When the charge on the parasitic capacitance Cgs makes Vgs approximately equal to Vth, the first transistor 104 turns on. If the absolute value of Vds of the first transistor 104 is greater than or equal to the absolute value of Vgs minus the absolute value of Vth, the drain voltage of the first transistor 104 decreases. Therefore, the ninth PMOS transistor 209 will no longer charge the parasitic capacitance Cgs of the first transistor 104, and its charging current will be absorbed by the parasitic capacitance Cgd of the first transistor 104. Thus, the gate-source voltage VGS of the first transistor 104 remains constant, resulting in a Miller plateau.
[0093] When the drain voltage of the first transistor 104 decreases, making the absolute value of its Vds less than or equal to the absolute value of Vgs minus the absolute value of Vth, the first transistor 104 exits the saturation region and enters the linear region. The ninth PMOS transistor 209 then charges the parasitic capacitance Cgs of the first transistor 104 again. Figure 2 The first transistor 104 will exit the Miller plateau, and the gate-source voltage VGS will continue to rise.
[0094] When Vd-210 rises to the point where the absolute value of Vds is greater than or equal to the absolute value of Vgs minus the absolute value of Vth, the eighth PMOS transistor 208 enters the saturation region from the linear region. At this time, there are two current sources in the vertical branch containing the eighth PMOS transistor 208, the seventh PMOS transistor 207, and the sixth NMOS transistor 206: one is the eighth PMOS transistor 208, and the other is the sixth NMOS transistor 206. The current provided by the sixth NMOS transistor 206 is much greater than the current provided by the eighth PMOS transistor 208, so this branch can only carry the current provided by the eighth PMOS transistor 208. Ultimately, in order to match the current provided by the eighth PMOS transistor 208, the sixth NMOS transistor 206 retreats from the saturation region to the linear region.
[0095] After the sixth NMOS transistor 206 enters the linear region, its resistance is relatively low. As Vd-210 rises, the eighth PMOS transistor 208 gradually turns off, causing the current in the vertical branch containing the eighth PMOS transistor 208, the seventh PMOS transistor 207, and the sixth NMOS transistor 206 to gradually approach zero. The sixth NMOS transistor 206, being in the linear region, has a very small resistance, and its current eventually approaches zero. Therefore, the voltage across the sixth NMOS transistor 206 becomes very small, causing Vg-207 to be pulled forcefully to LSPD_L. Finally, the gate of the ninth PMOS transistor 209 is pulled to LSPD_L, and the ninth PMOS transistor 209 enters the linear region. Due to its low resistance in the linear region, the charging current increases, accelerating the rise of Vd-210 to LSPD_H.
[0096] As Vd-210 rises, the fourth NMOS transistor 204 fully turns on, preparing for the next pullback. When the input is low, the first switch S1 and the second switch S2 exchange states through the logic processing circuit 101. Similarly, in the initial stage, the tenth NMOS transistor 210 is in the saturation region, discharging the parasitic capacitance Cgs at a constant rate, and Vd-210 begins to decrease linearly. After passing through the Miller plateau, as Vd-210 is gradually pulled low, the fourth NMOS transistor 204 also gradually turns off. The current through the branches containing the first current source 201, the third NMOS transistor 203, and the fourth NMOS transistor 204 eventually approaches 0. Vg-210 will be directly pulled to LSPD_H, and the tenth PMOS transistor 210 will fully turn on. After entering the linear region, again due to the small resistance across the transistor, the discharge current increases, accelerating the pullback of Vd-210 to LSPD_L.
[0097] In the above process, the change of Vd-210 switches the working regions of the fourth NMOS transistor 204 and the eighth PMOS transistor 208, and finally switches the working regions of the tenth PMOS transistor 210 and the ninth PMOS transistor 209 through the causal chain, achieving a dynamic resistance effect, accelerating the tail-end transition, and reducing switching losses.
[0098] It can also prevent transient common-mode interference. If the n-type MOSFET in the same bridge arm is turned off and the p-type MOSFET is turned on, assuming the output terminal will be pulled up quickly, due to the existence of parasitic capacitance Cgd, the gate voltage of the n-type MOSFET will also rise along with the drain voltage, which may cause the n-type MOSFET to turn on falsely.
[0099] However, this circuit can effectively suppress this situation, such as Figure 2 As shown, assuming transistor 104 is currently off, Vd_210 is pulled low to LSPD_L. If there is a large slew rate increase at the output, i.e., at the drain of the first transistor 104, due to the parasitic capacitance Cgd of the first transistor 104, Vd-210 will be pulled high instantaneously. At this time, the tenth PMOS transistor 210 will quickly enter the linear region. The impedance of the tenth PMOS transistor 210 in the linear region is less than that in the saturation region, resulting in a large discharge current, and Vd-210 will be quickly pulled low.
[0100] Without the fourth NMOS transistor 204 and the eighth PMOS transistor 208, when the first transistor 104 is turned off, the tenth PMOS transistor 210 will quickly enter the saturation region when the OUT terminal is momentarily raised. The impedance of the saturation region is relatively large, and the discharge current is usually relatively small. Vd-210 will recover to LSPD_L very slowly, with the recovery time being tens of times slower than the circuit structure provided in this paper. Furthermore, the peak voltage of Vd-210 is more likely to be raised to the turn-on voltage of the first transistor 104, resulting in poor transient immunity and increased switching losses.
[0101] Specifically, the pre-drive circuit 102, see [link to documentation]. Figure 3 ,include:
[0102] The high-side pre-drive circuit 300 includes: a thirteenth NMOS transistor 303, a fourteenth NMOS transistor 304, and a fifteenth NMOS transistor 305;
[0103] The drain of the thirteenth NMOS transistor 303 is connected to the gate, and the drain is connected to the third current source 301 through the third switch S3. The third current source 301 is connected to the high-side high level.
[0104] The source of the thirteenth NMOS transistor 303 is connected to the drain of the fourteenth NMOS transistor 304, and the source of the fourteenth NMOS transistor 304 is connected to a high-side low level.
[0105] The drain of the fifteenth NMOS transistor 305 is connected to the gate, and the drain is connected to the fourth current source 302 through the fourth switch S4. The fourth current source 302 is connected to the high-side high level, and the source of the fifteenth NMOS transistor 305 is connected to the high-side low level.
[0106] Specifically, the high-side pre-drive circuit 300 further includes:
[0107] The sixteenth NMOS transistor 306, the seventeenth PMOS transistor 307, and the eighteenth PMOS transistor 308;
[0108] The source of the eighteenth PMOS transistor 308 is connected to a high-side high level, and the drain of the eighteenth PMOS transistor 308 is connected to the source of the seventeenth PMOS transistor 307.
[0109] The gate and drain of the seventeenth PMOS transistor 307 are connected, and the drain of the seventeenth PMOS transistor 307 is connected to the drain of the sixteenth NMOS transistor 306.
[0110] The gate of the sixteenth NMOS transistor 306 is connected to the gate of the fifteenth NMOS transistor 305, and the source of the sixteenth NMOS transistor 306 is connected to a high-side low level.
[0111] Specifically, the high-side pre-drive circuit 300 further includes:
[0112] The nineteenth PMOS transistor 309 and the twentieth NMOS transistor 310;
[0113] The source of the nineteenth PMOS transistor 309 is connected to a high-side high level, and the gate of the nineteenth PMOS transistor 309 is connected to the gate of the seventeenth PMOS transistor 307.
[0114] The drain of the nineteenth PMOS transistor 309 is connected to the drain of the twentieth NMOS transistor 310, and the gate of the twentieth NMOS transistor 310 is connected to the gate of the thirteenth NMOS transistor 303.
[0115] A terminal is led out between the drain of the nineteenth PMOS transistor 309 and the drain of the twentieth NMOS transistor 310 to connect to the gate of the eighteenth PMOS transistor 308.
[0116] A terminal is led out between the drain of the nineteenth PMOS transistor 309 and the drain of the twentieth NMOS transistor 310 to connect to the gate of the fourteenth NMOS transistor 304.
[0117] Specifically, the control module 104 includes:
[0118] The drain of the second transistor 105 serves as the output terminal of the driving circuit.
[0119] The gate of the second transistor 105 is connected to a terminal between the drain of the nineteenth PMOS transistor 309 and the drain of the twentieth NMOS transistor 310.
[0120] The source of the second transistor 105 is connected to a high-side high-level circuit.
[0121] The driving principle of the high-side pre-drive circuit in this drive circuit will be explained in detail below.
[0122] See Figure 3 The driving circuit structure of this application can also be applied to the high-side pre-drive circuit of a P-type MOSFET. The circuit structure of the high-side pre-drive circuit 300 is the same as that of the low-side pre-drive circuit 200. Its working principle is as follows: If the input IN is high, it is processed by the logic processing circuit 101. The third switch S3 of the high-side pre-drive circuit 300 is closed, and the fourth switch S4 is open. Through the operation of the current mirror, the twentieth PMOS transistor 310 starts to work, pulling Vd-310 low. When Vd-310 is pulled down to a certain threshold, the fourteenth NMOS transistor 304 will gradually turn off. Eventually, Vg-310 will be pulled to HSPD-L, the transistor 310 enters the linear region, accelerating the decrease of Vd-310, and the second transistor 105 turns on.
[0123] Conversely, when the input IN is low, the fourth switch S4 in the high-side pre-drive circuit 300 closes and the third switch S3 opens after processing by the logic processing circuit 101. Subsequently, the nineteenth PMOS transistor 309 starts operating and begins to rise. Similarly, when it rises to a specific threshold, the eighteenth PMOS transistor 308 turns off. Finally, the nineteenth PMOS transistor 309 enters the linear region, accelerates its rise to HSPD-H, and the second transistor 105 turns off.
[0124] The switching of the auxiliary transistor's operating region is directly controlled by the change of the MOSFET gate voltage, forming a chain adjustment of the current mirror branch current, realizing the automatic switching of the current source's operating mode without the need for an external detection circuit; the critical point of the auxiliary transistor's switching operating region is determined by the correlation between the MOSFET gate voltage and its own overdrive voltage, without the need for an additional synchronization signal.
[0125] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. An anti-interference gate drive circuit based on current source operating region switching, characterized in that, include: Logic processing circuit, pre-drive circuit, current biasing circuit and control module; The input terminal of the logic processing circuit is used as the input terminal of the drive circuit to receive the input signal. The logic processing circuit is used to modulate the input signal into a standard control signal. The output terminal of the logic processing circuit is connected to the first input terminal of the pre-drive circuit. The second input terminal of the pre-drive circuit is connected to the output terminal of the current bias circuit. The pre-drive circuit is used to generate a drive signal according to the control signal and the power supply signal. The current bias circuit is used to generate a standard current source to supply the pre-drive circuit, the control module is used to control the output signal, and the output terminal of the control module serves as the output terminal of the drive circuit.
2. The circuit according to claim 1, characterized in that, The pre-drive circuit includes: A low-side pre-drive circuit, comprising: a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The drain of the third NMOS transistor is connected to the gate, and the drain is connected to a first current source through a first switch. The first current source is connected to a low-side high level. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to a low-side low level. The drain of the fifth NMOS transistor is connected to the gate, and the drain is connected to the second current source through the second switch. The second current source is connected to the low-side high level, and the source of the fifth NMOS transistor is connected to the low-side low level.
3. The circuit according to claim 2, characterized in that, The low-side pre-drive circuit also includes: The sixth NMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor; The source of the eighth PMOS transistor is connected to a low-side high level, and the drain of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate and drain of the seventh PMOS transistor are connected, and the drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the source of the sixth NMOS transistor is connected to the low-side low level.
4. The circuit according to claim 3, characterized in that, The low-side pre-drive circuit also includes: The ninth PMOS transistor and the tenth NMOS transistor; The source of the ninth PMOS transistor is connected to a low-side high level, and the gate of the ninth PMOS transistor is connected to the gate of the seventh PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate of the tenth NMOS transistor is connected to the gate of the third NMOS transistor. A terminal is led out between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor to connect to the gate of the eighth PMOS transistor. A terminal is led out between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor to connect to the gate of the fourth NMOS transistor.
5. The circuit according to claim 1, characterized in that, The control module includes: The first transistor, with its drain serving as the output terminal of the driving circuit. The gate of the first transistor is connected to a terminal between the drain of the ninth PMOS transistor and the drain of the tenth NMOS transistor. The source of the first transistor is connected to a low-side low level.
6. The circuit according to claim 1, characterized in that, The pre-drive circuit includes: A high-side pre-drive circuit, comprising: a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor; The drain of the thirteenth NMOS transistor is connected to the gate, and the drain is connected to a third current source through a third switch. The third current source is connected to a high-side high-level circuit. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to a high-side low level. The drain of the fifteenth NMOS transistor is connected to the gate, and the drain is connected to the fourth current source through the fourth switch. The fourth current source is connected to the high-side high level, and the source of the fifteenth NMOS transistor is connected to the high-side low level.
7. The circuit according to claim 6, characterized in that, The high-side pre-drive circuit further includes: The sixteenth NMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor; The source of the eighteenth PMOS transistor is connected to a high-side high level, and the drain of the eighteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor. The gate and drain of the seventeenth PMOS transistor are connected, and the drain of the seventeenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor. The gate of the sixteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor, and the source of the sixteenth NMOS transistor is connected to a high-side low level.
8. The circuit according to claim 7, characterized in that, The high-side pre-drive circuit further includes: The nineteenth PMOS transistor and the twentieth NMOS transistor; The source of the nineteenth PMOS transistor is connected to a high-side high level, and the gate of the nineteenth PMOS transistor is connected to the gate of the seventeenth PMOS transistor. The drain of the nineteenth PMOS transistor is connected to the drain of the twentieth NMOS transistor, and the gate of the twentieth NMOS transistor is connected to the gate of the thirteenth NMOS transistor. A terminal is led out between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor to connect to the gate of the eighteenth PMOS transistor. A terminal is led out between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor to connect to the gate of the fourteenth NMOS transistor.
9. The circuit according to claim 1, characterized in that, The control module includes: The second transistor, with its drain serving as the output terminal of the drive circuit, The gate of the second transistor is connected to a terminal between the drain of the nineteenth PMOS transistor and the drain of the twentieth NMOS transistor. The source of the second transistor is connected to a high-side high-level circuit.