Gate drive circuit and power semiconductor chip

Abstract

The application discloses a gate drive circuit and a power semiconductor chip. The circuit comprises a voltage source module for generating at least two different voltage signals; a drive output network for selectively outputting the voltage signals to the gate according to a control signal to drive the conduction of the power device; a control module for controlling the drive output network to output one voltage signal generated by the voltage source module to the gate within a first preset time period in the conduction stage of the power device to generate a first gate voltage for turning on the power device; and for controlling the drive output network to output another voltage signal generated by the voltage source module to the gate within a second preset time period after the first preset time period ends to generate a second gate voltage for turning on the power device; wherein the second gate voltage is higher than the first gate voltage. The application solves the technical problems of insufficient short-circuit resistance time and difficulty in balancing response speed and reliability of the protection mechanism under the existing driving mode.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a gate drive circuit and a power semiconductor chip. Background Technology

[0002] Wide-bandgap power semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronic systems due to their high breakdown voltage, low on-resistance, and high-speed switching characteristics. However, these devices exhibit extremely high current rise rates during turn-on transients. When faults such as short circuits or bridge arm shoot-through occur, current peaks exceeding the device's tolerance limits can be generated in a very short time, leading to thermal failure due to rapid energy accumulation. In practical applications, the short-circuit withstand time of some devices is less than 1.5 microseconds, or even as low as several hundred nanoseconds, posing a severe challenge to the design of drive protection circuits.

[0003] To drive the aforementioned power devices, conventional gate drive circuits typically use a constant voltage (e.g., 18V) to turn on the devices in order to reduce conduction losses and ensure switching speed.

[0004] However, this fixed-voltage driving method cannot suppress current spikes and current rise rates during the initial turn-on phase. When a short-circuit fault occurs, the I×V energy product accumulated by the device in a very short time quickly exceeds the safety threshold, leading to thermal failure. Due to the extremely narrow short-circuit withstand time window, existing protection mechanisms face a dilemma in setting the response time: if the protection threshold is set too low, it is prone to frequent false triggering due to transient current spikes during normal switching; if it is set too high, the device will have already suffered permanent damage before the protection action. Therefore, how to improve short-circuit withstand capability without excessively increasing system complexity has become a pressing technical problem to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a gate drive circuit and a power semiconductor chip to solve the technical problems of existing gate drive circuits, which use constant voltage turn-on, resulting in excessively high current spikes in power devices during turn-on transients and short-circuit faults, insufficient short-circuit withstand time, and easy false triggering or untimely response of protection mechanisms.

[0006] In a first aspect, this application provides a gate drive circuit for driving silicon carbide power devices and / or gallium nitride power devices, comprising: A voltage source module for generating at least two different voltage signals; A drive output network, the output of which is connected to the gate of the power device, is used to selectively output the voltage signal to the gate according to the control signal, so as to drive the power device to conduct. The control module is used to control the drive output network to output a voltage signal generated by the voltage source module to the gate during the conduction phase of the power device within a first preset time period, so as to generate a first gate voltage that turns on the power device. And for outputting another voltage signal generated by the voltage source module to the gate during a second preset period after the first preset period ends, to generate a second gate voltage that turns on the power device; The second gate voltage is higher than the first gate voltage.

[0007] In a second aspect, this application provides a power semiconductor chip, including a silicon carbide power device or a gallium nitride power device, and a gate-level driving circuit as described in the first aspect above.

[0008] The gate drive circuit and power semiconductor chip provided in this application generate at least two different voltage signals by setting a voltage source module. A control module controls the drive output network to output a lower first gate voltage during a first preset time period of the power device's turn-on phase, and then outputs a higher second gate voltage during a subsequent second preset time period. This time-division switching gate voltage control method effectively suppresses the current rise rate and turn-on transient current spikes by driving the power device with a lower voltage during the initial turn-on phase. This significantly reduces the accumulated I×V energy product of the device in the event of a short circuit or bridge arm shoot-through, extending the short-circuit withstand time window. Switching to a higher voltage after the device enters a stable conduction state ensures lower on-resistance and ideal switching speed, avoiding increased conduction losses. Compared to traditional constant voltage drive schemes, this application suppresses current spikes at the source without relying on additional current detection circuits or complex feedback loops. This alleviates the dilemma of response time setting in protection mechanisms, reduces the risk of false triggering, and improves the reliability and safety of the system.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a gate-level driving circuit provided in an embodiment of this application is shown.

[0012] Figure 2 A schematic diagram of the structure of the drive output network provided in an embodiment of this application is shown.

[0013] Figure 3 This illustration shows another structural diagram of the drive output network provided in an embodiment of this application. Detailed Implementation

[0014] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0016] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0017] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0018] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0019] The gate drive circuit and power semiconductor chip provided in this application are applied in power electronic systems employing silicon carbide (SiC) and / or gallium nitride (GaN) power devices. Typical applications include, but are not limited to, electric vehicle traction inverters, photovoltaic inverters, uninterruptible power supplies (UPS), switching power supplies, and various motor drivers. In these systems, power devices (such as SiC MOSFETs or GaN HEMTs) are typically connected in a half-bridge or full-bridge topology, receiving signals from the drive circuit to perform high-speed switching operations, thereby completing the power conversion task.

[0020] Figure 1 A schematic diagram of a gate-level driver circuit provided in an embodiment of this application is shown, as follows: Figure 1 As shown in the embodiments of this application, the gate drive circuit is used to drive silicon carbide power devices and / or gallium nitride power devices, including a voltage source module, a drive output network, and a control module.

[0021] The voltage source module is used to generate at least two different voltage signals. Optionally, in practical applications, the voltage source module can be a circuit unit capable of outputting two or more voltage amplitudes, such as including a fixed positive voltage source and an adjustable voltage source, or integrating multiple voltage regulator circuits with different voltage outputs. In the embodiments of this application, the voltage source module needs to provide at least a relatively low positive voltage (e.g., 15V) and a relatively high positive voltage (e.g., 18V) to meet the different needs of the power device during the initial turn-on and after stable conduction.

[0022] The output of the drive output network is connected to the gate of the power device, selectively outputting a voltage signal to the gate according to the control signal to drive the power device to conduct. Optionally, the drive output network selects a suitable voltage signal from multiple voltage signals provided by the voltage source module according to the command from the control module, and reliably applies that voltage to the gate of the power device, thereby driving the device to conduct or turn off. The drive output network can be implemented using various circuits, such as a selection circuit composed of multiple switching transistors, or a signal path composed of analog switches and buffers. Regardless of the specific structure, the drive output network should have fast response, low output impedance, and sufficient voltage and current handling capability.

[0023] The control module is used to control the drive output network to output a voltage signal generated by the voltage source module to the gate during a first preset time period during the power device's conduction phase, thereby generating a first gate voltage that turns on the power device; and to control the drive output network to output another voltage signal generated by the voltage source module to the gate during a second preset time period after the first preset time period ends, thereby generating a second gate voltage that turns on the power device. The second gate voltage is higher than the first gate voltage. Optionally, the control module is responsible for implementing a time-sharing voltage regulation strategy during the power device's conduction phase. Specifically, during the first preset time period, the control module commands the drive output network to send a voltage signal output by the voltage source module to the gate, generating a first gate voltage that turns on the power device; after the first preset time period ends, the second preset time period begins, at which point the control module commands the drive output network to switch to outputting another, higher voltage signal, generating a second gate voltage that turns on the power device. The key point here is that the second gate voltage is higher than the first gate voltage.

[0024] The first preset time period refers to the time window from when the power device receives the turn-on command until the turn-on transient ends and the current stabilizes. The length of this time period can be preset according to the specific device model, operating current level, and application scenario, generally covering the stage with the highest current rise rate in the initial turn-on phase, typically 2 to 3 microseconds. The second preset time period is the stable conduction stage after the end of the first preset time period and before the device is turned off by the command. In this embodiment, a lower gate voltage (e.g., 15V) is applied during the first preset time period, and a higher gate voltage (e.g., 18V) is applied during the second preset time period.

[0025] The reason this "low-then-high" voltage switching strategy can solve the problems of existing technologies is that, in the initial turn-on phase of a power device, a lower gate voltage reduces the channel conductance, thereby suppressing the rate of rise (di / dt) of the drain current and the peak current. When a short circuit or bridge arm shoot-through fault occurs, the lower current spike means a smaller I×V energy integral accumulated on the device, thus significantly extending the time required for the device to reach the thermal failure threshold. After the device has passed the turn-on transient and entered a stable conduction state, switching to a higher gate voltage allows the channel to open fully, reducing on-resistance and ensuring that normal conduction losses and switching efficiency are not affected. Compared to traditional constant voltage drive schemes (e.g., always turn-on at 18V), the scheme in this embodiment does not require an external current sensor or complex feedback loop to suppress the current spike in the initial turn-on phase from the source, providing a longer response time window for the protection circuit, while avoiding false triggering problems caused by excessively low protection threshold settings.

[0026] In summary, the gate drive circuit provided in this application, through the coordinated operation of the voltage source module, the drive output network, and the control module, achieves time-division dynamic control of the gate voltage during the conduction phase of the power device. It can effectively solve the technical problems of insufficient short-circuit withstand time and difficulty in balancing response speed and reliability under the existing constant voltage drive method. It has the beneficial effects of suppressing current spikes, extending short-circuit withstand time, reducing false trigger rate, and maintaining low conduction loss.

[0027] In some embodiments, in the gate drive circuit provided in this application, the control module is further configured to control the drive output network to output another voltage signal generated by the voltage source module to the gate during the power device's turn-off phase, thereby generating a gate voltage that turns off the power device. Optionally, in addition to the aforementioned time-sharing voltage regulation during the turn-on phase, the control module is also responsible for the power device's turn-off process. During the turn-off phase, the control module instructs the drive output network to obtain a turn-off voltage signal from the voltage source module and apply it to the gate of the power device, thereby reliably switching the device to the off state. In practical applications, the gate voltage used for turn-off is usually different from the turn-on voltage. For enhancement-mode devices such as SiC MOSFETs or GaNHEMTs, the gate voltage needs to be pulled down below the device's threshold voltage, or even a negative voltage, during turn-off to ensure complete turn-off and avoid accidental turn-on. A common practice is for the voltage source module to additionally provide a zero-volt or negative voltage as the turn-off voltage signal.

[0028] Through the above methods, the gate drive circuit provided in this application embodiment can not only suppress current spikes and extend short-circuit withstand time during the conduction phase, but also provide reliable gate negative voltage or zero voltage drive during the turn-off phase, ensuring that the power device quickly turns off after receiving the turn-off command, avoiding problems such as bridge arm shoot-through or tail current caused by incomplete turn-off. This further improves the integrity of the drive circuit and the reliability of the system.

[0029] In some embodiments, Figure 2 A schematic diagram of the structure of the drive output network provided in an embodiment of this application is shown, as follows: Figure 2 As shown, the drive output network provided in this application embodiment includes a first switch Q1, a second switch Q2, a third switch Q3, a first resistor R1, a second resistor R2, and a third resistor R3.

[0030] The first terminal of the first switch Q1 is connected to the voltage source module, the second terminal of the first switch Q1 is connected to the first terminal of the first resistor R1, and the control terminal of the first switch Q1 is connected to the control module. The first terminal of the second switch Q2 is connected to the first terminal of the second resistor R2, the second terminal of the second switch Q2 is grounded, and the control terminal of the second switch Q2 is connected to the control module. The first terminal of the third switch Q3 is connected to the first terminal of the third resistor R3, the second terminal of the third switch Q3 is grounded, and the control terminal of the third switch Q3 is connected to the control module. The second terminals of the first resistor R1, the second resistor R2, and the third resistor R3 are all connected to the gate of the power device. The control module is used to adjust the voltage division ratio of the first resistor R1, the second resistor R2, and the third resistor R3 by controlling the on / off state of each switch, thereby generating different voltages at the gate of the power device to achieve the multiple gate voltages required for on / off switching.

[0031] Optionally, in this embodiment, a resistor divider network is used in conjunction with a switching transistor to achieve flexible switching of the gate voltage. The voltage source module can be a fixed positive voltage source, which is applied to the first terminal of Q1. Q1, Q2, and Q3 are all controllable switching devices, typically implemented using MOSFETs, and their on / off states are determined by the logic level output by the control module. Since the second terminals of Q2 and Q3 are grounded, when they are on, they will ground the lower terminals of the corresponding resistors, thus forming a voltage divider circuit with R1 for the positive voltage; when they are off, the corresponding resistor branches are equivalent to open circuits and do not participate in the voltage division. By combining the on / off states of Q1, Q2, and Q3, the control module can change the total resistance from the voltage source to the gate and the voltage division ratio. For example, when Q1 and Q2 are on and Q3 is off, the current flows from the voltage source through Q1, R1, and then through R2 and Q2 to ground. R1 and R2 form a series voltage divider network, and the gate voltage is equal to the voltage source voltage multiplied by R2 / (R1+R2) (ignoring the on-resistance of the switching transistor). When Q1 is on and Q2 and Q3 are both off, all ground branches are disconnected, and the gate is directly connected to the voltage source through R1, with the gate voltage approximately equal to the voltage source voltage. When Q1 is off and Q2 and / or Q3 is on, the gate is connected to ground through a resistor, and the gate voltage is pulled down to near 0V, achieving turn-off. If negative voltage turn-off is required, a negative voltage source can be connected to the ground terminal of Q2 or Q3, which is a simple variation of this embodiment. This circuit structure is simple, low-cost, and has a fast switching speed, and can flexibly adapt to the drive voltage requirements of different power devices.

[0032] In some embodiments, such as Figure 2As shown, the control module controls the first and second switching transistors to turn on and the third switching transistor to turn off during a first preset time period, causing the first resistor and the second resistor to form a voltage divider network to generate a first gate voltage that turns on the power device. Optionally, the first preset time period corresponds to the transient process at the initial turn-on stage of the power device, typically lasting 2 to 3 microseconds. During this period, Q1 and Q2 are on, Q3 is off, R1 and R2 form a series voltage divider path, and the gate voltage is set to a low value (e.g., by selecting the resistance ratio of R1 and R2, the gate voltage is set to 15V). The lower gate voltage results in a smaller channel conductance of the power device, thereby effectively suppressing the rise rate of the drain current (di / dt) and the turn-on transient current spike. When a short circuit or bridge arm shoot-through fault occurs, this low-voltage driving method can significantly reduce the I×V energy integral accumulated in the device, extend the short-circuit withstand time, and provide a more sufficient response window for the protection circuit. Meanwhile, since low voltage output can be achieved simply by resistor voltage division, there is no need to add an extra power supply or complex control unit, which has the advantages of simple implementation and high reliability.

[0033] In some embodiments, such as Figure 2 As shown, the control module controls the first switch to turn on and the second and third switches to turn off during a second preset time period to generate a second gate voltage that turns on the power device. Optionally, the second preset time period immediately follows the first preset time period, corresponding to the stage where the power device has passed the turn-on transient and entered a stable conduction state. At this time, Q1 is on while Q2 and Q3 are both off, all grounding branches are disconnected, and the gate voltage is approximately equal to the positive voltage (e.g., 18V) provided by the voltage source module. The higher second gate voltage fully opens the channel of the power device, minimizing the on-resistance, thereby ensuring that the conduction loss under normal operating conditions is at a low level, and the switching speed is not affected by the low voltage drive in the early stage. Through this "low-then-high" time-division control strategy, the embodiments of this application achieve a good balance between suppressing the turn-on transient current spike and maintaining a steady-state low conduction loss, taking into account both safety and efficiency.

[0034] In some embodiments, such as Figure 2As shown, during the turn-off phase, the control module controls the second and / or third switching transistors to conduct, generating a gate voltage that turns off the power device. Optionally, when the power device needs to be turned off, the control module first turns off Q1, cutting off the power supply path from the positive voltage source to the gate; then it turns on Q2 and / or Q3, providing a low-impedance discharge path for the gate charge. The charge stored on the gate capacitor flows to ground through R1, R2 (or R3) and the conducting switching transistors, and the gate voltage drops rapidly to near 0V, reliably turning off the power device. If a faster turn-off speed is required, Q2 and Q3 can be turned on simultaneously. In this case, R2 and R3 are connected in parallel, reducing the equivalent discharge resistance, lowering the discharge time constant, and further improving the turn-off speed. In applications requiring higher turn-off reliability, the second terminals of Q2 and Q3 can be changed from ground to a negative voltage source. When Q2 and / or Q3 are turned on, the gate voltage is pulled down to a negative potential, enabling a more thorough turn-off and avoiding false turn-on caused by Miller capacitance coupling. The turn-off method in this embodiment does not require an additional negative voltage generation circuit; flexible and reliable turn-off control can be achieved using the existing resistor network.

[0035] In some embodiments, Figure 3 This paper illustrates another structural diagram of the drive output network provided in an embodiment of this application, as shown below. Figure 3 As shown, the drive output network provided in this embodiment includes a first buffer B1, a second buffer B2, and a fourth resistor R4. The first power supply terminal of the first buffer B1 is connected to a voltage source module to receive a positive voltage signal generated by the voltage source module, the second power supply terminal is used for ground potential, the input terminal is connected to a control module to receive a first control signal generated by the control module, and the output terminal is connected to the gate of the power device through the fourth resistor R4. The first power supply terminal of the second buffer B2 is used for ground potential, the second power supply terminal is connected to a negative voltage signal generated by the voltage source module, the input terminal is connected to the control module to receive a second control signal generated by the control module, and the output terminal is connected to the source of the power device. The control module is used to generate multiple gate voltages that turn the power device on or off by outputting different logic level combinations as the first control signal and the second control signal.

[0036] Optionally, the first buffer B1 and the second buffer B2 can be drive buffers or dedicated gate driver chips with high input impedance and low output impedance. Their function is to convert the low-voltage logic signal output by the control module into a voltage signal with sufficient driving capability. In this embodiment, the first buffer B1 is configured to output a positive voltage signal when the first control signal is valid, and to output ground potential (0V) when the first control signal is invalid. The second buffer B2 is configured to output a negative voltage signal (e.g., -4V) when the second control signal is valid, and to output ground potential (0V) when the second control signal is invalid. In this way, by controlling the output levels of the two buffers, different voltage differences Vgs can be obtained between the gate and the source. The fourth resistor R4 is used to limit the gate drive current and adjust the switching speed. Its resistance value can be selected according to the input capacitance and switching frequency requirements of the power device.

[0037] Compared to resistor-based voltage dividers, the combination of buffers and logic levels offers faster voltage switching speeds and stronger driving capabilities, while also supporting more flexible level configurations (e.g., independently adjustable positive and negative voltage amplitudes). This makes it suitable for applications with higher requirements for switching speed and driving strength.

[0038] In some embodiments, the control module outputs four logic level combinations, each corresponding to a different gate voltage output state, specifically including: In the first logic level combination, the first control signal is valid and the second control signal is invalid. This causes the first buffer B1 to output a positive voltage signal (e.g., +18V) and the second buffer B2 to output ground potential (0V), generating the first gate voltage that turns on the power device. At this time, the gate voltage of the power device is +18V and the source voltage is 0V, therefore the Vgs of the power device is 18V. This voltage is usually used for the turn-on drive of the power device, but in this example, since there is a higher turn-on voltage (second gate voltage) later, the +18V here can actually be used as a relatively low turn-on voltage, depending on the configuration of the voltage source module.

[0039] In the second logic level combination, both the first and second control signals are active, causing the first buffer B1 to output a positive voltage signal (e.g., +18V) and the second buffer B2 to output a negative voltage signal (e.g., -4V), generating a second gate voltage that turns on the power device. At this time, the gate voltage is +18V, the source voltage is -4V, and the power device's Vgs = 22V. It is evident that by lowering the source potential to a negative voltage, Vgs is increased even if the gate voltage remains unchanged. This method can achieve a higher effective drive voltage without increasing the gate positive voltage amplitude, thereby further reducing the on-resistance. Of course, the parameters of the voltage source module can also be adjusted to output +15V from the first buffer B1 and -4V from the second buffer B2, resulting in different combinations such as Vgs = +19V. This application does not limit this approach.

[0040] The third logic level combination invalidates both the first and second control signals, causing the first buffer B1 to output ground potential (0V) and the second buffer B2 to output ground potential (0V), generating the third gate voltage that turns off the power device. At this time, both the gate and source of the power device are 0V, Vgs = 0V. Zero-voltage turn-off ensures reliable device shutdown and is suitable for most conventional turn-off requirements.

[0041] In the fourth logic level combination, the first control signal is invalid, and the second control signal is valid. This causes the first buffer B1 to output ground potential (0V), and the second buffer B2 to output a negative voltage signal (e.g., -4V), generating a fourth gate voltage that turns off the power device. Since the source is at a negative potential, this helps to extract gate charge more quickly, achieving rapid turn-off. Simultaneously, the negative source potential can effectively suppress false turn-on caused by Miller capacitance coupling, improving the system's anti-interference capability. Therefore, the fourth logic level combination is suitable for scenarios with higher requirements for turn-off speed and anti-interference.

[0042] It is understood that the specific voltage amplitude (positive voltage and negative voltage values) of the above four logic level combinations can be adjusted according to the power device datasheet and application requirements. The +18V, -4V, and other values ​​provided in the embodiments of this application are only examples and do not constitute a limitation on the scope of protection of this application.

[0043] In some embodiments, the control module combines the above four logic level combinations with timing control to achieve complete turn-on and turn-off process management. Specifically, during the power device turn-on phase, the control module outputs the first logic level combination during a first preset time period, making Vgs equal to a positive voltage (e.g., +18V), generating a lower first gate voltage. During a second preset time period after the first preset time period ends, the control module switches to outputting the second logic level combination, making Vgs equal to the difference between the positive and negative voltages (e.g., +22V), generating a higher second gate voltage. This suppresses current spikes with a relatively low Vgs during the initial turn-on phase and reduces conduction losses with a higher Vgs after stable turn-on. During the turn-off phase, the control module can select to output the third or fourth logic level combination as needed. For example, the third logic level combination can be used in normal switching operations to simplify control; in situations requiring rapid turn-off or where strong interference exists, the fourth logic level combination can be used to obtain stronger resistance to false turn-on.

[0044] It is understood that the settings for the first and second preset time periods are consistent with those in the aforementioned embodiments. The first preset time period is typically 2 to 3 microseconds, and the specific value can be calibrated according to the model of the power device, the operating current level, and the actual test results. The control module can use digital logic circuits (such as CPLDs or FPGAs) or a microcontroller in conjunction with a timer to implement the above timing control, or it can use analog timing circuits (such as RC delays). This application embodiment does not limit this.

[0045] This application also provides an embodiment of a power semiconductor chip, including a silicon carbide power device and / or a gallium nitride power device, and a gate-level driving circuit as described in the above embodiments. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip.

[0046] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A gate drive circuit for driving silicon carbide power devices and / or gallium nitride power devices, characterized in that, include: A voltage source module for generating at least two different voltage signals; A drive output network, the output of which is connected to the gate of the power device, is used to selectively output the voltage signal to the gate according to the control signal, so as to drive the power device to conduct. The control module is used to control the drive output network to output a voltage signal generated by the voltage source module to the gate during the conduction phase of the power device within a first preset time period, so as to generate a first gate voltage that turns on the power device. And for outputting another voltage signal generated by the voltage source module to the gate during a second preset period after the first preset period ends, to generate a second gate voltage that turns on the power device; The second gate voltage is higher than the first gate voltage.

2. The gate drive circuit according to claim 1, characterized in that, The control module is also used to control the drive output network to output another voltage signal generated by the voltage source module to the gate during the turn-off phase of the power device, so as to generate a gate voltage that turns off the power device.

3. The gate drive circuit according to any one of claims 1 to 2, characterized in that, The drive output network includes a first switch, a second switch, a third switch, a first resistor, a second resistor, and a third resistor; The first terminal of the first switching transistor is connected to the voltage source module, the second terminal of the first switching transistor is connected to the first terminal of the first resistor, and the control terminal of the first switching transistor is connected to the control module. The first terminal of the second switch is connected to the first terminal of the second resistor, the second terminal of the second switch is grounded, and the control terminal of the second switch is connected to the control module. The first terminal of the third switch is connected to the first terminal of the third resistor, the second terminal of the third switch is grounded, and the control terminal of the third switch is connected to the control module. The second terminals of the first resistor, the second resistor, and the third resistor are all connected to the gate of the power device; The control module is used to adjust the voltage division ratio of the first resistor, the second resistor, and the third resistor by controlling the on and off states of each switching transistor, so as to generate multiple gate voltages that turn the power device on or off.

4. The gate drive circuit according to claim 3, characterized in that, The control module controls the first and second switching transistors to be turned on and the third switching transistor to be turned off during the first preset time period, so that the first resistor and the second resistor form a voltage divider network to generate a first gate voltage that turns on the power device.

5. The gate drive circuit according to claim 3, characterized in that, The control module controls the first switch to be turned on and the second and third switches to be turned off during the second preset time period, so as to generate a second gate voltage that turns on the power device.

6. The gate drive circuit according to claim 3, characterized in that, During the turn-off phase, the control module controls the second switch and / or the third switch to turn on, thereby generating a gate voltage that turns off the power device.

7. The gate drive circuit according to any one of claims 1 to 2, characterized in that, The drive output network includes: a first buffer, a second buffer, and a fourth resistor; The first power supply terminal of the first buffer is connected to the voltage source module to receive a positive voltage signal generated by the voltage source module, the second power supply terminal is used for ground potential, the input terminal is connected to the control module to receive a first control signal generated by the control module, and the output terminal is connected to the gate of the power device through the fourth resistor. The first power supply terminal of the second buffer is used for ground potential, the second power supply terminal is connected to a negative voltage signal generated by the voltage source module, the input terminal is connected to the control module to receive a second control signal generated by the control module, and the output terminal is connected to the source of the power device. The control module is used to generate multiple gate voltages that turn the power device on or off by outputting different combinations of logic levels as the first control signal and the second control signal.

8. The gate drive circuit according to claim 7, characterized in that, The control module outputs four logic level combinations, including: A first logic level combination is used to cause the first buffer to output the positive voltage signal and the second buffer to output the ground potential, so as to generate a first gate voltage that turns on the power device; The second logic level combination is used to cause the first buffer to output the positive voltage signal and the second buffer to output the negative voltage signal, so as to generate a second gate voltage that turns on the power device; A third logic level combination is used to cause the first buffer to output the ground potential and the second buffer to output the ground potential, so as to generate a third gate voltage that turns off the power device; A fourth logic level combination causes the first buffer to output the ground potential and the second buffer to output the negative voltage signal, thereby generating a fourth gate voltage that turns off the power device.

9. The gate drive circuit according to claim 8, characterized in that, The control module outputs the first logic level combination during the first preset time period, outputs the second logic level combination during the second preset time period, and outputs the third logic level combination or the fourth logic level combination during the shutdown phase.

10. A power semiconductor chip, characterized in that, It includes silicon carbide power devices and / or gallium nitride power devices, as well as gate-level drive circuits as described in any one of claims 1 to 9.

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