A power semiconductor switch protection method, circuit and drive system

Abstract

The embodiment of the application discloses a power semiconductor switch protection method, a circuit and a driving system. The power semiconductor switch protection method comprises the following steps: acquiring a power semiconductor switch parameter; determining a boundary constraint condition and an optimization target according to the power semiconductor switch parameter; performing iterative optimization on a preset protection response model based on the boundary constraint condition and the optimization target to obtain a target result, so as to protect and optimize parameters of the power semiconductor switch based on the target result. The power semiconductor switch protection method, the circuit and the driving system provided by the embodiment can guarantee the reliability of the power semiconductor switch protection and improve the efficiency of the power semiconductor switch.

Description

Technical Field

[0001] The present invention relates to power semiconductor switch protection technology, and more particularly to a power semiconductor switch protection method, circuit and driving system. Background Technology

[0002] Power semiconductor switches, such as SiC-based MOSFETs, are core components of inverters (motor controllers) due to their high-frequency and high-efficiency characteristics. To reduce operating energy consumption, the switching speed of power semiconductors is typically increased by reducing the gate drive resistance of the MOSFETs, thereby reducing switching losses and improving efficiency. However, the extremely high switching speed of power semiconductors brings about protection issues. Currently, existing power semiconductor switch protection methods often have limitations that affect the switching speed. Summary of the Invention

[0003] This invention provides a power semiconductor switch protection method, circuit, and driving system to improve power semiconductor switch efficiency while ensuring the reliability of power semiconductor switch protection.

[0004] In a first aspect, embodiments of the present invention provide a power semiconductor switch protection method, comprising: Obtain the parameters of the power semiconductor switch; Based on the power semiconductor switching parameters, determine the boundary constraints and optimization objectives; Based on the boundary constraints and the optimization objective, the preset protection response model is iteratively optimized to obtain the target result, and the power semiconductor switch is protected and its parameters are optimized based on the target result; the step of determining the boundary constraints and optimization objective according to the power semiconductor switch parameters includes: Based on the power semiconductor switch parameters, determine the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike of the power semiconductor switch; The short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike of the power semiconductor switch are used as boundary constraints.

[0005] Optionally, determining the boundary constraints and optimization objectives based on the power semiconductor switching parameters includes: Based on the power semiconductor switch parameters, determine the driving resistance of the power semiconductor switch; Minimizing the driving resistance is the optimization objective.

[0006] Optionally, the iterative optimization of the preset protection response model based on the boundary constraints and the optimization objective to obtain the target result includes: Based on the boundary constraint condition and the optimization objective, iterative optimization is performed on a preset protection response model to obtain an optimized blanking capacitor, a compensation resistor and a driving resistor; the preset protection response model includes the blanking capacitor and the compensation resistor, and the optimization objective includes the driving resistor.

[0007] Optionally, the performing iterative optimization on the preset protection response model based on the boundary constraint condition and the optimization objective to obtain a target result includes: Taking minimizing the driving resistor as the optimization objective based on the boundary constraint condition, iterative optimization is performed on the preset protection response model to obtain the maximum blanking capacitor and the minimum compensation resistor that satisfy t≤T and Vno<Vde; t is the protection response time in the preset protection response model, T is the short-circuit withstand time of the power semiconductor switch, Vno is the maximum allowable false trigger voltage spike of the power semiconductor switch, and Vde is the desaturation protection threshold voltage of the power semiconductor switch.

[0008] Optionally, the preset protection response model is t=(C×Vde) / [Ich+(Vcc-Vde) / Rc], where t is the protection response time, C is the capacitance value of the blanking capacitor, Vde is the desaturation protection threshold voltage, Ich is the current of the constant current source, Vcc is the power supply voltage, and Rc is the resistance value of the compensation resistor.

[0009] Optionally, the power semiconductor switch parameters include at least one of the short-circuit withstand time, the desaturation protection threshold voltage, and the maximum allowable false trigger voltage spike of the power semiconductor switch.

[0010] In a second aspect, embodiments of the present invention provide a power semiconductor switch protection circuit, comprising: a driving unit and a desaturation detection unit, wherein the driving unit includes a driving resistor, and the desaturation detection unit includes a blanking capacitor and a compensation resistor; one end of the power semiconductor switch is electrically connected to one end of the compensation resistor and one end of the blanking capacitor respectively, the other end of the compensation resistor is electrically connected to a power supply, the other end of the blanking capacitor is grounded, the other end of the power semiconductor switch is grounded, and the driving resistor is electrically connected to the control end of the power semiconductor switch; the power semiconductor switch protection method as described in the first aspect is applied to the power semiconductor switch protection circuit.

[0011] Optionally, the desaturation detection unit further comprises at least two diodes connected in series, the anodes of the at least two diodes connected in series are electrically connected to one end of the power semiconductor switch, and the cathodes of the at least two diodes connected in series are electrically connected to one end of the blanking capacitor; the power semiconductor switch protection circuit further comprises a constant current source, and the constant current source is electrically connected to one end of the blanking capacitor.

[0012] Thirdly, embodiments of the present invention provide a driving system, including: a driver, the driver including the power semiconductor switch protection circuit as described in the second aspect.

[0013] The power semiconductor switch protection method, circuit, and driving system provided in this invention include: acquiring power semiconductor switch parameters; determining boundary constraints and optimization objectives based on the power semiconductor switch parameters; iteratively optimizing a preset protection response model based on the boundary constraints and optimization objectives to obtain a target result; and then protecting and optimizing the power semiconductor switch based on the target result. The power semiconductor switch protection method, circuit, and driving system provided in this embodiment iteratively optimize a preset protection response model based on the determined boundary constraints and optimization objectives to obtain a target result, and then protect and optimize the power semiconductor switch based on the target result, thereby achieving synergy between power semiconductor switch protection and parameter optimization. Attached Figure Description

[0014] Figure 1 This is a flowchart of a power semiconductor switch protection method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of a power semiconductor switch protection method provided in Embodiment 2 of the present invention; Figure 3 This is a structural block diagram of a power semiconductor switch protection device provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of a power semiconductor switch protection circuit provided in Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of a terminal provided in Embodiment 4 of the present invention. Detailed Implementation

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0016] Example 1 Figure 1 This is a flowchart of a power semiconductor switch protection method provided in Embodiment 1 of the present invention. This embodiment can be applied to the protection of power semiconductor switches, etc. The detection method can be executed by a power semiconductor switch protection device, which can be integrated into an electronic device such as a computer. The device can be implemented in the form of software and / or hardware. The method specifically includes the following steps: Step 110: Obtain the power semiconductor switch parameters.

[0017] The power semiconductor switch parameters include at least one of the following: short-circuit withstand time, desaturation protection threshold voltage, maximum permissible false trigger voltage spike, transconductance, power semiconductor switch charge, and loop stray inductance. In one embodiment, the power semiconductor switch parameters include the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike.

[0018] Step 120: Determine the boundary constraints and optimization objectives based on the power semiconductor switch parameters.

[0019] In one implementation, the boundary constraints include short-circuit withstand time, desaturation protection threshold voltage of the power semiconductor switch, and maximum permissible false trigger voltage spike of the power semiconductor switch, with the optimization objective being to minimize the drive resistance of the power semiconductor switch.

[0020] Step 130: Based on the boundary constraints and optimization objectives, iteratively optimize the preset protection response model to obtain the target result, and then use the target result to protect and optimize the parameters of the power semiconductor switch.

[0021] In one implementation, a preset protection response model is iteratively optimized based on boundary constraints and an optimization objective to obtain optimized blanking capacitors, compensation resistors, and drive resistors. The preset protection response model includes blanking capacitors and compensation resistors, while the optimization objective includes drive resistors. Based on the optimized blanking capacitors, compensation resistors, and drive resistors, the power semiconductor switch is protected.

[0022] It should be noted that the values ​​of each parameter in this embodiment can be determined according to the actual detection requirements, and are not limited here.

[0023] The power semiconductor switch protection method provided in this embodiment includes: acquiring power semiconductor switch parameters; determining boundary constraints and optimization objectives based on the power semiconductor switch parameters; iteratively optimizing a preset protection response model based on the boundary constraints and optimization objectives to obtain the target result; and then protecting and optimizing the power semiconductor switch based on the target result. The power semiconductor switch protection method provided in this embodiment, by iteratively optimizing a preset protection response model based on the determined boundary constraints and optimization objectives to obtain the target result, and then protecting and optimizing the power semiconductor switch based on the target result, achieves synergy between power semiconductor switch protection and parameter optimization, improving the efficiency of the power semiconductor switch while ensuring the reliability of the power semiconductor switch protection.

[0024] Example 2 Figure 2This is a flowchart of a power semiconductor switch protection method provided in Embodiment 2 of the present invention. This embodiment can be applied to the protection of power semiconductor switches, etc. The detection method can be executed by a power semiconductor switch protection device, which can be integrated into an electronic device such as a computer. The device can be implemented in the form of software and / or hardware. The method specifically includes the following steps: Step 210: Obtain the power semiconductor switch parameters.

[0025] The power semiconductor switch parameters include at least one of the following: short-circuit withstand time, desaturation protection threshold voltage, maximum permissible false trigger voltage spike, transconductance, power semiconductor switch charge, and loop stray inductance. In one embodiment, the power semiconductor switch parameters include the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike.

[0026] Step 220: Based on the power semiconductor switch parameters, determine the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike of the power semiconductor switch.

[0027] Among them, the power semiconductor switch parameters include the specific values ​​corresponding to the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike of the power semiconductor switch.

[0028] Step 230: Use the short-circuit withstand time, desaturation protection threshold voltage, and maximum permissible false trigger voltage spike of the power semiconductor switch as boundary constraints. Step 240: Determine the drive resistance of the power semiconductor switch based on its parameters.

[0029] Among them, the power semiconductor switch parameters include the driving resistance of the power semiconductor switch.

[0030] Step 250: Minimize the driving resistance as the optimization objective.

[0031] Specifically, maximizing dv / dt, i.e., minimizing the drive resistance Rg, is the optimization objective, where dv / dt is the rate of change of the turn-off voltage of the power semiconductor switch. In one embodiment, the power semiconductor switch parameters include transconductance Vds and stray inductance Ls, dv / dt = Ls × di / dt, where di / dt is the rate of change of the turn-off current of the power semiconductor switch, di / dt = f(Rg, Vds). The smaller Rg is, the higher di / dt is, and the higher dv / dt is, the higher the efficiency of the power semiconductor switch.

[0032] Step 260: Based on boundary constraints and optimization objectives, iteratively optimize the preset protection response model to obtain the target result. Then, based on the target result, perform protection and parameter optimization on the power semiconductor switch, specifically including: Based on the boundary constraint condition in step 230 and the optimization objective in step 250 described above, iterative optimization is performed on a preset protection response model to obtain the maximum blanking capacitor and the minimum compensation resistor that satisfy t≤T and Vno<Vde; wherein t is the protection response time in the preset protection response model, T is the short-circuit withstand time of the power semiconductor switch, Vno is the maximum allowable false trigger voltage spike of the power semiconductor switch, and Vde is the desaturation protection threshold voltage of the power semiconductor switch.

[0033] In one embodiment, the preset protection response model is t=(C×Vde) / [Ich+(Vcc-Vde) / Rc], where t is the protection response time, C is the capacitance value of the blanking capacitor, Vde is the desaturation protection threshold voltage, Ich is the current of the constant current source, Vcc is the power supply voltage, and Rc is the resistance value of the compensation resistor. Based on the preset protection response model described above, the maximum blanking capacitor and the minimum compensation resistor that satisfy t≤T and Vno<Vde are obtained, so as to protect the power semiconductor switch.

[0034] For example, T is 2.0 μs, with a 0.5 μs margin reserved, t≤1.5 μs, and Vde is 6.5 V. At the start of optimization, that is, at the start of iterative optimization, the driving resistor Rg takes the minimum allowable value such as 2 Ω, the theoretical power semiconductor switch speed dv / dt under this Rg is calculated to be, for example, 80 V / ns, and the required blanking capacitor such as 470 pF is derived inversely according to Vno<Vde in the boundary constraint condition, for example, Vno<2 V. Substituting 470 pF into the above formula for t, the compensation resistor required to satisfy t≤1.5 μs is calculated to be, for example, 5.6 kΩ. If the calculated compensation resistor is within a reasonable range (non-negative and power consumption is acceptable), then the driving resistor Rg of 2 Ω, the blanking capacitor of 470 pF, and the compensation resistor of 5.6 kΩ are the optimal solution. If there is no solution for the compensation resistor Rc, the driving resistor Rc can be increased (to reduce dv / dt) to re-perform iteration, so as to obtain the optimal solution.

[0035] It should be noted that the values of each parameter in this embodiment can be specifically determined according to actual detection requirements, and are not limited herein.

[0036] The power semiconductor switch protection method provided in this embodiment includes: acquiring power semiconductor switch parameters; determining the short-circuit withstand time, desaturation protection threshold voltage, and maximum allowable false trigger voltage spike of the power semiconductor switch based on the power semiconductor switch parameters; using the short-circuit withstand time, desaturation protection threshold voltage, and maximum allowable false trigger voltage spike of the power semiconductor switch as boundary constraints; determining the driving resistance of the power semiconductor switch based on the power semiconductor switch parameters; minimizing the driving resistance as the optimization objective; iteratively optimizing a preset protection response model based on the boundary constraints and the optimization objective to obtain the target result, and then protecting and optimizing the power semiconductor switch based on the target result. The power semiconductor switch protection method provided in this embodiment uses minimizing the driving resistance as the optimization objective, iteratively optimizes a preset protection response model based on the boundary constraints and the optimization objective to obtain the target result, and then protects and optimizes the power semiconductor switch based on the target result, achieving synergy between power semiconductor switch protection and parameter optimization. This improves the efficiency of the power semiconductor switch while ensuring the reliability of the power semiconductor switch protection; furthermore, minimizing the driving resistance while ensuring safety reduces power semiconductor switch losses and improves power semiconductor switch efficiency.

[0037] Example 3 Figure 3 This is a power semiconductor switch protection device provided in Embodiment 3 of the present invention. The power semiconductor switch protection device can be integrated into electronic devices such as computers. (Reference) Figure 3 The power semiconductor switch protection device includes: a parameter acquisition module 310, a condition determination module 320, and a power semiconductor switch protection module 330; wherein, the parameter acquisition module 310 is used to acquire power semiconductor switch parameters; the condition determination module 320 is used to determine boundary constraints and optimization objectives based on the power semiconductor switch parameters; and the power semiconductor switch protection module 330 is used to iteratively optimize a preset protection response model based on the boundary constraints and optimization objectives to obtain the target result, and to protect and optimize the power semiconductor switch based on the target result.

[0038] Based on the above implementation, the condition determination module 320 includes: a first unit and a second unit; wherein, the first unit is used to determine the short-circuit withstand time, desaturation protection threshold voltage and maximum permissible false trigger voltage spike of the power semiconductor switch according to the power semiconductor switch parameters; the second unit is used to use the short-circuit withstand time, desaturation protection threshold voltage and maximum permissible false trigger voltage spike of the power semiconductor switch as boundary constraint conditions.

[0039] In one embodiment, the condition determination module 320 includes: a resistance determination unit and a target determination unit; wherein the resistance determination unit is configured to determine the driving resistance of the power semiconductor switch according to parameters of the power semiconductor switch; the target determination unit is configured to take minimizing the driving resistance as an optimization target.

[0040] In one embodiment, the power semiconductor switch protection module 330 is specifically configured to perform iterative optimization on a preset protection response model based on boundary constraint conditions and the optimization target, so as to obtain an optimized blanking capacitor, compensation resistor and driving resistance; the preset protection response model includes the blanking capacitor and the compensation resistor, and the optimization target includes the driving resistance.

[0041] In one embodiment, the power semiconductor switch protection module 330 is specifically configured to perform iterative optimization on the preset protection response model based on boundary constraint conditions and with minimizing the driving resistance as the optimization target, so as to obtain the maximum blanking capacitor and the minimum compensation resistor that satisfy t≤T and Vno<Vde; t is the protection response time in the preset protection response model, T is the short-circuit withstand time of the power semiconductor switch, Vno is the maximum allowable false trigger voltage spike of the power semiconductor switch, and Vde is the desaturation protection threshold voltage of the power semiconductor switch.

[0042] Optionally, the preset protection response model is t=(C×Vde) / [Ich+(Vcc-Vde) / Rc], where t is the protection response time, C is the capacitance value of the blanking capacitor, Vde is the desaturation protection threshold voltage, Ich is the current of the constant current source, Vcc is the power supply voltage, and Rc is the resistance value of the compensation resistor.

[0043] Optionally, the parameters of the power semiconductor switch include at least one of the short-circuit withstand time, desaturation protection threshold voltage, maximum allowable false trigger voltage spike, transconductance, power semiconductor switch charge, and loop stray inductance of the power semiconductor switch.

[0044] Figure 4 is a power semiconductor switch protection circuit provided in Embodiment 3 of the present invention. Reference Figure 4 , the power semiconductor switch protection circuit includes: a driving unit 10 and a desaturation detection unit 20, the driving unit 10 includes a driving resistor Rg, and the desaturation detection unit 20 includes a blanking capacitor Cb and a compensation resistor Rc; one end of the power semiconductor switch Q1 is electrically connected to one end of the compensation resistor Rc and one end of the blanking capacitor Cb respectively, the other end of the compensation resistor Rc is electrically connected to a power supply, the other end of the blanking capacitor Cb is grounded, the other end of the power semiconductor switch Q1 is grounded, and the driving resistor Rg is electrically connected to the control end of the power semiconductor switch Q1; the power semiconductor switch protection method according to any embodiment of the present invention is applied to the power semiconductor switch protection circuit, and the specific process may refer to any of the foregoing embodiments, which will not be repeated herein.

[0045] In one embodiment, the power semiconductor switch Q1 is a SiC-based MOS transistor, and the driving resistor Rg is electrically connected to the gate of the MOS transistor.

[0046] Optionally, the desaturation detection unit further includes at least two diodes D0 connected in series. The anodes of the at least two diodes D0 are electrically connected to one end of the power semiconductor switch Q1, and the cathodes of the at least two diodes are electrically connected to one end of the blanking capacitor Cb. The power semiconductor switch protection circuit also includes a constant current source, which is electrically connected to one end of the blanking capacitor Cb. Specifically, the constant current source is electrically connected to one end of the blanking capacitor Cb through the power semiconductor switch, and the constant current source is also grounded through the power semiconductor switch.

[0047] Furthermore, the optimized blanking capacitor and compensation resistor obtained from the power semiconductor switch protection method in any of the above embodiments are used as the blanking capacitor and compensation resistor in the power semiconductor switch protection circuit, respectively, to protect the power semiconductor switch and coordinately optimize its parameters. A large-capacity blanking capacitor enhances the ability to "swallow" high-frequency voltage spikes, while the compensation resistor dynamically replenishes the charging current of the blanking capacitor, resolving the physical deadlock between "large capacitor noise immunity" and "short-time response." When a fault occurs, the charging current of the blanking capacitor is: It = Ich + (VCC - Vde) / Rc; where Ich is the current of the constant current source, Vcc is the power supply voltage, Vde is the desaturation protection threshold voltage, and Rc is the resistance value of the compensation resistor. For example, Rc is 5.6kΩ, and the initial charging current of the blanking capacitor can reach the order of several mA. Transient voltage and negative voltage safety clamping are implemented by setting transient suppression diode D1 and Schottky diode D2 at the desaturation detection node to prevent transient high voltage overshoot and negative voltage pumping lock-up, thereby ensuring the stability of the power semiconductor switch protection circuit. This ensures that while improving the efficiency of the power semiconductor switch, the power semiconductor switch protection circuit still has sub-microsecond response capability and high anti-interference capability, thus improving protection reliability.

[0048] This embodiment also provides a driver, which includes the power semiconductor switch protection circuit described in any embodiment of the present invention. This embodiment also provides a drive system, which includes the driver. In one embodiment, the drive system is a drive system for a vehicle, such as a new energy vehicle.

[0049] The power semiconductor switch protection device, power semiconductor switch protection circuit, driver, and drive system provided in this embodiment belong to the same inventive concept as the power semiconductor switch protection method provided in any embodiment of the present invention, and have corresponding beneficial effects. For technical details not covered in this embodiment, please refer to the power semiconductor switch protection method provided in any embodiment of the present invention.

[0050] Example 4 Figure 5 This is a schematic diagram of the structure of a terminal provided in Embodiment 4 of the present invention. Figure 5 A block diagram of an exemplary device 412 suitable for implementing embodiments of the present invention is shown. Figure 5 The device 412 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0051] like Figure 5 As shown, device 412 is represented as a general-purpose device. Components of device 412 may include, but are not limited to: one or more processors 416, storage device 428, and bus 418 connecting different system components (including storage device 428 and processor 416).

[0052] Bus 418 represents one or more of several bus architectures, including a memory device bus or memory device controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Subversive Alliance (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0053] Device 412 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by device 412, including volatile and non-volatile media, removable and non-removable media.

[0054] Storage device 428 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 430 and / or cache memory 432. Device 412 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 434 may be used to read and write non-removable, non-volatile magnetic media (… Figure 5 Not shown; usually referred to as a "hard drive"). Although Figure 5As not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc, such as a Compact Disc Read-Only Memory (CD-ROM), a Digital Video Disc Read-Only Memory (DVD-ROM), or other optical media. In these cases, each drive may be connected to bus 418 via one or more data media interfaces. Storage device 428 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0055] A program / utility 440 having a set (at least one) of program modules 442 may be stored in, for example, a storage device 428. Such program modules 442 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 442 typically perform the functions and / or methods described in the embodiments of the present invention.

[0056] Device 412 can also communicate with one or more external devices 414 (e.g., keyboard, pointing terminal, display 424, etc.), and with one or more terminals that enable a user to interact with device 412, and / or with any terminal that enables device 412 to communicate with one or more other computing terminals (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 422. Furthermore, device 412 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 420. Figure 5 As shown, network adapter 420 communicates with other modules of device 412 via bus 418. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with device 412, including but not limited to: microcode, terminal drivers, redundant processors, external disk drive arrays, Redundant Arrays of Independent Disks (RAID) systems, tape drives, and data backup storage systems.

[0057] Processor 416 (which can be considered as the power semiconductor switch protection device described above) executes various functional applications and data processing by running a program stored in storage device 428, such as implementing the power semiconductor switch protection method provided in the embodiments of the present invention, which includes: Obtain the parameters of the power semiconductor switch; Based on the power semiconductor switching parameters, determine the boundary constraints and optimization objectives; Based on boundary constraints and optimization objectives, the preset protection response model is iteratively optimized to obtain the target result, which is then used to protect and optimize the parameters of the power semiconductor switch.

[0058] Example 5 Embodiment 5 of the present invention provides a computer-readable storage medium storing a computer program thereon. When executed by a controller, the program implements the power semiconductor switch protection method provided in the embodiments of the present invention, the method comprising: Obtain the parameters of the power semiconductor switch; Based on the power semiconductor switching parameters, determine the boundary constraints and optimization objectives; Based on boundary constraints and optimization objectives, the preset protection response model is iteratively optimized to obtain the target result, which is then used to protect and optimize the parameters of the power semiconductor switch.

[0059] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0060] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0061] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0062] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or terminal. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0063] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, rearrangements, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for protecting a power semiconductor switch, characterized in that, comprising: acquiring parameters of the power semiconductor switch; determining a boundary constraint condition and an optimization target according to the parameters of the power semiconductor switch; performing iterative optimization on a preset protection response model based on the boundary constraint condition and the optimization target to obtain a target result, so as to protect the power semiconductor switch and perform parameter optimization on the power semiconductor switch based on the target result; the step of determining the boundary constraint condition and the optimization target according to the parameters of the power semiconductor switch comprises: determining the short-circuit withstand time, the desaturation protection threshold voltage and the maximum allowable false trigger voltage spike of the power semiconductor switch according to the parameters of the power semiconductor switch; taking the short-circuit withstand time, the desaturation protection threshold voltage and the maximum allowable false trigger voltage spike of the power semiconductor switch as the boundary constraint condition.

2. The power semiconductor switch protection method according to claim 1, characterized in that, the step of determining the boundary constraint condition and the optimization target according to the parameters of the power semiconductor switch comprises: determining the driving resistance of the power semiconductor switch according to the parameters of the power semiconductor switch; taking minimization of the driving resistance as the optimization target.

3. The power semiconductor switch protection method according to claim 1, characterized in that, the step of performing iterative optimization on the preset protection response model based on the boundary constraint condition and the optimization target to obtain the target result comprises: performing iterative optimization on the preset protection response model based on the boundary constraint condition and the optimization target to obtain optimized blanking capacitance, compensation resistance and driving resistance; the preset protection response model comprises the blanking capacitance and the compensation resistance, and the optimization target comprises the driving resistance.

4. The power semiconductor switch protection method according to claim 1, characterized in that, the step of performing iterative optimization on the preset protection response model based on the boundary constraint condition and the optimization target to obtain the target result comprises: taking minimization of the driving resistance as the optimization target based on the boundary constraint condition, performing iterative optimization on the preset protection response model to obtain the maximum blanking capacitance and the minimum compensation resistance that satisfy t≤T and Vno<Vde; wherein t is the protection response time in the preset protection response model, T is the short-circuit withstand time of the power semiconductor switch, Vno is the maximum allowable false trigger voltage spike of the power semiconductor switch, and Vde is the desaturation protection threshold voltage of the power semiconductor switch.

5. The power semiconductor switch protection method according to claim 1, characterized in that, the preset protection response model is t=(C×Vde) / [Ich+(Vcc-Vde) / Rc], wherein t is the protection response time, C is the capacitance value of the blanking capacitance, Vde is the desaturation protection threshold voltage, Ich is the current of a constant current source, Vcc is the power supply voltage, and Rc is the resistance value of the compensation resistance.

6. The power semiconductor switch protection method according to claim 1, characterized in that, the parameters of the power semiconductor switch include at least one of the short-circuit withstand time, the desaturation protection threshold voltage and the maximum allowable false trigger voltage spike of the power semiconductor switch.

7. A power semiconductor switch protection circuit, characterized in that, comprising: The system includes a driving unit and a desaturation detection unit. The driving unit includes a driving resistor, and the desaturation detection unit includes a blanking capacitor and a compensation resistor. One end of the power semiconductor switch is electrically connected to one end of the compensation resistor and one end of the blanking capacitor, respectively. The other end of the compensation resistor is electrically connected to the power supply. The other end of the blanking capacitor is grounded, and the other end of the power semiconductor switch is grounded. The driving resistor is electrically connected to the control terminal of the power semiconductor switch. The power semiconductor switch protection method as described in any one of claims 1-6 is applied to the power semiconductor switch protection circuit.

8. The power semiconductor switch protection circuit according to claim 7, characterized in that, The desaturation detection unit further includes at least two diodes connected in series, the anodes of which are electrically connected to one end of the power semiconductor switch, and the cathodes of which are electrically connected to one end of the blanking capacitor; the power semiconductor switch protection circuit further includes a constant current source, which is electrically connected to one end of the blanking capacitor.

9. A drive system, characterized in that, Includes: a driver, said driver including the power semiconductor switch protection circuit as described in any one of claims 7-8.

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