Driving circuit, driving method and driving system

Abstract

The application relates to a driving circuit, a driving method and a driving system. The driving circuit comprises a comparison amplification circuit, a driving tube, a first slew rate control circuit and a capacitor. The comparison amplification circuit generates an amplification voltage by receiving a reference voltage and a feedback voltage. The driving tube generates a driving signal by receiving the amplification voltage output by the comparison amplification circuit. The first slew rate control circuit is connected to the output end of the comparison amplification circuit and the control end of the driving tube. The capacitor is connected to the control end of the driving tube. The driving process of the driving circuit comprises a pre-opening stage and a pre-closing stage. In the pre-opening stage, the first slew rate control circuit charges the capacitor to the amplitude of the amplification voltage. In the pre-closing stage, the first slew rate control circuit discharges the capacitor to zero. The application sets the slew rate control circuit to control the slew rate of the voltage at the control end of the driving tube in the preset driving stage, so that the rising edge and the falling edge of the driving current become gentle, the high-frequency component is effectively reduced, and the electromagnetic interference (EMI) performance is optimized.

Description

Technical Field

[0001] This application relates to the field of optical detection, specifically to a driving circuit, driving method, and driving system. Background Technology

[0002] In applications such as light detection and LED driving, especially in integrated automotive chips or rain and light detection applications in automobiles, the driving circuit typically uses a comparator amplifier circuit in conjunction with a driving transistor (such as a MOSFET) to form a negative feedback loop to output a stable driving current. The control terminal voltage of the driving transistor directly determines the magnitude of the output current of the driving circuit. At the instant of switching on and off, the control terminal voltage will jump rapidly, resulting in extremely steep rising and falling edges of the output current, thereby generating more high-frequency harmonic components and causing serious electromagnetic interference (EMI) problems, affecting system reliability and the normal operation of other circuits.

[0003] To suppress EMI, existing technologies often add an RC filter network to the control terminal of the driver transistor or use a dedicated slew rate control chip. However, RC filtering reduces the loop response speed, and the slew rate fluctuates greatly with process and temperature variations, making precise control difficult. Dedicated chips increase system cost and PCB area, and have poor compatibility with external components. In addition, some solutions use comparators to detect voltage thresholds to control the switching speed of the transistor in segments, but comparators are susceptible to output ripple and may cause false switching, resulting in a high control risk.

[0004] Therefore, there is an urgent need for a drive circuit with a simple structure and controllable slew rate to effectively improve the smoothness of the drive current waveform and optimize EMI performance. Summary of the Invention

[0005] To address the above problems, this application provides a driving circuit, including:

[0006] A comparator amplifier circuit is used to receive a reference voltage and a feedback voltage to generate an amplified voltage. A driving transistor, the control terminal of which is connected to the output terminal of the comparator amplifier circuit, to generate a driving signal based on the amplified voltage; A first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit and the control terminal of the driving transistor. A capacitor, the first end of which is connected to the control terminal of the driving transistor; The driving process of the driving circuit includes a pre-turn-on stage and a pre-turn-off stage; in the pre-turn-on stage, the capacitor is charged to the amplitude of the amplified voltage by the first slew rate control circuit; in the pre-turn-off stage, the capacitor is discharged to zero by the first slew rate control circuit.

[0007] Furthermore, the driving circuit also includes a first switch, a third switch, and a fourth switch; the driving process also includes a stable driving stage; the first slew rate control circuit is a follower. The output terminal of the comparator amplifier circuit is connected to the control terminal of the driving transistor via the first switch. The first input terminal of the follower is connected to the output terminal of the comparator amplifier circuit or grounded via the third switch; the output terminal of the follower is connected to the control terminal of the driver transistor via the fourth switch. The driving circuit is configured such that, during the pre-start phase, the first switch is off, the third switch is on and connected to the output terminal of the comparator amplifier circuit, the fourth switch is on, and the follower replicates the amplified voltage to charge the capacitor. During the stable driving phase, at least one of the third switch or the fourth switch is open, and the first switch is closed. During the pre-shutdown phase, the first switch is turned off, the fourth switch is turned on, and the input terminal of the follower is switched to ground via the third switch.

[0008] Furthermore, the driving circuit also includes a fifth switch, the control terminal of the driving transistor is grounded through the fifth switch, and the driving process also includes a complete turn-off phase; The fifth switch is configured to be open during the pre-opening phase, the stable driving phase, and the pre-shutdown phase; and to be open during the complete shutdown phase.

[0009] Furthermore, the driving circuit also includes a second switch, and the second input terminal of the comparator amplifier circuit is connected to the first terminal of the driving transistor via the second switch to receive the feedback voltage; The second switch and the first switch are simultaneously turned on or simultaneously turned off.

[0010] Furthermore, the driving circuit also includes a first output adjustment circuit, which includes multiple parallel adjustment branches. The first output adjustment circuit is configured to adjust the number of parallel adjustment branches according to the output current of the driving circuit. The adjustment branch includes a driving transistor and a first resistor connected in series.

[0011] Furthermore, the capacitor is an adjustable capacitor; The adjustable capacitor is configured to adjust its capacitance value according to the number of the adjusted branches connected in parallel.

[0012] Furthermore, the capacitance value of the adjustable capacitor is negatively correlated with the number of the integrated adjustment branches.

[0013] Furthermore, the driving circuit also includes a second output adjustment circuit, which includes a programmable voltage source. The output terminal of the programmable voltage source is connected to the first input terminal of the comparator amplifier circuit to provide the comparator amplifier circuit with an adjustable reference voltage.

[0014] Furthermore, the programmable voltage source includes a current source and a multi-digit digital-to-analog converter connected in sequence.

[0015] Furthermore, the follower is configured to determine the magnitude of the charging current for the capacitor based on the high-order bits of the multi-bit digital-to-analog converter.

[0016] Furthermore, the magnitude of the current is positively correlated with the high-order value of the multi-bit digital-to-analog converter.

[0017] Furthermore, the capacitor includes a first terminal and a second terminal, the first terminal of the capacitor is connected to the control terminal of the driving transistor, the driving circuit further includes a second slew rate control circuit, and the second terminal of the capacitor is connected to the second slew rate control circuit; The second slew rate control circuit is configured to provide a preset initial voltage to the second terminal of the capacitor during the pre-turn-on phase, wherein the initial voltage is greater than or equal to the threshold voltage at which the driving transistor is turned on.

[0018] Furthermore, the driving circuit also includes a sixth switch; the second slew rate control circuit includes a first power transistor, the first power transistor including a first terminal, a second terminal and a control terminal; the first terminal of the first power transistor is connected to the control terminal of the first power transistor, and the second terminal of the first power transistor is grounded; The second terminal of the capacitor is connected to the control terminal of the first power transistor, and the second terminal of the capacitor is grounded through the sixth switch; The second slew rate control circuit is configured such that, during the pre-turn-on phase, the stable drive phase, and the pre-turn-off phase, the sixth switch is disconnected; and during the complete turn-off phase, the sixth switch is turned on.

[0019] Furthermore, the drive circuit is used to connect to an external power element, and the drive circuit also includes a third slew rate control circuit, which is configured to be connected to the control terminal of the power element. The third slew rate control circuit is configured to provide a preset control voltage to the power element during the pre-start phase.

[0020] Furthermore, the power element is a transistor, and the third slew rate control circuit includes a second power transistor, a third power transistor, a fourth power transistor, and a comparator. The comparator is used to compare the control terminal voltage of the transistor with a preset base reference voltage. The third slew rate control circuit is configured such that when the control terminal voltage of the transistor is less than the preset base reference voltage, the second power transistor and the third power transistor form a current mirror to charge the control terminal of the transistor; when the control terminal voltage of the transistor is greater than the preset base reference voltage, the third power transistor and the fourth power transistor form an inverter.

[0021] The driving circuit also includes a seventh switch and an eighth switch; The second terminal of the second power transistor and the second terminal of the third power transistor are connected to the same voltage source; The first end of the second power transistor is connected to the control terminal of the second power transistor, and the first end of the second power transistor is connected to a current source; The control terminal of the second power transistor is connected to the control terminal of the third power transistor via the seventh switch; The first end of the third power transistor is connected to the first end of the fourth power transistor, and the control end of the third power transistor is also connected to the control end of the fourth power transistor through the eighth switch. The third slew rate control circuit is configured such that when the control terminal voltage of the power element is less than the preset base reference voltage, the seventh switch is turned on and the eighth switch is turned off; when the control terminal voltage of the power element is greater than the preset base reference voltage, the seventh switch is turned off and the eighth switch is turned on, and the control terminals of the third power transistor and the fourth power transistor receive a low-level signal; during the complete turn-off phase, the seventh switch remains off and the eighth switch remains on, and the control terminals of the third power transistor and the fourth power transistor receive a high-level signal.

[0022] The output of the comparator amplifier circuit is also connected to a virtual output circuit. The virtual output circuit is configured to provide a closed feedback loop for the comparison amplifier circuit to maintain the stability of the operating point of the comparison amplifier circuit.

[0023] The virtual output circuit includes a virtual driving transistor and a virtual resistor, which are matched with the adjustment branch.

[0024] Furthermore, the driving circuit is an integrated chip.

[0025] This application further provides a driving method with slew rate control, applied to a driving circuit, the driving circuit including a comparator amplifier circuit, a driving transistor, a first slew rate control circuit, and a capacitor; the comparator amplifier circuit is used to receive a reference voltage and a feedback voltage to generate an amplified voltage; the control terminal of the driving transistor is connected to the output terminal of the comparator amplifier circuit to generate a driving voltage according to the amplified voltage; the input terminal of the first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit, and the output terminal of the first slew rate control circuit is connected to the control terminal of the driving transistor; the first terminal of the capacitor is connected to the control terminal of the driving transistor; the method includes: The driving process of the configured driving circuit includes a pre-turn-on phase and a pre-turn-off phase; During the pre-start phase, the first slew rate control circuit is controlled to slowly charge the capacitor to the amplitude of the amplified voltage. During the pre-shutdown phase, the first slew rate control circuit is controlled to slowly discharge the capacitor to zero.

[0026] Furthermore, the driving circuit further includes a first switch, a third switch, and a fourth switch; the first slew rate control circuit is a follower; the output terminal of the comparator amplifier circuit is connected to the control terminal of the driving transistor via the first switch; the first input terminal of the follower is connected to the output terminal of the comparator amplifier circuit or grounded via the third switch; the output terminal of the follower is connected to the control terminal of the driving transistor via the fourth switch; the method further includes: The driving process of the configured driving circuit also includes a stable driving phase; During the pre-opening phase, the first switch is controlled to open, the third switch is controlled to open and connect to the output terminal of the comparator amplifier circuit, and the fourth switch is controlled to open, so that the follower replicates the amplified voltage to charge the capacitor; During the stable driving phase, at least one of the third switch or the fourth switch is controlled to open, and the first switch is controlled to turn on. During the pre-shutdown phase, the first switch is controlled to open, the fourth switch is controlled to open, and the input terminal of the follower is controlled to be switched to ground via the third switch.

[0027] Furthermore, the driving circuit also includes a fifth switch, and the control terminal of the driving transistor is grounded via the fifth switch. The method further includes: The driving process of the configured driving circuit also includes a complete shutdown phase; During the pre-opening phase, the stable driving phase, and the pre-shutdown phase, the fifth switch is controlled to open. During the complete shutdown phase, the fifth switch is turned on.

[0028] Furthermore, the driving circuit also includes a second switch, and the second input terminal of the comparator amplifier circuit is connected to the output terminal of the driving transistor via the second switch. The method further includes: Control the second switch and the first switch to be turned on or off simultaneously.

[0029] Furthermore, the driving circuit further includes a first output adjustment circuit, which includes multiple parallel adjustment branches, and the method further includes: The number of the regulating branches is adjusted according to the output current of the drive circuit.

[0030] Furthermore, the capacitor is an adjustable capacitor, and the method further includes: The capacitance value of the adjustable capacitor is negatively correlated with the number of the regulating branches connected in parallel.

[0031] Furthermore, the driving circuit further includes a second output adjustment circuit, which includes a programmable voltage source. The output terminal of the programmable voltage source is connected to the first input terminal of the comparator amplifier circuit. The method further includes: The programmable voltage source is controlled to provide an adjustable reference voltage to the comparator amplifier circuit.

[0032] Furthermore, the programmable voltage source includes a current source and a multi-digit digital-to-analog converter connected in sequence, and the method further includes: The first slew rate control circuit determines the charging current of the capacitor based on the high-order bit of the multi-digit digital-to-analog converter, wherein the current is positively correlated with the high-order bit value of the multi-digit digital-to-analog converter.

[0033] Further, the capacitor includes a first terminal and a second terminal, the first terminal of the capacitor is connected to the control terminal of the driving transistor, the driving circuit further includes a second slew rate control circuit, the second terminal of the capacitor is connected to the second slew rate control circuit, and the method further includes: During the pre-turn-on phase, the second slew rate control circuit is controlled to provide a preset initial voltage to the second terminal of the capacitor, wherein the initial voltage is greater than or equal to the threshold voltage at which the driving transistor is turned on.

[0034] Furthermore, the driving circuit is used to connect to an external power element, and the driving circuit further includes a third slew rate control circuit configured to be connected to the control terminal of the power element. The method further includes: During the pre-start phase, the third slew rate control circuit provides a preset control voltage to the power element.

[0035] Further, the power element is a transistor, and the third slew rate control circuit includes a second power transistor, a third power transistor, a fourth power transistor, and a comparator. The comparator is used to compare the control terminal voltage of the transistor with a preset base reference voltage; the method further includes: When the control terminal voltage is less than the preset base reference voltage, the second power transistor and the third power transistor are controlled to form a current mirror to charge the control terminal of the transistor. When the control terminal voltage is greater than the preset base reference voltage, the third power transistor and the fourth power transistor are controlled to form an inverter.

[0036] This application also provides a drive system including the drive circuit described above.

[0037] Furthermore, it also includes a light-emitting device, the driving circuit is connected to the light-emitting device, wherein the second end of the driving tube outputs a driving signal, the driving signal being used to drive the light-emitting device to emit light.

[0038] Furthermore, it also includes a power element, through which the driving circuit is connected to the light-emitting device.

[0039] This application relates to a driving circuit, driving method, and driving system. The driving circuit includes a comparator amplifier circuit, a driving transistor, a first slew rate control circuit, and a capacitor. The comparator amplifier circuit receives a reference voltage and a feedback voltage to generate an amplified voltage. The control terminal of the driving transistor is connected to the output terminal of the comparator amplifier circuit to generate a driving signal based on the amplified voltage. The first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit and the control terminal of the driving transistor. The first terminal of the capacitor is connected to the control terminal of the driving transistor. The driving process of the driving circuit includes a pre-turn-on stage and a pre-turn-off stage. In the pre-turn-on stage, the capacitor is charged to the amplitude of the amplified voltage by the first slew rate control circuit. In the pre-turn-off stage, the capacitor is discharged to zero by the first slew rate control circuit. By setting the slew rate control circuit, this application controls the slew rate of the control terminal voltage of the driving transistor within a preset driving stage, making the rising and falling edges of the driving current smoother, effectively reducing high-frequency components, and optimizing electromagnetic interference (EMI) performance. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the overall structure of the driving circuit in this application; Figure 2 This is a timing diagram of each signal corresponding to the driving circuit of this application; Figure 3 This is a schematic diagram of the connection structure of the first slew rate control circuit in the driving circuit of this application; Figure 4 This is a schematic diagram of the connection structure of the second slew rate control circuit in the driving circuit of this application; Figure 5 This is a timing diagram of each signal when the drive circuit of this application is not connected to the second slew rate control circuit; Figure 6 This is a timing diagram of each signal when the driving circuit of this application is connected to the second slew rate control circuit; Figure 7 This is a schematic diagram of the connection structure of the third slew rate control circuit in the driving circuit of this application; Figure 8 This is a timing diagram of each signal when the drive circuit of this application is not connected to the third slew rate control circuit; Figure 9 This is a timing diagram of each signal when the driving circuit of this application is connected to the third slew rate control circuit; Figure 10 This is a schematic diagram of the virtual output circuit connection structure in the driver circuit of this application; Figure 11 This is a flowchart of the driving method of this application.

[0041] Explanation of reference numerals in the attached figures 1. Comparison amplifier circuit; 2. First slew rate control circuit; 3. Load circuit; 4. Second slew rate control circuit; 5. Third slew rate control circuit; 6. Programmable voltage source. Detailed Implementation

[0042] To gain a more detailed understanding of the features and technical content of the embodiments disclosed herein, the following description is provided in conjunction with the accompanying drawings. Figure 1-11 The implementation of the embodiments of this disclosure is described in detail. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, various details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other instances, well-known structures and apparatuses may be simplified in their depiction to simplify the drawings.

[0043] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0044] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0045] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0046] Unless otherwise stated, the term "multiple" means two or more.

[0047] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0049] To provide a clearer understanding of the purpose, structure, features, and functions of this application, detailed descriptions are provided below with reference to embodiments.

[0050] This invention provides a driving circuit, including a comparator amplifier circuit 1, a driving transistor M, a first slew rate control circuit 2, and a capacitor C. For details, please refer to [link to relevant documentation]. Figure 1 .

[0051] The comparator amplifier circuit 1 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator amplifier circuit 1 is used to receive a reference voltage Vref, and the second input terminal of the comparator amplifier circuit 1 is used to receive a feedback voltage Vres. Based on the reference voltage Vref and the feedback voltage Vres, an amplified voltage Vop is generated and output at the output terminal of the comparator amplifier circuit 1.

[0052] In one embodiment, the first input terminal of the comparator amplifier circuit 1 is a non-inverting input terminal, and the second input terminal of the comparator amplifier circuit 1 is an inverting input terminal.

[0053] The control terminal of the driving transistor M is connected to the output terminal of the comparator amplifier circuit 1. The first terminal of the driving transistor M is connected to the load, and the second terminal of the driving transistor M is grounded through the first resistor R. The driving transistor M is used to generate a driving signal based on the amplified voltage Vop, that is, to drive the load with the driving current I_LED.

[0054] In one embodiment, the load can be an LED. The technical solution of this application is described in detail below using an LED as an example. That is, the driving circuit can be used to drive the LED to emit light at a preset interval.

[0055] The feedback voltage Vres is obtained from the connection node between the second terminal of the driving transistor M and the first resistor R.

[0056] The input terminal of the first slew rate control circuit 2 is connected to the output terminal of the comparator amplifier circuit 1, and the output terminal of the first slew rate control circuit 2 is connected to the control terminal of the drive transistor M.

[0057] The capacitor C includes a first end and a second end. Its first end is connected to the control end of the driving transistor M. At the same time, the first end of the capacitor C is also connected to the output end of the first slew rate control circuit 2.

[0058] In one embodiment, the driving transistor M is a MOS transistor, preferably an NMOS transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate.

[0059] The process of driving the LED to emit light by the driving circuit includes a pre-on stage and a pre-off stage. In the pre-on stage, the capacitor C is charged to the amplitude of the amplification voltage Vop by the first slew rate control circuit 2 at a preset first slope, that is, the control terminal voltage Vgate of the driving transistor M increases to the amplitude of the amplification voltage at the first slope; in the pre-off stage, the capacitor C is discharged to zero by the first slew rate control circuit 2 at a preset second slope.

[0060] The first slope and the second slope are set according to actual needs, and this application does not impose specific restrictions.

[0061] See Figure 2 In this application, the process of driving the LED to light up or turn off is controlled by the LED ON light-emitting enable signal. When the LED ON light-emitting enable signal is high, it enables the LED, that is, when the LED ON light-emitting enable signal is 1, the LED is driven to light up. This process includes a pre-on stage, a stable driving stage, and a pre-off stage. When the LED ON light-emitting enable signal is low, it is in the complete off stage, that is, when LED ON is 0, the LED is driven to turn off. It can be understood that driving the LED to turn off means that the LED does not light up.

[0062] The pre-start phase is controlled by the rising edge control window TR. When the rising edge control window TR is high, it is enabled. That is, when TR=1, the rising edge slew rate of the drive circuit is controlled, that is, the rising edge of the drive circuit is increased with the first slope.

[0063] The stable driving phase is controlled by the stable driving window TS. When the stable driving window TS is high, it is enabled. That is, when TS=1, stable driving of LED light is executed.

[0064] The pre-shutdown phase is controlled by the falling edge control window TF. When the falling edge control window TF is high, it is enabled. That is, when TF=1, the falling edge slew rate is controlled, that is, the falling edge of the drive circuit decreases with the second slope.

[0065] It is understandable that when the LED enable signal is ON=1, the rising edge control window TR=1, the stable drive window TS=1, and the falling edge control window TF=1 are executed sequentially. At any given time, typically only one of these windows is enabled. Ultimately, the driving current I_LED applied to the LED is as follows: Figure 2 The timing changes corresponding to I_LED.

[0066] By setting the first slew rate control circuit 2, during the initial transition phase of LED turn-on (i.e., the pre-turn-on phase), the control terminal voltage Vgate of the driver transistor M rises slowly with a controlled first slope, executing the rising edge slew rate control; during the final transition phase of LED turn-off (i.e., the pre-turn-off phase), it falls slowly with a controlled second slope, executing the falling edge slew rate control. In integrated automotive chips / cars for rain and light detection, by setting the first slew rate control circuit 2, the rising and falling edge slew rates of the drive current I_LED output by the driver circuit become smoother, effectively reducing high-frequency components in the drive current waveform and optimizing electromagnetic interference (EMI) performance.

[0067] In one specific implementation, see Figure 3 The driving circuit also includes a first switch S1, a third switch S3, and a fourth switch S4. The output terminal of the comparator amplifier circuit 1 is connected to the control terminal of the driving transistor M via the first switch S1. Specifically, the first switch S1 has a first terminal and a second terminal. The output terminal Vop of the comparator amplifier circuit 1 is connected to the first terminal of the first switch S1, and the second terminal of the first switch S1 is connected to the control terminal of the driving transistor M.

[0068] In this embodiment, the first slew rate control circuit 2 is a follower B1, which includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the follower B1 is connected to the output terminal of the comparator amplifier circuit 1 or grounded via a third switch S3. Specifically, when the first input terminal of the follower is connected to the output terminal of the comparator amplifier circuit 1, the connection node is located at the first end of the first switch S1. The output terminal of the follower B1 is connected to the control terminal of the driving transistor M via a fourth switch S4. Specifically, when the output terminal of the follower B1 is connected to the control terminal of the driving transistor M via the fourth switch S4, the connection node is located at the second end of the first switch S1. The second input terminal of the follower B1 is connected to the output terminal of the follower B1, forming a unity-gain buffer.

[0069] The first input of follower B1 is the non-inverting input, and the second input of follower B1 is the inverting input.

[0070] The process of driving an LED to emit light also includes a stable driving stage, in which the LED ON enable signal and the stable driving window TS are both high, and the rising edge control window TR and the falling edge control window TF are both low. Different driving stages are executed by controlling the switching of the first switch S1, the third switch S3, and the fourth switch S4.

[0071] Specifically, during the pre-start phase, the first switch S1 is open, which disconnects the connection between the comparator amplifier circuit 1 and the control terminal of the driver transistor M. The third switch S3 is turned on, connecting the output terminal of the follower B1 to the output terminal of the comparator amplifier circuit 1. The fourth switch S4 is turned on, connecting the output terminal of the follower B1 to the capacitor C. The follower B1 charges the capacitor C by replicating the amplified voltage Vop, causing the control terminal voltage Vgate of the driver transistor M to gradually increase to the amplitude of the amplified voltage as the capacitor C is charged.

[0072] During the stable driving phase, at least one of the third switch S3 or the fourth switch S4 is turned off, that is, the electrical connection between the follower B1 and the control terminal of the driving transistor M is disconnected; at the same time, the first switch S1 is turned on, and the comparator amplifier circuit 1 provides a stable driving signal to the driving transistor M, that is, provides a stable control terminal voltage Vgate to the driving transistor M.

[0073] During the pre-shutdown phase, the first switch S1 is turned off, which disconnects the connection between the comparator amplifier circuit 1 and the control terminal of the driving transistor M. The fourth switch S4 is turned on, and the input terminal of the follower B1 is switched to ground via the third switch S3, causing the capacitor C to discharge slowly through the follower B1, thereby causing the control terminal voltage Vgate of the driving transistor M to decrease slowly at the second slope.

[0074] By controlling the switching process of the first switch S1, the third switch S3, and the fourth switch S4 to execute different driving stages, the slew rate of the driving circuit during the pre-turn-on and pre-turn-off stages is effectively reduced, thus reducing electromagnetic interference in the driving circuit.

[0075] In another embodiment, the drive circuit further includes a fifth switch S5, and the control terminal node of the drive transistor M is grounded via the fifth switch S5.

[0076] Specifically, during the pre-start phase, stable drive phase, and pre-stop phase, the fifth switch S5 is disconnected, and there is no electrical connection between the control terminal of the drive tube M and ground.

[0077] The driving process also includes a complete shutdown phase, i.e., the LED ON=0. During the complete shutdown phase, the fifth switch S5 is turned on, and the control terminal of the driving transistor M is connected to ground to ensure that the voltage Vgate at the control terminal of the driving transistor M is stably maintained at zero during the complete shutdown phase.

[0078] During the complete shutdown phase, the fifth switch S5 is turned on to directly short-circuit the control terminal voltage Vgate of the driver transistor M to ground and quickly discharge it to 0V, ensuring that the driver transistor M is completely turned off and preventing leakage current from the LED in the off state.

[0079] In one embodiment, the drive circuit further includes a feedback loop.

[0080] Specifically, the driving circuit also includes a second switch S2. The second input terminal (i.e., the inverting input terminal) of the comparator amplifier circuit 1 is connected to the second terminal (source) of the driving transistor M via the second switch S2 to obtain a feedback voltage Vres from the feedback node between the second terminal of the driving transistor M and the first resistor R. The feedback voltage Vres reflects the magnitude of the current flowing through the first resistor R.

[0081] In this configuration, the second switch S2 and the first switch S1 are either simultaneously turned on or simultaneously turned off.

[0082] During the pre-opening phase, the first switch S1 and the second switch S2 are simultaneously turned off. At this time, the inverting input terminal of the comparator amplifier circuit 1 is disconnected from the feedback node. The control terminal voltage Vgate of the drive transistor M is slowly charged by the follower B1 to the capacitor C, ensuring that the follower B1 controls the rising edge to increase at a preset first slope during the pre-opening phase.

[0083] During the stable driving phase, the first switch S1 and the second switch S2 are turned on simultaneously. The comparator amplifier circuit 1, the driving transistor M, and the first resistor R form a complete negative feedback loop, and precise constant current driving is achieved through the comparator amplifier circuit 1.

[0084] During the pre-shutdown phase, the first switch S1 and the second switch S2 are simultaneously turned off, the negative feedback loop is disconnected, and the control terminal voltage Vgate of the drive transistor M is slowly discharged by the follower B1 to the capacitor C, ensuring that the follower B1 controls the falling edge to change at a preset second slope during the pre-shutdown phase.

[0085] During the complete shutdown phase, the first switch S1 and the second switch S2 remain open. At this time, the fifth switch S5 is closed to directly ground the control terminal of the drive transistor M, ensuring that the drive transistor M is completely shut off.

[0086] By synchronously disconnecting the second switch S2 and the first switch S1, it is ensured that the comparator amplifier circuit 1 is disconnected from the driver transistor M during the pre-turn-on and turn-off phases when slew rate control is required. This ensures that the follower B1 can independently control the rising and falling slopes of the control terminal voltage Vgate of the driver transistor M. During the stable driving phase, the second switch S2 and the first switch S1 are synchronously turned on, closing the feedback loop and achieving precise constant current driving.

[0087] Furthermore, the drive circuit also includes a first output adjustment circuit. The first output adjustment circuit includes multiple parallel adjustment branches, each adjustment branch including a drive transistor M connected in series with each other and a first resistor R.

[0088] The first ends of each driving transistor M are connected in parallel to form the first end of the adjustment branch. That is, the first ends of the parallel adjustment branches are connected to the RLED node of the load circuit 3. The second end of the driving transistor M is connected to the first end of the corresponding first resistor R, and the second end of the first resistor R is grounded.

[0089] The adjustment principle of the first output adjustment circuit is explained by taking an example of an eight-channel parallel adjustment branch. Of course, the number of parallel adjustment branches can be flexibly set according to the actual output current requirements of the drive circuit, and the range can be set to 4, 6, 8, 16 or more parallel adjustment branches.

[0090] The first output regulation circuit includes eight parallel regulation branches, wherein the first end of the eight parallel regulation branches is connected to the RLED node of the load circuit 3, the control terminals of the driving transistors M of all eight regulation branches are connected to each other, and the driving transistors M of all eight regulation branches receive the same control terminal voltage Vgate.

[0091] The first output regulation circuit is configured to adjust the number of parallel regulation branches according to the output current required by the drive circuit. The more parallel regulation branches, the smaller the final equivalent resistance Rled formed by the first output regulation circuit, and the larger the drive current I_LED output by the drive circuit under the same reference voltage Vref. Conversely, the fewer parallel regulation branches, the smaller the drive current I_LED output by the drive circuit.

[0092] In this application, the number of these 8 regulating branches connected to the loop is controlled by a 2-to-4 decoder through a 2-bit binary code R<1:0>.

[0093] A 2-to-4 decoder converts the received 2-bit binary code into 4 different output signals, each corresponding to a different number of input branches for the regulation branch.

[0094] Specifically, if the resistance value of the first resistor R is denoted as R, then when R<1:0>=00, it is connected to the 1st adjustment branch, and the equivalent resistance Rled formed by the first output adjustment circuit is R; when R<1:0>=01, it is connected to the 2nd adjustment branch, and the equivalent resistance Rled formed by the first output adjustment circuit is R / 2; when R<1:0>=10, it is connected to the 4th adjustment branch, and the equivalent resistance Rled formed by the first output adjustment circuit is R / 4; when R<1:0>=11, it is connected to the 8th adjustment branch, and the equivalent resistance Rled formed by the first output adjustment circuit is R / 8.

[0095] By using a 2-to-4 decoder with 2-bit binary encoding and 8 parallel adjustment branches, the output current range can be adjusted to four levels.

[0096] In this application, the capacitor C charged by the follower B1 during the pre-start phase is an adjustable capacitor. The adjustable capacitor is configured to adjust its capacitance value according to the number of parallel adjustment branches.

[0097] The capacitance value of the adjustable capacitor is negatively correlated with the number of parallel adjustment branches. Since the adjustable capacitor, together with the gate parasitic capacitances of all the driving transistors M in the parallel circuit, constitutes the total output load capacitance Ctotal of the comparator amplifier circuit 1, it can be understood that when the follower B1 charges and discharges the adjustable capacitor, it simultaneously charges and discharges the gate parasitic capacitances of the driving transistors M. However, the more parallel adjustment branches there are, the more driving transistors M are connected in parallel, resulting in a larger total parasitic capacitance of the first output adjustment circuit. In this case, a smaller capacitance value should be selected for the adjustable capacitor to ensure that the total output load capacitance Ctotal remains constant, thus maintaining the stability of the comparator amplifier circuit 1 and keeping the slew rate constant during the pre-turn-on and pre-turn-off phases.

[0098] For example, assuming the gate parasitic capacitance of a driving transistor M is 1pF, when the equivalent resistance Rled is switched to R, R / 2, R / 4, and R / 8, the number of driving transistors M connected in parallel increases by 1, 2, 4, and 8 respectively. The total gate parasitic capacitance of the first output adjustment circuit gradually increases by 1pF, 2pF, 4pF, and 8pF respectively. At this time, the values ​​of the adjustable capacitors are selected as 11pF, 10pF, 8pF, and 4pF respectively, thus ensuring that the total output load capacitance Ctotal of the comparator amplifier circuit 1 is maintained at 12pF.

[0099] See also Figure 1 The driving circuit described in this application further includes a second output adjustment circuit, which includes a programmable voltage source 6. The output terminal of the programmable voltage source 6 is connected to the first input terminal of the comparator amplifier circuit 1, that is, the non-inverting input terminal of the comparator amplifier circuit 1, and provides an adjustable reference voltage Vref to the comparator amplifier circuit 1.

[0100] Understandably, when the number of integrated regulating branches is fixed, the output current of the drive circuit can be further finely adjusted by regulating the size of the programmable voltage source 6. That is, the output current of the drive circuit is first coarsely regulated by adjusting the number of integrated regulating branches. For example, the coarse regulation can be set to four levels, as described above, for four different numbers of integrated regulating branches. Then, at each determined level, the programmable voltage source 6 is adjusted to further finely regulate the output current of the drive circuit.

[0101] In one specific embodiment, the programmable voltage source 6 includes a current source and a multi-digital-to-analog converter (RDAC) connected in sequence. The current source injects current into the RDAC, and the RDAC outputs a corresponding analog reference voltage Vref according to its digital code.

[0102] For example, the multi-bit analog-to-digital converter RDAC is an 8-bit analog-to-digital converter RDAC<7:0>. When the 8-bit analog-to-digital converter RDAC<7:0>=00000000, Vref=0V; when RDAC<7:0>=11111111, Vref=Vref_max, where Vref_max is the preset maximum reference voltage value.

[0103] When the digital code of the 8-bit digital-to-analog converter RDAC<7:0> changes from 0 to 255, the reference voltage Vref received by the comparator amplifier circuit 1 steps at fixed intervals from 0 to Vref_max, where the step interval is (Vref_max-0) / 256, and the output current of the programmable voltage source 6 is (Vref_max-0) / 256×code_of_RDAC<7:0>, where code_of_RDAC<7:0> is the value corresponding to the 8-bit digital code of the 8-bit digital-to-analog converter RDAC<7:0>.

[0104] RDAC<7:0> represents the 8-bit binary code from the least significant bit (bit0) to the most significant bit (bit7) in the control register of the 8-bit digital-to-analog converter.

[0105] By coordinating the number of multi-bit analog-to-digital converters (RDACs) with the number of parallel adjustment branches, finer adjustments can be achieved at any of the four positions of the equivalent resistance Rled formed by the first output adjustment circuit. For example, by setting an 8-bit analog-to-digital converter (RDAC<7:0>), with 256 variations of the digital code from 0 to 255, 256 fine adjustments can be achieved at any of the four positions of the equivalent resistance Rled.

[0106] In one embodiment, follower B1 is configured to determine the magnitude of the current charging capacitor C or the total output load capacitor Ctotal based on the high-order bit of the multi-bit digital-to-analog converter RDAC. That is, the current magnitude is positively correlated with the value of the high-order bit of the multi-bit digital-to-analog converter RDAC.

[0107] For example, follower B1 is configured to determine the current magnitude for charging the capacitor based on the high 2 bits of the multi-bit analog-to-digital converter RDAC. Of course, the current magnitude for charging the capacitor to ground can also be determined based on the high 3 bits or high 4 bits of the multi-bit analog-to-digital converter RDAC. This application does not impose any specific limitations.

[0108] Specifically, the multi-bit analog-to-digital converter RDAC is an 8-bit analog-to-digital converter, and the follower B1 selects different current levels to charge the capacitor based on the 8-bit analog-to-digital converter RDAC<7:6>. This can be understood as the follower B1 selecting different output current levels based on the high 2 bits of the 8-bit analog-to-digital converter's control register <7:6>, which corresponds to the output reference voltage Vref.

[0109] For example, the high 2 bits of the control register of the 8-bit digital-to-analog converter are bit<7:6>=00, which corresponds to the 0~63 range, and the charging current provided by the follower B1 is 7μA.

[0110] The high 2 bits of the 8-bit digital-to-analog converter control register bit<7:6>=01, which corresponds to the 64~127 range. The charging current provided by the follower B1 is 8μA.

[0111] The high 2 bits of the 8-bit digital-to-analog converter control register bit<7:6>=10, which corresponds to the 128~191 range. The charging current provided by the follower B1 is 10μA.

[0112] The high 2 bits of the 8-bit digital-to-analog converter control register bit<7:6>=11, which corresponds to the 192~255 range. The charging current provided by the follower B1 is 12μA.

[0113] The charging current provided by the follower B1 is determined based on the high-order bits of the multi-bit analog-to-digital converter (RDAC), and the current magnitude is positively correlated with the value of the high-order bits of the RDAC. To simplify the process, this application divides the RDAC into multiple intervals to set the charging current of the follower B1 for the capacitor in each interval. However, the specific value of the charging current provided by the follower B1 in each interval can be set according to actual needs.

[0114] For different reference voltages Vref, the amplified voltage Vop output by comparator amplifier circuit 1 varies with the reference voltage Vref. If follower B1 uses a fixed charging current, for higher reference voltages Vref, the charging current may be too small, and the control terminal voltage Vgate of driver transistor M may not reach the amplified voltage Vop output by comparator amplifier circuit 1 after the pre-turn-on phase ends, resulting in poor slew rate control. Conversely, for lower reference voltages Vref, the charging current may be too large, and the control terminal voltage Vgate of driver transistor M may reach the amplified voltage Vop output by comparator amplifier circuit 1 too early before the pre-turn-on phase ends, resulting in a still high slew rate. This application ensures that the programmable voltage source 6 can achieve the best slew rate control effect of the drive circuit under different output current levels by determining the magnitude of the charging current provided by follower B1 based on the high bit of the multi-bit digital-to-analog converter RDAC.

[0115] In one embodiment, capacitor C includes a first terminal and a second terminal. See details. Figure 4 The first end of capacitor C is connected to the control terminal of the driving transistor M; the driving circuit also includes a second slew rate control circuit 4, and the second end of capacitor C is connected to the second slew rate control circuit 4.

[0116] In this capacitor, the first terminal of capacitor C is the positive terminal, and the second terminal of capacitor C is the negative terminal.

[0117] The second slew rate control circuit 4 is configured to provide a preset initial voltage to the second terminal of capacitor C during the pre-turn-on phase. This initial voltage is greater than or equal to the threshold voltage Vth at which the drive transistor M turns on.

[0118] See Figure 5 If the negative terminal of capacitor C is directly grounded, during the pre-turn-on phase, follower B1 charges capacitor C, and the control terminal voltage Vgate of driver transistor M charges from 0 to the amplified voltage Vop output by comparator amplifier circuit 1. Because driver transistor M has a turn-on threshold voltage Vth, the drive current I_LED output by the drive circuit cannot start outputting from the initial time of the pre-turn-on phase. Furthermore, at slow-slow process corners (SS process corners) and low temperatures of -40℃, the turn-on threshold voltage Vth of driver transistor M will be raised, resulting in a longer waiting time for the output current I_LED of the drive circuit, for example, about 2μs before the output current of the drive circuit starts outputting. This leads to an actual slew rate adjustment time of only about 1μs, resulting in an unsatisfactory slew rate control effect. Figure 5 The timing diagram corresponding to I_LED.

[0119] By setting the second slew rate control circuit 4 to provide a preset initial voltage to the second terminal of capacitor C, the drive circuit can output the drive current I_LED earlier at slow-slow process angles (SS process angles) and low temperatures of -40℃, thus increasing the actual slew rate adjustment time. See details... Figure 6 The timing diagram corresponding to I_LED is used to improve the slew rate control effect.

[0120] See also Figure 4 The driving circuit also includes a sixth switch S6. The second slew rate control circuit 4 includes a first power transistor M1, which is connected as a diode. Specifically, the first power transistor M1 includes a first terminal, a second terminal, and a control terminal. The first terminal of the first power transistor M1 is connected to the control terminal, and the second terminal is grounded. The second terminal of capacitor C is connected to the control terminal of the first power transistor M1, and the second terminal of capacitor C is also grounded through the sixth switch S6.

[0121] In one embodiment, the first power transistor M1 is an NMOS transistor with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate.

[0122] The second slew rate control circuit 4 is configured such that: during the pre-turn-on stage, the stable drive stage, and the pre-turn-off stage, the sixth switch S6 is open; during the complete turn-off stage, the sixth switch S6 is on.

[0123] Specifically, see Figure 6During the pre-turn-on, stable drive, and pre-turn-off phases when the LED ON enable signal is high, the sixth switch S6 is open, and the voltage (VC negative) at the second terminal of capacitor C is clamped at the preset initial voltage. Through the coupling effect of capacitor C, the control terminal voltage Vgate of the driving transistor M is at a level close to or already on at the initial moment of the pre-turn-on phase. At this time, when the follower B1 charges capacitor C, the driving circuit can output the driving current I_LED earlier, which increases the actual slew rate adjustment time and thus improves the slew rate control effect. During the complete turn-off phase when the LED ON enable signal is low, the sixth switch S6 is turned on, and the second terminal of capacitor C is directly grounded through the sixth switch S6 to completely discharge capacitor C, so that the driving transistor M is in a completely off state.

[0124] In one embodiment, see Figure 7 The output terminal of the drive circuit is connected to the external load circuit 3. The external load circuit 3 includes a power element Q1, which is a power element outside the drive circuit. In this application, the drive circuit also includes a third slew rate control circuit 5, which is configured to be connected to the control terminal of the power element Q1.

[0125] The third slew rate control circuit 5 is configured to provide a preset control voltage to the power element Q1 during the pre-turn-on phase.

[0126] In one embodiment, the power element Q1 is a transistor, preferably an NPN transistor. The control terminal of the power element is the base of the transistor. The collector of the transistor is connected to the light-emitting diode (LED), and the emitter of the transistor is connected to the first terminal of the driver transistor M.

[0127] See Figure 8 If only the slew rate of the drive current generated within the drive circuit is controlled, and the LED ON enable signal is directly applied to the base of the transistor, a current spike of nearly 4mA will be generated in the drive current of the LED when the base voltage Vbase of the transistor changes from 0 to 1. By setting a third slew rate control circuit 5 to provide a preset control voltage to the transistor, the base voltage Vbase of the transistor can be pre-processed for controllable charging, thus avoiding the current spike at the instant the LED ON enable signal pulse changes from 0 to 1. For details, please refer to [link to relevant documentation]. Figure 8 .

[0128] Continue to participate Figure 7The third slew rate control circuit 5 provides an adjustable preset control voltage. Specifically, the third slew rate control circuit 5 includes a second power transistor M2, a third power transistor M3, a fourth power transistor M4, and a comparator COMP. The comparator COMP is used to compare the base voltage Vbase of the transistors with a preset base reference voltage Vref_bjt.

[0129] The third slew rate control circuit 5 is configured as follows: when the base voltage Vbase of the transistor is less than the preset base reference voltage Vref_bjt, the second power transistor M2 and the third power transistor M3 form a current mirror to charge the base of the transistor; when the base voltage Vbase of the transistor is greater than the preset base reference voltage Vref_bjt, the third power transistor M3 and the fourth power transistor M4 form an inverter. When the LED ON enable signal is high, the third power transistor M3 is turned on, while the fourth power transistor M4 is turned off. At this time, the base voltage Vbase of the transistor is maintained by the third power transistor M3 to achieve stable clamping; when the LED ON enable signal is low, the third power transistor M3 is turned off, while the fourth power transistor M4 is turned on to pull down the base voltage Vbase of the transistor to the bottom, thereby completely turning off the transistor.

[0130] Furthermore, the drive circuit also includes a seventh switch S7 and an eighth switch S8. The second terminal of the second power transistor M2 and the second terminal of the third power transistor M3 are connected to the same voltage source AVDD. The first terminal of the second power transistor M2 is connected to the control terminal of the second power transistor M2. The first terminal of the second power transistor M2 is also connected to the current source I2. The control terminal of the second power transistor M2 is connected to the control terminal of the third power transistor M3 through the seventh switch S7. The first terminal of the third power transistor M3 is connected to the first terminal of the fourth power transistor M4. The control terminal of the third power transistor M3 is also connected to the control terminal of the fourth power transistor M4 through the eighth switch S8.

[0131] In one embodiment, the second power transistor M2 and the third power transistor M3 are configured as PMOS transistors. The first terminal of the second power transistor M2 and the first terminal of the third power transistor M3 are both drains of the PMOS transistors, and the second terminal of the second power transistor M2 and the second terminal of the third power transistor M3 are both sources of the PMOS transistors. The control terminal of the second power transistor M2 and the control terminal of the third power transistor M3 are both gates of the PMOS transistors. The fourth power transistor M4 is configured as an NMOS transistor. The first terminal of the fourth power transistor M4 is the drain of the NMOS transistor, the second terminal of the fourth power transistor M4 is the source of the NMOS transistor, and the control terminal of the fourth power transistor M4 is the gate of the NMOS transistor.

[0132] The third slew rate control circuit 5 is configured as follows: When the base voltage Vbase of the transistor is lower than the preset base reference voltage Vref_bjt, the seventh switch S7 is turned on, and the eighth switch S8 is turned off; specifically, when the light emission enable signal LED ON changes from 0 to 1, the base voltage Vbase of the transistor is 0, at this time Vbase<Vref_bjt, the seventh switch S7 is closed and turned on, the eighth switch S8 is turned off, the gate of the third power transistor M3 is connected to the gate of the second power transistor M2, the third power transistor M3 and the second power transistor M2 form a current mirror, and the third power transistor M3 copies the current I2 by N times and charges the base voltage Vbase of the transistor until Vbase>Vref_bjt, so that the base voltage Vbase of the transistor rises at a fixed slew rate.

[0133] In one embodiment, N is 20, that is, the third power transistor M3 copies the current I2 by 20 times.

[0134] When the base voltage Vbase of the transistor is higher than the preset base reference voltage Vref_bjt, the seventh switch S7 is turned off, the eighth switch S8 is turned on, and the control terminal of the third power transistor M3 and the control terminal of the fourth power transistor M4 receive the inverted signal of the light emission enable signal LEDON; specifically, after Vbase>Vref_bjt, the seventh switch S7 is turned off, the eighth switch S8 is closed and turned on, the third power transistor M3 and the fourth power transistor M4 form a set of inverters, when the light emission enable signal LED ON is at a high level, the control terminal of the third power transistor M3 and the control terminal of the fourth power transistor M4 receive a low level signal, at this time, the voltage at the base control terminal of the transistor Vbase=AVDD-Ib×Ron, where Ib is the base current of the transistor, Ron is the on-resistance of the third power transistor M3, the base voltage Vbase of the transistor is slightly lower than AVDD but can maintain the saturation conduction of the transistor, and the base voltage Vbase of the transistor is maintained through the third power transistor M3 to achieve stable clamping.

[0135] In the complete turn-off phase, the seventh switch S7 remains off, the eighth switch S8 remains on, and the control terminal of the third power transistor M3 and the control terminal of the fourth power transistor M4 receive a high level signal; specifically, when the light emission enable signal LED ON changes from 1 to 0, the level signals received by the control terminal of the third power transistor M3 and the control terminal of the fourth power transistor M4 change from a low level signal to a high level signal, at this time, the third power transistor M3 is turned off, the fourth power transistor M4 is turned on, the base voltage Vbase of the transistor is pulled down to 0 through the fourth power transistor M4, and the transistor is turned off. Finally, smooth waveforms of the base voltage Vbase of the transistor and the driving current I_LED are realized, which effectively reduces electromagnetic interference during the driving process.

[0136] In one embodiment, refer to Figure 10The output of the comparator amplifier circuit 1 is also connected to the virtual output circuit 7. The virtual output circuit 7 is configured to provide a closed feedback loop for the comparator amplifier circuit 1 to maintain the stability of the operating point of the comparator amplifier circuit 1.

[0137] The virtual output circuit 7 includes a virtual drive transistor M0 and a virtual resistor R0. The virtual drive transistor M0 and the virtual resistor R0 are matched with the adjustment branch. That is, the virtual drive transistor M0 has the same specifications and connection method as the drive transistor M of the adjustment branch, and the virtual resistor R0 has the same specifications and connection method as the first resistor R of the adjustment branch.

[0138] In an optional embodiment, the virtual output circuit 7 further includes a virtual transistor Q0, which is connected to the drain of the virtual driving transistor M0, such that the virtual driving transistor M0 and the driving transistor M of the driving circuit have similar drain voltages when connected to the external load circuit 3.

[0139] By connecting a virtual output circuit 7 to the output of the comparator amplifier circuit 1, even if the drive current output by the drive circuit is 0, the drive circuit still forms a closed loop. When it is necessary to drive the external load circuit 3, the drive circuit has a stable and clear operating point and can establish the drive loop more quickly.

[0140] In one specific embodiment, the aforementioned driving circuit is an integrated chip that can be used in rain and light detection chips in automobiles to drive external load light-emitting diodes (LEDs).

[0141] Integrating the driver circuit into a single chip can effectively reduce the area of ​​the driver circuit.

[0142] By configuring a first slew rate control circuit 2, a second slew rate control circuit 4, and a third slew rate control circuit 5, during the initial transition phase of LED turn-on (i.e., the pre-turn-on phase), the control terminal voltage Vgate of the driver transistor M rises slowly with a controlled first slope, executing rising edge slew rate control; during the final transition phase of LED turn-off (i.e., the pre-turn-off phase), it falls slowly with a controlled second slope, executing falling edge slew rate control. By configuring the first slew rate control circuit 2, the rising edge slew rate and falling edge slew rate of the drive current I_LED output by the driver circuit become smoother, effectively reducing high-frequency components in the drive current waveform and optimizing electromagnetic interference (EMI) performance.

[0143] This invention also provides a driving method with slew rate control, applied to the above-mentioned driving circuit, see [link to relevant documentation]. Figure 11 The method includes: S1: The driving process of the configuration driving circuit includes a pre-turn-on phase and a pre-turn-off phase; S2: During the pre-start phase, the first slew rate control circuit 2 slowly charges the capacitor to the amplitude of the amplified voltage. S3: During the pre-shutdown phase, the first slew rate control circuit 2 slowly discharges the capacitor to zero.

[0144] With the above configuration, during the transition phase when the LED is turned on and off, the control terminal voltage Vgate of the driving transistor M rises or falls slowly with a controlled slope, thereby making the rising and falling edges of the driving current I_LED output by the driving circuit smooth, effectively reducing the high-frequency components in the driving current waveform and optimizing the electromagnetic interference (EMI) performance.

[0145] In this application, the process of driving the LED to light up or turn off is controlled by the LED ON enable signal. When the LED ON enable signal is high, it enables the LED, that is, when the LED ON enable signal = 1, the LED is driven to light up. This process includes a pre-on stage, a stable driving stage, and a pre-off stage. When the LED ON enable signal is low, it is in the complete off stage, that is, when LED ON = 0, the LED is driven to turn off. It can be understood that driving the LED to turn off means that the LED does not light up.

[0146] The pre-start phase is controlled by the rising edge control window TR. When the rising edge control window TR is high, it is enabled. That is, when TR=1, the rising edge slew rate of the drive circuit is controlled, that is, the rising edge of the drive circuit is increased with the first slope.

[0147] The stable driving phase is controlled by the stable driving window TS. When the stable driving window TS is high, it is enabled. That is, when TS=1, the stable driving of the light-emitting diode (LED) is executed to emit light.

[0148] The pre-shutdown phase is controlled by the falling edge control window TF. When the falling edge control window TF is high, it is enabled. That is, when TF=1, the falling edge slew rate is controlled, that is, the falling edge of the drive circuit decreases with the second slope.

[0149] It is understandable that when the LED enable signal is ON=1, the rising edge control window TR=1, the stable drive window TS=1, and the falling edge control window TF=1 are executed sequentially. At any given time, only one of these windows is usually in the enabled state.

[0150] The aforementioned driving method with slew rate control further includes: The driving process of configuring the driving circuit also includes a stable driving phase; During the pre-start phase, the first switch S1 is opened, the third switch S3 is turned on to connect to the output terminal of the comparator amplifier circuit 1, and the fourth switch S4 is turned on so that the follower B1 replicates the amplified voltage Vop to charge the capacitor. The control terminal voltage of the drive transistor gradually increases to the amplitude of the amplified voltage Vop as the capacitor is charged.

[0151] During the stable driving phase, at least one of the control switches S3 or S4 is turned off, and the control switch S1 is turned on, so that the comparator amplifier circuit 1 provides a stable control terminal voltage Vgate to the driving transistor M.

[0152] During the pre-shutdown phase, the first control switch S1 is turned off, the fourth control switch S4 is turned on, and the input terminal of the control follower B1 is switched to ground via the third switch S3, so that the capacitor slowly discharges through the follower B1, thereby causing the control terminal voltage Vgate of the drive transistor M to slowly decrease at the second slope.

[0153] Different driving stages are executed by controlling the switching of the first switch S1, the third switch S3, and the fourth switch S4. In the pre-turn-on and pre-turn-off stages, the control terminal voltage Vgate of the driving transistor M is independently controlled by the follower B1. This allows the slew rate of the driving transistor M to be precisely controlled at a first slope during the pre-turn-on stage, slowly rising to the amplified voltage Vop output by the amplifier circuit. During the stable driving stage, the comparator amplifier circuit 1 provides a precise and stable control terminal voltage Vgate for the driving transistor M. This effectively reduces the slew rate of the driving circuit during the turn-on and turn-off stages, and reduces electromagnetic interference in the driving circuit.

[0154] The aforementioned driving method with slew rate control further includes: The driving process of configuring the driving circuit also includes a complete shutdown phase, that is, the light-emitting enable signal LED ON=0; During the pre-start phase, stable drive phase, and pre-stop phase, the fifth control switch S5 is disconnected, and there is no electrical connection between the control terminal of the drive tube and ground. During the complete shutdown phase, the fifth switch S5 is turned on. After the LED ON goes low, closing the fifth switch S5 directly shorts the control terminal voltage Vgate of the driver transistor M to ground, achieving rapid discharge to 0V, ensuring that the driver transistor is completely turned off, and preventing leakage current from the external load LED in the off state.

[0155] The aforementioned driving method with slew rate control further includes: Control the second switch S2 and the first switch S1 to be turned on or off simultaneously.

[0156] By synchronously controlling the second switch S2 and the first switch S1, the negative feedback loop of the comparator amplifier circuit 1 is ensured to be cut off during the slew rate control period. The control terminal voltage Vgate of the drive transistor M is only slowly charged by the follower B1 to the capacitor, ensuring that the rising edge of the follower B1 increases with a preset first slope during the pre-turn-on phase, thus avoiding control conflicts between the comparator amplifier circuit 1 and the follower B1. During the stable driving phase, the negative feedback loop is closed, achieving precise constant current driving.

[0157] Furthermore, during the pre-shutdown phase, the first switch S1 and the second switch S2 are simultaneously turned off, the negative feedback loop is disconnected, and the control terminal voltage Vgate of the drive transistor M is slowly discharged by the follower B1 to the capacitor C, ensuring that the follower B1 controls the falling edge to decrease at a preset second slope during the pre-shutdown phase.

[0158] During the complete shutdown phase, the first switch S1 and the second switch S2 remain open. At this time, the fifth switch S5 is closed to directly ground the control terminal of the drive transistor M, ensuring that the drive transistor M is completely shut off.

[0159] By synchronously disconnecting the second switch S2 and the first switch S1, it is ensured that the comparator amplifier circuit 1 is disconnected from the driving transistor M during the pre-turn-on stage and the turn-off stage, which require slew rate control. This ensures that the follower B1 can independently control the rising and falling slopes of the control terminal voltage Vgate of the driving transistor M. During the stable driving stage, the second switch S2 and the first switch S1 are synchronously turned on, closing the negative feedback loop and achieving precise constant current driving.

[0160] The aforementioned driving method with slew rate control further includes: controlling the number of parallel regulating branches to be adjusted according to the output current of the driving circuit, and adjusting the number of parallel regulating branches to be adjusted according to the required output current I_LED of the driving circuit. The more parallel regulating branches there are, the smaller the equivalent resistance Rled formed by the parallel branches, and the larger the driving current I_LED output by the driving circuit under the same reference voltage Vref; conversely, the fewer the number of parallel regulating branches, the smaller the driving current I_LED output by the driving circuit.

[0161] Taking an example with 8 regulating branches, this application controls these 8 regulating branches to be connected in parallel into the loop via a 2-to-4 decoder using a 2-bit binary code R<1:0>. The 2-to-4 decoder converts the received 2-bit binary code into 4 different output signals, each corresponding to a different number of regulating branches connected in parallel.

[0162] Specifically, if the resistance value of the first resistor R is denoted as R, then when Rled_sel<1:0>=00, it is connected to the 1st adjustment branch, and the equivalent resistance Rled=R; when Rled_sel<1:0>=01, it is connected to the 2nd adjustment branch, and the equivalent resistance Rled=R / 2; when Rled_sel<1:0>=10, it is connected to the 4th adjustment branch, and the equivalent resistance Rled=R / 4; when Rled_sel<1:0>=11, it is connected to the 8th adjustment branch, and the equivalent resistance Rled=R / 8.

[0163] By using 2-bit binary encoding in conjunction with 8 parallel adjustment branches, the output current range can be adjusted to four levels, effectively reducing circuit complexity.

[0164] The aforementioned driving method with slew rate control further includes: controlling the capacitance value of the adjustable capacitor to be negatively correlated with the number of parallel regulating branches.

[0165] Specifically, the adjustable capacitor and the gate parasitic capacitance of the driving transistor M constitute the total output load capacitance of the comparator amplifier circuit 1. It can be understood that when the follower B1 charges and discharges the adjustable capacitor, it also charges and discharges the gate parasitic capacitance of the driving transistor M. However, the more parallel adjustment branches there are, the more parallel driving transistors M there are, which makes the total parasitic capacitance of the first output adjustment circuit larger. At this time, the adjustable capacitor should be selected with a smaller capacitance value to ensure that the total output load capacitance Ctotal remains unchanged, so as to ensure that the stability of the comparator amplifier circuit 1 remains consistent and that the slew rate remains unchanged during the pre-turn-on and pre-turn-off phases.

[0166] The aforementioned driving method with slew rate control further includes: a programmable voltage source 6 comprising a current source and a multi-digital-to-analog converter (RDAC) connected in sequence. The current source injects current into the RDAC, and the RDAC outputs a corresponding analog reference voltage Vref according to its digital code. For details, please refer to the example description of the programmable voltage source 6 in the driving circuit; it will not be repeated here.

[0167] By coordinating the number of multi-bit analog-to-digital converters (RDACs) with the number of parallel adjustment branches, more fine adjustments can be achieved within any one of the four ranges of the equivalent resistance Rled formed by the first output adjustment circuit. For example, by setting an 8-bit RDAC, with its digital code ranging from 0 to 255 (256 variations), 256 fine adjustments can be achieved within any one of the four ranges of the equivalent resistance Rled.

[0168] The aforementioned driving method with slew rate control further includes: controlling the first slew rate control circuit 2 to determine the magnitude of the charging current for the capacitor based on the high-order bits of the multi-digit analog-to-digital converter, wherein the magnitude of the current is positively correlated with the value of the high-order bits of the multi-digit analog-to-digital converter.

[0169] In one specific embodiment, the follower B1 is configured to determine the current magnitude for charging the capacitor based on the high 2 bits of the multi-bit digital-to-analog converter. Of course, the current magnitude for charging the capacitor to ground can also be determined based on the high 3 or high 4 bits of the multi-bit digital-to-analog converter. This application does not impose any specific limitations.

[0170] For different reference voltages Vref, the amplified voltage Vop output by comparator amplifier circuit 1 varies with the reference voltage Vref. If follower B1 provides a fixed charging current, for higher reference voltages Vref, the charging current may be too small, and the control terminal voltage of the drive transistor may not reach the amplified voltage Vop output by comparator amplifier circuit 1 after the pre-turn-on phase ends, resulting in poor slew rate control. Conversely, for lower reference voltages Vref, the charging current may be too large, and the control terminal voltage of the drive transistor may reach the amplified voltage Vop output by comparator amplifier circuit 1 too early before the pre-turn-on phase ends, resulting in a still high slew rate. This application ensures that the programmable voltage source 6 can achieve the best slew rate control effect of the drive circuit at different output current levels by determining the charging current of follower B1 to the capacitor based on the high bit of the multi-bit digital-to-analog converter.

[0171] The aforementioned driving method with slew rate control further includes: in the pre-turn-on phase, controlling the second slew rate control circuit 4 to provide a preset initial voltage to the second terminal of the capacitor, wherein the initial voltage is greater than or equal to the threshold voltage at which the driving transistor is turned on.

[0172] If the negative terminal of capacitor C is directly grounded, during the pre-turn-on phase, follower B1 charges capacitor C, and the control terminal voltage of the driver transistor starts charging from 0 to the amplified voltage Vop output by comparator amplifier circuit 1. Because the driver transistor M has a turn-on threshold voltage Vth, the output current I_LED of the driver circuit cannot start outputting from the initial time of the pre-turn-on phase. Furthermore, at slow-slow process corners (SS process corners) and low temperatures of -40℃, the turn-on threshold voltage Vth of the driver transistor will be raised, causing the output current I_LED of the driver circuit to wait even longer, for example, about 2μs before the output current of the driver circuit starts outputting. This results in an actual slew rate adjustment time of only about 1μs, leading to an unsatisfactory slew rate control effect.

[0173] By setting the second slew rate control circuit 4 to provide an initial preset voltage Vref_C to the second terminal of capacitor C, the drive circuit can output the drive current I_LED earlier at slow-slow process angle (SS process angle) and low temperature of -40℃, so that the actual slew rate adjustment time can be increased, thereby improving the slew rate control effect.

[0174] The aforementioned driving method with slew rate control further includes: during the pre-start phase, controlling the third slew rate control circuit 5 to provide a preset control voltage to the power element Q1.

[0175] The power component Q1 can be a transistor.

[0176] If only the drive current generated internally by the drive circuit is controlled by slew rate, and the LED ON enable signal is directly applied to the base of the transistor, a current spike of nearly 4mA will be generated on the external drive current output by the transistor. By setting a third slew rate control circuit 5 to provide a preset control voltage to the transistor, the base of the transistor can be pre-processed for controllable charging, thus avoiding the output current spike at the instant the LED ON enable signal pulse changes from 0 to 1.

[0177] The aforementioned driving method with slew rate control, in the pre-start phase, controls the third slew rate control circuit 5 to provide a preset control voltage to the power element Q1, and further includes: When the control terminal voltage of the transistor is less than the preset base reference voltage, the second power transistor M2 and the third power transistor M3 are controlled to form a current mirror to charge the base of the transistor.

[0178] When the base voltage Vbase of the transistor is greater than the preset base reference voltage Vref_bjt, the third power transistor M3 and the fourth power transistor M4 are controlled to form an inverter. Specifically, when the LED ON enable signal is high, the third power transistor M3 is turned on and the fourth power transistor M4 is turned off. At this time, the base voltage Vbase of the transistor is maintained by the third power transistor M3 to achieve stable clamping. When the LED ON enable signal is low, the third power transistor M3 is turned off and the fourth power transistor M4 is turned on to pull down the base voltage Vbase of the transistor to the bottom, so as to completely turn off the transistor.

[0179] Specifically, when the base voltage Vbase of the transistor is less than the preset base reference voltage Vref_bjt, the seventh switch S7 is turned on and the eighth switch S8 is turned off, and the third power transistor M3 and the second power transistor M2 form a current mirror; when the base voltage Vbase of the transistor is greater than the preset base reference voltage Vref_bjt, the seventh switch S7 is turned off and the eighth switch S8 is turned on, and the third power transistor M3 and the fourth power transistor M4 form an inverter. The control terminals of the third power transistor M3 and the fourth power transistor M4 receive low-level signals. When the LED ON enable signal is high, the control terminals of the third power transistor M3 and the fourth power transistor M4 receive low-level signals. The base voltage Vbase of the transistor is slightly lower than AVDD but can maintain the transistor's saturation conduction. The base voltage Vbase of the transistor is maintained by the third power transistor M3, achieving stable clamping; in the complete turn-off phase, the LED ON enable signal... When ON changes from 1 to 0, the seventh switch S7 remains open, and the eighth switch S8 remains on. The control terminals of the third power transistor M3 and the fourth power transistor M4 receive high-level signals. At this time, the third power transistor M3 is off and the fourth power transistor M4 is on. The base voltage Vbase of the transistor is pulled down to 0 through the fourth power transistor M4, turning off the transistor and achieving a smooth waveform of the base voltage Vbase and the drive current I_LED.

[0180] It should be noted that the description of the driving circuit structure and the description of the driving method in this application can be understood by those skilled in the art by combining them according to the specific circumstances.

[0181] The present invention also provides a driving system, including the driving circuit described above.

[0182] In one specific embodiment, the driving system further includes a light-emitting device such as a light-emitting diode (LED), and a driving circuit is connected to the light-emitting device. The second terminal of the driving transistor in the driving circuit outputs a driving signal, which is used to drive the light-emitting device to emit light.

[0183] The driving system also includes power components (such as transistors). The driving circuit is connected to the light-emitting device through the power components. That is, the driving current output by the driving circuit drives the light-emitting diode (LED) to emit light after passing through the power components.

[0184] This application relates to a driving circuit, driving method, and driving system. The driving circuit includes a comparator amplifier circuit, a driving transistor, a first slew rate control circuit, and a capacitor. The comparator amplifier circuit receives a reference voltage and a feedback voltage to generate an amplified voltage. The control terminal of the driving transistor is connected to the output terminal of the comparator amplifier circuit to generate a driving signal based on the amplified voltage. The first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit and the control terminal of the driving transistor. The first terminal of the capacitor is connected to the control terminal of the driving transistor. The driving process of the driving circuit includes a pre-turn-on stage and a pre-turn-off stage. In the pre-turn-on stage, the capacitor is charged to the amplitude of the amplified voltage by the first slew rate control circuit. In the pre-turn-off stage, the capacitor is discharged to zero by the first slew rate control circuit. By setting the slew rate control circuit, this application controls the slew rate of the control terminal voltage of the driving transistor within a preset driving stage, making the rising and falling edges of the driving current smoother, effectively reducing high-frequency components, and optimizing electromagnetic interference (EMI) performance.

[0185] In the description of this specification, references to terms such as "an embodiment," "some embodiments," "specifically," or "optional embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0186] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0187] This application has been described with reference to the above-mentioned embodiments; however, the above embodiments are merely examples for implementing this application. It must be noted that the disclosed embodiments do not limit the scope of this application. On the contrary, any modifications and refinements made without departing from the spirit and scope of this application are within the scope of patent protection of this application.

Claims

1. A driving circuit, comprising: A comparator amplifier circuit is used to receive a reference voltage and a feedback voltage to generate an amplified voltage. A driving transistor, the control terminal of which is controllably connected to the output terminal of the comparator amplifier circuit to generate a driving signal based on the amplified voltage; A first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit and the control terminal of the driving transistor. A capacitor, the first end of which is connected to the control terminal of the driving transistor; The driving process of the driving circuit includes a pre-turn-on stage and a pre-turn-off stage; in the pre-turn-on stage, the capacitor is charged to the amplitude of the amplified voltage by the first slew rate control circuit; in the pre-turn-off stage, the capacitor is discharged to zero by the first slew rate control circuit.

2. The driving circuit according to claim 1, characterized in that, The driving circuit further includes a first switch, a third switch, and a fourth switch; the driving process further includes a stable driving stage; the first slew rate control circuit is a follower. The output terminal of the comparator amplifier circuit is connected to the control terminal of the driving transistor via the first switch. The first input terminal of the follower is connected to the output terminal of the comparator amplifier circuit or grounded via the third switch; the output terminal of the follower is connected to the control terminal of the driver transistor via the fourth switch. The driving circuit is configured such that, during the pre-start phase, the first switch is off, the third switch is on and connected to the output terminal of the comparator amplifier circuit, the fourth switch is on, and the follower replicates the amplified voltage to charge the capacitor. During the stable driving phase, at least one of the third switch or the fourth switch is open, and the first switch is closed. During the pre-shutdown phase, the first switch is turned off, the fourth switch is turned on, and the input terminal of the follower is switched to ground via the third switch.

3. The driving circuit according to claim 2, characterized in that, The driving circuit also includes a fifth switch, the control terminal of the driving transistor is grounded through the fifth switch, and the driving process also includes a complete turn-off phase. The fifth switch is configured to be open during the pre-opening phase, the stable driving phase, and the pre-shutdown phase; and to be open during the complete shutdown phase.

4. The driving circuit according to claim 2, characterized in that, The driving circuit further includes a second switch, and the second input terminal of the comparator amplifier circuit is connected to the first terminal of the driving transistor via the second switch to receive the feedback voltage; The second switch and the first switch are simultaneously turned on or simultaneously turned off.

5. The driving circuit according to claim 2, characterized in that, The driving circuit further includes a first output adjustment circuit, which includes multiple parallel adjustment branches. The first output adjustment circuit is configured to adjust the number of parallel adjustment branches according to the output current of the driving circuit. The adjustment branch includes a driving transistor and a first resistor connected in series.

6. The driving circuit according to claim 5, characterized in that, The capacitor is an adjustable capacitor; The adjustable capacitor is configured to adjust its capacitance value according to the number of the adjusted branches connected in parallel.

7. The driving circuit according to claim 6, characterized in that, The capacitance value of the adjustable capacitor is negatively correlated with the number of the regulating branches connected in parallel.

8. The driving circuit according to claim 5, characterized in that, The driving circuit further includes a second output adjustment circuit, which includes a programmable voltage source. The output terminal of the programmable voltage source is connected to the first input terminal of the comparator amplifier circuit to provide the comparator amplifier circuit with an adjustable reference voltage.

9. The driving circuit according to claim 8, characterized in that, The programmable voltage source includes a current source and a multi-digit digital-to-analog converter connected in sequence.

10. The driving circuit according to claim 9, characterized in that, The follower is configured to determine the magnitude of the charging current for the capacitor based on the high-order bits of the multi-bit digital-to-analog converter.

11. The driving circuit according to claim 10, characterized in that, The magnitude of the current is positively correlated with the high-order value of the multi-bit digital-to-analog converter.

12. The driving circuit according to claim 3, characterized in that, The capacitor also includes a second terminal, and the driving circuit also includes a second slew rate control circuit, with the second terminal of the capacitor connected to the second slew rate control circuit. The second slew rate control circuit is configured to provide a preset initial voltage to the second terminal of the capacitor during the pre-turn-on phase, wherein the initial voltage is greater than or equal to the threshold voltage at which the driving transistor is turned on.

13. The driving circuit according to claim 12, characterized in that, The driving circuit further includes a sixth switch; the second slew rate control circuit includes a first power transistor, the first power transistor including a first terminal, a second terminal and a control terminal; the first terminal of the first power transistor is connected to the control terminal of the first power transistor, and the second terminal of the first power transistor is grounded. The second terminal of the capacitor is connected to the control terminal of the first power transistor, and the second terminal of the capacitor is grounded through the sixth switch; The second slew rate control circuit is configured such that, during the pre-turn-on phase, the stable drive phase, and the pre-turn-off phase, the sixth switch is open; and during the complete turn-off phase, the sixth switch S6 is turned on.

14. The driving circuit according to claim 3, characterized in that, The drive circuit is used to connect to an external power element, and the drive circuit also includes a third slew rate control circuit, which is configured to be connected to the control terminal of the power element. The third slew rate control circuit is configured to provide a preset control voltage to the power element during the pre-start phase.

15. The driving circuit according to claim 14, characterized in that, The power element is a transistor, and the third slew rate control circuit includes a second power transistor, a third power transistor, a fourth power transistor, and a comparator. The comparator is used to compare the control terminal voltage of the transistor with a preset base reference voltage. The third slew rate control circuit is configured such that when the control terminal voltage of the transistor is less than the preset base reference voltage, the second power transistor and the third power transistor form a current mirror to charge the control terminal of the transistor; when the control terminal voltage of the transistor is greater than the preset base reference voltage, the third power transistor and the fourth power transistor form an inverter.

16. The driving circuit according to claim 15, characterized in that, The driving circuit also includes a seventh switch and an eighth switch; The second terminal of the second power transistor and the second terminal of the third power transistor are connected to the same voltage source; The first end of the second power transistor is connected to the control terminal of the second power transistor, and the first end of the second power transistor is connected to a current source; The control terminal of the second power transistor is connected to the control terminal of the third power transistor via the seventh switch; The first end of the third power transistor is connected to the first end of the fourth power transistor, and the control end of the third power transistor is also connected to the control end of the fourth power transistor through the eighth switch. The third slew rate control circuit is configured such that when the control terminal voltage of the power element is less than the preset base reference voltage, the seventh switch is turned on and the eighth switch is turned off; when the control terminal voltage of the power element is greater than the preset base reference voltage, the seventh switch is turned off and the eighth switch is turned on, and the control terminals of the third power transistor and the fourth power transistor receive a low-level signal; during the complete turn-off phase, the seventh switch remains off and the eighth switch remains on, and the control terminals of the third power transistor and the fourth power transistor receive a high-level signal.

17. The driving circuit according to claim 5, characterized in that, The output of the comparator amplifier circuit is also connected to a virtual output circuit. The virtual output circuit is configured to provide a closed feedback loop for the comparison amplifier circuit to maintain the stability of the operating point of the comparison amplifier circuit.

18. The driving circuit according to claim 17, characterized in that, The virtual output circuit includes a virtual driving transistor and a virtual resistor, which are matched with the adjustment branch.

19. The driving circuit according to claim 1, characterized in that, The driving circuit is an integrated chip.

20. A driving method with slew rate control, applied to a driving circuit, the driving circuit including a comparator amplifier circuit, a driving transistor, a first slew rate control circuit, and a capacitor; The comparator amplifier circuit receives a reference voltage and a feedback voltage to generate an amplified voltage; the control terminal of the driving transistor is connected to the output terminal of the comparator amplifier circuit to generate a driving signal based on the amplified voltage; the input terminal of the first slew rate control circuit is connected to the output terminal of the comparator amplifier circuit, and the output terminal of the first slew rate control circuit is connected to the control terminal of the driving transistor; the first terminal of the capacitor is connected to the control terminal of the driving transistor; characterized in that... The method includes: The driving process of the configured driving circuit includes a pre-turn-on phase and a pre-turn-off phase; During the pre-start phase, the first slew rate control circuit is controlled to charge the capacitor to the amplitude of the amplified voltage. During the pre-shutdown phase, the first slew rate control circuit is controlled to discharge the capacitor to zero.

21. The driving method according to claim 20, characterized in that, The driving circuit further includes a first switch, a third switch, and a fourth switch; the first slew rate control circuit is a follower; the output terminal of the comparator amplifier circuit is connected to the control terminal of the driving transistor via the first switch; the first input terminal of the follower is connected to the output terminal of the comparator amplifier circuit or grounded via the third switch; the output terminal of the follower is connected to the control terminal of the driving transistor via the fourth switch. The method further includes: The driving process of the configured driving circuit also includes a stable driving phase; During the pre-opening phase, the first switch is controlled to open, the third switch is controlled to open and connect to the output terminal of the comparator amplifier circuit, and the fourth switch is controlled to open, so that the follower replicates the amplified voltage to charge the capacitor; During the stable driving phase, at least one of the third switch or the fourth switch is controlled to open, and the first switch is controlled to turn on. During the pre-shutdown phase, the first switch is controlled to open, the fourth switch is controlled to open, and the input terminal of the follower is controlled to be switched to ground via the third switch.

22. The driving method according to claim 21, characterized in that, The driving circuit further includes a fifth switch, and the control terminal of the driving transistor is grounded via the fifth switch. The method further includes: The driving process of the configured driving circuit also includes a complete shutdown phase; During the pre-opening phase, the stable driving phase, and the pre-shutdown phase, the fifth switch is controlled to open. During the complete shutdown phase, the fifth switch is turned on.

23. The driving method according to claim 21, characterized in that, The driving circuit further includes a second switch, and the second input terminal of the comparator amplifier circuit is connected to the output terminal of the driving transistor via the second switch. The method further includes: Control the second switch and the first switch to be turned on or off simultaneously.

24. The driving method according to claim 21, characterized in that, The driving circuit further includes a first output adjustment circuit, which includes multiple parallel adjustment branches. The method further includes: The number of the regulating branches is adjusted according to the output current of the drive circuit.

25. The driving method according to claim 24, characterized in that, The capacitor is an adjustable capacitor, and the method further includes: The capacitance value of the adjustable capacitor is negatively correlated with the number of the regulating branches connected in parallel.

26. The driving method according to claim 20, characterized in that, The driving circuit further includes a second output adjustment circuit, which includes a programmable voltage source. The output terminal of the programmable voltage source is connected to the first input terminal of the comparator amplifier circuit. The method further includes: The programmable voltage source is controlled to provide an adjustable reference voltage to the comparator amplifier circuit.

27. The driving method according to claim 26, characterized in that, The programmable voltage source includes a current source and a multi-digit digital-to-analog converter connected in sequence, and the method further includes: The first slew rate control circuit determines the charging current of the capacitor based on the high-order bit of the multi-digit digital-to-analog converter, wherein the current is positively correlated with the high-order bit value of the multi-digit digital-to-analog converter.

28. The driving method according to claim 20, characterized in that, The capacitor further includes a second terminal, the driving circuit further includes a second slew rate control circuit, the second terminal of the capacitor is connected to the second slew rate control circuit, and the method further includes: During the pre-turn-on phase, the second slew rate control circuit is controlled to provide a preset initial voltage to the second terminal of the capacitor, wherein the initial voltage is greater than or equal to the threshold voltage at which the driving transistor is turned on.

29. The driving method according to claim 20, characterized in that, The driving circuit is used to connect to an external power element. The driving circuit further includes a third slew rate control circuit, which is configured to be connected to the control terminal of the power element. The method further includes: During the pre-start phase, the third slew rate control circuit provides a preset control voltage to the power element.

30. The driving method according to claim 29, characterized in that, The power element is a transistor, and the third slew rate control circuit includes a second power transistor, a third power transistor, a fourth power transistor, and a comparator. The comparator is used to compare the control terminal voltage of the transistor with a preset base reference voltage. The method further includes: When the control terminal voltage is less than the preset base reference voltage, the second power transistor and the third power transistor are controlled to form a current mirror to charge the control terminal of the transistor. When the control terminal voltage is greater than the preset base reference voltage, the third power transistor and the fourth power transistor are controlled to form an inverter.

31. A drive system, characterized in that, Includes the drive circuit as described in any one of claims 1 to 19.

32. The drive system according to claim 31, characterized in that, It also includes a light-emitting device, the driving circuit is connected to the light-emitting device, wherein the second end of the driving tube outputs a driving signal, the driving signal being used to drive the light-emitting device to emit light.

33. The drive system according to claim 32, characterized in that, It also includes a power element, through which the driving circuit is connected to the light-emitting device.

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